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 # Generated files by hugo
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content/posts/2024/generator-functions.md

@@ -0,0 +1,209 @@
+---
+title: "Polynomial Generator Functions"
+date: 2024-12-28T12:33:01+01:00
+draft: false
+toc: false
+images:
+math: true
+tags: 
+  - signal-processing
+  - polynomials
+  - digital-circuits
+  - python
+---
+
+Previously I went over some interesting techniques for 
+[synthesizing sinusoids]({{< relref "../2022/synthesizing-sinusoids" >}}). 
+There were some interesting points to take away from that discussion. First
+the CIC topology essentially calculated the Nᵗʰ moments or derivatives in a 
+signal and essentially reconstructed a corresponding response using a polynomial
+with those moments or piece-wise derivatives.
+
+This leads to a interesting question when synthesizing a time-limited
+waveform: What are the properties for using polynomial generator functions
+for waveform synthesis if we follow a simple cascade of integrators? The 
+general structure for a cascade of integrators is shown below.
+
+
+``` goat
+   
+       .-.              .-.              .-.            
+c₃ -->| Σ +-----*----->| Σ +-----*----->| Σ +-----*---->  N sequence Waveform
+       '-'      |       '-'      |       '-'      |     
+        ^       v        ^       v        ^       v     
+        |    .-----.     |    .-----.     |    .-----.  
+        |    | z⁻¹ |<--  |    | z⁻¹ |<--  |    | z⁻¹ |<-- Initial Conditions
+        |    '--+--'     |    '--+--'     |    '--+--'    3ʳᵈ Order Polynomial
+        |       |        |       |        |       |       c₂, c₁, c₀
+         '-----'          '-----'          '-----'     
+
+```
+
+The concept here is that the registers are initialized with coefficients
+derived from the desired polynomial response and sequenced for a fixed set of
+cycles before we trigger a reset. This is some what a simplified scenario but
+one could imagine the sequence can be used to modulate a RF carrier in order
+to transmit amplitude modulated symbols. As we will see the approach of using
+generator functions will allow us to synthesize high-precision waveforms with
+exact frequency characteristics with just a few predetermined coefficients.
+
+At first glance, we can reason that many of the desirable properties that one would 
+like to see here are similar to that of window functions (e.g. Hanning or
+Kaiser Windows)[^1]. This is because we are interested in both the time and 
+frequency properties of the generated sequence simultaneously. The key 
+difference here however is that we are constrained to polynomial dynamics.
+As a result the text-book approach for approximating a sum of weighted cosines
+may not be the best approach. Although taking a padé-approximant, using a 
+rational polynomial basis, may be a good choice in some cases. More generally
+nesting or convolving our polynomial basis will result in higher oder 
+polynomal. In order to realize a transcendental response we would need to
+revisit the feedback coefficient for each integrator.
+
+## Determining Initial Conditions
+
+There are a few ways to go about defining a polynomial \\(P(x)\\). Either in terms of
+the roots or in terms of the characteristic equation. Both are useful, 
+especially when we consider the derivative components at the extents of our
+synthesized waveform.
+
+$$ P(x) = (x-p_1) (x-p_2) (x-p_3) ... (x-p_n) $$
+
+$$ P(x) = a_n x^n + ... + a_2 x^2 + a_1 x + a_0 $$
+
+We can back calculate the corresponding initial conditions for our cascade
+of integrators by considering the super-position of each component \\(a_n\\) 
+seperately. Lets denote our initial conditions as \\( c_n + ... + c_2 + c_1 + c_0 \\)
+for our Nᵗʰ order polynomial. As shown in the diagram above the coefficient 
+\\(c_n\\) is directly accumulated on the left most integrator. It should be obvious
+that the first two coefficients: \\(a_1\\) & \\(a_0\\) from our characteristic equation 
+directly related correspond to \\(c_1\\) & \\(c_0\\) respectively. Now we can infer the 
+mapping by recursion and equating the derivative components. For example \\(P(x) = a_2 x^2\\): the
+contribution from \\(a_2\\) on the 2nd order derivative is calculated as taking 
+the 2nd derivative of \\(P(x)\\) and evaluating its value with x=0 which gives 
+us \\(c_2 = 2 * a_2\\). Now equating the 1st derivative from \\(a_2\\) 
+similarly gives \\(c_1 = a_2\\) and finally \\(c_0 = 0\\). If there were lower 
+order terms, the contribution from \\(a_1\\) for example would be calculated 
+independently and added together.
+
+This was a simpler example but one can reason that if the mapping for a particular \\( a_n \\) is
+\\( m(n,i), ... , m(n,1), m(n,0) \\) such that for all \\( i \\) the initial conditions are
+\\(c_n = \sum^n_{i=0} m(n,i) * a_i\\). The final value for the initial condition \\(c_n\\) is then
+sum of all mapping terms from each \\(a_n\\). Then for some given mapping of a Nᵗʰ order polynomial
+we can add one more integration stage to the far right integrating the output 
+to realize a N+1ᵗʰ order polynomial. This is equivalent to multiplying the 
+response with \\( x + 1 \\). Now it should be clear that when we equate the 
+derivative terms the N+1ᵗʰ order terms can be derived from the Nᵗʰ order terms 
+simply by adding the appropriate contributions after the aforementioned 
+multiplication. That is \\( m(n+1,i) = m(n,i) + m(n,i-1) \\) where \\( m(n+1,i) \\) 
+are the mapping terms for the N+1ᵗʰ order polynomial.
+Interestingly the mapping here generates a set of basis coefficients related to
+the sterling-numbers of the second kind. More specifically the 
+[A019538](https://oeis.org/A019538) sequence. Using python and numpy as np 
+we can write the following recursive function:
+
+``` python
+def mapping_coefficients(order: int) -> np.array:
+    """Determine nth coefficient scaling factor for initial condition."""
+    assert order >= 0
+    # Start with coefficient from n-1
+    if order == 0:
+        return np.array([1])
+    elif order == 1:
+        return np.array([1, 0])
+    else:
+        base = mapping_coefficients(order - 1)
+    coef = np.zeros((order + 1,))
+    for elem in range(order - 1):
+        # for each element calculate new coefficient
+        # Based on expanding d/dx * P(x) * (x+1)
+        coef[elem + 1] = (order - elem - 1) * (base[elem] + base[elem + 1])
+    # m_n will always be n!
+    coef[0] = base[0] * order
+    return coef
+
+```
+
+This function will derive the \\( m(n,i) \\) mapping values based on our recursive 
+derivation above. In order to then determine the initial conditions we similarly
+iterate over the characteristic coefficients \\( a_n \\) and accumulate all 
+contributions to resolve the initial conditions \\( c_n \\).
+
+``` python
+def initial_condition(self, poly_coef: np.array) -> np.array:
+    """Set register values based on polynomial coefficients."""
+    init_coef = np.zeros((poly_coef.size,))
+    for index, elem in enumerate(poly_coef):
+        init_coef[index:] += elem * mapping_coefficients(poly_coef.size - index - 1)
+    return init_coef
+
+```
+
+It is worthwhile to point out that not all polynomial functions can be realized
+with this method. While not all zeros in \\( P(x) \\) have to be real, we do 
+require the characteristic coefficients \\( a_n \\) and thereby \\( c_n \\) to
+to be real numbers.
+
+## Frequency Response
+
+Here we will consider a simplified scenario to exemplify the frequency \
+characteristics for generated polynomials.
+Specifically polynomials of even orders with real roots such
+that we can decompose the polynomial \\(P(x)\\) as a product of several 
+elements in the form of \\( (x+p_1)(x+p_2) \\). We can show that the 
+fourier-transform of of this element is in the form of \\( sinc(d ω)^2 \\)
+where \\( d = (p_1 - p_2)/2 \\) such that we can derive relations for the 
+polynomial \\( P(x) = d^2-x^2 \\) and scale them accordingly.
+
+$$
+\hat{P}(x) = \int^{d/2}_{d/2} (d^2-x^2) cos(k x) dx 
+\quad = \quad 
+\frac{8 \sin{ (d k) }}{k^3} -  \frac{8 d \cos{ (d k ) }}{k^2}
+$$
+
+Here we have an example where \\(d=1\\) and we observe the expected
+characteristic functions in both time and frequency space.
+
+{{< figure src="/images/posts/generator/P2.svg" >}}
+{{< figure src="/images/posts/generator/F2.svg" >}}
+
+We can numerically solve for some of the filter properties of interest and 
+compare to other simple windows. There is little suprise in the table below
+as the roll-off and rejection is closely related to the 3dB bandwidth.
+Here we see that the frequency response of P(x) is somewhere inbetween a 
+rectangular window and that of the raise-cosine or Hann window.
+
+| Property      | 2nd Order Poly len(2d) | Rectangle len(2d)     | Hann len(2d)          |
+|---------------|------------------------|-----------------------|-----------------------|
+| DC Value      | \\(\frac{2d^3}{3}\\)   | \\(2d^2\\)            | \\(2d^2\\)            |
+| 3dB Bandwidth | \\(\sim 2.498/d\\)     | \\(\sim 1.895/d\\)    | \\(\sim 3.168/d\\)    |
+| 1st Null      | \\(\sim 4.5/d\\)       | \\(\frac{\pi}{d}\\)   | \\(\frac{2\pi}{d}\\)  |
+| Roll Off      | 40 dB / decade         | 20 dB / decade        | 60 dB / decade        |
+| First Sidelobe| -21 dB                 | -13 dB                | -31 dB                |
+
+For completeness we also include the analytical expression for the Hann window
+frourier transform.
+
+$$
+\hat{H}(x) = \int^{d/2}_{d/2} (1+cos(\frac{2\pi x}{d})) cos(k x) dx 
+\quad = \quad 
+\frac{2 \pi^2 sin(d k)}{k(d^2 k^2-\pi^2)}
+$$
+
+Because we have a clean analytical representation of the frequency response
+it is simple to manipulate our coefficients to get a more desirable response.
+The second order function is limited to a three term composition: 
+\\(sinc + sinc/k^2 + cos/k^2\\). Adding assymetry or using odd-order polynomials 
+can resolve band-pass characteristics which are also interesting. 
+
+In the example below we have chosen to place poles at \\(\pm d\\) and 
+\\(\pm 1.2 d\\) in order to minimize the first sidelobe level using a 
+8ᵗʰ order polynomial.
+
+{{< figure src="/images/posts/generator/P4.svg" title="" width="500" >}}
+{{< figure src="/images/posts/generator/F4.svg" title="" width="500" >}}
+
+## References:
+
+[^1]: A. Nuttall, ''Some windows with very good sidelobe behavior,'' IEEE 
+Trans. Acoust., Speech, Signal Process. , vol. 29, no. 1, pp. 84-91, February 
+1981 [Online]:  http://dx.doi.org/10.1109/TASSP.1981.1163506.

content/posts/2025/analog-verification.md

@@ -0,0 +1,315 @@
+---
+title: "Analogue Verification"
+date: 2025-02-03T09:52:41+01:00
+draft: false
+toc: false
+images:
+tags: 
+  - circuit-design
+  - methodology
+  - verification
+  - analog-circuits
+---
+
+This page briefly discusses aspects for planning and structuring analogue
+verification and some of the inherent issues related with coverage. Most of
+the examples will reference Cadence design tools which is common place but
+alternative with similar flavors exist. This is somewhat specific to analogue
+simulation that validates design from a functional point of view. This ties in
+with the construction of the test bench that will probe various aspects of the
+design to confirm that is operates as expected.
+
+## Design Sign-Off
+
+Sign-off for an analogue design could can imply a multitude of things depending
+its dependency. An exhaustive list of delivery items is shown below. Many of
+these are only relevant at certain points in the hierarchy but standardizing
+the flow for creating each item is essential for systematic design. This
+should allow you develop a check-list automated or manual for certain aspects
+in each deliverable that ensure quality.
+
+- Specification Table
+- Schematic
+- Spice Netlist ✔
+- Verilog Netlist ✔
+- Layout
+- GDSII ✔
+- DRC Report ✔
+- ERC Report ✔
+- LVS Report ✔
+- LEF Abstract ✔
+- Testbench
+- Design Documentation
+- Verification Report
+- Design Review Checklist
+- Digital Timing Model
+- Test/Trimming Plan
+
+Fortunately many of these items (✔) do not necessarily require manual intervention
+and can for the most part be part of a automated flow that sanity-checks
+different aspects of the design.
+
+## Design Flow Automation
+
+Several components in the industry analogue design flow are illustrated below
+with their relative association. The verification process only touches a small
+part in the overall picture but provides key indicators for many other aspects
+of the design flow such as project planning, lab work, and software development.
+
+```mermaid
+graph LR
+    external@{ shape: notch-rect, label: "3rd Party IP" }
+    requirements@{ shape: notch-rect, label: "Design\nRequirements" }
+    design@{ shape: cyl, label: "Cadence\nDesign Database" }
+    reports@{ shape: docs, label: "DRC/ERC/LVS Reports\nCircuit Netlists" }
+    abstracts@{ shape: cyl, label: "GDSII\nLEF/DEF Abstracts" }
+    simulation@{ shape: docs, label: "JSON Database\nVerification Reports\nCircuit Documentation" }
+    labwork@{ shape: docs, label: "Measurement Reports\nRoot-Cause Analysis\n" }
+    webdocs@{ shape: procs, label: "**Documentation Portal**\nUsage Guide\nDesign Theory\netc."}
+    spotfire@{ shape: cyl, label: "Characterization Data"}
+    external ==> design
+    requirements ==> design
+    design == NVAFLOW ==> reports
+    design == NVAFLOW ==> abstracts
+    design == RDBDOC ==> simulation
+    simulation ==> webdocs
+    labwork ==> webdocs
+```
+
+Here I have highlighted two integration tools that automate and assist in
+generating various aspects of the design sign-off. Some of which are not user
+facing such as GDSII and LVS results which are handled by NVAFLOW and is
+closely tied to the process-development-kit (PDK). The other tool is RDBDOC
+which assists parsing the cadence database in order to generate and template
+reports.
+
+The point here being is that when we sign-off at top-level it is not unusual
+for a large number of designs to be incorporated. Each of which should be
+checked while it is frozen for external delivery. Such a tool can rigorously
+generate all outputs systematically while also performing a series of sanity
+checks to grantee design quality.
+
+## Verification Plan
+
+Planning analogue verification in a structured manner is challenging primarily
+because one must often carefully consider what is important when simulating a
+design. It is very easy to exhaustively simulate without actually gaining
+confidence in the design.
+
+Typically one would setup a test bench that checks for both specific
+performance metrics such as phase-margin in a amplifier and generic performance
+metric such as off-state leakage. Here is it good practice to have a base-line
+of checks reflecting best-practices. A few examples of design-agnostic checks:
+
+- Supply sensitivity
+- Bias sensitivity
+- Nominal current
+- Leakage current
+- Peak-to-Peak current
+- Off-state / grounded controls
+- Assertions for illegal states
+- Distortion / Linearity
+- Calibration/Configuration edge cases
+- Debug coverage
+- Output/Input impedance
+
+It is important to keep in mind that these metrics are a baseline for evaluating
+performance at a distance. One can obviously run a simulation an study the
+transient waveform in detail but it is usually not feasible to do this over 500+
+simulation points. This is why it is important to derive metrics for performance
+that accurately reflect underlying characteristics with one or several numbers
+that can be judged over corners and montecarlo.
+
+Now as example a typical verification plan is presented that varies
+process parameters in order to expose variations and weakness in the design
+such that we have a good expectation of what post-silicon performance
+characteristics will look like. This plan is divided into three steps with
+increasing simulation effort.
+
+``` markdown
+This is a baseline where the designer must recognize the best way to stress
+aspects of the design and adjust the plan accordingly.
+```
+
+### Simulation Corners
+
+Generally there are three aspect to simulation corner definition:
+Front-End-Of-Line (FEOL), Back-End-Of-Line (BEOL), Voltage+Temperature. These
+parameters are very closely tied to the process and qualification standard the
+circuit aims to achieve. Naturally the more demanding our qualification the harder
+it is to guarantee performance over coreners. For example we can target a
+temperature range of 0° 70°, -40° 85°, -40° 125° depending if we consider
+consumer, industrial, or grade-1 automotive qualification in the JEDEC standard.
+
+We distinguish between FEOL and BEOL because these are two different sets of
+process parameters that are affected during fabrication that do not correlate
+with one another. FEOL generally relates to device characteristics such as
+threshold voltage, off-leakage, transconductance, and current drive while BEOL
+relates to interconnect and Metal-Oxide-Metal passives such as capacitors and
+inductors. A process will specify bias for FEOL and BEOL while the designer
+will specify a bias for temperature and voltage. Together a collection of
+parameter biases are grouped as corners and used to simulate circuits under
+various post-silicon conditions.
+
+FEOL corners will come in a variety of flavors for different purposes and
+should be studied carefully. Analog circuits are generally not that interested
+in worst-case leakage corners but a worst-case noise corner maybe available.
+Analogue is generally interested in FF and SS extremities, sometimes called
+total corners not to be confused with the global corners FFG and SSG, to if
+trim ranges and bias ranges are sufficient to meet performance requirements.
+
+Separately we should study BEOL corners. This is usually somewhat easier as the
+extremities simply best and worst case capacitance as CWORST/CBEST or best and
+worst interconnect time-constants as RCBEST/RCWORST. The designer should know
+which set of extremes is worst. Typically low frequency analogue will suffer
+most from CWORST/CBEST variation. High freuquency analogue and custom digital
+may opt to use the RCWORST/RCBEST corners.
+
+Verification can be planned and separated into three levels of confidence,
+each with increasing simulation time. It is always advised to select corners
+to find the best and worst case process conditions for our circuit.
+
+### Level 1: Corner Simulations
+
+Level 1 focuses on total corner simulation without montecarlo. The purpose here
+is to demonstrate a brief overview of passing performance with DFM checks such
+as EMIR and Aging. There maybe some back-and-forth with the layout and design
+at this point as verification results are checked.
+
+| **VT Corner** | **High Voltage** | **Nom. Voltage** | **Low Voltage** |
+|---------------|------------------|------------------|-----------------|
+| **High Temp** | | |FF/SS + CBEST/CWORST|
+| **Nom Temp**  | |TT + CBEST/NOM/CWORST| |
+| **Low Temp**  |FF/SS + CBEST/CWORST| | |
+
+Total Simulations: 11 + EMIR + Aging
+
+With these preliminary set of results one can pass some judgement over
+circuit performance during design review. By including the DFM simulations
+here (i.e. EMIR and Aging) the layout will be relatively close to the final
+result.
+
+### Level 2: Montecarlo Simulations
+
+Level 2 focuses on presenting a typical distribution of performance metrics
+using montecarlo methods. Here we must make an important choice of which mc
+corner is used. Generally foundries will recommend to use the global corners:
+FFG, SSG, FSG, SFG, and only apply local mismatch. This will yield good
+statistical distributions in our testbench metrics and allow use to make
+gaussian estimations to limit the number of simulations runs of the same
+confidence interval opposed to a unknown distribution. A alternative here is
+to use the typical corner and enable both local and global process variation.
+
+| **VT Corner** | **High Voltage** | **Nom. Voltage** | **Low Voltage** |
+|---------------|------------------|------------------|-----------------|
+| **High Temp** | | |FFG/SSG+CBEST/CWORST|
+| **Nom Temp**  | |TT+CNOM| |
+| **Low Temp**  |FFG/SSG+CBEST/CWORST| | |
+
+Total Simulations: 225 with 25 mc runs per corner
+
+### Level 3: Completion
+
+Level 3 is intended to be the target set of corners used to validate a design
+across corners using montecarlo methods. This is an exhaustive simulation
+job and doesn't quite cover all possible scenarios when combining FEOL+BEOL+VT.
+Generally however it will a good representation of post-silicon results with a
+high quality testbench.
+
+| **VT Corner** | **High Voltage** | **Nom. Voltage** | **Low Voltage** |
+|---------------|------------------|------------------|-----------------|
+| **High Temp** |FFG/SSG+CBEST/CWORST| |FFG/SSG+CBEST/CWORST|
+| **Nom Temp**  | |FFG/TT/FSG/SFG/SSG+CBEST/CNOM/CWORST| |
+| **Low Temp**  |FFG/SSG+CBEST/CWORST| |FFG/SSG+CBEST/CWORST|
+
+Total Simulations: 775 + EMIR + Aging with 25 mc runs per corner
+
+This set of results ultimately feeds into the test program for the device.
+The distributions can be used to set limits and measurement inferences
+when binning and sorting fabricated devices.
+
+## Verification Report
+
+Reporting on our verification results should provide a overview on what the 
+circuit targets where, where the senstivities lie, and how non-idialities 
+manifest in circuit behavior. Lets discuss a general report structure and 
+provide an example.
+
+- Design Files
+- Simulator Setup
+- Target Specifications
+- Simulation Parameters
+- Simulation Notes
+- Results and Statistical Summary
+- Distributions
+- EMIR/Aging Results
+
+With a ADE result database from Cadence we can export the data using skill
+and generate a generic database file that can be parsed and post-processed by
+python. This allows us to make a clean report that need minimal user input
+while providing a good overview on simulation results external to the Cadence
+environment. A cut-down version of such a report is detailed below. Notice
+the designer should still contribute certain annotations to the report such
+that it is self explanitory.
+
+> # Verification Summary: MYLIB divider_tb
+>   
+> lieuwel 2018-01-01
+> 
+> ## Test Description
+> 
+> This is a preliminary verification report for the divider circuit
+> which is a 8-bit reconfigurable clock divider operating on the RF clock
+> after the 4x clock divider from the counter module. This test bench
+> is intended to verify correct operation for all divider settings.
+> 
+> ## Test: Interactive.2:MYLIB_divider_tb_1
+>   
+> Simulation started on 1st Jan 2018 and ran for 2035 minutes.
+> The yield for this test is 100% to 100% (1675 of 1675 points passed)
+> Verification state: 1/3
+> 
+> ### Design Setup
+> 
+> Library Name: MYLIB
+> Cell Name: divider_tb
+> View Name: schematic
+> Simulator: spectre
+> 
+> ### Parameters
+> 
+> |Name|Expression|Values|
+> | :---: | :---: | :---: |
+> |clk_sr|15p|1.5e-11|
+> |clk_pw|clk_pd/2|3.333333e-10|
+> |clk_pd|4/6G|6.666667e-10|
+> |div|0|0:255|
+> |vdd|1.1|1.045, 1.1, 1.155|
+> 
+> ### Specifications
+> 
+> |Output|Specification|Pass/Fail|
+> | :---: | :---: | :---: |
+> |EnergyPerCycle|< 1p|Pass|
+> |div_err|-100m - 100m|Pass|
+> |div_meas|-|Info|
+> |dly_out|< 100p|Pass|
+> |fin|1.5G ±1%|Pass|
+> 
+> ### Output: EnergyPerCycle
+>   
+> Sample presents a mixed distribution. Using < 1p as specification requirement.
+> 
+> |Corner|P0.16|P0.5|P0.84|Pass/Fail|
+> | :---: | :---: | :---: | :---: | :---: |
+> |C_BEST_HTHV|193f|193f, 193f|193f, 193f|Pass|
+> |C_BEST_HTLV|168f|168f, 168f|168f, 168f|Pass|
+> 
+> {{< figure src="/images/posts/verification/energypercycle-c-best-hthv.png"   title="C_BEST_HTHV" width="250" >}}
+> {{< figure src="/images/posts/verification/energypercycle-c-best-htlv.png"   title="C_BEST_HTLV" width="250" >}}
+>
+> ## Summary
+>
+> Tests pass with good margin
+> 
+> EMIR - pass (pre-TO)

content/posts/2025/dynamic-search.md

@@ -0,0 +1,30 @@
+---
+title: "Single-Bit Heuristics"
+date: 2025-01-13T12:31:02+01:00
+draft: true 
+toc: false
+images:
+tags: 
+  - signal-processing
+  - digital-circuits
+  - python
+---
+
+
+
+
+
+``` goat
+                                   
+              .                                 
+        .-.   |\                 .-.      
+Vin -->| Σ +--+⨍+------*------->| Σ +-->  Digitized Sequence
+        '-'   |/       |         '-'  
+         ^-   '        v          ^   
+         |         .--------.     |   
+         |         |  H(z)  |     |   
+         |         '---+----'     |   
+         |             |          |   
+          '------------*---------'    
+                   
+```

content/posts/2025/mixed-signal-simulation.md

@@ -0,0 +1,68 @@
+---
+title: "Mixed Signal Circuits & Digital Simulation"
+date: 2025-02-04T10:46:19+01:00
+draft: false
+toc: false
+images:
+tags: 
+  - circuit-design
+  - methodology
+  - verification
+  - mixed-signal
+---
+
+These days it is not usual even for "analogue" chips that we perform digital
+integration at the top-level. This is mainly because the digital integration
+flow is very well versed in 3rd-party IP integration and providing confidence
+in the result assuming well defined constraints. Here I will outline a various
+aspects for co-simulation of hard-macro analogue sub-modules in the digital
+design flow. Note that in this context full-custom-digital is often also viewed
+as analogue as from a integration point-of-view they are effectively equivalent.
+
+## Design Views
+
+As we progress through the analogue design flow, progressively more of the digital
+design views can be delivered at each stage. As shown here, first
+a functional definition can provided with a behavioral model. This can be in
+the form of a verilog netlist where ports are well defined and the underlying
+functionality is described using HDL statements. This requires us to discretize
+aspects of the design and choose what functionality is implemented
+as the end-goal here is digital integration testing.
+
+```mermaid
+graph LR
+    A2(Schematic)
+    A3(Layout)
+    A4(Simulation)
+    A2 --> A3
+    A3 --> A4
+    D1(Verilog Netlist)
+    D2(Abstract View)
+    D3(Timing View)
+    A2 --> D1
+    A3 --> D2
+    A4 --> D3
+    style D1 fill:none, stroke:none
+    style D2 fill:none, stroke:none
+    style D3 fill:none, stroke:none
+```
+
+Subsequently an abstract is generated based on the layout. Naturally
+this is used for floor-planning and place & route tools that realize a physical
+design. There are some minor nuances here such as pin definition and keep-out
+areas that will constrain the digital tools. However the key checks are simple:
+are all pins defined and accessible, and is there sufficient clearance to the
+boundary to avoid metal spacing violations.
+
+Finally a timing view can be generated depending on how the underlying circuit
+is constructed. This process is slightly different when looking at a
+circuit where we interface directly with custom digital or transistor level
+elements. It is advisable to avoid this specialized part of the flow because
+it will require us to resimulate and perform our own characterization of the
+timing data using Cadence Liberate. If the digital interface is limited to
+standard-cell we can rely on standard-library defined timing-characterization
+and the associated digital corners that are used with the rest of the design.
+
+## Innovus Flow
+
+## Liberate Flow

content/posts/2025/source/analysis.ipynb

@@ -0,0 +1,22 @@
+{
+ "cells": [
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {
+    "vscode": {
+     "languageId": "plaintext"
+    }
+   },
+   "outputs": [],
+   "source": []
+  }
+ ],
+ "metadata": {
+  "language_info": {
+   "name": "python"
+  }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 2
+}

content/posts/2025/source/models.py

@@ -0,0 +1,153 @@
+from sympy import Symbol, log, sin
+from scipy import constants
+from quantiphy import Quantity
+import control as ct
+
+eval_constants = {
+    "k": constants.k,  # Boltzmann contant
+    "T": constants.convert_temperature(25.0, "Celsius", "Kelvin"),
+    "q": constants.e,  # Elementary charge
+}
+
+_pi = constants.pi
+_kT = constants.Boltzmann * constants.convert_temperature(25.0, "Celsius", "Kelvin")
+
+
+class Crystal:
+    def __init__(self, frequency: float = 4.8e7, noise_floor_dBc: float = -160):
+        self.frequency = frequency
+        self.noise_floor_dBc = noise_floor_dBc
+        ## TODO low-frequency jitter offset contribution
+
+    def xtal_jitter(self, bandwidth, ref_frequency):
+        """XTAL jitter estimate over bandwidth"""
+        return Quantity(
+            (
+                2
+                * 10 ** (self.noise_floor_dBc / 10)
+                * bandwidth
+                / (ref_frequency * 2 * _pi) ** 2
+            )
+            ** 0.5,
+            units="s_rms",
+        )
+
+
+class Oscillator:
+    """
+    VCO Phase-Noise Model of LC Oscillator
+
+    Bandwidth upper limit is set by the refence clock
+    Back off by 10x in sampled systems for stability
+    More accurately take xtal into account and equate jitter
+
+    Reference B. Razavi, "Jitter-Power Trade-Offs in PLLs,"
+    in IEEE Transactions on Circuits and Systems I: Regular Papers,
+    vol. 68, no. 4, pp. 1381-1387, April 2021, doi: 10.1109/TCSI.2021.3057580.
+    """
+
+    def __init__(
+        self,
+        f_center: float = 5e9,
+        vout_max: float = 1.0,
+        ibias: float = 5.0e-3,
+        q_factor: float = 10,
+        eta: float = 2.4,  # noise excess factor (1+gamma)
+    ):
+        self.R = _pi * vout_max / ibias / 2
+        self.f_center = f_center
+        self.vout_max = vout_max
+        self.q_factor = q_factor
+        self.ibias = ibias
+        self.eta = eta
+
+    @property
+    def vco_alpha(self):
+        """Oscillator Noise Figure alpha"""
+        return (
+            _kT / (self.q_factor**2) * self.eta * (_pi / self.ibias) ** 2 / self.R / 8
+        )
+
+    def pll_phase_noise(self, pll_bandwidth):
+        """Estimate on a LC oscillator phase-noise as alpha/f**2"""
+        return self.vco_alpha * (self.f_center / pll_bandwidth) ** 2
+
+    def pll_jitter(self, pll_bandwidth, ref_frequency):
+        """PLL jitter estimate due to VCO"""
+        return Quantity(
+            (
+                4
+                * self.pll_phase_noise(pll_bandwidth)
+                * pll_bandwidth
+                / (ref_frequency * 2 * _pi) ** 2
+            )
+            ** 0.5,
+            units="s_rms",
+        )
+
+    def opt_bandwidth(self, ref_xtal: Crystal):
+        """Optimal PLL bandwidth for matching reference noise."""
+        f_ratio = self.f_center / ref_xtal.frequency
+        eff_ref_noise = 2 * 10 ** (ref_xtal.noise_floor_dBc / 10) * f_ratio**2
+        return Quantity(
+            (4 * self.vco_alpha * self.f_center**2 / _pi / eff_ref_noise) ** 0.5,
+            units="Hz",
+        )
+
+    def jitter_tol(self, adc_tol_db: float, adc_resolution: float, adc_clock: float):
+        """Jitter tolerance calculation for m-dB penalty in ADC performance"""
+        return Quantity(
+            (
+                (10 ** (adc_tol_db / 10) - 1)
+                / (3 * _pi**2 * adc_clock**2 * 2 ** (2 * adc_resolution - 1))
+            )
+            ** 0.5,
+            units="s_rms",
+        )
+
+
+# LC Tank Parameter Selection
+# E. Hegazi, H. Sjoland and A. A. Abidi,
+# "A filtering technique to lower LC oscillator phase noise,"
+# in IEEE Journal of Solid-State Circuits,
+# vol. 36, no. 12, pp. 1921-1930, Dec. 2001, doi: 10.1109/4.972142
+# A. Mazzanti and P. Andreani,
+# "Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise,"
+# in IEEE Journal of Solid-State Circuits,
+# vol. 43, no. 12, pp. 2716-2729, Dec. 2008,
+
+
+class Divider:
+    # Error-Feedback Topology
+    # https://www.youtube.com/watch?v=t1TY-D95CY8&t=4373s
+
+    ω = Symbol("ω")
+
+    def __init__(self, order: int = 2, fb_int:int = 100, fb_frac:float = 0.1337):
+        self.fb_int = fb_int
+        self.fb_frac = fb_frac
+        self.order = order
+
+    @property
+    def noise_function_approx(self):
+        return (_pi / 3 / self.ω) ** self.order
+
+    @property
+    def noise_function_exact(self):
+        return (2 * sin(self.ω / 2)) ** self.order
+
+    @property
+    def psd_out(self):
+        return self.noise_function_exact**2 / 12
+    
+    @property
+    def modulator_c2p(self):
+        return ct.tf([0,1],[1,-1],dt=True)*(2*_pi/(self.fb_int+self.fb_frac))
+
+    @property
+    def pll_ntf(self):
+        pass
+
+    @property
+    def modulator_response_ss(self):
+        return ct.tf2ss(self.modulator_c2p) * ct.tf2ss(self.pll_ntf)

content/publications/2018/a-0-006-mm-tsqrd-1-2-rmu-w-analogue-to-time-converter-for-asynchronous-bio-sensors.md

@@ -49,17 +49,17 @@ This section introduces the operating principle and circuit dynamics of the prop
 
 A block diagram of the proposed architecture is detailed in Fig. 2a. For clarity, this shows the single ended equivalent of the fully differential circuit that was implemented. The difference in potential between two electrode inputs V<sub>R<sub> & V<sub>IN<sub> is chopped at the chopper frequency f<sub>chp<sub> to generate a up-modulated voltage waveform that couples the input onto V<sub>X<sub> through C<sub>I<sub>. The essential mechanism here is that signals appearing on V<sub>X<sub> induce a current that feeds into two oscillators with different polarities after being demodulated. This current forces the oscillators accumulate a relative phase difference because the phase is dependent on the integral of injected current [^19]. This phase difference is then evaluated for each oscillator tap using XOR logic to yield multiple time-encoded PWM signals that can also be chopped using digital logic. The resulting digital signal is capacitively coupled onto V<sub>X<sub> in parallel to close the loop. This is the main signal amplifying path that realises a first-order asynchronous ΔΣ modulator and this sense using N phase detectors in parallel represents asynchronous quantization of the phase difference with a resolution of log<sub>2<sub>(1+N) bits. Using this interpretation we can construct the corresponding analytical model that is shown in Fig. 2b and will assist in deducing the design's parameter dependencies.
 
-$$  H(s) = \frac{ 1 }{ s / k_1 + N f } \approx \frac{1}{s\cdot \frac{N C_{gate} V_{RG}}{Gm}+\frac{C_F}{C_I}\frac{C_U}{C_U+\:\:\text{\makebox[-3pt][l]{\\(\nearrow\\)}}C_G/N}} $$
+$$  H(s) =\frac{ 1 }{ s / k_1 + N f } \approx \frac{1}{s \cdot \frac{N C_{gate} V_{RG}}{Gm}+\frac{C_F}{C_I}\frac{C_U}{C_U + C_G/N}} $$
 
-$$  f = {\frac{C_F}{C_{I}+C_{F}}} \cdot \frac{N C_{U}}{C_{F}+N C_{U}+ \text{\makebox[-3pt][l]{\\(\nearrow\\)}}C_{G}} $$
+$$  f = {\frac{C_F}{C_{I}+C_{F}}} \cdot \frac{N C_{U}}{C_{F}+N C_{U}+C_{G}} $$
 
 First the expression in Eq. 1 can be derived to characterise the signal amplifying loop. The feedback factor \\(f\\) evaluated in Eq. 2 corresponds to the capacitive coupling of a particular PWM phase Q on to V<sub>X<sub> with respect to the capacitors C<sub>I<sub>, C<sub>F<sub>, C<sub>G<sub>, C<sub>U<sub>. In this case C<sub>G<sub> can be digitally tuned to provide varying gain settings (41-53 dB). The oscillator's integration factor k<sub>1<sub> is derived by evaluating the impulse sensitivity function (ISF). The ISF captures how the oscillator phase is affected as a function of charge being injected into the virtual supply of the oscillator V<sub>R<sub> [^19]. Following the derivation for Eq. 2 in [^11] this factor can be assumed constant and is simply dependent on the transconductance Gm, loading capacitance of each delay stage C<sub>gate<sub>, and the voltage across the oscillator V<sub>RG<sub> such that k<sub>1<sub>=Gm/(N C<sub>gate<sub> V<sub>RG<sub>).
 
-The second control loop is used to reject near-DC aggressors that will appear at the input of the main transconductor. Chopping will prevent the input-referred noise profile from being corrupted by flicker noise but in turn several large tones will appear at harmonics of f<sub>chp<sub> because off-set is being up-modulated. Moreover because this structure is not providing narrowband amplification the feedback must actively suppress these tones to avoid the output from being saturated and distorted. These components are integrated with a gain of approximately A<sub>ripple<sub>=k<sub>1<sub>/f<sub>chp<sub> which induces a 90\\(^\circ\\) phase shift. The phase-shift can be corrected for by using the chopper clock that is delayed by 1/4<sup>th<sup> of the period when demodulating Q to recover the off-set. The flicker rejection further depends on the transfer function F(s) which represents how the recovered signal is smoothed and fed back onto V<sub>X<sub>. Using a charge pump in addition to the pseudo-resistor R<sub>P<sub> will yield an expression for F(s) according to Eq. 3 where C<sub>L<sub> and I\tss{Δ} represent the main integration capacitor and charge pump bias current respectively. This is also shown in Fig. 2.
+The second control loop is used to reject near-DC aggressors that will appear at the input of the main transconductor. Chopping will prevent the input-referred noise profile from being corrupted by flicker noise but in turn several large tones will appear at harmonics of f<sub>chp<sub> because off-set is being up-modulated. Moreover because this structure is not providing narrowband amplification the feedback must actively suppress these tones to avoid the output from being saturated and distorted. These components are integrated with a gain of approximately A<sub>ripple<sub>=k<sub>1<sub>/f<sub>chp<sub> which induces a 90\\(^\circ\\) phase shift. The phase-shift can be corrected for by using the chopper clock that is delayed by 1/4<sup>th<sup> of the period when demodulating Q to recover the off-set. The flicker rejection further depends on the transfer function F(s) which represents how the recovered signal is smoothed and fed back onto V<sub>X<sub>. Using a charge pump in addition to the pseudo-resistor R<sub>P<sub> will yield an expression for F(s) according to Eq. 3 where C<sub>L<sub> and I<sub>Δ<sub> represent the main integration capacitor and charge pump bias current respectively. This is also shown in Fig. 2.
 
 $$  F(s) = \frac{N   I_{\Delta}}{s (C_{L} C_{I} R_{P}   s + C_{L} + C_{I})} $$
 
-Combining F(s) and A<sub>ripple<sub> will then predict how the noise aggressors at V<sub>x<sub> are removed. The frequency dependent response in Fig. 3 evaluates this control mechanism at different points in the loop using the following implemented circuit parameters: N=5, f<sub>chp<sub>=75 kHz, C<sub>I<sub>=288 fF, C<sub>G<sub>=69 fF, C<sub>F<sub>=C<sub>U<sub>=14 fF, R<sub>P<sub>=100 MΩ, C<sub>L<sub>=1.6 pF, I\tss{Δ}=5 nA. This shows the influence of noise at the input (e²<sub>flk<sub>) with respect to the ripple at the ATC output and the fluctuations on V<sub>X<sub> as a function of frequency. First notice the increased chopper frequency enables this circuit to increase its bandwidth and reject more of the low-frequency band including common-mode signals that asymmetrically couple onto V<sub>X<sub>. In addition the second order low-pass characteristic provides increased rejection of the chopper and oscillator tones such that the two control loops operate in isolation. A known drawback of increasing f<sub>chp<sub> is the reduction in input impedance but as shown in Sec. 10 this reduction can be mitigated with technology scaling and using a smaller value for C<sub>I<sub>.
+Combining F(s) and A<sub>ripple<sub> will then predict how the noise aggressors at V<sub>x<sub> are removed. The frequency dependent response in Fig. 3 evaluates this control mechanism at different points in the loop using the following implemented circuit parameters: N=5, f<sub>chp<sub>=75 kHz, C<sub>I<sub>=288 fF, C<sub>G<sub>=69 fF, C<sub>F<sub>=C<sub>U<sub>=14 fF, R<sub>P<sub>=100 MΩ, C<sub>L<sub>=1.6 pF, I<sub>Δ<sub>=5 nA. This shows the influence of noise at the input (e²<sub>flk<sub>) with respect to the ripple at the ATC output and the fluctuations on V<sub>X<sub> as a function of frequency. First notice the increased chopper frequency enables this circuit to increase its bandwidth and reject more of the low-frequency band including common-mode signals that asymmetrically couple onto V<sub>X<sub>. In addition the second order low-pass characteristic provides increased rejection of the chopper and oscillator tones such that the two control loops operate in isolation. A known drawback of increasing f<sub>chp<sub> is the reduction in input impedance but as shown in Sec. 10 this reduction can be mitigated with technology scaling and using a smaller value for C<sub>I<sub>.
 
 {{< figure src="/images/jssc2018/noise_tf.svg" title="Figure 3: The closed loop response of the flicker rejection loop due to input-referred noise e²<sub>flk<sub> evaluated with respect to the ripple magnitude seen at Q (solid), the feedback seen at V<sub>X<sub> (dotted), and the open loop response F(s)\\(\cdot\\)A<sub>ripple<sub> (dashed)." width="500" >}}
 
@@ -67,22 +67,22 @@ Given these dynamics there is still important distinction to be made with regard
 
 # 4 Circuit Implementation
 
-{{< figure src="/images/jssc2018/obi_sch.svg" title="Figure 4: The transistor level implementation of the ATC circuit in Fig. 2a. Here the complementary structure in a) represents the main transconductor; b) represents the pseudo-differential oscillator where each delay cell is shown in c); The flicker rejection stage is shown in d) where only the grey section is replicated for each phase. Note that all devices have their body connected to the corresponding supplies with the exception of M\tss{5-8} which have the body connected to the drain of M<sub>9<sub>. Furthermore M\tss{13-16} and M\tss{21-22} their body connected to V<sub>R<sub> and either terminal of C<sub>L<sub> respectively." width="500" >}}
+{{< figure src="/images/jssc2018/obi_sch.svg" title="Figure 4: The transistor level implementation of the ATC circuit in Fig. 2a. Here the complementary structure in a) represents the main transconductor; b) represents the pseudo-differential oscillator where each delay cell is shown in c); The flicker rejection stage is shown in d) where only the grey section is replicated for each phase. Note that all devices have their body connected to the corresponding supplies with the exception of M<sub>5-8<sub> which have the body connected to the drain of M<sub>9<sub>. Furthermore M\<sub>13-16<sub> and M\<sub>21-22<sub> their body connected to V<sub>R<sub> and either terminal of C<sub>L<sub> respectively." width="500" >}}
 
-The transistor schematic for the proposed ATC is presented in Fig. 4 and the sizing of each device is listed in Table 1. This circuit can be segmented into four parts corresponding to the transconductor, oscillator, delay stage, and flicker rejection circuit. Each sub-block, including the capacitor array, will be described below. This configuration uses two bias voltages V<sub>BN<sub> & V<sub>BP<sub> to source the annotated drain currents. Both of these voltages are derived on-chip using a simple current mirror structure and a 1 μ A off-chip reference. Furthermore an external reference voltage V<sub>C<sub> is used to control the common mode voltage of V<sub>R<sub> that is placed at V<sub>DD<sub>/2. Note that the 65 nm technology used here provides transistors that can be configured with 150 mV (lvt), 250 mV (vt), and 350 mV (hvt) threshold voltages (V<sub>TH<sub>). The lvt option is used exclusively to reduce the supply voltage to 0.5 V with the exception of M\tss{23-24} which use a 250 mV threshold.
+The transistor schematic for the proposed ATC is presented in Fig. 4 and the sizing of each device is listed in Table 1. This circuit can be segmented into four parts corresponding to the transconductor, oscillator, delay stage, and flicker rejection circuit. Each sub-block, including the capacitor array, will be described below. This configuration uses two bias voltages V<sub>BN<sub> & V<sub>BP<sub> to source the annotated drain currents. Both of these voltages are derived on-chip using a simple current mirror structure and a 1 μ A off-chip reference. Furthermore an external reference voltage V<sub>C<sub> is used to control the common mode voltage of V<sub>R<sub> that is placed at V<sub>DD<sub>/2. Note that the 65 nm technology used here provides transistors that can be configured with 150 mV (lvt), 250 mV (vt), and 350 mV (hvt) threshold voltages (V<sub>TH<sub>). The lvt option is used exclusively to reduce the supply voltage to 0.5 V with the exception of M<sub>23-24<sub> which use a 250 mV threshold.
 
 Table 1:  Device Sizing in micrometers with the labels from Fig. 4
 |		Device | Size (W/L) | Device | Size (W/L) |
 |----|----|----|----|
-|		M<sub>0<sub> 			| 26/5 				| M\tss{15-16} 			| 0.2/2.5 |
-|		M\tss{1-2} 		| 16/0.25 		| M\tss{17-18} 			| 2/5 |
-|		M\tss{3-4} 		| 2/1 				| M\tss{19-20} 			| 10/0.2 |
-|		M\tss{5-6} 		| 4/0.5 			| M\tss{21-22} 			| 1.6/0.4 |
-|		M\tss{7-8} 		| 0.8/1.4 		| M\tss{23-24} 			| 0.96/4 |
+|		M<sub>0<sub> 			| 26/5 				| M\<sub>15-16<sub> 			| 0.2/2.5 |
+|		M\<sub>1-2<sub> 		| 16/0.25 		| M\<sub>17-18<sub> 			| 2/5 |
+|		M\<sub>3-4<sub> 		| 2/1 				| M\<sub>19-20<sub> 			| 10/0.2 |
+|		M\<sub>5-6<sub> 		| 4/0.5 			| M\<sub>21-22<sub> 			| 1.6/0.4 |
+|		M\<sub>7-8<sub> 		| 0.8/1.4 		| M\<sub>23-24<sub> 			| 0.96/4 |
 |		M<sub>9<sub> 			| 32/0.1 			| Logic 						| 0.3/0.1 |
 |		M<sub>10<sub> 		| 6/5 				| Switch<sub>CHP<sub> 	| 1/0.1 (P<sub>type<sub>) |
-|		M\tss{11-12} 	| 1.5/2.4 		| Switch<sub>X<sub> 		| 1/0.2 (N<sub>type<sub>) |
-|		M\tss{13-14} 	| 2.3/2.5 		| C<sub>L<sub> 					| 21/21 |
+|		M\<sub>11-12<sub> 	| 1.5/2.4 		| Switch<sub>X<sub> 		| 1/0.2 (N<sub>type<sub>) |
+|		M\<sub>13-14<sub> 	| 2.3/2.5 		| C<sub>L<sub> 					| 21/21 |
 
 ## 5 Low-Noise Transconductor
 
@@ -98,7 +98,7 @@ The main feature of the oscillators (Fig. 4b) used by this ATC is that it uses d
 
 ## 7 Flicker Rejection Stage
 
-The flicker removal circuit (Fig. 4d) biases the input of the transconductor by feeding back common mode and differential mode signals using a cross coupled load to enable low voltage operation without an additional common-mode-feedback circuit[^20]. The differential feedback provides flicker cancellation by demodulating the digital output using a switched current DAC that integrates on C<sub>L<sub> which is a large vertical metal-insulator-metal (MIM) capacitor placed over the analogue circuitry. The diode connected devices M\tss{21-22} represent pseudo-resistors of 100 MΩ that provide a resistive path to V<sub>X<sub> and further smooths high frequency tones from f<sub>chp<sub> and f<sub>osc<sub>. A significant variation in resistive value is inherently expected but it is important to note that it does not influence the signal amplifying path and the non-dominant poles are far away from the 8 kHz bandwidth of F(s) in Eq. 3 by virtue of not using a second analogue integrator that may compromise stability. The common mode feedback regulates V<sub>R<sub> with respect to V<sub>C<sub> by biasing the common mode of V<sub>X<sub>. For this loop the gain arises from transconductance ratio gm\tss{M19-M20}/gm\tss{M23-M24} together with the drain resistance ratio rds<sub>M10<sub>/(rds<sub>M0<sub>+rds<sub>M9<sub>). This readily provides over 30 dB of gain with the dominant pole provided by the pseudo-resistors that will also attenuate the input common mode signals.
+The flicker removal circuit (Fig. 4d) biases the input of the transconductor by feeding back common mode and differential mode signals using a cross coupled load to enable low voltage operation without an additional common-mode-feedback circuit[^20]. The differential feedback provides flicker cancellation by demodulating the digital output using a switched current DAC that integrates on C<sub>L<sub> which is a large vertical metal-insulator-metal (MIM) capacitor placed over the analogue circuitry. The diode connected devices M<sub>21-22<sub> represent pseudo-resistors of 100 MΩ that provide a resistive path to V<sub>X<sub> and further smooths high frequency tones from f<sub>chp<sub> and f<sub>osc<sub>. A significant variation in resistive value is inherently expected but it is important to note that it does not influence the signal amplifying path and the non-dominant poles are far away from the 8 kHz bandwidth of F(s) in Eq. 3 by virtue of not using a second analogue integrator that may compromise stability. The common mode feedback regulates V<sub>R<sub> with respect to V<sub>C<sub> by biasing the common mode of V<sub>X<sub>. For this loop the gain arises from transconductance ratio gm\<sub>M19-M20<sub>/gm\<sub>M23-M24<sub> together with the drain resistance ratio rds<sub>M10<sub>/(rds<sub>M0<sub>+rds<sub>M9<sub>). This readily provides over 30 dB of gain with the dominant pole provided by the pseudo-resistors that will also attenuate the input common mode signals.
 
 ## 8 Capacitive Feedback Network
 
@@ -128,27 +128,27 @@ Eq. 6 calculates the expected input resistance and provides a first order estima
 
 Mismatch due to process variation is the primary cause of distortion during multi-bit signal conversion. Minimising this source of nonlinearity is essential for both synchronous and asynchronous ΔΣ modulators because mismatch in the feedback DAC is not shaped by the loop filter [^27]. Fortunately the modulating property of the oscillator can remove this distortion if the phase readout is performed in a parallel fashion [^5]. Here we will concisely demonstrate that property arises because the mismatch induced components are simply being averaged and induce a DC-offset together with tones at the harmonic components of f<sub>osc<sub>. This uses a mapping that relates the phase difference \\(x\\) to the generated PWM waveform as a function of time \\(\tau\\) defined in Eq. 7. The following expression in Eq. 8 then evaluates the analogue feedback voltage that appears on V<sub>X<sub> in the ideal case for a given a phase difference of Δφ between the two oscillators.
 
-$$  A(\tau,x) \triangleq\begin{cases} 1  &  \tau   (mod\: 1) \: < \:x  0  &  \text{otherwise} \end{cases} $$
+$$  A(\tau,x) \triangleq \begin{cases} 1  &  \tau ( mod 1 )   <  x \\\\  0  &  \text{otherwise} \end{cases} $$
 
-$$  V_{X}(t) =  f \cdot \sum_{k=0}^{N-1} \underbrace{A( t \cdot f_{osc}+\frac{k}{N}\:,\: \Delta \phi )}_{Q_{k}(t)} $$
+$$  V_{X}(t) =  f \cdot \sum_{k=0}^{N-1} \underbrace{ A \left( t \cdot f_{osc}+\frac{k}{N} , \Delta \phi \right)}_{ Q_k(t) } $$
 
-$$  Q_{k}(t) = (1+\frac{\sigma_{C,k}}{C_U})   A(  t \cdot f_{osc} + \frac{k}{N} \: , \: \sigma_{\tau-\mu,k} + \Delta \phi) $$
+$$  Q_{k}(t) = (1+\frac{\sigma_{C,k}}{C_U})   A(  t \cdot f_{osc} + \frac{k}{N}   ,   \sigma_{\tau-\mu,k} + \Delta \phi) $$
 
-There are two independent sources of mismatch for each phase: the deviation in capacitor weights of C<sub>U<sub> σ<sub>C,k<sub> and the differential delay variation in oscillator stages as a fraction of the oscillation period σ\tss{τ,k} that includes the digital gates generating Q (i.e. inverters and XOR-gate). These are used to formulate Eq. 9 which considers a particular phase of Q(t) and the random mismatch variables that have process dependent normal distributions. The variation in delay will locally increase/decrease the pulse-width of Q for a specific phase \\(k\\). This is a time-invariant component of the gate delay while Δφ and T<sub>osc<sub> are signal dependent. Precisely formulating the cumulative variation of σ\tss{τ} will relate the transistor sizing, gate capacitance, and threshold voltage of each delay during operation.
+There are two independent sources of mismatch for each phase: the deviation in capacitor weights of C<sub>U<sub> σ<sub>C,k<sub> and the differential delay variation in oscillator stages as a fraction of the oscillation period σ<sub>τ,k<sub> that includes the digital gates generating Q (i.e. inverters and XOR-gate). These are used to formulate Eq. 9 which considers a particular phase of Q(t) and the random mismatch variables that have process dependent normal distributions. The variation in delay will locally increase/decrease the pulse-width of Q for a specific phase \\(k\\). This is a time-invariant component of the gate delay while Δφ and T<sub>osc<sub> are signal dependent. Precisely formulating the cumulative variation of σ<sub>τ<sub> will relate the transistor sizing, gate capacitance, and threshold voltage of each delay during operation.
 
-Notice that A is a linear function of Δφ with a gain of 1 for the DC component of the PWM output which can be further expanded to extract the high frequency behaviour. However by design these components are intentionally avoided which should reveal that that the capacitor weights are always uniformly averaged irrespective Δφ. Closed-loop operation feeds back each σ\tss{τ,k} such that the sum all components has zero mean, that is σ\tss{τ-μ,k}\ = σ\tss{τ,k}-(\\(\sum_{k=0}^{N-1}\\) σ\tss{τ,k}/N). The residual variation in delay for each phase inevitably induces spurs at at harmonics of f<sub>osc<sub>.
+Notice that A is a linear function of Δφ with a gain of 1 for the DC component of the PWM output which can be further expanded to extract the high frequency behaviour. However by design these components are intentionally avoided which should reveal that that the capacitor weights are always uniformly averaged irrespective Δφ. Closed-loop operation feeds back each σ<sub>τ,k<sub> such that the sum all components has zero mean, that is σ<sub>τ-μ,k<sub>\ = σ<sub>τ,k<sub>-(\\(\sum_{k=0}^{N-1}\\) σ<sub>τ,k<sub>/N). The residual variation in delay for each phase inevitably induces spurs at at harmonics of f<sub>osc<sub>.
 
 {{< figure src="/images/jssc2018/vco_model.svg" title="Figure 6: A continuous-time multi-phase VCO model for evaluating parameter sensitivity with transient simulations using the logical operator **B** in Eq. 10." width="500" >}}
 
 Verifying this behaviour is best done by modifying the behavioural model commonly used for oscillators[^28] to accommodate multi-phase readout using the above expressions. Such a model is shown in Fig. 6. This configuration uses an internal time variable at V<sub>T<sub> that accumulates according to f<sub>osc<sub>. Given a set of quantisation levels L<sub>k<sub> or equivalently the number of phases, a logical function **B** will compute the corresponding PWM waveform of Q which are weighted by the associated capacitor C<sub>k<sub>. In this case the digital gate delay arising from computing the phase difference and applying feedback to the capacitive DAC can also be modelled by adjusting τ<sub>dly<sub>.
 
-$$  \begin{split}\mathbf{B}(\phi_{S},\phi_{R},L) \triangleq & \left(\phi_{S} > L > \phi_{R} \right) \lor \left(\phi_{S} < \phi_{R} < L \right)   								 &  \lor \left( L < \phi_{S} < \phi_{R} \right)\end{split} $$
+$$  \mathbf{B}(\phi_{S},\phi_{R},L) \triangleq \left(\phi_{S} > L > \phi_{R} \right) \lor \left(\phi_{S} < \phi_{R} < L \right) \lor \left( L < \phi_{S} < \phi_{R} \right) $$
 
-The logical expression in Eq. 10 simply compares the two phases with respect to L and evaluates the digital condition for which the output should be high. This representation implies that the delays correspond to the interval between each level which can be distributed uniformly as L<sub>k<sub>=(0.5+k)/L for integers k from 0 to N-1. By distributing the quantisation levels from 0 to 1 the corresponding delays are inherently normalised to the periodicity of φ\tss{S/R} without explicitly having to compute values with respect to f<sub>osc<sub> even when it is dynamically changing. In addition a difference in oscillator frequency between X\tss{1-2} can also be accommodated by adding a second integrated frequency component to the summation node.
+The logical expression in Eq. 10 simply compares the two phases with respect to L and evaluates the digital condition for which the output should be high. This representation implies that the delays correspond to the interval between each level which can be distributed uniformly as L<sub>k<sub>=(0.5+k)/L for integers k from 0 to N-1. By distributing the quantisation levels from 0 to 1 the corresponding delays are inherently normalised to the periodicity of φ<sub>S/R<sub> without explicitly having to compute values with respect to f<sub>osc<sub> even when it is dynamically changing. In addition a difference in oscillator frequency between X\<sub>1-2<sub> can also be accommodated by adding a second integrated frequency component to the summation node.
 
-{{< figure src="/images/jssc2018/dac_mm.svg" title="Figure 7: Simulated output spectrum with a 2.5 kHz input at -6 dB of the full input-range for a equivalent asynchronous flash quantiser with 2.6 bits of resolution and 5 % mismatch in σ\tss{τ,k} and σ<sub>C,k<sub>." width="500" >}}
+{{< figure src="/images/jssc2018/dac_mm.svg" title="Figure 7: Simulated output spectrum with a 2.5 kHz input at -6 dB of the full input-range for a equivalent asynchronous flash quantiser with 2.6 bits of resolution and 5 % mismatch in σ<sub>τ,k<sub> and σ<sub>C,k<sub>." width="500" >}}
 
-{{< figure src="/images/jssc2018/dac_mm2.svg" title="Figure 8: Simulated output spectrum with a 2.5 kHz input at -6 dB of the full input-range for a asynchronous VCO quantiser with 2.6 bits of resolution, 300 kHz f<sub>osc<sub> and 5 % mismatch in σ\tss{τ,k} and σ<sub>C,k<sub>." width="500" >}}
+{{< figure src="/images/jssc2018/dac_mm2.svg" title="Figure 8: Simulated output spectrum with a 2.5 kHz input at -6 dB of the full input-range for a asynchronous VCO quantiser with 2.6 bits of resolution, 300 kHz f<sub>osc<sub> and 5 % mismatch in σ<sub>τ,k<sub> and σ<sub>C,k<sub>." width="500" >}}
 
 Now the impact of mismatch can be simulated by adding parameter variation in the quantiser levels and the feedback weights (f). The analogous case where the mismatch is not modulated (i.e. f<sub>osc<sub> is 0) loosely corresponds to a flash-based ADC since the phase is simply being compared with N thresholds. The corresponding spectra of the flash quantiser is shown in Fig. 7 and oscillating quantiser is shown in Fig. 8 where we observe the distortion components in different bands of the spectrum.
 
@@ -196,15 +196,16 @@ Table 2: System Characteristics and Comparison with State-of-the-Art
 |		Technology[nm]				| **65**			| 40		| 130		| 40		| 40		| 65		| 65		| 90		| 180		| 65|
 |		Modality 							| **Time**			| Time		| Volt. 	| Time		| Volt.		| Volt.		| Volt.		| Volt.		| Volt.		| Mix |
 |		Supply-V[V]					| **0.5** 			| 0.6		| 1.2		| 1.2		| 1.2		| 0.6 		| 1			| 1			| 0.45 		| 0.5 |
-|		Supply-I[A]					| \textbf{2.55 μ}	| 5.5 μ	| 5.3 μ	| 14 μ	| 2.5 μ	| 3 n 		| 3.3 μ	| 2.8 μ | 2.1 μ	| 10 μ |
+|		Supply-I[A]					| **2.55 μ**	| 5.5 μ	| 5.3 μ	| 14 μ	| 2.5 μ	| 3 n 		| 3.3 μ	| 2.8 μ | 2.1 μ	| 10 μ |
 |		Bandwidth[Hz]					| **11 k** 		| 150		| 500		| 5 k		| 200		| 370		| 8.2 k	| 10.5 k	| 10 k 	| 10 k	|
 |		Input Range[mVpp] 		| **4**  			| 40 		| - 		| 8 		| 100 		| 25 		| 220 		| 1 		| 1 		| 1 |
-|		CMRR[dB] 				| \textbf{(>)60(^\star)}  		| 60 		| 90 		| 97 		| - 		| 60 		| (>)80 	| (>)45 	| 73 		| 75 |
+|		CMRR[dB] 				| **>60**  		| 60 		| 90 		| 97 		| - 		| 60 		| (>)80 	| (>)45 	| 73 		| 75 |
 |		SFDR[dB] 				| **60**  			| 56 		| 72 		| 70 		| 79 		| 75 		| (>)40 	| (>)37 	| (>)46 	| (>)34 |
-|		Noise Floor[V/\rtxt{Hz}]		| **36 n**		| 0.6 μ | 46n		| 32 n		| -			| 1.4 μ	| 27.5n		| 35n		| 29n 		| 100n	|
+|		Noise Floor[V/√Hz]		| **36 n**		| 0.6 μ | 46n		| 32 n		| -			| 1.4 μ	| 27.5n		| 35n		| 29n 		| 100n	|
 |		RMS Noise[μ V<sub>rms<sub>]	| **3.8**		| 7.8		| 1.1 		| 2.3		| 5.2		| 26		| 4.1		| 3.04 		| 3.2 μ | 4.9 μ	|
 |		Area[mm²]				| **0.006**		| 0.015		| 0.013		| 0.015		| 0.135		| 0.15		| 0.042		| 0.137		| 0.25 		| 0.013 |
-|		NEF / PEF							| \textbf{2.2 / 2.4}		| 8.1 / 39| 2.9 / 10| 4.7 / 27| 22 / 581| 2.1 / 2.6| 3.2 / 10| 1.9 / 3.6 | 1.57 / 1.1	| 5.99 / 18 |
+|		NEF / PEF							| **2.2 / 2.4**		| 8.1 / 39| 2.9 / 10| 4.7 / 27| 22 / 581| 2.1 / 2.6| 3.2 / 10| 1.9 / 3.6 | 1.57 / 1.1	| 5.99 / 18 |
+
 
 
 {{< figure src="/images/jssc2018/breakdown.svg" title="Figure 19: Power and area contributions from each sub-circuit." width="500" >}}
@@ -230,17 +231,21 @@ The authors would like to thank Dr. Pantelis Georgiou, and the Europractice Adva
 [^4]: P.Prabha etal., ''A highly digital VCO-based ADC architecture for  current sensing applications,'' IEEE J. Solid-State Circuits,  vol.50, no.8, pp. 1785--1795, Aug 2015.
 [^3]: T.Anand, K.A.A. Makinwa, and P.K. Hanumolu, ''A VCO based highly digital  temperature sensor with 0.034 $^\circ$C/mV supply sensitivity,''  IEEE J. Solid-State Circuits, vol.51, no.11, pp. 2651--2663, Nov  2016.
 [^10]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational  amplifiers and their application to continuous-time filters in nanoscale  CMOS,'' IEEE J. Solid-State Circuits, vol.49, no.12, pp.  2758--2772, Dec 2014.
-[^23]: L.B. Leene and T.G. Constandinou, ''A 0.5V time-domain instrumentation  circuit with clocked and unclocked
+[^23]: L.B. Leene and T.G. Constandinou, ''A 0.5V time-domain instrumentation  circuit with clocked and unclocked
+Delta
+Sigma operation,'' in  2017 IEEE International Symposium on Circuits and Systems (ISCAS), May  2017, pp. 1--4.
 [^12]: Y.Chen etal., ''A continuous-time digital IIR filter with  signal-derived timing and fully agile power consumption,'' IEEE J.  Solid-State Circuits, vol.53, no.2, pp. 418--430, Feb 2018.
 [^22]: S.Pavan, ''Analysis of chopped integrators, and its application to  continuous-time delta-sigma modulator design,'' IEEE Trans. Circuits  Syst. I, vol.64, no.8, pp. 1953--1965, Aug 2017.
 [^24]: W.S.T. Yan and H.C. Luong, ''A 900-MHz cmos low-phase-noise  voltage-controlled ring oscillator,'' IEEE Trans. Circuits Syst.  II, vol.48, no.2, pp. 216--221, Feb 2001.
 [^17]: R.R. Harrison and C.Charles, ''A low-power low-noise CMOS amplifier for  neural recording applications,'' IEEE J. Solid-State Circuits,  vol.38, no.6, pp. 958--965, June 2003.
 [^19]: A.Hajimiri and T.H. Lee, ''A general theory of phase noise in electrical  oscillators,'' IEEE J. Solid-State Circuits, vol.33, no.2, pp.  179--194, Feb 1998.
-[^17]: R.R. Harrison and C.Charles, ''A low-power low-noise CMOS amplifier for  neural recording applications,'' IEEE J. Solid-State Circuits,  vol.38, no.6, pp. 958--965, June 2003.
+[^25]: T.Denison etal., ''A 2
+muW 100 nV/rtHz chopper-stabilized  instrumentation amplifier for chronic measurement of neural field  potentials,'' IEEE J. Solid-State Circuits, vol.42, no.12, pp.  2934--2945, Dec 2007.
 [^14]: Y.Li, D.Zhao, and W.A. Serdijn, ''A sub-microwatt asynchronous  level-crossing ADC for biomedical applications,'' IEEE Trans.  Biomed. Circuits Syst., vol.7, no.2, pp. 149--157, April 2013.
 [^13]: W.Tang etal., ''Continuous time level crossing sampling ADC for  bio-potential recording systems,'' IEEE Trans. Circuits Syst. I,  vol.60, no.6, pp. 1407--1418, June 2013.
 [^9]: G.D. Colletta etal., ''A 20 nW 0.25 V inverter-based  asynchronous delta-sigma modulator in 130 nm digital CMOS process,''  IEEE Trans. VLSI Syst., vol.25, no.12, pp. 3455--3463, Dec 2017.
-[^14]: Y.Li, D.Zhao, and W.A. Serdijn, ''A sub-microwatt asynchronous  level-crossing ADC for biomedical applications,'' IEEE Trans.  Biomed. Circuits Syst., vol.7, no.2, pp. 149--157, April 2013.
+[^16]: F.M. Yaul and A.P. Chandrakasan, ''A noise-efficient 36 nV/
+txtHz  chopper amplifier using an inverter-based 0.2 V supply input stage,''  IEEE J. Solid-State Circuits, vol.52, no.11, pp. 3032--3042, Nov  2017.
 [^29]: H.Kassiri etal., ''Rail-to-rail-input dual-radio 64-channel  closed-loop neurostimulator,'' IEEE J. Solid-State Circuits,  vol.52, no.11, pp. 2793--2810, Nov 2017.
 [^28]: C.C. Kuo etal., ''Fast statistical analysis of process variation  effects using accurate PLL behavioral models,'' IEEE Trans.  Circuits Syst. I, vol.56, no.6, pp. 1160--1172, June 2009.
 [^7]: C.C. Tu, Y.K. Wang, and T.H. Lin, ''A low-noise area-efficient chopped  VCO-based CTDSM for sensor applications in 40 nm CMOS,'' IEEE  J. Solid-State Circuits, vol.52, no.10, pp. 2523--2532, Oct 2017.
@@ -249,9 +254,12 @@ The authors would like to thank Dr. Pantelis Georgiou, and the Europractice Adva
 [^32]: T.Yang and J.Holleman, ''An ultralow-power low-noise CMOS biopotential  amplifier for neural recording,'' IEEE Trans. Circuits Syst. II,  vol.62, no.10, pp. 927--931, Oct 2015.
 [^21]: S.Mondal and D.A. Hall, ''An ECG chopper amplifier achieving 0.92 NEF  and 0.85 PEF with AC-coupled inverter-stacking for noise efficiency  enhancement,'' May 2017, pp. 1--4.
 [^11]: L.B. Leene and T.G. Constandinou, ''Time domain processing techniques using  ring oscillator-based filter structures,'' IEEE Trans. Circuits Syst.  I, vol.64, no.12, pp. 3003--3012, Dec 2017.
-[^30]: P.Harpe etal., ''A 0.20$ $mm$^2$ 3$ $nW signal acquisition IC  for miniature sensor nodes in 65 nm CMOS,'' IEEE J. Solid-State  Circuits, vol.51, no.1, pp. 240--248, Jan 2016.
+[^33]: D.Han etal., ''A 0.45 V 100-channel neural-recording IC with  sub-
+mu w/channel consumption in 0.18
+mu m CMOS,'' IEEE Trans.  Biomed. Circuits Syst., vol.7, no.6, pp. 735--746, Dec 2013.
 [^34]: R.Muller, S.Gambini, and J.M. Rabaey, ''A 0.013 mm	sqrd, 5 W,  DC-coupled neural signal acquisition IC with 0.5 V supply,''  IEEE J. Solid-State Circuits, vol.47, no.1, pp. 232--243, Jan  2012.
 [^15]: A.Bagheri etal., ''Low-frequency noise and offset rejection in  DC-coupled neural amplifiers: A review and digitally-assisted design  tutorial,'' IEEE Trans. Biomed. Circuits Syst., vol.11, no.1, pp.  161--176, Feb 2017.
 [^20]: S.Chatterjee, Y.Tsividis, and P.Kinget, ''0.5-V analog circuit techniques  and their application in OTA and filter design,'' IEEE J.  Solid-State Circuits, vol.40, no.12, pp. 2373--2387, Dec 2005.
-[^33]: D.Han etal., ''A 0.45 V 100-channel neural-recording IC with  sub-
+[^26]: C.C. Enz and E.A. Vittoz, Charge-based MOS transistor modeling: the  EKV model for low-power and RF IC design.\hskip 1em plus 0.5em minus  0.4em
+elax John Wiley & Sons, Aug 2006.
 [^27]: K.-D. Chen and T.-H. Kuo, ''An improved technique for reducing baseband tones  in sigma-delta modulators employing data weighted averaging algorithm without  adding dither,'' IEEE Trans. Circuits Syst. II, vol.46, no.1,  pp. 63--68, Jan 1999.

content/publications/2018/autonomous-soc-for-neural-local-field-potential-recording-in-mm-scale-wireless-implants.md

@@ -52,7 +52,7 @@ This ENGINI prototype has been developed for a 0.35 μ m CMOS technology such th
 This provides a stable power supply for the electronics and back-scatters digitised recordings. The circuit architecture is shown in Fig. 3. This contains a binary weighted capacitor bank C<sub>T<sub>, a passive full wave rectifier, and a sensing circuit which are all digitally-controlled. The principle of operation can be described as follows. First, the cross-coupled rectifier converts the induced AC voltage to a DC power on V<sub>x<sub>. Then, the low voltage amplifier A<sub>2<sub> performs auto-zeroing by shorting C<sub>F<sub> and simultaneously sampling the rectified voltage onto C<sub>I<sub>. After sampling, the parallel binary-weighted capacitor bank C<sub>T<sub> is adjusted to tune or de-tune LC tank on the secondary side. There is therefore a voltage fluctuation at node V<sub>x<sub>. The change in V<sub>x<sub> is amplified 30\\(\times\\) by A<sub>2<sub> which corresponds to the ratio C<sub>I<sub>/C<sub>F<sub>. The polarity of the resulting change is digitised using the comparator, instructing the digital control to add or remove parallel capacitors in the next cycle of regulation. Two supply voltage level indicators from the biasing circuit further assist this feedback to increase or reduce the supply voltage and whether to perform LSK respectively. The resistor R<sub>z<sub> is added after the output of rectifier such that the speed at which V<sub>X<sub> can be controlled is not dependent on the load capacitance C<sub>L<sub> which may be quite large. This allows fast regulation with a clock speed of 846 kHz at the cost of some reduction in power efficiency due to the voltage drop from V<sub>X<sub> to V<sub>DD<sub>.
 
 {{< figure src="/images/biocas2017/REG.svg" title="Figure 3: Adaptive power conversion and regulation circuit using full-wave rectifier, tunable LC tank, auto-zeroing amplifier and strong arm comparator" width="500" >}}
-%
+
 
 ## 6  \\(\Delta\Sigma\\) Instrumentation Circuit
 
@@ -61,7 +61,7 @@ This provides a stable power supply for the electronics and back-scatters digiti
 The instrumentation circuit used to acquire the electrode recordings is based on the time-domain \\(\Delta\Sigma\\) modulator in [^11]. This uses differential oscillators as the integration element with an asynchronous signal quantizer. However the implementation presented here introduces an additional Gm-C integrator and a feed-forward path to realise second-order noise shaping. This reduces the oversampling ratio (OSR) requirement and substantially increases the dynamic range of the system. A single-ended equivalent of the fully-differential structure used here is shown in Fig. 4.
 
 {{< figure src="/images/biocas2017/SDM.svg" title="Figure 4: Simplified equivalent of the second-order \\(\Delta\Sigma\\) modulator using time-domain signal quantization exhibiting a bandpass response due to the switched current DAC which removes any electrode offset." width="500" >}}
-%
+
 
 Note that this is a DC-coupled configuration where the analogue node V<sub>O<sub> tracks the electrode potential. An electrode offset larger than \\(\pm\\)100 mV can be accommodated without saturating the modulator by adding the digitally switched and duty cycled current in the feedback path. The quantized signal Q is AC coupled onto V<sub>O<sub> with a relatively large attenuation factor due to capacitive division α=1/(C<sub>0<sub>/C<sub>C<sub>+1) which will allow the in-band signal gain. This can be confirmed using the small signal model for this circuit described in Eq. 1-4 where H(s) represents the second-order loop filter and C(s) the charge pump with capacitive feed-forward. The factor k1=OSR f<sub>smp<sub>/2 reflects the modulator bandwidth in terms of the target sampling frequency f<sub>smp<sub>. The factor k2=2\\(\pi\\) f<sub>hp<sub> represents the integration constant of the charge pump in terms of the high-pass cut-off frequency f<sub>hp<sub>. This approach is inspired by the first order modulator in [^12]. The implemented circuit uses an OSR of 64, a 1 Hz high-pass corner frequency, and third order CIC filter to decimate the output. This leads to the noise and signal transfer functions shown in Fig. 5.
 
@@ -118,7 +118,7 @@ Table 1: System Characteristics and Comparison with State-of-the-Art
 
 # 9 Conclusion
 
-This work demonstrates a compact system on chip architecture for LFP based recording systems that aims to distribute several implantable probes into the cortical tissue in a scalable fashion by relying on autonomous sensor operation. Using the resonant tuning for supply regulation and \\(\Delta\Sigma\\) modulator instrumentation has lead to a significant reduction in system complexity typically seen in BMI SoCs. Moreover this configuration is able to operate at high efficiency without much constraint on technology requirements since the overall system power budget is estimated to be 80 μ W from preliminary simulation results. The approach to brain machine interfaces presented here will lead to safer and simpler systems while delivering high fidelity multi-electrode recordings which is essential for applications in a clinical environment.%
+This work demonstrates a compact system on chip architecture for LFP based recording systems that aims to distribute several implantable probes into the cortical tissue in a scalable fashion by relying on autonomous sensor operation. Using the resonant tuning for supply regulation and \\(\Delta\Sigma\\) modulator instrumentation has lead to a significant reduction in system complexity typically seen in BMI SoCs. Moreover this configuration is able to operate at high efficiency without much constraint on technology requirements since the overall system power budget is estimated to be 80 μ W from preliminary simulation results. The approach to brain machine interfaces presented here will lead to safer and simpler systems while delivering high fidelity multi-electrode recordings which is essential for applications in a clinical environment.
 
 # 10 Acknowledgement
 

content/publications/2018/direct-digital-wavelet-synthesis-for-embedded-biomedical-microsystems.md

@@ -41,7 +41,9 @@ The rest of this paper if organised as follows: Sec 3 will introduce a recurrent
 
 There are a number of recursive oscillator topologies available in the literature with two identifiable basis; biquads and waveguides[^9]. The feed-forward structure proposed here is derived from the standard coupled quadrature structure that provides feedback with equi-amplitude quadrature outputs. This structure is shown in Fig. 2a. The feed-forward configuration uses two integrators in negative feedback with two coefficients f and k to specify frequency and Q-factor respectively. This will require the same number of coefficient multiplications as the coupled quadrature configuration but uses 4 2-input summation nodes opposed to 2. The benefit here is that there are only 2 scaling coefficients and they are linearly dependent on the desired oscillation frequency. The conventional structure has f²\:dependence that requires excessive integrator precision to accurately resolve very small frequencies typically of interest for biomedical signals.
 
-$$ 	\begin{bmatrix}\hat{x}_Q \hat{x}_I\end{bmatrix} =\underbrace{\begin{bmatrix}(1-k f) & -f f & (1-k f)\end{bmatrix}}_{\mathbf{R}(k,f)}\cdot\begin{bmatrix}x_Q x_I\end{bmatrix} $$
+$$ 	\begin{bmatrix}\hat{x}_Q \hat{x}_I\end{bmatrix} = \mathbf{R}(k,f) \cdot\begin{bmatrix}x_Q x_I\end{bmatrix} $$
+
+$$ \mathbf{R}(k,f) = \begin{bmatrix}(1-k f) & -f \\\\ f & (1-k f)\end{bmatrix} $$
 
 Digital oscillators are usually characterised in terms of a rotation matrix \\(\mathbf{R}\\)(k,f) that is applied to two state variables x<sub>Q<sub> and x<sub>I<sub>. This representation is formulated in Eq. 1. For clarity the k²\: factor is ignored in this analysis since it yields a simpler solution to the basic feed-forward configuration. In this case we are interested in manipulating the pole location adaptively which is why we will solve for the complex pole positions of this dynamic system below.
 
@@ -55,7 +57,7 @@ $$ 	\begin{split}poles\left(\frac{1}{1+D_O(z)}\right) = 1 - k f \pm √{ f^2 k^2
 
 Finding the poles yields the two solutions in Eq. 4 that correspond to the complex pair P\tss{Q/I} which dictate the oscillatory behaviour of this circuit. This reveals the behaviour shown in Fig. 2b which is that adjusting k will rotate the pole-pair in and out of the unit circle resulting in a growing or receding complex exponential or oscillation. It is also readily seen that for the case k=0 the pole locations lie outside the unit circle. Solving for a steady state solution where P\tss{Q/I} are on the unit circle gives k=f/2.
 
-# 4 DDWS Core]{\\(\Delta\Sigma^2\\) type DDWS Core
+# 4 DDWS Core \\(\Delta\Sigma^2\\) type DDWS Core
 
 In order to realise the proposed multiplier-free DDWS, two additional components will be introduced. The first is a second order digital ΔΣ \: modulator that will allow us to mitigate the need to for high-precision multipliers and the second is a controller module that will regulate the dynamic oscillatory behaviour given a set input parameters. This configuration is shown in Fig. 3 together with sub-blocks for amplitude tracking and noise shaping.
 
@@ -65,26 +67,7 @@ Introducing a ΔΣ \: modulator is a well established means reduce hardware comp
 
 The block diagram in Fig. 3 also includes logic for tracking the peak to peak amplitude of the internal oscillation. This is done by detecting zero-crossings of either integrator and latching the other that will at that moment be at the peak amplitude. The oscillation amplitude is used to control the dynamics of the wavelet generator and prevents saturation.
 
-\begin{algorithm}
-	\DontPrintSemicolon
-	\KwIn{Wavelet synthesis parameters (f, c<sub>bw<sub>, ic, vpp)}
-	\KwResult{Quadrature bit-streams (D1\tss{Q/I}, D2\tss{Q/I})}
-	**Initialise:** x1<sub>Q<sub>=ic, x1<sub>I<sub>=0, x2<sub>Q<sub>=vpp/2, x2<sub>I<sub>=0, s1=c<sub>bw<sub>, s2=-c<sub>bw<sub>
-	\Begin{
-		\ShowLn
-		k1 = 0.5 + s1(D1<sub>PP<sub> - vpp)
-		k2 = 0.5 + s2(D2<sub>PP<sub> - vpp)
-		\\(\mathbf{x1}\\)\tss{Q/I}[n] = \\(\mathbf{R}\\)(k1,f) \\(\cdot\\) \\(\mathbf{x1}\\)\tss{Q/I}[n-1]
-		\\(\mathbf{x2}\\)\tss{Q/I}[n] = \\(\mathbf{R}\\)(k2,f) \\(\cdot\\) \\(\mathbf{x2}\\)\tss{Q/I}[n-1]
-		\uIf{ D1<sub>PP<sub> \textgreater   vpp **or** $|\\(k1\\)|$ \textless   c<sub>bw<sub>/2}{s1=-c<sub>bw<sub>}
-		\ElseIf{ D1<sub>PP<sub> \textless   ic **and** s2\textless0 }{s1=c<sub>bw<sub>}
-		\uIf{ D2<sub>PP<sub> \textgreater   vpp **or** $|\\(k2\\)|$ \textless   c<sub>bw<sub>/2}{s2=-c<sub>bw<sub>}
-		\ElseIf{ D2<sub>PP<sub> \textless   ic **and** s1\textless0 }{s2=c<sub>bw<sub>}
-	}
-	\BlankLine
-	\caption{DDWS Controller}
-	\label{algo:ddws-control}
-\end{algorithm}
+
 
 An overview of the control logic is described in Alg. 1. Here the notation from Eq. 1 is used to simplify how the oscillator states evolve by using the rotation matrix. In the behavioural implementation lines 5-6 are realised by a series of conditional statements that increment/decrement the oscillator states \\(\mathbf{x}\\)\tss{Q/I} and then compute the feed forward value by adding or subtracting k1/k2. Notice that we use the state variable s1/s2 to iteratively make sure only one oscillator is growing in amplitude while the other is shrinking in amplitude but at all times the growth is bounded by how close the peak to peak value is to the target maximum vpp. In fact several configurable parameters are used here in addition to vpp to specify the wavelet dynamics. Like before f controls the oscillation frequency in rads per second. The parameter ic determines the extinction ratio between the minimum and maximum oscillation amplitudes and c<sub>bw<sub> controls the window bandwidth together with ic to allow high or low out-of-band rejection.
 

content/publications/2019/a-68-rmu-w-31-ks-s-fully-capacitive-noise-shaping-sar-adc-with-102-db-sndr.md

@@ -49,9 +49,10 @@ $$  QNP \approx \underbrace{\left( V^2_{DD} e^{-3\tau} + \frac{V^2_{DD}}{2^{2N}}
 
 The expression in Eq. 2 parametrises the overall SAR resolution as N, the loop fillter order as M, and the number of time constants we allow the capacitive DAC to settle as τ \:in order to estimate QNP. This construction shows that settling and quantisation errors are shaped by the loop filter reducing the noise power by the term outside the brackets. Both in Fig. 3 and in the formulation we observe a strong dependency with regard to M as long as we provide sufficient settling time during SAR conversion. This result suggests that the noise-shaping feed-back must avoid driving the capacitive DAC with active amplifiers during successive-approximation to avoid slowing down the conversion speed or equivalently increasing the power requirement of each amplifier. We can also confirm here that the order of the loop filter does not need to be very high if the QNP needs to match the SNP.
 
-$$  MNP \approx \underbrace{\left( \frac{\pi^2 2^{-2D}}{3 \cdot 2^K   OSR^3} + \frac{\pi^{2E} 2^{-2K}}{(1+2E) OSR^{1+2E}} \right)}_{\text{DWA-MSB + MES-LSB DAC}} \frac{\sigma^2   V^2_{DD}}{3} $$
+$$  MNP \approx \Delta^2 \underbrace{ \left( \frac{\pi^2 2^{-2D}}{3 \cdot 2^K   OSR^3} + \frac{\pi^{2E} 2^{-2K}}{(1+2E) OSR^{1+2E}} \right) }_{\text{DWA-MSB + MES-LSB DAC}} $$
 
-The MNP is evaluated in Eq. 3 with respect to the MES noise shaping order E, the number of bits D used to calibrate each capacitor in the MSB DAC in an idealised way. K represents the MSB DAC resolution in bits. Using a capacitor standard deviation \\(\sigma=0.5%\\) and K=4, the MNP of several configurations is shown in Fig. 4. The observation here is that for small OSR values the mismatch noise is typically dominated by the MSB DAC as the mismatch is not sufficiently shaped. It is relatively expensive to increase the number of elements in the MSB DAC since the scaling is linear and increasing the OSR diminishes the advantage of performing SAR. Instead we propose to calibrate the 15 capacitors in the MSB section as D will reduce the MNP more efficiently. The mismatch from the LSB section contains many more elements and is more effectively shaped using a second-order MES technique.
+The MNP is evaluated in Eq. 3 with respect to the MES noise shaping order E, the number of bits D used to calibrate each capacitor in the MSB DAC in an idealised way. K represents the MSB DAC resolution in bits. 
+\\( \Delta^2 = \frac{\sigma^2 V^2_{DD}}{3}\\) represents the the capacitor mismatch power using a standard deviation \\(\sigma=0.5%\\) and K=4, the MNP of several configurations is shown in Fig. 4. The observation here is that for small OSR values the mismatch noise is typically dominated by the MSB DAC as the mismatch is not sufficiently shaped. It is relatively expensive to increase the number of elements in the MSB DAC since the scaling is linear and increasing the OSR diminishes the advantage of performing SAR. Instead we propose to calibrate the 15 capacitors in the MSB section as D will reduce the MNP more efficiently. The mismatch from the LSB section contains many more elements and is more effectively shaped using a second-order MES technique.
 
 The above trends are used to optimise the FOM<sub>S<sub> in a similar fashion to [^3] by correlating hardware requirements with power and accuracy estimators for several configurations. Given an initial 18 bit target precision, we propose the following configuration: CT=50 pF, M=2,τ=5, K=5, D=4, E=2 with the OSR set to 16 to ease the decimation effort.
 
@@ -117,7 +118,8 @@ This works presents a 17 bit Noise Shaping SAR ADC with reduced oversampling rat
 
 # Refernces:
 
-[^11]: S.Pavan, R.Schreier, and G.C. Temes, Understanding Delta-Sigma Data  Converters.\hskip 1em plus 0.5em minus 0.4em
+[^11]: S.Pavan, R.Schreier, and G.C. Temes, Understanding Delta-Sigma Data  Converters.\hskip 1em plus 0.5em minus 0.4em
+elax IEEE, 2017. [Online]:  http://dx.doi.org/10.1002/9781119258308
 [^12]: R.Schreier, J.Silva, J.Steensgaard, and G.C. Temes, ''Design-oriented  estimation of thermal noise in switched-capacitor circuits,'' IEEE  Trans. Circuits Syst. I, vol.52, no.11, pp. 2358--2368, Nov 2005.  [Online]: http://dx.doi.org/10.1109/TCSI.2005.853909
 [^10]: M.Aboudina and B.Razavi, ''A new DAC mismatch shaping technique for  sigma–delta modulators,'' IEEE Trans. Circuits Syst. II,  vol.57, no.12, pp. 966--970, Dec 2010. [Online]:  http://dx.doi.org/10.1109/TCSII.2010.2083172
 [^13]: J.Liu, G.Wen, and N.Sun, ''Second-order DAC MES for SAR ADCs,''  IET Elec. Letters, vol.53, no.24, pp. 1570--1572, 2017. [Online]:  http://dx.doi.org/10.1049/el.2017.3138
@@ -126,7 +128,8 @@ This works presents a 17 bit Noise Shaping SAR ADC with reduced oversampling rat
 [^5]: A.AlMarashli, J.Anders, J.Becker, and M.Ortmanns, ''A nyquist rate SAR  ADC employing incremental sigma delta DAC achieving peak SFDR=107 dB  at 80 kS/s,'' IEEE J. Solid-State Circuits, vol.53, no.5, pp.  1493--1507, May 2018. [Online]:  http://dx.doi.org/10.1109/JSSC.2017.2776299
 [^4]: I.Jang etal., ''A 4.2 mW 10 MHz BW 74.4 dB SNDR  continuous-time delta-sigma modulator with SAR-assisted digital-domain  noise coupling,'' IEEE J. Solid-State Circuits, vol.53, no.4, pp.  1139--1148, April 2018. [Online]:  http://dx.doi.org/10.1109/JSSC.2017.2778284
 [^3]: L.B. Leene and T.G. Constandinou, ''A 0.016 mm	sqrd 12 b $\Delta\Sigma$  SAR with 14 fJ/conv. for ultra low power biosensor arrays,''  IEEE Trans. Circuits Syst. I, vol.64, no.10, pp. 2655--2665, Oct  2017. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2703580
-[^3]: L.B. Leene and T.G. Constandinou, ''A 0.016 mm	sqrd 12 b $\Delta\Sigma$  SAR with 14 fJ/conv. for ultra low power biosensor arrays,''  IEEE Trans. Circuits Syst. I, vol.64, no.10, pp. 2655--2665, Oct  2017. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2703580
+[^1]: Y.Chae, K.Souri, and K.A.A. Makinwa, ''A 6.3
+mu W 20 bit incremental  zoom-ADC with 6 ppm INL and 1 mu V offset,'' IEEE J.  Solid-State Circuits, vol.48, no.12, pp. 3019--3027, Dec 2013. [Online]:  http://dx.doi.org/10.1109/JSSC.2013.2278737
 [^16]: S.Choi etal., ''An 84.6 dB-SNDR and 98.2 dB-SFDR  residue-integrated SAR ADC for low-power sensor applications,''  IEEE J. Solid-State Circuits, vol.53, no.2, pp. 404--417, Feb  2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2774287
 [^2]: Y.Shu, L.Kuo, and T.Lo, ''An oversampling SAR ADC with DAC mismatch  error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz  BW in 55 nm CMOS,'' IEEE J. Solid-State Circuits, vol.51,  no.12, pp. 2928--2940, Dec 2016. [Online]:  http://dx.doi.org/10.1109/JSSC.2016.2592623
 [^7]: J.A. Fredenburg and M.P. Flynn, ''A 90 MS/s 11 MHz bandwidth 62 dB  SNDR noise-shaping SAR ADC,'' IEEE J. Solid-State Circuits,  vol.47, no.12, pp. 2898--2904, Dec 2012. [Online]:  http://dx.doi.org/10.1109/JSSC.2012.2217874

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