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fix on several equations
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Lieuwe Leene
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@ -2,3 +2,5 @@
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# Generated files by hugo
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public/
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resources/_gen
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.hugo*
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.fig/
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@ -71,7 +71,7 @@ $$ P(x) = (x-p_1) (x-p_2) (x-p_3) ... (x-p_n) $$
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$$ P(x) = a_n x^n + ... + a_2 x^2 + a_1 x + a_0 $$
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We can back calculate the corresponding initial conditions for our cascade
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of integrators by considering the super-position of each component $a_n$
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of integrators by considering the super-position of each component \\(a_n\\)
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seperately. Lets denote our initial conditions as \\( c_n + ... + c_2 + c_1 + c_0 \\)
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for our Nᵗʰ order polynomial. As shown in the diagram above the coefficient
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\\(c_n\\) is directly accumulated on the left most integrator. It should be obvious
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@ -82,19 +82,20 @@ contribution from \\(a_2\\) on the 2nd order derivative is calculated as taking
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the 2nd derivative of \\(P(x)\\) and evaluating its value with x=0 which gives
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us \\(c_2 = 2 * a_2\\). Now equating the 1st derivative from \\(a_2\\)
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similarly gives \\(c_1 = a_2\\) and finally \\(c_0 = 0\\). If there were lower
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order terms, the contribution from a_1 for example would be calculated
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order terms, the contribution from \\(a_1\\) for example would be calculated
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independently and added together.
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This was a simpler example but one can reason that if the mapping for a particular \\( a_n \\) is
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\\( m_n, ... , m_1, m_0 \\) such that for all \\( n \\) the initial conditions are
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\\(c_n = m_n a_n\\). Then for some given mapping of a Nᵗʰ order polynomial
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\\( m(n,i), ... , m(n,1), m(n,0) \\) such that for all \\( i \\) the initial conditions are
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\\(c_n = \sum^n_{i=0} m(n,i) * a_i\\). The final value for the initial condition \\(c_n\\) is then
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sum of all mapping terms from each \\(a_n\\). Then for some given mapping of a Nᵗʰ order polynomial
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we can add one more integration stage to the far right integrating the output
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to realize a N+1ᵗʰ order polynomial. This is equivalent to multiplying the
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response with \\( x + 1 \\). Now it should be clear that when we equate the
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derivative terms the N+1ᵗʰ order terms can be derived from the Nᵗʰ order terms
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simply by adding the appropriate contributions after the aforementioned
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multiplication. That is \\( k_n = m_n + m_{n-1} \\) where \\( k_n \\) are the
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mapping terms for the N+1ᵗʰ order polynomial.
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multiplication. That is \\( m(n+1,i) = m(n,i) + m(n,i-1) \\) where \\( m(n+1,i) \\)
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are the mapping terms for the N+1ᵗʰ order polynomial.
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Interestingly the mapping here generates a set of basis coefficients related to
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the sterling-numbers of the second kind. More specifically the
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[A019538](https://oeis.org/A019538) sequence. Using python and numpy as np
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@ -122,7 +123,7 @@ def mapping_coefficients(order: int) -> np.array:
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```
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This function will derive the \\( m_n \\) mapping values based on our recursive
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This function will derive the \\( m(n,i) \\) mapping values based on our recursive
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derivation above. In order to then determine the initial conditions we similarly
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iterate over the characteristic coefficients \\( a_n \\) and accumulate all
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contributions to resolve the initial conditions \\( c_n \\).
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@ -49,17 +49,17 @@ This section introduces the operating principle and circuit dynamics of the prop
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A block diagram of the proposed architecture is detailed in Fig. 2a. For clarity, this shows the single ended equivalent of the fully differential circuit that was implemented. The difference in potential between two electrode inputs V<sub>R<sub> & V<sub>IN<sub> is chopped at the chopper frequency f<sub>chp<sub> to generate a up-modulated voltage waveform that couples the input onto V<sub>X<sub> through C<sub>I<sub>. The essential mechanism here is that signals appearing on V<sub>X<sub> induce a current that feeds into two oscillators with different polarities after being demodulated. This current forces the oscillators accumulate a relative phase difference because the phase is dependent on the integral of injected current [^19]. This phase difference is then evaluated for each oscillator tap using XOR logic to yield multiple time-encoded PWM signals that can also be chopped using digital logic. The resulting digital signal is capacitively coupled onto V<sub>X<sub> in parallel to close the loop. This is the main signal amplifying path that realises a first-order asynchronous ΔΣ modulator and this sense using N phase detectors in parallel represents asynchronous quantization of the phase difference with a resolution of log<sub>2<sub>(1+N) bits. Using this interpretation we can construct the corresponding analytical model that is shown in Fig. 2b and will assist in deducing the design's parameter dependencies.
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$$ H(s) = \frac{ 1 }{ s / k_1 + N f } \approx \frac{1}{s\cdot \frac{N C_{gate} V_{RG}}{Gm}+\frac{C_F}{C_I}\frac{C_U}{C_U+\:\:\text{\makebox[-3pt][l]{\\(\nearrow\\)}}C_G/N}} $$
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$$ H(s) =\frac{ 1 }{ s / k_1 + N f } \approx \frac{1}{s \cdot \frac{N C_{gate} V_{RG}}{Gm}+\frac{C_F}{C_I}\frac{C_U}{C_U + C_G/N}} $$
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$$ f = {\frac{C_F}{C_{I}+C_{F}}} \cdot \frac{N C_{U}}{C_{F}+N C_{U}+ \text{\makebox[-3pt][l]{\\(\nearrow\\)}}C_{G}} $$
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$$ f = {\frac{C_F}{C_{I}+C_{F}}} \cdot \frac{N C_{U}}{C_{F}+N C_{U}+C_{G}} $$
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First the expression in Eq. 1 can be derived to characterise the signal amplifying loop. The feedback factor \\(f\\) evaluated in Eq. 2 corresponds to the capacitive coupling of a particular PWM phase Q on to V<sub>X<sub> with respect to the capacitors C<sub>I<sub>, C<sub>F<sub>, C<sub>G<sub>, C<sub>U<sub>. In this case C<sub>G<sub> can be digitally tuned to provide varying gain settings (41-53 dB). The oscillator's integration factor k<sub>1<sub> is derived by evaluating the impulse sensitivity function (ISF). The ISF captures how the oscillator phase is affected as a function of charge being injected into the virtual supply of the oscillator V<sub>R<sub> [^19]. Following the derivation for Eq. 2 in [^11] this factor can be assumed constant and is simply dependent on the transconductance Gm, loading capacitance of each delay stage C<sub>gate<sub>, and the voltage across the oscillator V<sub>RG<sub> such that k<sub>1<sub>=Gm/(N C<sub>gate<sub> V<sub>RG<sub>).
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The second control loop is used to reject near-DC aggressors that will appear at the input of the main transconductor. Chopping will prevent the input-referred noise profile from being corrupted by flicker noise but in turn several large tones will appear at harmonics of f<sub>chp<sub> because off-set is being up-modulated. Moreover because this structure is not providing narrowband amplification the feedback must actively suppress these tones to avoid the output from being saturated and distorted. These components are integrated with a gain of approximately A<sub>ripple<sub>=k<sub>1<sub>/f<sub>chp<sub> which induces a 90\\(^\circ\\) phase shift. The phase-shift can be corrected for by using the chopper clock that is delayed by 1/4<sup>th<sup> of the period when demodulating Q to recover the off-set. The flicker rejection further depends on the transfer function F(s) which represents how the recovered signal is smoothed and fed back onto V<sub>X<sub>. Using a charge pump in addition to the pseudo-resistor R<sub>P<sub> will yield an expression for F(s) according to Eq. 3 where C<sub>L<sub> and I\tss{Δ} represent the main integration capacitor and charge pump bias current respectively. This is also shown in Fig. 2.
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The second control loop is used to reject near-DC aggressors that will appear at the input of the main transconductor. Chopping will prevent the input-referred noise profile from being corrupted by flicker noise but in turn several large tones will appear at harmonics of f<sub>chp<sub> because off-set is being up-modulated. Moreover because this structure is not providing narrowband amplification the feedback must actively suppress these tones to avoid the output from being saturated and distorted. These components are integrated with a gain of approximately A<sub>ripple<sub>=k<sub>1<sub>/f<sub>chp<sub> which induces a 90\\(^\circ\\) phase shift. The phase-shift can be corrected for by using the chopper clock that is delayed by 1/4<sup>th<sup> of the period when demodulating Q to recover the off-set. The flicker rejection further depends on the transfer function F(s) which represents how the recovered signal is smoothed and fed back onto V<sub>X<sub>. Using a charge pump in addition to the pseudo-resistor R<sub>P<sub> will yield an expression for F(s) according to Eq. 3 where C<sub>L<sub> and I<sub>Δ<sub> represent the main integration capacitor and charge pump bias current respectively. This is also shown in Fig. 2.
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$$ F(s) = \frac{N I_{\Delta}}{s (C_{L} C_{I} R_{P} s + C_{L} + C_{I})} $$
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Combining F(s) and A<sub>ripple<sub> will then predict how the noise aggressors at V<sub>x<sub> are removed. The frequency dependent response in Fig. 3 evaluates this control mechanism at different points in the loop using the following implemented circuit parameters: N=5, f<sub>chp<sub>=75 kHz, C<sub>I<sub>=288 fF, C<sub>G<sub>=69 fF, C<sub>F<sub>=C<sub>U<sub>=14 fF, R<sub>P<sub>=100 MΩ, C<sub>L<sub>=1.6 pF, I\tss{Δ}=5 nA. This shows the influence of noise at the input (e²<sub>flk<sub>) with respect to the ripple at the ATC output and the fluctuations on V<sub>X<sub> as a function of frequency. First notice the increased chopper frequency enables this circuit to increase its bandwidth and reject more of the low-frequency band including common-mode signals that asymmetrically couple onto V<sub>X<sub>. In addition the second order low-pass characteristic provides increased rejection of the chopper and oscillator tones such that the two control loops operate in isolation. A known drawback of increasing f<sub>chp<sub> is the reduction in input impedance but as shown in Sec. 10 this reduction can be mitigated with technology scaling and using a smaller value for C<sub>I<sub>.
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Combining F(s) and A<sub>ripple<sub> will then predict how the noise aggressors at V<sub>x<sub> are removed. The frequency dependent response in Fig. 3 evaluates this control mechanism at different points in the loop using the following implemented circuit parameters: N=5, f<sub>chp<sub>=75 kHz, C<sub>I<sub>=288 fF, C<sub>G<sub>=69 fF, C<sub>F<sub>=C<sub>U<sub>=14 fF, R<sub>P<sub>=100 MΩ, C<sub>L<sub>=1.6 pF, I<sub>Δ<sub>=5 nA. This shows the influence of noise at the input (e²<sub>flk<sub>) with respect to the ripple at the ATC output and the fluctuations on V<sub>X<sub> as a function of frequency. First notice the increased chopper frequency enables this circuit to increase its bandwidth and reject more of the low-frequency band including common-mode signals that asymmetrically couple onto V<sub>X<sub>. In addition the second order low-pass characteristic provides increased rejection of the chopper and oscillator tones such that the two control loops operate in isolation. A known drawback of increasing f<sub>chp<sub> is the reduction in input impedance but as shown in Sec. 10 this reduction can be mitigated with technology scaling and using a smaller value for C<sub>I<sub>.
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{{< figure src="/images/jssc2018/noise_tf.svg" title="Figure 3: The closed loop response of the flicker rejection loop due to input-referred noise e²<sub>flk<sub> evaluated with respect to the ripple magnitude seen at Q (solid), the feedback seen at V<sub>X<sub> (dotted), and the open loop response F(s)\\(\cdot\\)A<sub>ripple<sub> (dashed)." width="500" >}}
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@ -67,22 +67,22 @@ Given these dynamics there is still important distinction to be made with regard
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# 4 Circuit Implementation
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{{< figure src="/images/jssc2018/obi_sch.svg" title="Figure 4: The transistor level implementation of the ATC circuit in Fig. 2a. Here the complementary structure in a) represents the main transconductor; b) represents the pseudo-differential oscillator where each delay cell is shown in c); The flicker rejection stage is shown in d) where only the grey section is replicated for each phase. Note that all devices have their body connected to the corresponding supplies with the exception of M\tss{5-8} which have the body connected to the drain of M<sub>9<sub>. Furthermore M\tss{13-16} and M\tss{21-22} their body connected to V<sub>R<sub> and either terminal of C<sub>L<sub> respectively." width="500" >}}
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{{< figure src="/images/jssc2018/obi_sch.svg" title="Figure 4: The transistor level implementation of the ATC circuit in Fig. 2a. Here the complementary structure in a) represents the main transconductor; b) represents the pseudo-differential oscillator where each delay cell is shown in c); The flicker rejection stage is shown in d) where only the grey section is replicated for each phase. Note that all devices have their body connected to the corresponding supplies with the exception of M<sub>5-8<sub> which have the body connected to the drain of M<sub>9<sub>. Furthermore M\<sub>13-16<sub> and M\<sub>21-22<sub> their body connected to V<sub>R<sub> and either terminal of C<sub>L<sub> respectively." width="500" >}}
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The transistor schematic for the proposed ATC is presented in Fig. 4 and the sizing of each device is listed in Table 1. This circuit can be segmented into four parts corresponding to the transconductor, oscillator, delay stage, and flicker rejection circuit. Each sub-block, including the capacitor array, will be described below. This configuration uses two bias voltages V<sub>BN<sub> & V<sub>BP<sub> to source the annotated drain currents. Both of these voltages are derived on-chip using a simple current mirror structure and a 1 μ A off-chip reference. Furthermore an external reference voltage V<sub>C<sub> is used to control the common mode voltage of V<sub>R<sub> that is placed at V<sub>DD<sub>/2. Note that the 65 nm technology used here provides transistors that can be configured with 150 mV (lvt), 250 mV (vt), and 350 mV (hvt) threshold voltages (V<sub>TH<sub>). The lvt option is used exclusively to reduce the supply voltage to 0.5 V with the exception of M\tss{23-24} which use a 250 mV threshold.
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The transistor schematic for the proposed ATC is presented in Fig. 4 and the sizing of each device is listed in Table 1. This circuit can be segmented into four parts corresponding to the transconductor, oscillator, delay stage, and flicker rejection circuit. Each sub-block, including the capacitor array, will be described below. This configuration uses two bias voltages V<sub>BN<sub> & V<sub>BP<sub> to source the annotated drain currents. Both of these voltages are derived on-chip using a simple current mirror structure and a 1 μ A off-chip reference. Furthermore an external reference voltage V<sub>C<sub> is used to control the common mode voltage of V<sub>R<sub> that is placed at V<sub>DD<sub>/2. Note that the 65 nm technology used here provides transistors that can be configured with 150 mV (lvt), 250 mV (vt), and 350 mV (hvt) threshold voltages (V<sub>TH<sub>). The lvt option is used exclusively to reduce the supply voltage to 0.5 V with the exception of M<sub>23-24<sub> which use a 250 mV threshold.
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Table 1: Device Sizing in micrometers with the labels from Fig. 4
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| Device | Size (W/L) | Device | Size (W/L) |
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|----|----|----|----|
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| M<sub>0<sub> | 26/5 | M\tss{15-16} | 0.2/2.5 |
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| M\tss{1-2} | 16/0.25 | M\tss{17-18} | 2/5 |
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| M\tss{3-4} | 2/1 | M\tss{19-20} | 10/0.2 |
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| M\tss{5-6} | 4/0.5 | M\tss{21-22} | 1.6/0.4 |
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| M\tss{7-8} | 0.8/1.4 | M\tss{23-24} | 0.96/4 |
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| M<sub>0<sub> | 26/5 | M\<sub>15-16<sub> | 0.2/2.5 |
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| M\<sub>1-2<sub> | 16/0.25 | M\<sub>17-18<sub> | 2/5 |
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| M\<sub>3-4<sub> | 2/1 | M\<sub>19-20<sub> | 10/0.2 |
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| M\<sub>5-6<sub> | 4/0.5 | M\<sub>21-22<sub> | 1.6/0.4 |
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| M\<sub>7-8<sub> | 0.8/1.4 | M\<sub>23-24<sub> | 0.96/4 |
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| M<sub>9<sub> | 32/0.1 | Logic | 0.3/0.1 |
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| M<sub>10<sub> | 6/5 | Switch<sub>CHP<sub> | 1/0.1 (P<sub>type<sub>) |
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| M\tss{11-12} | 1.5/2.4 | Switch<sub>X<sub> | 1/0.2 (N<sub>type<sub>) |
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| M\tss{13-14} | 2.3/2.5 | C<sub>L<sub> | 21/21 |
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| M\<sub>11-12<sub> | 1.5/2.4 | Switch<sub>X<sub> | 1/0.2 (N<sub>type<sub>) |
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| M\<sub>13-14<sub> | 2.3/2.5 | C<sub>L<sub> | 21/21 |
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## 5 Low-Noise Transconductor
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@ -98,7 +98,7 @@ The main feature of the oscillators (Fig. 4b) used by this ATC is that it uses d
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## 7 Flicker Rejection Stage
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The flicker removal circuit (Fig. 4d) biases the input of the transconductor by feeding back common mode and differential mode signals using a cross coupled load to enable low voltage operation without an additional common-mode-feedback circuit[^20]. The differential feedback provides flicker cancellation by demodulating the digital output using a switched current DAC that integrates on C<sub>L<sub> which is a large vertical metal-insulator-metal (MIM) capacitor placed over the analogue circuitry. The diode connected devices M\tss{21-22} represent pseudo-resistors of 100 MΩ that provide a resistive path to V<sub>X<sub> and further smooths high frequency tones from f<sub>chp<sub> and f<sub>osc<sub>. A significant variation in resistive value is inherently expected but it is important to note that it does not influence the signal amplifying path and the non-dominant poles are far away from the 8 kHz bandwidth of F(s) in Eq. 3 by virtue of not using a second analogue integrator that may compromise stability. The common mode feedback regulates V<sub>R<sub> with respect to V<sub>C<sub> by biasing the common mode of V<sub>X<sub>. For this loop the gain arises from transconductance ratio gm\tss{M19-M20}/gm\tss{M23-M24} together with the drain resistance ratio rds<sub>M10<sub>/(rds<sub>M0<sub>+rds<sub>M9<sub>). This readily provides over 30 dB of gain with the dominant pole provided by the pseudo-resistors that will also attenuate the input common mode signals.
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The flicker removal circuit (Fig. 4d) biases the input of the transconductor by feeding back common mode and differential mode signals using a cross coupled load to enable low voltage operation without an additional common-mode-feedback circuit[^20]. The differential feedback provides flicker cancellation by demodulating the digital output using a switched current DAC that integrates on C<sub>L<sub> which is a large vertical metal-insulator-metal (MIM) capacitor placed over the analogue circuitry. The diode connected devices M<sub>21-22<sub> represent pseudo-resistors of 100 MΩ that provide a resistive path to V<sub>X<sub> and further smooths high frequency tones from f<sub>chp<sub> and f<sub>osc<sub>. A significant variation in resistive value is inherently expected but it is important to note that it does not influence the signal amplifying path and the non-dominant poles are far away from the 8 kHz bandwidth of F(s) in Eq. 3 by virtue of not using a second analogue integrator that may compromise stability. The common mode feedback regulates V<sub>R<sub> with respect to V<sub>C<sub> by biasing the common mode of V<sub>X<sub>. For this loop the gain arises from transconductance ratio gm\<sub>M19-M20<sub>/gm\<sub>M23-M24<sub> together with the drain resistance ratio rds<sub>M10<sub>/(rds<sub>M0<sub>+rds<sub>M9<sub>). This readily provides over 30 dB of gain with the dominant pole provided by the pseudo-resistors that will also attenuate the input common mode signals.
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## 8 Capacitive Feedback Network
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@ -128,27 +128,27 @@ Eq. 6 calculates the expected input resistance and provides a first order estima
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Mismatch due to process variation is the primary cause of distortion during multi-bit signal conversion. Minimising this source of nonlinearity is essential for both synchronous and asynchronous ΔΣ modulators because mismatch in the feedback DAC is not shaped by the loop filter [^27]. Fortunately the modulating property of the oscillator can remove this distortion if the phase readout is performed in a parallel fashion [^5]. Here we will concisely demonstrate that property arises because the mismatch induced components are simply being averaged and induce a DC-offset together with tones at the harmonic components of f<sub>osc<sub>. This uses a mapping that relates the phase difference \\(x\\) to the generated PWM waveform as a function of time \\(\tau\\) defined in Eq. 7. The following expression in Eq. 8 then evaluates the analogue feedback voltage that appears on V<sub>X<sub> in the ideal case for a given a phase difference of Δφ between the two oscillators.
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$$ A(\tau,x) \triangleq\begin{cases} 1 & \tau (mod\: 1) \: < \:x 0 & \text{otherwise} \end{cases} $$
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$$ A(\tau,x) \triangleq \begin{cases} 1 & \tau ( mod 1 ) < x \\\\ 0 & \text{otherwise} \end{cases} $$
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$$ V_{X}(t) = f \cdot \sum_{k=0}^{N-1} \underbrace{A( t \cdot f_{osc}+\frac{k}{N}\:,\: \Delta \phi )}_{Q_{k}(t)} $$
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$$ V_{X}(t) = f \cdot \sum_{k=0}^{N-1} \underbrace{ A \left( t \cdot f_{osc}+\frac{k}{N} , \Delta \phi \right)}_{ Q_k(t) } $$
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$$ Q_{k}(t) = (1+\frac{\sigma_{C,k}}{C_U}) A( t \cdot f_{osc} + \frac{k}{N} \: , \: \sigma_{\tau-\mu,k} + \Delta \phi) $$
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$$ Q_{k}(t) = (1+\frac{\sigma_{C,k}}{C_U}) A( t \cdot f_{osc} + \frac{k}{N} , \sigma_{\tau-\mu,k} + \Delta \phi) $$
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There are two independent sources of mismatch for each phase: the deviation in capacitor weights of C<sub>U<sub> σ<sub>C,k<sub> and the differential delay variation in oscillator stages as a fraction of the oscillation period σ\tss{τ,k} that includes the digital gates generating Q (i.e. inverters and XOR-gate). These are used to formulate Eq. 9 which considers a particular phase of Q(t) and the random mismatch variables that have process dependent normal distributions. The variation in delay will locally increase/decrease the pulse-width of Q for a specific phase \\(k\\). This is a time-invariant component of the gate delay while Δφ and T<sub>osc<sub> are signal dependent. Precisely formulating the cumulative variation of σ\tss{τ} will relate the transistor sizing, gate capacitance, and threshold voltage of each delay during operation.
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There are two independent sources of mismatch for each phase: the deviation in capacitor weights of C<sub>U<sub> σ<sub>C,k<sub> and the differential delay variation in oscillator stages as a fraction of the oscillation period σ<sub>τ,k<sub> that includes the digital gates generating Q (i.e. inverters and XOR-gate). These are used to formulate Eq. 9 which considers a particular phase of Q(t) and the random mismatch variables that have process dependent normal distributions. The variation in delay will locally increase/decrease the pulse-width of Q for a specific phase \\(k\\). This is a time-invariant component of the gate delay while Δφ and T<sub>osc<sub> are signal dependent. Precisely formulating the cumulative variation of σ<sub>τ<sub> will relate the transistor sizing, gate capacitance, and threshold voltage of each delay during operation.
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Notice that A is a linear function of Δφ with a gain of 1 for the DC component of the PWM output which can be further expanded to extract the high frequency behaviour. However by design these components are intentionally avoided which should reveal that that the capacitor weights are always uniformly averaged irrespective Δφ. Closed-loop operation feeds back each σ\tss{τ,k} such that the sum all components has zero mean, that is σ\tss{τ-μ,k}\ = σ\tss{τ,k}-(\\(\sum_{k=0}^{N-1}\\) σ\tss{τ,k}/N). The residual variation in delay for each phase inevitably induces spurs at at harmonics of f<sub>osc<sub>.
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Notice that A is a linear function of Δφ with a gain of 1 for the DC component of the PWM output which can be further expanded to extract the high frequency behaviour. However by design these components are intentionally avoided which should reveal that that the capacitor weights are always uniformly averaged irrespective Δφ. Closed-loop operation feeds back each σ<sub>τ,k<sub> such that the sum all components has zero mean, that is σ<sub>τ-μ,k<sub>\ = σ<sub>τ,k<sub>-(\\(\sum_{k=0}^{N-1}\\) σ<sub>τ,k<sub>/N). The residual variation in delay for each phase inevitably induces spurs at at harmonics of f<sub>osc<sub>.
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{{< figure src="/images/jssc2018/vco_model.svg" title="Figure 6: A continuous-time multi-phase VCO model for evaluating parameter sensitivity with transient simulations using the logical operator **B** in Eq. 10." width="500" >}}
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Verifying this behaviour is best done by modifying the behavioural model commonly used for oscillators[^28] to accommodate multi-phase readout using the above expressions. Such a model is shown in Fig. 6. This configuration uses an internal time variable at V<sub>T<sub> that accumulates according to f<sub>osc<sub>. Given a set of quantisation levels L<sub>k<sub> or equivalently the number of phases, a logical function **B** will compute the corresponding PWM waveform of Q which are weighted by the associated capacitor C<sub>k<sub>. In this case the digital gate delay arising from computing the phase difference and applying feedback to the capacitive DAC can also be modelled by adjusting τ<sub>dly<sub>.
|
||||
|
||||
$$ \begin{split}\mathbf{B}(\phi_{S},\phi_{R},L) \triangleq & \left(\phi_{S} > L > \phi_{R} \right) \lor \left(\phi_{S} < \phi_{R} < L \right) & \lor \left( L < \phi_{S} < \phi_{R} \right)\end{split} $$
|
||||
$$ \mathbf{B}(\phi_{S},\phi_{R},L) \triangleq \left(\phi_{S} > L > \phi_{R} \right) \lor \left(\phi_{S} < \phi_{R} < L \right) \lor \left( L < \phi_{S} < \phi_{R} \right) $$
|
||||
|
||||
The logical expression in Eq. 10 simply compares the two phases with respect to L and evaluates the digital condition for which the output should be high. This representation implies that the delays correspond to the interval between each level which can be distributed uniformly as L<sub>k<sub>=(0.5+k)/L for integers k from 0 to N-1. By distributing the quantisation levels from 0 to 1 the corresponding delays are inherently normalised to the periodicity of φ\tss{S/R} without explicitly having to compute values with respect to f<sub>osc<sub> even when it is dynamically changing. In addition a difference in oscillator frequency between X\tss{1-2} can also be accommodated by adding a second integrated frequency component to the summation node.
|
||||
The logical expression in Eq. 10 simply compares the two phases with respect to L and evaluates the digital condition for which the output should be high. This representation implies that the delays correspond to the interval between each level which can be distributed uniformly as L<sub>k<sub>=(0.5+k)/L for integers k from 0 to N-1. By distributing the quantisation levels from 0 to 1 the corresponding delays are inherently normalised to the periodicity of φ<sub>S/R<sub> without explicitly having to compute values with respect to f<sub>osc<sub> even when it is dynamically changing. In addition a difference in oscillator frequency between X\<sub>1-2<sub> can also be accommodated by adding a second integrated frequency component to the summation node.
|
||||
|
||||
{{< figure src="/images/jssc2018/dac_mm.svg" title="Figure 7: Simulated output spectrum with a 2.5 kHz input at -6 dB of the full input-range for a equivalent asynchronous flash quantiser with 2.6 bits of resolution and 5 % mismatch in σ\tss{τ,k} and σ<sub>C,k<sub>." width="500" >}}
|
||||
{{< figure src="/images/jssc2018/dac_mm.svg" title="Figure 7: Simulated output spectrum with a 2.5 kHz input at -6 dB of the full input-range for a equivalent asynchronous flash quantiser with 2.6 bits of resolution and 5 % mismatch in σ<sub>τ,k<sub> and σ<sub>C,k<sub>." width="500" >}}
|
||||
|
||||
{{< figure src="/images/jssc2018/dac_mm2.svg" title="Figure 8: Simulated output spectrum with a 2.5 kHz input at -6 dB of the full input-range for a asynchronous VCO quantiser with 2.6 bits of resolution, 300 kHz f<sub>osc<sub> and 5 % mismatch in σ\tss{τ,k} and σ<sub>C,k<sub>." width="500" >}}
|
||||
{{< figure src="/images/jssc2018/dac_mm2.svg" title="Figure 8: Simulated output spectrum with a 2.5 kHz input at -6 dB of the full input-range for a asynchronous VCO quantiser with 2.6 bits of resolution, 300 kHz f<sub>osc<sub> and 5 % mismatch in σ<sub>τ,k<sub> and σ<sub>C,k<sub>." width="500" >}}
|
||||
|
||||
Now the impact of mismatch can be simulated by adding parameter variation in the quantiser levels and the feedback weights (f). The analogous case where the mismatch is not modulated (i.e. f<sub>osc<sub> is 0) loosely corresponds to a flash-based ADC since the phase is simply being compared with N thresholds. The corresponding spectra of the flash quantiser is shown in Fig. 7 and oscillating quantiser is shown in Fig. 8 where we observe the distortion components in different bands of the spectrum.
|
||||
|
||||
@ -196,15 +196,16 @@ Table 2: System Characteristics and Comparison with State-of-the-Art
|
||||
| Technology[nm] | **65** | 40 | 130 | 40 | 40 | 65 | 65 | 90 | 180 | 65|
|
||||
| Modality | **Time** | Time | Volt. | Time | Volt. | Volt. | Volt. | Volt. | Volt. | Mix |
|
||||
| Supply-V[V] | **0.5** | 0.6 | 1.2 | 1.2 | 1.2 | 0.6 | 1 | 1 | 0.45 | 0.5 |
|
||||
| Supply-I[A] | \textbf{2.55 μ} | 5.5 μ | 5.3 μ | 14 μ | 2.5 μ | 3 n | 3.3 μ | 2.8 μ | 2.1 μ | 10 μ |
|
||||
| Supply-I[A] | **2.55 μ** | 5.5 μ | 5.3 μ | 14 μ | 2.5 μ | 3 n | 3.3 μ | 2.8 μ | 2.1 μ | 10 μ |
|
||||
| Bandwidth[Hz] | **11 k** | 150 | 500 | 5 k | 200 | 370 | 8.2 k | 10.5 k | 10 k | 10 k |
|
||||
| Input Range[mVpp] | **4** | 40 | - | 8 | 100 | 25 | 220 | 1 | 1 | 1 |
|
||||
| CMRR[dB] | \textbf{(>)60(^\star)} | 60 | 90 | 97 | - | 60 | (>)80 | (>)45 | 73 | 75 |
|
||||
| CMRR[dB] | **>60** | 60 | 90 | 97 | - | 60 | (>)80 | (>)45 | 73 | 75 |
|
||||
| SFDR[dB] | **60** | 56 | 72 | 70 | 79 | 75 | (>)40 | (>)37 | (>)46 | (>)34 |
|
||||
| Noise Floor[V/\rtxt{Hz}] | **36 n** | 0.6 μ | 46n | 32 n | - | 1.4 μ | 27.5n | 35n | 29n | 100n |
|
||||
| Noise Floor[V/√Hz] | **36 n** | 0.6 μ | 46n | 32 n | - | 1.4 μ | 27.5n | 35n | 29n | 100n |
|
||||
| RMS Noise[μ V<sub>rms<sub>] | **3.8** | 7.8 | 1.1 | 2.3 | 5.2 | 26 | 4.1 | 3.04 | 3.2 μ | 4.9 μ |
|
||||
| Area[mm²] | **0.006** | 0.015 | 0.013 | 0.015 | 0.135 | 0.15 | 0.042 | 0.137 | 0.25 | 0.013 |
|
||||
| NEF / PEF | \textbf{2.2 / 2.4} | 8.1 / 39| 2.9 / 10| 4.7 / 27| 22 / 581| 2.1 / 2.6| 3.2 / 10| 1.9 / 3.6 | 1.57 / 1.1 | 5.99 / 18 |
|
||||
| NEF / PEF | **2.2 / 2.4** | 8.1 / 39| 2.9 / 10| 4.7 / 27| 22 / 581| 2.1 / 2.6| 3.2 / 10| 1.9 / 3.6 | 1.57 / 1.1 | 5.99 / 18 |
|
||||
|
||||
|
||||
|
||||
{{< figure src="/images/jssc2018/breakdown.svg" title="Figure 19: Power and area contributions from each sub-circuit." width="500" >}}
|
||||
@ -230,17 +231,21 @@ The authors would like to thank Dr. Pantelis Georgiou, and the Europractice Adva
|
||||
[^4]: P.Prabha etal., ''A highly digital VCO-based ADC architecture for current sensing applications,'' IEEE J. Solid-State Circuits, vol.50, no.8, pp. 1785--1795, Aug 2015.
|
||||
[^3]: T.Anand, K.A.A. Makinwa, and P.K. Hanumolu, ''A VCO based highly digital temperature sensor with 0.034 $^\circ$C/mV supply sensitivity,'' IEEE J. Solid-State Circuits, vol.51, no.11, pp. 2651--2663, Nov 2016.
|
||||
[^10]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational amplifiers and their application to continuous-time filters in nanoscale CMOS,'' IEEE J. Solid-State Circuits, vol.49, no.12, pp. 2758--2772, Dec 2014.
|
||||
[^23]: L.B. Leene and T.G. Constandinou, ''A 0.5V time-domain instrumentation circuit with clocked and unclocked
Delta
Sigma operation,'' in 2017 IEEE International Symposium on Circuits and Systems (ISCAS), May 2017, pp. 1--4.
|
||||
[^23]: L.B. Leene and T.G. Constandinou, ''A 0.5V time-domain instrumentation circuit with clocked and unclocked
|
||||
Delta
|
||||
Sigma operation,'' in 2017 IEEE International Symposium on Circuits and Systems (ISCAS), May 2017, pp. 1--4.
|
||||
[^12]: Y.Chen etal., ''A continuous-time digital IIR filter with signal-derived timing and fully agile power consumption,'' IEEE J. Solid-State Circuits, vol.53, no.2, pp. 418--430, Feb 2018.
|
||||
[^22]: S.Pavan, ''Analysis of chopped integrators, and its application to continuous-time delta-sigma modulator design,'' IEEE Trans. Circuits Syst. I, vol.64, no.8, pp. 1953--1965, Aug 2017.
|
||||
[^24]: W.S.T. Yan and H.C. Luong, ''A 900-MHz cmos low-phase-noise voltage-controlled ring oscillator,'' IEEE Trans. Circuits Syst. II, vol.48, no.2, pp. 216--221, Feb 2001.
|
||||
[^17]: R.R. Harrison and C.Charles, ''A low-power low-noise CMOS amplifier for neural recording applications,'' IEEE J. Solid-State Circuits, vol.38, no.6, pp. 958--965, June 2003.
|
||||
[^19]: A.Hajimiri and T.H. Lee, ''A general theory of phase noise in electrical oscillators,'' IEEE J. Solid-State Circuits, vol.33, no.2, pp. 179--194, Feb 1998.
|
||||
[^25]: T.Denison etal., ''A 2
muW 100 nV/rtHz chopper-stabilized instrumentation amplifier for chronic measurement of neural field potentials,'' IEEE J. Solid-State Circuits, vol.42, no.12, pp. 2934--2945, Dec 2007.
|
||||
[^25]: T.Denison etal., ''A 2
|
||||
muW 100 nV/rtHz chopper-stabilized instrumentation amplifier for chronic measurement of neural field potentials,'' IEEE J. Solid-State Circuits, vol.42, no.12, pp. 2934--2945, Dec 2007.
|
||||
[^14]: Y.Li, D.Zhao, and W.A. Serdijn, ''A sub-microwatt asynchronous level-crossing ADC for biomedical applications,'' IEEE Trans. Biomed. Circuits Syst., vol.7, no.2, pp. 149--157, April 2013.
|
||||
[^13]: W.Tang etal., ''Continuous time level crossing sampling ADC for bio-potential recording systems,'' IEEE Trans. Circuits Syst. I, vol.60, no.6, pp. 1407--1418, June 2013.
|
||||
[^9]: G.D. Colletta etal., ''A 20 nW 0.25 V inverter-based asynchronous delta-sigma modulator in 130 nm digital CMOS process,'' IEEE Trans. VLSI Syst., vol.25, no.12, pp. 3455--3463, Dec 2017.
|
||||
[^16]: F.M. Yaul and A.P. Chandrakasan, ''A noise-efficient 36 nV/
txtHz chopper amplifier using an inverter-based 0.2 V supply input stage,'' IEEE J. Solid-State Circuits, vol.52, no.11, pp. 3032--3042, Nov 2017.
|
||||
[^16]: F.M. Yaul and A.P. Chandrakasan, ''A noise-efficient 36 nV/
|
||||
txtHz chopper amplifier using an inverter-based 0.2 V supply input stage,'' IEEE J. Solid-State Circuits, vol.52, no.11, pp. 3032--3042, Nov 2017.
|
||||
[^29]: H.Kassiri etal., ''Rail-to-rail-input dual-radio 64-channel closed-loop neurostimulator,'' IEEE J. Solid-State Circuits, vol.52, no.11, pp. 2793--2810, Nov 2017.
|
||||
[^28]: C.C. Kuo etal., ''Fast statistical analysis of process variation effects using accurate PLL behavioral models,'' IEEE Trans. Circuits Syst. I, vol.56, no.6, pp. 1160--1172, June 2009.
|
||||
[^7]: C.C. Tu, Y.K. Wang, and T.H. Lin, ''A low-noise area-efficient chopped VCO-based CTDSM for sensor applications in 40 nm CMOS,'' IEEE J. Solid-State Circuits, vol.52, no.10, pp. 2523--2532, Oct 2017.
|
||||
@ -249,9 +254,12 @@ The authors would like to thank Dr. Pantelis Georgiou, and the Europractice Adva
|
||||
[^32]: T.Yang and J.Holleman, ''An ultralow-power low-noise CMOS biopotential amplifier for neural recording,'' IEEE Trans. Circuits Syst. II, vol.62, no.10, pp. 927--931, Oct 2015.
|
||||
[^21]: S.Mondal and D.A. Hall, ''An ECG chopper amplifier achieving 0.92 NEF and 0.85 PEF with AC-coupled inverter-stacking for noise efficiency enhancement,'' May 2017, pp. 1--4.
|
||||
[^11]: L.B. Leene and T.G. Constandinou, ''Time domain processing techniques using ring oscillator-based filter structures,'' IEEE Trans. Circuits Syst. I, vol.64, no.12, pp. 3003--3012, Dec 2017.
|
||||
[^33]: D.Han etal., ''A 0.45 V 100-channel neural-recording IC with sub-
mu w/channel consumption in 0.18
mu m CMOS,'' IEEE Trans. Biomed. Circuits Syst., vol.7, no.6, pp. 735--746, Dec 2013.
|
||||
[^33]: D.Han etal., ''A 0.45 V 100-channel neural-recording IC with sub-
|
||||
mu w/channel consumption in 0.18
|
||||
mu m CMOS,'' IEEE Trans. Biomed. Circuits Syst., vol.7, no.6, pp. 735--746, Dec 2013.
|
||||
[^34]: R.Muller, S.Gambini, and J.M. Rabaey, ''A 0.013 mm sqrd, 5 W, DC-coupled neural signal acquisition IC with 0.5 V supply,'' IEEE J. Solid-State Circuits, vol.47, no.1, pp. 232--243, Jan 2012.
|
||||
[^15]: A.Bagheri etal., ''Low-frequency noise and offset rejection in DC-coupled neural amplifiers: A review and digitally-assisted design tutorial,'' IEEE Trans. Biomed. Circuits Syst., vol.11, no.1, pp. 161--176, Feb 2017.
|
||||
[^20]: S.Chatterjee, Y.Tsividis, and P.Kinget, ''0.5-V analog circuit techniques and their application in OTA and filter design,'' IEEE J. Solid-State Circuits, vol.40, no.12, pp. 2373--2387, Dec 2005.
|
||||
[^26]: C.C. Enz and E.A. Vittoz, Charge-based MOS transistor modeling: the EKV model for low-power and RF IC design.\hskip 1em plus 0.5em minus 0.4em
elax John Wiley & Sons, Aug 2006.
|
||||
[^26]: C.C. Enz and E.A. Vittoz, Charge-based MOS transistor modeling: the EKV model for low-power and RF IC design.\hskip 1em plus 0.5em minus 0.4em
|
||||
elax John Wiley & Sons, Aug 2006.
|
||||
[^27]: K.-D. Chen and T.-H. Kuo, ''An improved technique for reducing baseband tones in sigma-delta modulators employing data weighted averaging algorithm without adding dither,'' IEEE Trans. Circuits Syst. II, vol.46, no.1, pp. 63--68, Jan 1999.
|
||||
|
||||
@ -52,7 +52,7 @@ This ENGINI prototype has been developed for a 0.35 μ m CMOS technology such th
|
||||
This provides a stable power supply for the electronics and back-scatters digitised recordings. The circuit architecture is shown in Fig. 3. This contains a binary weighted capacitor bank C<sub>T<sub>, a passive full wave rectifier, and a sensing circuit which are all digitally-controlled. The principle of operation can be described as follows. First, the cross-coupled rectifier converts the induced AC voltage to a DC power on V<sub>x<sub>. Then, the low voltage amplifier A<sub>2<sub> performs auto-zeroing by shorting C<sub>F<sub> and simultaneously sampling the rectified voltage onto C<sub>I<sub>. After sampling, the parallel binary-weighted capacitor bank C<sub>T<sub> is adjusted to tune or de-tune LC tank on the secondary side. There is therefore a voltage fluctuation at node V<sub>x<sub>. The change in V<sub>x<sub> is amplified 30\\(\times\\) by A<sub>2<sub> which corresponds to the ratio C<sub>I<sub>/C<sub>F<sub>. The polarity of the resulting change is digitised using the comparator, instructing the digital control to add or remove parallel capacitors in the next cycle of regulation. Two supply voltage level indicators from the biasing circuit further assist this feedback to increase or reduce the supply voltage and whether to perform LSK respectively. The resistor R<sub>z<sub> is added after the output of rectifier such that the speed at which V<sub>X<sub> can be controlled is not dependent on the load capacitance C<sub>L<sub> which may be quite large. This allows fast regulation with a clock speed of 846 kHz at the cost of some reduction in power efficiency due to the voltage drop from V<sub>X<sub> to V<sub>DD<sub>.
|
||||
|
||||
{{< figure src="/images/biocas2017/REG.svg" title="Figure 3: Adaptive power conversion and regulation circuit using full-wave rectifier, tunable LC tank, auto-zeroing amplifier and strong arm comparator" width="500" >}}
|
||||
%
|
||||
|
||||
|
||||
## 6 \\(\Delta\Sigma\\) Instrumentation Circuit
|
||||
|
||||
@ -61,7 +61,7 @@ This provides a stable power supply for the electronics and back-scatters digiti
|
||||
The instrumentation circuit used to acquire the electrode recordings is based on the time-domain \\(\Delta\Sigma\\) modulator in [^11]. This uses differential oscillators as the integration element with an asynchronous signal quantizer. However the implementation presented here introduces an additional Gm-C integrator and a feed-forward path to realise second-order noise shaping. This reduces the oversampling ratio (OSR) requirement and substantially increases the dynamic range of the system. A single-ended equivalent of the fully-differential structure used here is shown in Fig. 4.
|
||||
|
||||
{{< figure src="/images/biocas2017/SDM.svg" title="Figure 4: Simplified equivalent of the second-order \\(\Delta\Sigma\\) modulator using time-domain signal quantization exhibiting a bandpass response due to the switched current DAC which removes any electrode offset." width="500" >}}
|
||||
%
|
||||
|
||||
|
||||
Note that this is a DC-coupled configuration where the analogue node V<sub>O<sub> tracks the electrode potential. An electrode offset larger than \\(\pm\\)100 mV can be accommodated without saturating the modulator by adding the digitally switched and duty cycled current in the feedback path. The quantized signal Q is AC coupled onto V<sub>O<sub> with a relatively large attenuation factor due to capacitive division α=1/(C<sub>0<sub>/C<sub>C<sub>+1) which will allow the in-band signal gain. This can be confirmed using the small signal model for this circuit described in Eq. 1-4 where H(s) represents the second-order loop filter and C(s) the charge pump with capacitive feed-forward. The factor k1=OSR f<sub>smp<sub>/2 reflects the modulator bandwidth in terms of the target sampling frequency f<sub>smp<sub>. The factor k2=2\\(\pi\\) f<sub>hp<sub> represents the integration constant of the charge pump in terms of the high-pass cut-off frequency f<sub>hp<sub>. This approach is inspired by the first order modulator in [^12]. The implemented circuit uses an OSR of 64, a 1 Hz high-pass corner frequency, and third order CIC filter to decimate the output. This leads to the noise and signal transfer functions shown in Fig. 5.
|
||||
|
||||
@ -118,7 +118,7 @@ Table 1: System Characteristics and Comparison with State-of-the-Art
|
||||
|
||||
# 9 Conclusion
|
||||
|
||||
This work demonstrates a compact system on chip architecture for LFP based recording systems that aims to distribute several implantable probes into the cortical tissue in a scalable fashion by relying on autonomous sensor operation. Using the resonant tuning for supply regulation and \\(\Delta\Sigma\\) modulator instrumentation has lead to a significant reduction in system complexity typically seen in BMI SoCs. Moreover this configuration is able to operate at high efficiency without much constraint on technology requirements since the overall system power budget is estimated to be 80 μ W from preliminary simulation results. The approach to brain machine interfaces presented here will lead to safer and simpler systems while delivering high fidelity multi-electrode recordings which is essential for applications in a clinical environment.%
|
||||
This work demonstrates a compact system on chip architecture for LFP based recording systems that aims to distribute several implantable probes into the cortical tissue in a scalable fashion by relying on autonomous sensor operation. Using the resonant tuning for supply regulation and \\(\Delta\Sigma\\) modulator instrumentation has lead to a significant reduction in system complexity typically seen in BMI SoCs. Moreover this configuration is able to operate at high efficiency without much constraint on technology requirements since the overall system power budget is estimated to be 80 μ W from preliminary simulation results. The approach to brain machine interfaces presented here will lead to safer and simpler systems while delivering high fidelity multi-electrode recordings which is essential for applications in a clinical environment.
|
||||
|
||||
# 10 Acknowledgement
|
||||
|
||||
|
||||
@ -41,7 +41,9 @@ The rest of this paper if organised as follows: Sec 3 will introduce a recurrent
|
||||
|
||||
There are a number of recursive oscillator topologies available in the literature with two identifiable basis; biquads and waveguides[^9]. The feed-forward structure proposed here is derived from the standard coupled quadrature structure that provides feedback with equi-amplitude quadrature outputs. This structure is shown in Fig. 2a. The feed-forward configuration uses two integrators in negative feedback with two coefficients f and k to specify frequency and Q-factor respectively. This will require the same number of coefficient multiplications as the coupled quadrature configuration but uses 4 2-input summation nodes opposed to 2. The benefit here is that there are only 2 scaling coefficients and they are linearly dependent on the desired oscillation frequency. The conventional structure has f²\:dependence that requires excessive integrator precision to accurately resolve very small frequencies typically of interest for biomedical signals.
|
||||
|
||||
$$ \begin{bmatrix}\hat{x}_Q \hat{x}_I\end{bmatrix} =\underbrace{\begin{bmatrix}(1-k f) & -f f & (1-k f)\end{bmatrix}}_{\mathbf{R}(k,f)}\cdot\begin{bmatrix}x_Q x_I\end{bmatrix} $$
|
||||
$$ \begin{bmatrix}\hat{x}_Q \hat{x}_I\end{bmatrix} = \mathbf{R}(k,f) \cdot\begin{bmatrix}x_Q x_I\end{bmatrix} $$
|
||||
|
||||
$$ \mathbf{R}(k,f) = \begin{bmatrix}(1-k f) & -f \\\\ f & (1-k f)\end{bmatrix} $$
|
||||
|
||||
Digital oscillators are usually characterised in terms of a rotation matrix \\(\mathbf{R}\\)(k,f) that is applied to two state variables x<sub>Q<sub> and x<sub>I<sub>. This representation is formulated in Eq. 1. For clarity the k²\: factor is ignored in this analysis since it yields a simpler solution to the basic feed-forward configuration. In this case we are interested in manipulating the pole location adaptively which is why we will solve for the complex pole positions of this dynamic system below.
|
||||
|
||||
@ -55,7 +57,7 @@ $$ \begin{split}poles\left(\frac{1}{1+D_O(z)}\right) = 1 - k f \pm √{ f^2 k^2
|
||||
|
||||
Finding the poles yields the two solutions in Eq. 4 that correspond to the complex pair P\tss{Q/I} which dictate the oscillatory behaviour of this circuit. This reveals the behaviour shown in Fig. 2b which is that adjusting k will rotate the pole-pair in and out of the unit circle resulting in a growing or receding complex exponential or oscillation. It is also readily seen that for the case k=0 the pole locations lie outside the unit circle. Solving for a steady state solution where P\tss{Q/I} are on the unit circle gives k=f/2.
|
||||
|
||||
# 4 DDWS Core]{\\(\Delta\Sigma^2\\) type DDWS Core
|
||||
# 4 DDWS Core \\(\Delta\Sigma^2\\) type DDWS Core
|
||||
|
||||
In order to realise the proposed multiplier-free DDWS, two additional components will be introduced. The first is a second order digital ΔΣ \: modulator that will allow us to mitigate the need to for high-precision multipliers and the second is a controller module that will regulate the dynamic oscillatory behaviour given a set input parameters. This configuration is shown in Fig. 3 together with sub-blocks for amplitude tracking and noise shaping.
|
||||
|
||||
@ -65,26 +67,7 @@ Introducing a ΔΣ \: modulator is a well established means reduce hardware comp
|
||||
|
||||
The block diagram in Fig. 3 also includes logic for tracking the peak to peak amplitude of the internal oscillation. This is done by detecting zero-crossings of either integrator and latching the other that will at that moment be at the peak amplitude. The oscillation amplitude is used to control the dynamics of the wavelet generator and prevents saturation.
|
||||
|
||||
\begin{algorithm}
|
||||
\DontPrintSemicolon
|
||||
\KwIn{Wavelet synthesis parameters (f, c<sub>bw<sub>, ic, vpp)}
|
||||
\KwResult{Quadrature bit-streams (D1\tss{Q/I}, D2\tss{Q/I})}
|
||||
**Initialise:** x1<sub>Q<sub>=ic, x1<sub>I<sub>=0, x2<sub>Q<sub>=vpp/2, x2<sub>I<sub>=0, s1=c<sub>bw<sub>, s2=-c<sub>bw<sub>
|
||||
\Begin{
|
||||
\ShowLn
|
||||
k1 = 0.5 + s1(D1<sub>PP<sub> - vpp)
|
||||
k2 = 0.5 + s2(D2<sub>PP<sub> - vpp)
|
||||
\\(\mathbf{x1}\\)\tss{Q/I}[n] = \\(\mathbf{R}\\)(k1,f) \\(\cdot\\) \\(\mathbf{x1}\\)\tss{Q/I}[n-1]
|
||||
\\(\mathbf{x2}\\)\tss{Q/I}[n] = \\(\mathbf{R}\\)(k2,f) \\(\cdot\\) \\(\mathbf{x2}\\)\tss{Q/I}[n-1]
|
||||
\uIf{ D1<sub>PP<sub> \textgreater vpp **or** $|\\(k1\\)|$ \textless c<sub>bw<sub>/2}{s1=-c<sub>bw<sub>}
|
||||
\ElseIf{ D1<sub>PP<sub> \textless ic **and** s2\textless0 }{s1=c<sub>bw<sub>}
|
||||
\uIf{ D2<sub>PP<sub> \textgreater vpp **or** $|\\(k2\\)|$ \textless c<sub>bw<sub>/2}{s2=-c<sub>bw<sub>}
|
||||
\ElseIf{ D2<sub>PP<sub> \textless ic **and** s1\textless0 }{s2=c<sub>bw<sub>}
|
||||
}
|
||||
\BlankLine
|
||||
\caption{DDWS Controller}
|
||||
\label{algo:ddws-control}
|
||||
\end{algorithm}
|
||||
|
||||
|
||||
An overview of the control logic is described in Alg. 1. Here the notation from Eq. 1 is used to simplify how the oscillator states evolve by using the rotation matrix. In the behavioural implementation lines 5-6 are realised by a series of conditional statements that increment/decrement the oscillator states \\(\mathbf{x}\\)\tss{Q/I} and then compute the feed forward value by adding or subtracting k1/k2. Notice that we use the state variable s1/s2 to iteratively make sure only one oscillator is growing in amplitude while the other is shrinking in amplitude but at all times the growth is bounded by how close the peak to peak value is to the target maximum vpp. In fact several configurable parameters are used here in addition to vpp to specify the wavelet dynamics. Like before f controls the oscillation frequency in rads per second. The parameter ic determines the extinction ratio between the minimum and maximum oscillation amplitudes and c<sub>bw<sub> controls the window bandwidth together with ic to allow high or low out-of-band rejection.
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@ -49,9 +49,10 @@ $$ QNP \approx \underbrace{\left( V^2_{DD} e^{-3\tau} + \frac{V^2_{DD}}{2^{2N}}
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The expression in Eq. 2 parametrises the overall SAR resolution as N, the loop fillter order as M, and the number of time constants we allow the capacitive DAC to settle as τ \:in order to estimate QNP. This construction shows that settling and quantisation errors are shaped by the loop filter reducing the noise power by the term outside the brackets. Both in Fig. 3 and in the formulation we observe a strong dependency with regard to M as long as we provide sufficient settling time during SAR conversion. This result suggests that the noise-shaping feed-back must avoid driving the capacitive DAC with active amplifiers during successive-approximation to avoid slowing down the conversion speed or equivalently increasing the power requirement of each amplifier. We can also confirm here that the order of the loop filter does not need to be very high if the QNP needs to match the SNP.
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$$ MNP \approx \underbrace{\left( \frac{\pi^2 2^{-2D}}{3 \cdot 2^K OSR^3} + \frac{\pi^{2E} 2^{-2K}}{(1+2E) OSR^{1+2E}} \right)}_{\text{DWA-MSB + MES-LSB DAC}} \frac{\sigma^2 V^2_{DD}}{3} $$
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$$ MNP \approx \Delta^2 \underbrace{ \left( \frac{\pi^2 2^{-2D}}{3 \cdot 2^K OSR^3} + \frac{\pi^{2E} 2^{-2K}}{(1+2E) OSR^{1+2E}} \right) }_{\text{DWA-MSB + MES-LSB DAC}} $$
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The MNP is evaluated in Eq. 3 with respect to the MES noise shaping order E, the number of bits D used to calibrate each capacitor in the MSB DAC in an idealised way. K represents the MSB DAC resolution in bits. Using a capacitor standard deviation \\(\sigma=0.5%\\) and K=4, the MNP of several configurations is shown in Fig. 4. The observation here is that for small OSR values the mismatch noise is typically dominated by the MSB DAC as the mismatch is not sufficiently shaped. It is relatively expensive to increase the number of elements in the MSB DAC since the scaling is linear and increasing the OSR diminishes the advantage of performing SAR. Instead we propose to calibrate the 15 capacitors in the MSB section as D will reduce the MNP more efficiently. The mismatch from the LSB section contains many more elements and is more effectively shaped using a second-order MES technique.
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The MNP is evaluated in Eq. 3 with respect to the MES noise shaping order E, the number of bits D used to calibrate each capacitor in the MSB DAC in an idealised way. K represents the MSB DAC resolution in bits.
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\\( \Delta^2 = \frac{\sigma^2 V^2_{DD}}{3}\\) represents the the capacitor mismatch power using a standard deviation \\(\sigma=0.5%\\) and K=4, the MNP of several configurations is shown in Fig. 4. The observation here is that for small OSR values the mismatch noise is typically dominated by the MSB DAC as the mismatch is not sufficiently shaped. It is relatively expensive to increase the number of elements in the MSB DAC since the scaling is linear and increasing the OSR diminishes the advantage of performing SAR. Instead we propose to calibrate the 15 capacitors in the MSB section as D will reduce the MNP more efficiently. The mismatch from the LSB section contains many more elements and is more effectively shaped using a second-order MES technique.
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The above trends are used to optimise the FOM<sub>S<sub> in a similar fashion to [^3] by correlating hardware requirements with power and accuracy estimators for several configurations. Given an initial 18 bit target precision, we propose the following configuration: CT=50 pF, M=2,τ=5, K=5, D=4, E=2 with the OSR set to 16 to ease the decimation effort.
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@ -117,7 +118,8 @@ This works presents a 17 bit Noise Shaping SAR ADC with reduced oversampling rat
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# Refernces:
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[^11]: S.Pavan, R.Schreier, and G.C. Temes, Understanding Delta-Sigma Data Converters.\hskip 1em plus 0.5em minus 0.4em
elax IEEE, 2017. [Online]: http://dx.doi.org/10.1002/9781119258308
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[^11]: S.Pavan, R.Schreier, and G.C. Temes, Understanding Delta-Sigma Data Converters.\hskip 1em plus 0.5em minus 0.4em
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elax IEEE, 2017. [Online]: http://dx.doi.org/10.1002/9781119258308
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[^12]: R.Schreier, J.Silva, J.Steensgaard, and G.C. Temes, ''Design-oriented estimation of thermal noise in switched-capacitor circuits,'' IEEE Trans. Circuits Syst. I, vol.52, no.11, pp. 2358--2368, Nov 2005. [Online]: http://dx.doi.org/10.1109/TCSI.2005.853909
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[^10]: M.Aboudina and B.Razavi, ''A new DAC mismatch shaping technique for sigma–delta modulators,'' IEEE Trans. Circuits Syst. II, vol.57, no.12, pp. 966--970, Dec 2010. [Online]: http://dx.doi.org/10.1109/TCSII.2010.2083172
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[^13]: J.Liu, G.Wen, and N.Sun, ''Second-order DAC MES for SAR ADCs,'' IET Elec. Letters, vol.53, no.24, pp. 1570--1572, 2017. [Online]: http://dx.doi.org/10.1049/el.2017.3138
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@ -126,7 +128,8 @@ This works presents a 17 bit Noise Shaping SAR ADC with reduced oversampling rat
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[^5]: A.AlMarashli, J.Anders, J.Becker, and M.Ortmanns, ''A nyquist rate SAR ADC employing incremental sigma delta DAC achieving peak SFDR=107 dB at 80 kS/s,'' IEEE J. Solid-State Circuits, vol.53, no.5, pp. 1493--1507, May 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2776299
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[^4]: I.Jang etal., ''A 4.2 mW 10 MHz BW 74.4 dB SNDR continuous-time delta-sigma modulator with SAR-assisted digital-domain noise coupling,'' IEEE J. Solid-State Circuits, vol.53, no.4, pp. 1139--1148, April 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2778284
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[^3]: L.B. Leene and T.G. Constandinou, ''A 0.016 mm sqrd 12 b $\Delta\Sigma$ SAR with 14 fJ/conv. for ultra low power biosensor arrays,'' IEEE Trans. Circuits Syst. I, vol.64, no.10, pp. 2655--2665, Oct 2017. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2703580
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[^1]: Y.Chae, K.Souri, and K.A.A. Makinwa, ''A 6.3
mu W 20 bit incremental zoom-ADC with 6 ppm INL and 1 mu V offset,'' IEEE J. Solid-State Circuits, vol.48, no.12, pp. 3019--3027, Dec 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2278737
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[^1]: Y.Chae, K.Souri, and K.A.A. Makinwa, ''A 6.3
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mu W 20 bit incremental zoom-ADC with 6 ppm INL and 1 mu V offset,'' IEEE J. Solid-State Circuits, vol.48, no.12, pp. 3019--3027, Dec 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2278737
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[^16]: S.Choi etal., ''An 84.6 dB-SNDR and 98.2 dB-SFDR residue-integrated SAR ADC for low-power sensor applications,'' IEEE J. Solid-State Circuits, vol.53, no.2, pp. 404--417, Feb 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2774287
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[^2]: Y.Shu, L.Kuo, and T.Lo, ''An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS,'' IEEE J. Solid-State Circuits, vol.51, no.12, pp. 2928--2940, Dec 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2592623
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[^7]: J.A. Fredenburg and M.P. Flynn, ''A 90 MS/s 11 MHz bandwidth 62 dB SNDR noise-shaping SAR ADC,'' IEEE J. Solid-State Circuits, vol.47, no.12, pp. 2898--2904, Dec 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2217874
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