lieuwe/hugo-site
1
0
Fork 0
mirror of https://github.com/lleene/hugo-site.git synced 2025-01-22 19:42:21 +01:00
Code Issues Packages Projects Releases Wiki Activity

WIP: Major content update

Browse Source
This commit is contained in:
Lieuwe Leene 2022-06-13 17:39:51 +02:00
parent 3ca7604967
commit 01d0a2c796
352 changed files with 84802 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
config.toml
View File

@ -23,7 +23,7 @@ themeColor = "#494f5c"
dateformShort = 'Jan 2'
dateformNum = '2006-01-02'
dateformNumTime = '2006-01-02 15:04 -0700'
homeSubtitle = "Welcome Friend 🐸"
homeSubtitle = "Welcome Friend"
[author]
name = 'L. B. Leene'
@ -48,12 +48,20 @@ themeColor = "#494f5c"
[[menu.main]]
name = "About"
url = "about/"
weight = 16
[[menu.main]]
name = "Projects"
url = "projects/"
weight = 16
weight = 1
[[menu.main]]
name = "Posts"
url = "posts/"
weight = 16
weight = 2
[[menu.main]]
name = "Publications"
url = "publications/"
weight = 3
[[menu.main]]
name = "Chips"
url = "chips/"
weight = 5
[[menu.main]]
name = "Resume"
url = "resume/"
weight = 10

63
content/about.md
View File

@ -1,49 +1,42 @@
---
title: "Hello friend 🐱‍👤"
date: 2021-08-23T17:52:07+02:00
title: "About"
date: 2022-05-21T19:52:54+02:00
draft: false
tags:
- personal
- introduction
- about
- config
---
## About This Site
This site shares a bit of informal documentation and blog-based record keeping
reflecting my day to day activities. Hopefully it's a good mix of technical and
just-for-fun discussion. Professionally I am a mixed-signal circuit designer
which means I compose integrated circuits mostly for sensors whose signals are
then processed for interesting features. Besides that I enjoy a bit of casual
programming as a hobby which is now predominantly based on python which makes
it easy to share and adapt code.
This site shares a bit of informal documentation and more blog-based record
keeping. Providing commentary on design decisions should be just as useful as
some of the technical documentation however included in my repositories.
### Contact
You can reach me at `lieuwe at leene dot dev`.
# research interests
## My Setup
# Proficiencies
I mainly use RHEL flavours of linux having both CentOS and Fedora machines. Most
hosted services run on CentOS 8 at the moment albeit they are approaching
end-of-life. Overall the package repository for CentOS 7/8 is just right. I
rarely need to compile anything from source and packages are very stable.
I will eventually migrate to Fedora completely which is where I operate my
development environment.
I have well over 10 years of design experience using Cadence and Seimens (Mentor Graphics)
EDA design suite extensively from process-development-kit integration to mixed-signal
design verification. Having predominantly designed mixed-signal instrumentation chips most of my
proficiency lies with the Virtuoso analogue design flow. However I have historically
worked in smaller design groups of 5-10 people where you need to be familiar with
the entire development process for a device from start to finish touching on process selection,
tool configuration, and production planning. Fortunately
This is a list of my most used self-hosted services:
- Gitea: Git server with web interface for repository mirrors and personal repos
- Plex: multi-media hosting service for streaming movies and tv-shows
- NextCloud: Cloud storage for synchronizing and sharing files
- Cockpit: Web base administration portal managing linux boxes
- RoundCube: Web based email client
- Postfix/Dovcot: Email stack providing SMTP for my domain
- NGINX: HTTP server serving as proxy for internal web services
- Danbooru: Ruby-on-rails based image hosting and tagging service
with ADE/Measto verification
but I am quite comfortable with skill and any Cadence know how for speeding up design development.
There are several others that I have tried but these really have been the things
I relied on the most in the past 5 years or so. I think the only thing that is
possibly missing from this list is possibly the equivalent of a centralized LDAP
service but I simply haven't had to manage more than handful of users.
## Programming languages
Currently I develop quite a bit of python utilities for scraping, labelling, and
managing media in an automated fashion. In part I am preparing data for one of
my long term projects which is related to image classification based on
structural decomposition rather than textural features. The main idea here is
to analyse and extract structure in an image before performing in-depth analysis
such that said analysis is most specific to its context.
- Python
- Skill
- C++
- Bash
- Matlab

25
content/chips.md Normal file
View File

@ -0,0 +1,25 @@
---
title: "Chips"
date: 2021-08-23T17:52:07+02:00
draft: false
toc: true
tags:
- personal
- CMOS
- fabrication
- devices
---
Here are some of the fabricated chips that I have had the privilege of
designing over the years. These designs are the result of joint efforts with
colleges and collaborators made possible by the Engineering and Physical
Sciences Research Council (EPSRC) UK.
{{< figure src="/images/chips/C0.png" title="AKIRA - A 18b NS-SAR ADC | 2019 | 0.18 um TSMC" width="500" >}}
{{< figure src="/images/chips/C1.jpg" title="ENGINI - A Neural Recording SoC | 2018 | 0.35 um AMS" width="500" >}}
{{< figure src="/images/chips/C2.jpg" title="ENGINI - A Wireless BMI SoC | 2017 | 0.35 um AMS" width="500" >}}
{{< figure src="/images/chips/C4_mod.png" title="PIKACHU - A Time Domain Instrumentation System | 2016 | 65 nm TSMC" width="500" >}}
{{< figure src="/images/chips/C5_mod.png" title="GOLEM - A Distributed Neural Processing SoC | 2015 | 0.18 um AMS" width="500" >}}
{{< figure src="/images/chips/C3_mod.png" title="KIITCHI - An Incremental Instrumentation System | 2013 | 0.18 um AMS" width="500" >}}
{{< figure src="/images/chips/C6.jpg" title="NGNI32 - Neural Recording ASIC | 2013 | 0.32 um AMS" width="500" >}}
{{< figure src="/images/chips/C7.jpg" title="NGNI16 - Ultra-Wide Band Transmitter | 2012 | 0.18 um AMS" width="500" >}}

161
content/posts/2021/assisted-vectorization.md Normal file
View File

@ -0,0 +1,161 @@
---
title: "Image Vectorization 🖇🍮"
date: 2021-12-08T19:26:46+01:00
draft: false
toc: true
tags:
- svg
- python
- code
- image
---
Automated vectorization and upscaling is useful in many scenarios particularly
for drawn art that can be segmented and is generally structured using strokes
and gradients. Here I will outline a methodology that is based around
structural analysis and direct regression methods then evaluate error metrics
for fine-tuning by comparing the output with non-vectorized up-scalers.
## Observations
Regarding image segmentation, I suspect the most common approach is directly
clustering the entire image using the colour and position. In
most scenarios this feature-space will be separable and is a well understood
problem statement. There result still poses some issues; first cluster enclosure
is difficult to resolve (convexity is not guaranteed), second gradient
components weaken the separability of the data. In addition we may need to
sub-sample the image since clustering is computationally expensive given the
mega-samples of image data.
## Outline
0. Coarse Analysis
- Cluster based on colour-space and |∇×F| |∇·F| normalized components
- Present image colour and segmentation complexity
- Partition image in delta space using histogram method
1. Pre-processing and edge thresholding
- Compute the YCbCr equivalent representation
- Map the input colour space based on k-means / SVM for maximum cluster separation
- Compute edges in images and fit spline segments with grouping
2. Fine image segmentation
- Use edges to initialize segments and segment regions based on colour deltas
- Complete segmentation by filling image
- Regression to fit colour for each segment
4. Image restructuring and grouping
- Simplify structures by creating region hierarchy
- SVG 2.0 supports mesh-gradients / Bezier surface composition
- Detect regular patterns with auto correlation / parameter comparison
3. Error evaluation and recalibration
- Use upscaled reference to evaluate error
- Identify segments that need to be restructured with more detail
## Action Items
- Colour surface fitting
- Given a set of samples, fit an appropriate colour gradient
- Image normalization and pre-processing
- Edge composition and image segmentation
- Define a model for segments of the image
- Define a model for closed and open edges
- Evaluate segment coverage of the image
- Heuristics for image hierarchy and optimizations
## Pre-processing Engine
Currently histogram binning has proven to be very effective for generating
initial clusters since it scales well with image size. This allows us to
quickly gauge the complexity of an image in terms of content separability.
These regions will be used to partition the image as edges are extracted
before more accurate mapping is performed.
The main challenge here is colour gradients that washout what should be
obvious centroids. Analysing the samples in batches can prevent this to some
extent but a more robust approach is needed. We could use a localized grouping
technique but accuracy may need be that important for this pre-processing step.
Another technique is that the image can first be clustered using the histogram
of derivative components followed by sub-classing a histogram for each gradient
cluster.
This idea for histogram-binning is surprisingly efficiently for artificial
images where the colour pallet is rich in features. A binary search for
parameterizing the local maxima detection will very quickly segment a wide
variety of images into 10 - 30 classifications.
## Edge extraction
At some point we will want to construct a model representing regions and shapes.
The principle component here is identifying edges segmenting the image. Edge
detection is relatively strait-forward as we only need look for extrema in the
derivative components. In most scenarios this is actually quite noisy and
it is not obvious how we should threshold for what is and what is not an edge.
Here we use the histogram-based clustering result for edge detection region to
region transitions are discretized and no adaptive threshold is required.
There will unavoidably be noisy regions where we see this boundary being spread
out or possibly just a select few pixels appearing in some sub-section due to
the clustering process. This can mostly be removed with a median filter if
necessary.
If the initial segmentation are generated based on k-means in the colour space,
two families of edges will be detected along segments: hard and soft edges.
Hard edges will correspond to the intended edges seen in the image where as
soft edges will arise due to the clustering technique. We can classify these
two families by looking at the norm of the derivative component along such an
edge. There will be more than one way to asses the correctness here but the
significance here is that soft edges present boundary conditions during colour
mapping while hard edges do not. Otherwise visual artefacts will arise are the
interface of two segments that originally was a smooth transition.
## Structural Variability
While we are targeting a-typical images for vectorization it is obvious that
'sharpness' in the final result depends on a subjective style that is difficult
to assess in terms of simple regress or interpolation. This problem however is
central to upscaling algorithms so the methodology here will be that a external
upscaling tool will guide the vectorization process. For example vectorizing
a pixel-art image yields better results 'nearest-neighbour' methods opposed to
Lanczos resampling.
## Regression over SVG colour surfaces
The SVG standard supports three methods for specifying colour profiles or
gradients: Flat, Linear, Radial. There are more advanced mechanisms through
embedding or meshing multiple components the aforementioned three readily
allow us to fit a first order colour contour through linear
regression. This will be our first objective for parameterizing
the colour for segments in our image. Another thing to note is that the gradient
can be transformed after being parameterized. This means that the a circular
gradient can be transformed to realize a family elliptical gradients.
Obviously this will not accommodate all colour contours that we find in images
but in such scenarios we may adopt piece-wise approximations or more accurate
masking of each component using the alpha channel. At some point we should
also be able to resolve mixtures and decompose the contour from a non-linear
or higher-order surface into multiple simpler contours. Again note that support
for advanced colour profiles is not well supported so composition through
these basic elements will yield the best support.
Using linear regression here with a second order polynomial kernel is a very
efficient method for directly quantifying the focal point of the colour
gradient if there is one.
## Contour estimation
My initial attempt to estimate the contour given a set of points was based on
using the convex-hull and recursively enclosing the outline in more detail
by interpolating in between the current outline and finding the closest point
orthogonal to the outline. This result yields a fast approximation of the
enclosing outline without many requirements on the set of points other than
having a dense outline. The drawback was that if it difficult to detect
incorrect interpolation and only resolves the outline with pixel-level
precision. If we pre-process the collection of points such that they
represent detected edges at sub-pixel resolution the later draw-back can be
addressed. Correctness or hypothesis testing could yield a more robust result
at the cost of increased complexity.

20
content/posts/2021/building-svg.md
View File

@ -87,7 +87,7 @@ added directly to KGT as a feature in future releases.
The final result is shown below.
![example_kgt.svg](/images/example_kgt.svg)
{{< figure src="/images/posts/example_kgt.svg" title="example_kgt.svg" >}}
## Tabatkins Railroad Diagrams
@ -118,15 +118,29 @@ would look like this:
``` python
import railroad
with open("./test.svg","w+") as file:
with open("./posts/test.svg","w+") as file:
obj = railroad.Diagram("foo", railroad.Choice(0, "bar", "baz"), css=style)
obj.writeSvg(file.write)
```
The final result is shown below.
![example_kgt.svg](/images/example_trd.svg)
{{< figure src="/images/posts/example_trd.svg" title="example_trd.svg" >}}
Note that this figure is quite a bit more compact but adding additional labels
or customizations outside the scope of the library will probably require
quite a bit of manual work. This could be a fun side project though.
# Using Hugo Short Codes
``` go
{< python-svg dest="/images/posts/test.svg" title="This is a pyuthon-svg exmaple." >}
railroad.Diagram("foo", railroad.Choice(0, "bar", "baz"), css=style)
{< /python-svg >}
```
{{< python-svg dest="/images/posts/test.svg" title="This is a python-svg exmaple." >}}
railroad.Diagram("foo", railroad.Choice(0, "bar", "baz"), css=style)
{{< /python-svg >}}

3
content/posts/2021/configure-nginx.md
View File

@ -1,9 +1,8 @@
---
title: "Setting up a NGINX configuration 🧩"
date: 2021-10-31T15:08:33+01:00
draft: false
draft: true
toc: false
images:
tags:
- website
- config

6
content/posts/2021/mermaid-uml.md
View File

@ -42,7 +42,7 @@ graph LR
This example generates the diagram show below.
![example_mermaid.svg](/images/example_mermaid.svg)
{{< figure src="/images/posts/example_mermaid.svg" title="example_mermaid.svg" >}}
There are four base themes: dark, default, forest, neutral. Additional
[customization](https://mermaid-js.github.io/mermaid/#/theming) is possible.
@ -73,7 +73,7 @@ diagrams of classes and inter-related structures. For example the UML diagram be
[pyviewer]({{< relref "pyside.md" >}} "pyside") which is image simple
browsing utility for compressed archives.
![example_pyviewer.svg](/images/example_pyviewer.svg)
{{< figure src="/images/posts/example_pyviewer.svg" title="example_pyviewer.svg" >}}
This does quite well at illustrating how classes are composed and which methods
are available at various scopes. It also helps organizing and structuring a
@ -153,7 +153,7 @@ function main() {
esac
# echo "IN:${ARGS[1]} OUT:${ARGS[3]}"
mmdc ${ARGS[@]} &> /dev/null
mogrify -trim "${ARGS[3]}"
mogrify -trim "${ARGS[3]}"
feh --reload 2 "${ARGS[3]}" &
sleep 0.1
inotifywait -qm --event modify --format '%w' "${ARGS[1]}" | \

38
content/posts/2021/my-2018-setup.md Normal file
View File

@ -0,0 +1,38 @@
---
title: "My 2018 Setup"
date: 2021-08-12T10:24:27+02:00
draft: false
toc: true
tags:
- website
- about
---
I mainly use RHEL flavours of linux having both CentOS and Fedora machines. Most
hosted services run on CentOS 8 at the moment albeit they are approaching
end-of-life. Overall the package repository for CentOS 7/8 is just right. I
rarely need to compile anything from source and packages are very stable.
I will eventually migrate to Fedora completely which is where I operate my
development environment.
This is a list of my most used self-hosted services:
- Gitea: Git server with web interface for repository mirrors and personal repos
- Plex: multi-media hosting service for streaming movies and tv-shows
- NextCloud: Cloud storage for synchronizing and sharing files
- Cockpit: Web base administration portal managing linux boxes
- RoundCube: Web based email client
- Postfix/Dovcot: Email stack providing SMTP for my domain
- NGINX: HTTP server serving as proxy for internal web services
- Danbooru: Ruby-on-rails based image hosting and tagging service
There are several others that I have tried but these really have been the things
I relied on the most in the past 5 years or so. I think the only thing that is
possibly missing from this list is possibly the equivalent of a centralized LDAP
service but I simply haven't had to manage more than handful of users.
Currently I develop quite a bit of python utilities for scraping, labelling, and
managing media in an automated fashion. In part I am preparing data for one of
my long term projects which is related to image classification based on
structural decomposition rather than textural features. The main idea here is
to analyse and extract structure in an image before performing in-depth analysis
such that said analysis is most specific to its context.

56
content/posts/2021/pyside.md
View File

@ -64,18 +64,62 @@ to a qml function call "swipe.update_paths" for example.
viewer.path_changed.connect(swipe.update_paths)
```
## Example: passing images as bindary data
For reference the code below outlines a simple example that loads an image from
a zip archive and makes the binary data available for QML to source. This
avoids the need for explicit file handles when generating or deflating images
that are needed for the QML front-end.
```python
class Archive(ZipFile):
"""Simple archive handler for loading data."""
@property
def binarydata(self) -> bytes:
"""Load file from archive by name."""
with self.open(self.source_file, "r") as file:
return file.read()
```
The example class above simply inherits from the zipfile standard library where
we read a image and store it as part of the `PyViewer` class shown below. This
class inherits from `QObject` such that the property is exposed to the qml
interface. In this case the `imageloader` is an `Archive` handler that is
shown above.
```python
class PyViewer(QObject):
"""QObject for binging user interface to python backend."""
@Property(QByteArray)
def image(self) -> QByteArray:
"""Return an image at index."""
return QByteArray(self.imageloader.binarydata).toBase64()
```
This setup allows a relatively clean call to the `viewer.image` property within
the QML context as shown below. Other data types such as `int`, `string`,
`float`, and booleans can be passed as expected without requiring the
QByteArray container.
```qml
Image {
anchors.fill: parent
fillMode: Image.PreserveAspectFit
mipmap: true
source = "data:image;base64," + viewer.image
}
```
## Downside
Debugging and designing QML in this environment is limited since the pyside
python library does not support all available QML/QT6 functionality. In most
cases you are looking at C++ Qt documentation for how the pyside data-types
and methods are supposed to behave without good hinting.
and methods are supposed to behave without good hinting. Having developed
native C++/QML projects previously helps a lot. The main advantage here is t
hat QML source code / frame-works can be reused.
Also the variety in data types that can be passed from one context to the other
is constrained although in this case I was able to manage with strings and byte
objects.
## Other Notes: TODO
## Other Notes:
```python
ImageCms.profileToProfile(img, 'USWebCoatedSWOP.icc',

11
content/projects/super_resolution.md → content/posts/2021/super_resolution.md
View File

@ -1,8 +1,9 @@
---
title: "Super Resolution 🧙‍♂️"
date: 2021-09-19T13:30:00+02:00
draft: false
draft: true
toc: true
math: true
tags:
- upscaling
- image-processing
@ -11,4 +12,10 @@ tags:
---
WIP: this is an on going effort for super-resolving images given learned context
and Super-Resolution Using a Generative Adversarial Network (SRGAN).
and Super-Resolution Using a Generative Adversarial Network (SRGAN). [^1]
$$ y_t = \beta_0 + \beta_1 x_t + \epsilon_t $$
now inline math \\( x + y \\) =]
[^1]: And that's the footnote.

75
content/posts/2022/latex-to-markdown.md Normal file
View File

@ -0,0 +1,75 @@
---
title: "Latex to Markdown"
date: 2022-04-28T13:42:40+02:00
draft: false
tags:
- markdown
- latex
- code
- python
- hugo
---
Recently I started porting some of my latex articles to markdown as they would
make a fine contribution to this website in simpler format. Making a simple
parser python isn't that bad and I could have used [Pandoc](https://pandoc.org/index.html)
but I wanted a particular format for rendering a hugo markdown page. So I
prepared several regex-based functions in python to dereference and construct
a hugo-compatible markdown file.
``` python3
class LatexFile:
def __init__(self, src_file: Path):
sys_path = path.abspath(src_file)
src_dir = path.dirname(sys_path)
src_file = path.basename(sys_path)
self.tex_src = self.flatten_input("\\input{" + src_file + "}", src_dir)
self.filter_tex(sys_path.replace(".tex", ".bbl"))
def filter_tex(self, bbl_file: Path) -> None:
"""Default TEX filterting proceedure."""
self.strip_tex()
self.preprocess()
self.replace_references(bbl_file)
self.replace_figures()
self.replace_tables()
self.replace_equations()
self.replace_sections()
self.postprocess()
```
The general process for converting a Latex document is outlined above. The
principle here is to create a flat text source which we then incrementally
format such that Latex components are translated correctly.
## Latex Components
In order to structure the python code I created several named-tuples for
self-contained Latex contexts such as figures, tables, equations, etc. then
by adding a `markdown` property we can replace these sections with hugo
friendly syntax using short-codes where appropriate.
``` python3
class Figure(NamedTuple):
"""Structured Figure Item."""
span: Tuple[int, int]
index: int
files: List[str]
caption: str
label: str
@property
def markdown(self) -> str:
"""Markdown string for this figure."""
fig_str = ""
for file in self.files[:-1]:
fig_str += "{{" + f'< figure src="{file}" width="500" >' + "}}\n"
fig_str += (
"{{"
+ f'< figure src="{self.files[-1] if self.files else ""}" title="Figure {self.index}: {self.caption}" width="500" >'
+ "}}\n"
)
return fig_str
```

271
content/posts/2022/synthesizing-sinusoids.md Normal file
View File

@ -0,0 +1,271 @@
---
title: "Synthesizing Sinusoids"
date: 2022-05-17T13:17:04+02:00
draft: false
toc: true
math: true
tags:
- signal-processing
- delta-sigma-modulation
- digital-circuits
- python
---
Here I will go over a hardware efficient digital-technique for synthesizing a
high-fidelity sinusoidal tone for self-test and electrical characterization
purposes. This will be a application of several state-of-the-art hardware
techniques to minimize hardware complexity while readily
generating a precise tone with well over 100 dB of dynamic range. Further more
the resulting output bit-stream is delta-sigma modulated enabling the use of a
low-complexity 4 bit digital-to-analogue-converter that employs
dynamic-element-matching.
## Synthesizer
``` goat
+-----------------------+ 16b +--------------+ 16b +-------------+ 4b
| 32 bit Recursive | / | 1:16 | / | 3rd Order | /
| Discrete-Time +---+-->| Rotated CIC +---+-->| Delta-Sigma +---+--> Output Bitstream
| Sinusoidal Oscillator | / | Interpolator | / | Modulator | /
+-----------------------+ +--------------+ +-------------+
```
The overall system composition is illustrated above and consists of three
modules. The first module is a recursive digital oscillator and operates at a
higher precision but lower clock rate to generate the target test-tone. The
proceeding modules encode this high-resolution digital signal into a low
resolution digital bit-stream there the quantization noise is shaped towards
the high-frequency band that can then be filtered out in the analogue-domain.
## Digital Oscillation
There are numerous all-digital methods for synthesizing a sinusoidal signal
precisely. The most challenging aspect here is the trigonometric functions that
are difficult compute given limited hardware resource. A common approach to
avoid this is to use a look-up table representing `cos(x)` for mapping phase to
amplitude but this generally requires a significant amount of memory.
Alternatively a recursive feedback mechanism can be used that will oscillate
with a known frequency and amplitude given a set of parameters. The later
approach has negligible memory requirements but instead requires full-precision
multiplication. However considering that we are required to perform delta-sigma
encoding at the output this feedback mechanism can run at a reduced clock-rate
allowing this multiplication to be performed in a pipelined fashion which is
considerably more affordable.
``` goat
- .-. .-.
.->| Σ +------*----->| Σ +---> Digital Sinusoid
| '-' | '-'
| ^ v ^
| | .-----. |
| | | z⁻¹ | '----- Offset
| | . '--+--'
| | /| |
| '+ |<---*
| K \| |
| ' v
| .-----.
'----------+ z⁻¹ |
'-----'
```
The biquad feedback configuration shown above is one of several oscillating
structures presented in [^1] with the equivalent a python model presented below.
The idea here is to perform full-precision synthesis at 64 or 32 bit with a
pipelined multiplier such that this loop runs at 1/M times the modulator clock
speed where M is the oversampling ratio that is chosen to optimize the
multiplier pipeline. In this case M=16 and we will be using 32 bit frequency
precision.
``` python3
class Resonator:
def __init__(self, frequency: float = 0.1, amplitude: float = 0.5):
K = 2 * np.cos(2 * np.pi * frequency)
self.A = 0.0
self.B = amplitude * np.sqrt(2.0 - K)
self.K = K
def update(self) -> int:
self.A, self.B = (self.A * self.K - self.B, self.A)
return self.A
```
The coefficient K determines the frequency of oscillation as a ratio relative to
the operating clock speed. Using \\( K = 2 cos( 2 \pi freq )\\) such that the
oscillation occurs as \\( freq \cdot fclk \\). The initial condition of the two
registers will determine the oscillation amplitude. Setting the first register
to zero and the second to \\( A \sqrt{2 - K} \\) will yield amplitude of \\(A\\)
around zero. We can then offset this signal to specify the level around which
tone oscillates.
## Band-Select Interpolation
The main drawback of not synthesizing the sinusoid at a fractional clock rate
is that we must take care of the aliased components when we increase the
data-rate. Fortunately there are a family of filters that are extremely
efficient at up-sampling a signal while rejecting the aliasing components known
as cascaded integrator-comb filters (CIC)[^2]. These filters consist of several
simple accumulators and differentiators that can be configured to reject
aliasing components.
$$ H(z) = \left( \frac{ 1 - z^{-M} }{ 1 - z^{-1} } \right)^N $$
The transfer function of such a filter is formulated above. This shows that a
CIC structures of order \\( N \\) operating at a oversampling ratio
\\( M \\) will distribute M zeros uniformly around the unit circle. This
completely removes any DC components that end up at the aliasing tones at
multiples of \\( fclk / M\\). However we know priori that we will introduce
aliasing components at integer multiples of the input tone when up-sampling:
\\( freq \cdot fclk / M \\). Making a slight modification to this structure
as discussed in [^3] allows us to further optimize a second-order CIC filter to
specifically reject these components instead.
$$ H(z) = \frac{ 1 - K \cdot z^{-M} + z^{-2M} }{ 1 - K_M z^{-1} + z^{-2} } $$
Notice that the coefficient K from the resonator structure is reused here and
we introduce a new scaling coefficient \\(K_M = 2 \cdot 2 * cos(2 \pi * freq / M )\\)
which we will approximate by tailor expansion to avoid the multiplication
requirement as this factor does not require high precision. Again a python
implementation is shown below for reference.
``` python3
class Interpolator:
def __init__(self, frequency: float = 0.1, osr: int = 32):
K = 2 * np.cos(2 * np.pi * frequency)
KM = 2 * np.cos(2 * np.pi * frequency / osr )
self.fir_coef = np.array([1, -K, 1]) # FIR coefficients
self.irr_coef = np.array([-KM, 1]) # IRR coefficients
self.comb_integrator = np.zeros((2,), dtype=float)
self.comb_decimator = np.zeros((3,), dtype=float)
self.osr = osr
self.count = 0
def update(self, new_val: float) -> float:
self.comb_integrator = np.append(
np.dot(self.fir_coef, self.comb_decimator)
+ np.dot(-self.irr_coef, self.comb_integrator),
self.comb_integrator[:-1],
)
if self.count == 0:
self.comb_decimator = np.append(new_val, self.comb_decimator[1:])
self.count = (self.count + 1) % self.osr
return self.comb_integrator[0]
```
Combing the two feedback mechanisms we can construct a second-order CIC based
digital resonator with a interpolated output that fully rejects aliasing
components. This configuration is shown below. Now let us use Taylor
approximation to resolve the coefficient KM such that it is reduced to
two-component addition. The first two non-zero coefficients for cos are
\\( cos(x) = 1 - x^2 / 2 \\). Hence we can approximate as follows
\\( KM = 2 - 1 >> \lfloor 2 \log_2( 2 \pi * freq / M ) \rfloor \\) where
\\(>>\\) is the binary shift-left operator.
``` goat
Fractional Clock Rate <+ +> Full Clock Rate
- .-. .-. .-.
.->| Σ +------*---------->| Σ +----->| Σ +-------*-------> Interpolated Sinusoid
| '-' | '-' '-' |
| ^ v - ^ ^ - ^ ^ . v
| | .-----. / | / | /| .--+--.
| | | z⁻ᴹ | | | | '+ |<-+ z⁻¹ |
| | . '--+--' . | | | KM \| '--+--'
| | /| | |\ | | | ' |
| '+ |<---*--->| +-' | | v
| K \| | |/ K | | .--+--.
| ' v ' | '---------+ z⁻¹ |
| .-----. | '-----'
'----------+ z⁻ᴹ +---------'
'-----'
```
The resulting configuration only requires one multiplication to be computed at
a fractional clock-rate. Note that practically a hardware implementation will
stagger the computation in time for each of the processing stages.
## Sigma-Delta Modulation
The purpose of digital sigma-delta modulation is primarily to reduce the
hardware requirements for signal-processing in the analogue-domain. Digitizing
a high resolution 16 bit signal is exceedingly expensive once we consider
component variation requirements if we want to preserve the fidelity of our
signal. The main idea here is the reduce the resolution of the output bitstream
while modulating the quantization noise such that accuracy is preserved in the
lower frequencies while noise due to the truncation of the digital bits is only
present at higher frequencies. This allows us to use a low resolution
digital-to-analogue converter that employs mismatch cancellation techniques
at low cost to further remove the impact of component imperfection from
corrupting the precision in-band.
A popular approach here is the use of multistage noise-shaping modulator
topologies. Here we will employ a special maximum-sequence-length configuration
from [^4] which avoids any unwanted periodicity commonly found in the output
of conventional modulators when processing certain static signals. A python
realization of this modulation process is shown below in the case of a first
order modulator.
``` python3
class Modulator:
def __init__(self, resolution: int = 16, coupling: int = 0) -> None:
self.acc = 0
self.coupling = coupling
self.resolution = resolution
def update(self, new_val: int) -> bool:
last_val = self.acc & 1
pre_calc = self.acc + new_val + (self.coupling if last_val else 0)
self.acc = pre_calc % (2 ** self.resolution)
return last_val
```
The third-order configuration of the modulator is shown below. Here the Nx[n]
components represent the coupling factor α and simply use the Cx[n-1] bitstream
from the last cycle. This factor is a small integer chosen such that
2^N-α is a prime number given a fixed modulator resolution N.
``` goat
. C1[n] .-.
D[n] |\ .-------------------------------->| Σ +--> Q[n]
--->+ + '-'
| \ ^ ^
\ | . C2[n] .-------. / |
N1[n]| | S1[n] |\ .---->+ 1-z⁻¹ +-----' |
--->+ +--*--->+ + '-------' |
| | | | \ |
/ | | \ | . C3[n] .-----+----.
| / | N2[n]| | S2[n] |\ .---->+ (1-z⁻¹)² |
.->+ / | --->+ +--*--->+ + '----------'
| |/ | | | | | \
| ' | / | | \ |
| .-----. | | / | N3[n]| | S3[n]
'-+ z⁻¹ +' .->+ / | --->+ +-.
'-----' | |/ | | | |
| ' | / | |
| .-----. | | / |
'-+ z⁻¹ +' .->+ / |
'-----' | |/ |
| ' |
| .-----. |
'-+ z⁻¹ +'
'-----'
```
The output Q[n] will represent a multi-bit quantization result that increases in
bit-depth as the modulator order increases as the derivative components of CX[n]
increase in dynamic range for higher order derivatives. This has a rather
unfortunate side-effect that the signal dynamic range is only a fraction of the
total output dynamic range in this case 1/8. Fortunately these components are
exclusively high-frequency and so including a 3-tap Bartlett-Window FIR a the
output alleviates this problem by amplifying the signal-band and rejecting
the quantization-noise. In that scenario the signal dynamic range uses a little
under half the full dynamic range of the signal seen at the output.
## References:
[^1]: C. S. Turner, ''Recursive discrete-time sinusoidal oscillators,'' IEEE Signal Process. Mag, vol. 20, no. 3, pp. 103-111, May 2003. [Online]: http://dx.doi.org/10.1109/MSP.2003.1203213.
[^2]: E. Hogenauer, ''An economical class of digital filters for decimation and interpolation,'' IEEE Trans. Acoust., Speech, Signal Process., vol. 29, no. 2, pp. 155-162, April 1981. [Online]: http://dx.doi.org/10.1109/TASSP.1981.1163535.
[^3]: L. Lo Presti, ''Efficient modified-sinc filters for sigma-delta A/D converters,'' IEEE Trans. Circuits Syst. II, vol. 47, no. 11, pp. 1204-1213, Nov. 2000. [Online]: http://dx.doi.org/10.1109/82.885128.
[^4]: K. Hosseini and M. P. Kennedy, ''Maximum Sequence Length MASH Digital Delta–Sigma Modulators,'' IEEE Trans. Circuits Syst. I, vol. 54, no. 12, pp. 2628-2638, Dec. 2007. [Online]: http://dx.doi.org/10.1109/TCSI.2007.905653.

597
content/publications/2011/implantable-biotelemetry.md Normal file
View File

@ -0,0 +1,597 @@
---
title: "Implantable Biotelemetry"
date: 2012-09-13T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
- chapter
- wireless
- CMOS
- biomedical
- implants
---
Lieuwe B. Leene
B.Eng Electronic Engineering Hong Kong University of Science & Technology, 2011
Supervised by: Dr Timothy G. Constandinou
A Thesis submitted in fulfilment of requirements for the degree of Master of Science Analogue and Digital Integrated Circuit Design of Imperial College London
Department of Electrical and Electronic Engineering Imperial College London
# Abstract
Recent developments in the field of neuroscience and health monitoring have identified the need for biotelemetry systems based around a ultra efficient power standard to allow for next generation biomedical implants and distributed en vivo sensory networks. The work presented here engages the design of the biotelemetry forward and reverse links with a top down perspective exploring the loss mechanics and inefficiencies of concern. This development has led to the the design of an optimized class-E based inductive link that includes a improved modulation scheme specific to the operation of the power amplifier as well as a integrated low complexity BPSK demodulator. In addition a frame work was developed around a scalable UWB delay modulation scheme that improves transmitter efficiency as well as circuit level designs for a widely tunable digital oscillator and a particularly energy efficient UWB pulse generator based off the impulse response of a LC resonator. In extension an UWB antenna is designed with significant improvements in the low-frequency group-delay and reflection co-efficient and a simple energy detection receiver is developed that will allow testing of the full custom digital layout that is designed for fully integrated the UWB transceiver system in $0.18 \mu m$ CMOS technology. The presented forward link achieves achieve a power transmission efficiency of 46% and 34% while transmitting 250kb/s. The UWB transmitter consumed $68.9\mu W$ of power for a PRF of 10MHz that corresponds to a data rate of 77.5 Mb/s.
# Acknowledgment
I would like to sincerely thank Dr Timothy G. Constandinou for supervising this project. His insightful support and valuable opportunities that has enabled me take this project from vague ideas to a taped out chip design. I would also like to thank Song Luan for his continuous feedback and technical expertise that has allowed me to rapidly develop some of the prototyped devices through out this project. In addition I would like to thank Olive Murphy for advice on testing antennas and allowing me to use the CST MICROWAVE STUDIO software to support my project. Finally, I would like to thank my family for their support over the past year and Ching Chen Ma for always providing that inspiring ambition.
# 1 Motivation
It has been slightly over 100 years since the advent of the world’s first ‘transistor’ and even more now than a decade ago, revolution has almost become synonymous with the advancement of the microelectronics industry with impacts that change the very backbone of society. The revolution of the last decade surely belonged to that of mobile devices industry which experienced an increase in user end data demand by over a hundred fold. On the other end of the spectrum however this surge of wireless connectivity of the past decade has synergized and inspired a new foundation of ideas for biomedical systems.
These novel systems are based around digitizing the medical diagnosis and treatment trough wireless en vivo sensory networks for true personalized medicine. By employing electronic implants that have demonstrated incredible potential due to the dense functionality of CMOS technology, the implantable system on chip have shown potential for restoring vision, treating paralysis, severe epilepsy and Parkinson’s disease [^2]. In addition to applications for novel heath monitoring systems and home-stay medication, bio-telemetry links to implanted devices have enabled the simultaneous study of several hundreds of functioning neurons in a localized area through multi electrode arrays (MEAs). These studies have given crucial insight to behavioral models of the brain for fields such as neuroscience. Recent advances have allowed patients with a spinal impairment to interact with the world through a brain machine interface bringing society closer to visions such as J. C. R. Licklider’s Man-Computer Symbiosis.
Although the idea of wireless powering of implanted devices has been around since the early 1960s for long term artificial cardiac pacemakers, the focus of current generation bio-telemetry systems has shifted from a functional orientation to building a framework for reliability and performance directed at commercial applications. As a result of new applications finding their way to employing bio-telemetry links where there are a net set challenges associated with handling the transmission of substantial data rates. The more recent neural recording system-on-chip (SOC) in particular has presented very challenging power requirements for the radio frequency (RF) transmitter driven by the restriction on heat dissapation inorder to prevent cell damage. As the demand for number of simultaneously neurons recorded exponentially increases every year, a significant amount of interest has been directed at finding more efficient alternatives for transmitting data out of the implant wirelessly and exploiting specialized encryption algorithms that reduce data rate requirements such as inter-spike-interval figures & spike-feature extraction [^3].
In similitude to the miniaturization principle of microelectronics, biomedical system miniaturization is also seen as an important merit that improves the comfort of the subject. Consequently the size of radiating elements inherent to the telemetry system is also an important topic for consideration that with recent demonstrations has brought to light the viability of power and data transmission via GHz radiation and may change bio-telemetry to a more specialized RFID tag based medical system in the future.
This thesis presents various system level reductions and efficiency optimizations on both the forward transmission link, from the external system towards the implant, as well as the reverse transmission link, from the implant to the external system. The overall focus revolves around presenting scalable topologies that may allow significant improvements in power consumption of the overhead transmission components which is key in enabling future neural studies and ultra-low power telemetry systems that can be incorporated with RF energy harvesting technologies to give way for next generation biomedical implants based on multi-element sensory networks.
All schematic designs presented in this document are based on a 0.18\\(\mu\\)m CMOS technology using a 1.2V supply. Circuit level simulations were carried out using Cadence IC5.1.41 with foundry provided PSP models. 2D & 3D electromagnetic simulations were carried out using the CST MICROWAVE STUDIO package.
# 2 Report Outline
Chapter 2 is based on introducing several general principles of conventional telemetry systems. A brief review shall be presented of the various system level topologies that have been used bio-telemetry systems by evaluating the strengths and weaknesses of each design methodology. In extension a design methodology is presented for the class-E power amplifier that is found in virtually all inductively coupled power links for bio-medical applications. We shall also present a brief introduction to UWB technology as well as a review of state-of-the-art neural interface systems to project our system requirements and topology.
Chapter 3 focuses on the forward link design by introducing a analytical description of the coil link in order to formulate target figures of merit followed by the employed power amplifier design with the associated simulation results. Techniques that minimize the loss introduced by phase transitions from BPSK modulation will be a very particular consideration that will be made at the end of the chapter together with the corresponding low complexity BSPK demodulator.
Chapter 4 in analogy focuses on the reverse link design by first introducing the basis for UWB techniques and proposing a scalable modulation technique for low power applications. This is followed by the design considerations of a digitally calibrated oscillator as well as an energy efficient bi-phasic UWB pulse generator. We shall also present the UWB antenna design considerations and propose a receiver topology for testing purposes.
Chapter 5 concludes upon the developments made throughout this thesis in addition to presenting a generalized evaluation. Finally aspects for future work and improvement shall be noted.
# 3 Contributions
The main contribution presented by this thesis are outlined below
- A complete wireless power transmission link trough coupled coil that achieves a net 45% efficiency with the measured coil characteristics as well study on the trade offs of circular and rectangular coil geometries.
- With the developed class E power amplifier an energy efficient BPSK modulation technique is introduced that not require additional supply modulation techniques in addition to a low power BPSK demodulator that consumes 1.5 uW from the unregulated supply.
- Framework for the UWB delay modulation scheme with conservative estimated on BER values and a scalable architecture for implementation.
- Complete UWB transceiver architecture is developed that transmits data at 890 fj/bit for which a full custom digital layout is designed that occupies 200 um by 300 um.
- Miniaturized UWB antenna design that occupies 1.3 cm² and achieves -12 dB reflection coefficient and sub 50 ps group delay over a bandwidth of 4GHz.
# 4 Introduction
The neural sensory implants of interest is generally located in a vital location such as under the skull and characteristically needs to process large aggregates of data as a multitude of neurons are recorded simultaneously for prolonged periods of time. As a result it is particularly challenging to power the implant as monthly operations to replace a battery can severely endanger the subject to infection. Moreover power requirements of several milliwatt would require a large battery. The inductive link in principle allows for a relatively efficient transmission of power without puncturing the skin while giving room for data transmission.
The overall design of telemetry systems pertains to the field of radio frequency electronic circuit design with the inclusion of a few essential aspects from power electronics. The biomedical telemetry application however tends to relax the high frequency requirements and focus more on efficient power induction that is more suitable below the 100 MHz frequency range for maximizing power gain [^4]. Although elaborate antenna systems are still designed to allow for full system-on-chip (SOC) integration the trend towards ubiquitous adoption of integrated UWB transmitters in implants seems to have given a different spin on the RF design aspect. As most bio-telemetry communication links are enabled trough near field coupling there is little gained for high antenna directivity and un-optimized RF coils have been demonstrated sufficient for UWB trough-skin broundary transmission [^5]. Moreover design theory behind UWB is more based on time-domain analysis aimed at minimizing pulse distortion where the traditional harmonic frequency analysis fails to give sufficient insight.
In this chapter, a review of the various system level topologies that have been used in recent bio-telemetry systems is presented by evaluating the strengths and weaknesses of each design methodology. In extension, a design methodology is briefly presented for the class-E power amplifier that ubiquitus inl inductively coupled power links. In addition, an introduction to UWB technology is presented together with a review of state-of-the-art neural interface systems to project our system requirements and topology.
# 5 Bio-Telemetry Schemes
Abstractly speaking, modern telemetry systems can be seen as a 3 channel system. As illustrated in figure 1 these channels correspond to power transmission, forward data transmission, and reverse data transmission. Although 3-channel systems have been reported where each channel is optimized for a single function in terms of carrier frequency and coil/antenna designs the component count is very high. In accordance to the characteristic of the reverse link where a fast bit rate is generally desired, the reverse link is often designed with explicit RF considerations by introducing a far field antenna but it has been demonstrated that single loop coils have considerable potential for near field coupling of RF radiation through the skin [^6]. The power transmission is generally done through inductive coupling at a frequency where the Q-factor of the coils is maximized and losses from the environment are kept to a minimum [^7]. The forward link may very similarly be designed trough inductive coupling but a higher carrier frequency is preferred to allow for more substantial data rates while trading off losses induced by the coils which have been shown to dominate over tissue absorbtions for frequencies above 100KHz [^8].
{{< figure src="/images/msc-thesis/s1.png" title="Figure 1: Generalized system architechture of a bi-directional telemetry system for medical implants." width="500" >}}
Contemporary implant systems have mainly focused on improving the system by choosing the right modulation techniques that allow two channels to by combined into one while still achieving similar performance and there by significantly reducing the number of off chip components on the implant side. In some sense this also relaxes the inter-channel interference as the as the interaction between power forward data transmission, for example, is modeled much more explicitly when combined without interference being prone to variations in the coupling coefficients.
The simplest implementatio for data modulation is amplitude modulation, ASK, of power wave form, where the DC-DC regulator driving the supply of the PA is directly adjusted according to a binary bit stream. However a supply regulation control loop is generally implemented on a system level that fixes the average induced power such that the supply at the implant side maintains a stable voltage. This control loop is rather essential as the coils may misalign or move during operation such that the supply must be recalibrated to avoid component damage or injuries due to overheating hence it is not desirable to introduce modulation noise directly into the control loop.
The alternative to ASK is FSK or PSK which allow for much faster data rates due to the fact that the detection of the phase/frequency shift is not limited by the relaxation time of the resonant pair at the implant side and since the Q-factors of the inductors is desirably large to minimize losses this response time limits modulation speeds [^9]. FSK generally doubles the number of resonant components required for power transmission to be efficient at both frequencies and may be considered undesirable but, unlike ASK and PSK, modulation does not degrade the power transmission efficiency. A binary phase shift keying can achieve faster uplink data rates than ASK without the need of additional passives but as will be discussed in chapter 3 the resonant modes of the two phase states are complementary to one another such that during phase transition a significant amount of power lost which results in the degradation in transmission efficiency when data is being transmitted trough the link. Technically speaking, inefficiency during modulation is not a major concern as data sent through the forward link is primarily used during system set up and remains inactive for the majority of the implant’s lifetime but it requires additional consideration to avoid system failure during the transmission of large amount of calibration data.
More recently the reverse link has also been integrated into the power transmission channel as well by using Load Shift Keying (LSK). This modulation technique is based on the fact that the current drained from the secondary power coil L2 is coupled to the total power drained from the power amplifier. A common implementation of this illustrated in figure 2 where a simple transistor driven by a OOK modulated data stream pulses a short circuit current from L2 which can be detected at the primary power coil. Note that the PA can still be modulated with the forward link data stream. This approach introduces a significant amount of simplicity into the design as power and bi-directional data is transmitted through a single coil potentially eliminating all off-chip components. In addition power hungry driver circuitry required for driving the antenna/coil of the reverse link has also been eliminated. The drawback naturally lies with the fact that the two data channels interfere with one another more severely than with separate coils regardless of the modulation schemes and moreover all data rates are limited by the bandwidth the inductive link. In addition, a significant amount of strain is put on the requirements of the on-chip supply regulator as the average power induced from the coil is continuously being modulated with higher frequency components from the OOK switching characteristic and may require the high-performance analog instrumentation components to have differential architectures that require more power and area.
{{< figure src="/images/msc-thesis/s2.png" title="Figure 2: LSK based telemetry system architechture" width="500" >}}
# 6 Power Amplifiers for Biomedical Applications
A quintessential aspect of power induction is minimizing losses at all stages of the power transmission link where the power amplifier used to be at the centre of attention but with the introduction of switch mode power amplifiers the near lossless operation has now become standard for MHz PA applications. The more classical load driving techniques that use class B or class C modes of operation made achieving over 70% efficiency with a varying load such as an implant challenging due to the matching requirements. Switch mode power amplifiers generally refer to amplifier topologies where the main driving transistor is severely over driven to the extent that the output is far into the non-linear domain by clipping effects such that the transistor can essentially be treated as an ideal switch. The basis of lossless switch mode operation lies with making sure the power transistor does not dissipate power and disregarding how nonlinear the intermediate waveforms are as long as a high-Q LC components are used to terminate all unwanted harmonics an ideal efficiency is expected at the load as all the sources of loss are negated. Since the switch mode structure inherently requires a LC pair it is ideal for driving an inductive load as the coil can be absorbed into the network without additional design considerations.
In order to gain further insight to the operation of switch mode amplifiers we shall present a time domain analysis of the switch mode Class E amplifier topology which allows us to mitigate nearly all losses by absorbing the power transistor paracitics into the network.
{{< figure src="/images/msc-thesis/pa1.png" title="Figure 3: Detailed Class-E PA schematic and the inductive link." width="500" >}}
The topology illustrated in figure 3 shows a power transistor biased by a choke inductor driving the primary coil which is coupled to the secondary coil that drives a half-wave rectifier. It is assumed that the DC load, coil Q-factor, and coil inductance is known for this analysis as well as \\(C_{L2}\\) being choosen according to the required switching frequency such that it forms a resonant tank with \\(L_2\\). The actual Class-E operation is derived trough the biasing condition of the transistor with a over-driven digital input which allows the transistor to be approximated by an ideal switch. More over it can be assumed that the current driving the primary & secondary coils is purely sinusoidal as the $L_1 C_{L1}$ tank is used to filter out non linearities introduced by the swithcing operation of the transistors. Before going into analytical details, the overall circuit needs to be reduced to a simple PA structure driving a single complex load. Note that the effective AC load that the rectifier presents to the secondary coil can be approximated in term of expected voltage drop across the diode bridge and the DC load resistor, that is;
$$ R_{AC} = \frac{1}{2} \frac{(V_{Load} + V_{Diode})^2}{P_{Load} P_{Diode}} || R_{Q2} $$
Now, using simple circuit techniques the circuit can be further reduced at the resonant switching frequency $\omega_s = (C_{L2} \cdot L_2 )^{-1/2}$ where the resonant tank at the secondary coil provides the largest reduction in coil losses [^10].
{{< figure src="/images/msc-thesis/pa2.png" title="Figure 4: Circuit schematic illustrating circuit reductions." width="500" >}}
{{< figure src="/images/msc-thesis/pa3.png" title="Figure 5: Schematic of the reduced circuit representing a Class-E PA with inductive load." width="500" >}}
Note that the series resistance of \\(L_1\\) may directly be absorbed by the effective real load \\(R_{EL}\\) and the series resistnace of \\(L_2\\) is absrobed trough equivilent loss of the the unloaded Q-factor corresponding to the resonant $L_2 C_{L2}$ tank. Formally, it has been assumed that the ac current observed at the resistive load purely sinusoidal and expressed as follows;
$$ i_{R}(\theta) = I_{rf} \cdot cos( \omega_s t ) = m I_{dc} \cdot cos( \theta ) $$
Where m is the ratio between \\(I_{rf}\\) and \\(I_{dc}\\) and $\omega_s t$ is normalized to \\(\theta\\) as the system is periodic over $T = 2\pi \backslash \omega_s$. Furthermore, let the switch be closed for some abitrary reference frame defined by \\(-a_1\\) and \\(a_2\\) centered around 0, such that;
$$ i_{sw} = \begin{cases} I_{dc} \left[1+m\cdot cos( \theta ) \right], & \mbox{for } -a_1 \textless \theta \textless a_2 0, & \mbox{ otherwise} \end{cases} $$
Note that the parameter \\(m\\) may be found be evaluating the charge conservation at the node \\(V_d\\) of the capcitor \\(C_{ds}\\) by;
$$ I_{dc} = \frac{I_{dc}}{2\pi} \int \limits_{-a_1}^{a_2} \left[1+m\cdot cos( \theta ) \right] d\theta $$
Similarly by integration the at the node \\(V_d\\) is given by;
$$ v_d (\theta) = \begin{cases} 0 , & \mbox{for } -a_1 \textless \theta \textless a_2 \frac{I_{dc}}{\omega C_{ds}} [ \theta - m \cdot sin(\theta) - a_2 - m \cdot sin ( a_2 ) ], & \mbox{ otherwise} \end{cases} $$
Given these waveforms one may perform a transform integral to find the power of the fundamental quadrature components which is expected to drive the load with the sinusoidal current \\(I_{rf}\\).
$$ V_{di} = \frac{I_{dc}}{\pi \cdot \omega C_{ds}} \cdot \frac{1}{2m} [ m \cdot sin^2 ( a_1 ) - m \cdot sin^2 (a_2) + 2 \cdot cos^2 ( a_1 ) - 2 \cdot cos^2 ( a_2 )] $$
$$ V_{dq} = \frac{m \cdot I_{dc}}{2 \pi \cdot \omega C_{ds}} \left[ m \left( sin^2 ( a_1 ) + sin^2 (a_2) \right) + \frac{ sin (2 a_1 ) - sin (2 a_2 ) }{2} + 2 \cdot cos ( a_1 ) sin ( a_2 ) \right] $$
With these components the phasor at the \\(V_d\\) side of \\(C_{L1}\\) must be match to the phasor at the known load $X_L + R_{EL}$ which specifies the coupling capacitor \\(C_{L1}\\) by impedence matching.
$$ R_{EL} =\frac{ - V_{di}}{m \cdot I_{dc}} $$
$$ C_{L1} =\frac{ V_{dq}}{m \cdot I_{dc}} - X_{L} $$
Finally we need to consider the conduction angle of the transisor, that is $a_1 + a_2$ in degrees. Intuetively, the larger the conduction angle (bouned by a maximum value of 180 degrees) of the transistor the more dynamic current oscillating trough the primary tank of the circuit for a given capacitance \\(C_{ds}\\) but this also results in a very large peak voltage at the drain of the power transistor inducing a significant amound of stress at the pinch-off region in the channel. For high power applications a conduction angle of 110 degrees is generally suggested for trading off driving capability and compoent lifetime but since bio-telemetry power requirements are small and a direct interface with digital control components is desirable, the PA presented in chapter 3 has a conduction angle of 180 degrees.
Note that one can also extract the DC component through using a transform integral which illustrates explicitly the linear scaling associated with the supply voltage and current load at the inductor. This characteristic is particularly useful for fine tuning the final PA configuration as it is initially difficult to specify the exact waveform at the rectifier, hence minimizing the power dissipated by the diodes remains challenging from the first cut design but is done at ease with simulation support.
# 7 Ultra Wide Band Technology
The UWB system is historically based on the spark gap transmitters developed by Marconi in the 1900s [^11]. Although there was potential for ground breaking data rates, the ability to control the UWB spectrum at the time was still in its infancy and made inter channel and multi user interference a serious problem. This ultimately resulted in the disregard for wide band communication in favor for the narrowband technology that was easier to regulate with respect to multiple end-users. The more recent 3.1GHz to 10.6GHz spectrum allocation for UWB applications that occupy at least 500MHz by the Federal Communications Commission (FCC) of United States in 2002 has sparked new interests in the field as commercial use is now permitted with a limited power spectral density of -41.3 dBm/MHz [^12].
The recent developments in ultra-wideband (UWB) technology have made a significant impact on a broad range of applications because it presents a set of relatively unique advantages: very short duty cycles, low power consumption and simple architectures which are ideal for modern cost efficient SOC miniaturizations that are often the focus of state-of-the-art research projects. In this respect, UWB has promised phenomenal performance for short range wireless channels allowing up to 100Mb/s data rates under very strict sub-mili watt power budgets with all-digital transmitter architectures that are much more robust in performance than their analog wave-mixing counterpart that can often not be integrated on the same chip due to substrate interference issues from other system components.
{{< figure src="/images/msc-thesis/spec.png" title="Figure 6: Illustration of the spectral characteristics for the three main classes of communication technologies and the associated modulation schemes." width="500" >}}
The foundation of UWB systems based around the characteristic low spectral density that results from very short pulses of energy but embody a very wide signal bandwidth. This characteristic allows the transmission of a signal with spectral energy distributed below the noise floor eliminating the chance of interference with coherent narrowband systems. The basis on which UWB is assured to attain the phenomenal bit rates suggested earlier comes from the well-known Shannon-Nyquist criterion that dictates the maximum channel capacity, \\(C\\), which can be achieved with arbitrarily small but nonzero probability of error and is given by [^13];
$$ C = BW \cdot log_2 \left( 1 + \frac{E_{signal}}{E_{noise}} \right) $$
Where \\(BW\\), \\(E_{signal}\\), \\(E_{noise}\\) are the channel bandwith, recieved in-band signal energy, recieved in-band noise energy respectively. Recognizing that SNR, \\(E_{signal}\\) / \\(E_{noise}\\) scales almost linearly with the total system power on both the transmitter and receiver side we observe that improving SNR by dissipating more power will, as disappointing as it is for high SNR environments such as nearfield biotelemetry, only improve the channel capacity in logarithmic fashion. However with a given bandwidth of several GHz we can still assure ourselves a Mb/s bit rate even with poor SNR ratios due to ultra low power transmitter operation from ther linear dependency of bandwidth.
Some of the most significant developments in this field lie with the fully integrated CMOS pulse shapers that adhere to the FCC mask regulations [^14]. Pulse shapers not pertaining to the field of biomedical implants generally quote the energy dissipated per pulse FOM which ranges from 2nJ/pulse to some of the more recent work that nearly achievies 4pJ/pulse [^15]. There have been several publication have proposed using a UWB reverse link data transmission for biomedical telemetry with much success in terms of low power operation and have achieved 900fJ/pulse but did not present spectral compliance[^16].
There are three performance metrics of the UWB pulse that are of interest for commercial applications as they allow complete specification of the signal to noise and interference ratios for linear receivers [^17]. These three metrics correspond to spectral efficiency, out-of-band emissions, and time-bandwidth product [^18].
The first of which being the most intuitive, that is the spectral efficiency, which indicates how efficiently the designated spectrum is used in terms of how well all the radiated energy is confined within the 10dB ultra-wide bandwidth. This is expressed as;
$$ \eta_{ch} = \frac{E_{ch}}{BW_{-10dB} \cdot max ( PSD_{W / MHz})} $$
Where the total in band spectral energy, \\(E_{ch}\\), is given by
$$ E_{ch} = \frac{1}{2 \pi} \int_{BW_{-10dB}} PSD ( \omega ) d\omega $$
The second figure of merit for UWB pulses evaluates the normalized amount of spurious spectral energy is generated by the pulse. That is;
$$ \eta_{0} = \frac{E_{tot} - E_{ch}}{E_{ch}} $$
Where the total radiated energy, \\(E_{tot}\\), is given by the time-domain integral
$$ E_{tot} = \int^{\infty}_{-\infty} p(t)^2 dt $$
Finally, the time-bandwidth product primarily indicates the utility of the pulse in terms of being able to carry information. Consider for example the Sinc function which precisely has 0% out of band emissions however its time domain square power is unbounded indicated by the divergent integral for \\(d^2\\). This implies that modulation based on a ideal Sinc wavelet is non-realizable by a causal system. The time-bandwidth product being related to the standard deviation in the spectral intensity and time domain intensity which is formulated as follows;
$$ D^2 = \frac{1}{2 \pi \cdot E_s} \int^{\infty}_{-\infty} \omega^2 \cdot | PSD(\omega)|^2 d \omega $$
Where the total radiated spectral energy, \\(E_{s}\\), is given by the frequency-domain integral\
$$ E_s = \frac{1}{2\pi} \int^{\infty}_{-\infty} | PSD(\omega)|^2 d \omega $$
$$ d^2 = \frac{1}{E_{tot}} \int^{\infty}_{-\infty} t^2 \cdot | f(t) |^2 dt $$
Such that the time-bandwidth product is summarized as;
$$ B_{t \omega} = D \cdot d $$
Table 1: Summary of the UWB FOM performance for different classes of analytic pulses[^1].
| | Spectral Efficiency | Out-of-Band Emissions | Time-BW Product|
|----|----|----|----|
|Sinc | 100% | 0% | (\infty) |
|Square | 60% | 12.8% | (\infty) |
|(2^{nd}) order | 59.2% | (2.8%) | 0.55 |
|Root-Raised cosine | 84.6% | (0.4%) | 0.85 |
|Gaussian | 56.5% | (3.3%) | 0.50 |
|Tanh | (58.4%) | (2.7%) | 0.53 |
A significant amount of progress has already been made towards to maximizing these figures of merit in a more general UWB framework by means of photonics and microwave systems [^19]. Only a select few of these advances are fully integrated systems and since compact integrability is the strict requirement for the implant side system there is a still lot of room for improvement for current implant-compatible UWB transceivers.
# 8 UWB Pulse Generation
Fully integrated UWB technology is a relatively recent breakthrough, as previous pulse generation systems were primarily based on step recovery and tunnel diodes that under pulsed excitation produced a very different radiation spectrum that carrier based modulation schemes [^20]. Interestingly the spectrum used for time domain UWB encoding was essentially the modulated impulse response of the diode in operation. Moreover these wideband spectrums were found to allow much more accurate special resolution as well as exhibit some degree of immunity to passive interference (i.e. echos) [^21]. The integrated UWB framework bases its pulse generation on a more synthetic approach as the GHz operation of current CMOS technology allows pulse modulation with pulse width far below the average temporal UWB pulse duration which is around 1ns. This in many cases has allowed for piece wise reconstruction of a theoretically derive pulse shape such as those mentioned in table 1.
{{< figure src="/images/msc-thesis/pl2.png" title="Figure 7: (left) spectrial representation of the oscilator and modulation waveforms (right) resulting UWB spectrum due to mixing." width="500" >}}
The most elementary form of fully integrated UWB pulse generation is derived from sub GHz OOK modulation of the GHz oscillator [^22]. With the frequency domain transforms are illustrated in figure 7, since digital and analog oscillators are relatively disposable in the FCC UWB band this approach is arguably the most elementary topology that can achieve relatively good performance if the startup and dead times are well calibrated. The challenging aspect of this topology is it is difficult to both suppress the spurious frequency sidebands as well as the DC component at the output.
{{< figure src="/images/msc-thesis/pl1.png" title="Figure 8: Illustration of the spectral characteristic of \\(1^{st}\\), \\(5^{th}\\), and \\(7^{th}\\) derivative based gaussian UWB pulses." width="500" >}}
An alternative approach to generating UWB pulses is based on the spectrum of Gaussian derivatives [^14]. The family of Gaussian functions are generally well known for their transform limited behavior and as illustrated in the previous section the Gaussian pulse has the most optimal time bandwidth product out of all analytic reference pulses. Since the actual Gaussian pulse has a strong DC component the derivatives are more realizable in RF systems.
$$ g^{(n)}(t) = \frac{d^n}{d t^n} \left( \frac{ A }{ √{2\pi} \cdot \sigma} \cdot exp \left\{ \frac{-t^2}{2 \sigma^2} \right\} \right) $$
$$ |G^{(n)} (\omega) | = A \cdot (\omega)^n \cdot exp \left\{ \frac{-( \omega \cdot \sigma )^2}{2} \right\} $$
From the expression of the Gaussian UWB spectrum it can be observed that there are two parameters for spectral tunability that allow fitting under the FCC mask which has been done extensively [^23]. These two parameters are \\(\sigma\\) and the n which correspond to the temporal pulse width and the derivative order of the Gaussian pulse. By increasing the derivative order of the generated gaussian pulse the overall spectrum is expected to shift to the higher frequencies while simutaniously becomming more concave at the fundamental lobe. By reducing \\(\sigma\\) the spectrum also shifts towards the higher frequency spectrum but in contrast does not affect the fractional bandwith of the fundametal lobe. The \\(1^{st}\\), \\(4^{th}\\), \\(5^{th}\\), and \\(7^{th}\\) order Gaussian derivatives have been demonstrated to fit the FCC mask in literature and are thier allocation under the FCC mask is illustrated in figure 8 for a relative comparison.
{{< figure src="/images/msc-thesis/pls1.png" title="Figure 9: Schematic of a simple Gaussian Pulse shaper." width="500" >}}
{{< figure src="/images/msc-thesis/pls3.png" title="Figure 10: (left) Ultra short pulse control signals driving the Gaussian pulse shaper. (right) Piece wise constructed gaussian outout pulse fed to the antenna." width="500" >}}
The integrated circuit implementation of these Gaussian pulse generators are typically fitted by a series of consecutive current pulses feeding into a coupling capacitor toward the antenna load. The pulses are typically under a 100ps long depending on the CMOS technology and by adjusting the driving capability of the MOSFET that is active during a particular phase the amplitude of the corresponding pulse can be adjusted according to the configuration that best fits the target Gaussian model. This topology has demonstrated some of the most energy efficient pulse generators yet, achieving a spectral energy density that nearly matches the FCC mask while consuming more than 4pJ per pulse.
In extension to the Gaussian pulse generator topologies, a more generalized structure has also been introduced which focuses on efficiently generating a very board band pulse and filtering out the unwanted spectral components after amplification trough by an RF power amplifier. The filter can be implemented as an integrated on-chip LC filter or using a microwave distributed element filter topology [^24]. A particularly challenging aspect of this topology is that, although the implementation is the most robust, the filter is required to have a near constant group delay over the pass band to maintain ultra-short pulse durations and avoid pulse distortion.
{{< figure src="/images/msc-thesis/pl3.png" title="Figure 11: (left) Schematic illustrating a RF PA amplifying a Broad band pulse that is then filtered by a lumped LC network. (right) Illustration showing how the broad band pulse is filtered to meet the FCC mask requirements by using a highpass filter. " width="500" >}}
Overall these three topologies allows for fully integrated systems where often the implementation can be translated into a completely digital architecture where only the transistors driving the RF output need to be considered in analog terms. This benefit allow for rapid prototyping with very small chip area requirements, complete generation of a UWB transmitter by digital synthesis has also been demonstrated [^25].
# 9 Projecting System Requirements
Due to the very rich physiological information neural signals carry, an overwhelming amount of interest has been seen in the monitoring of en vivo neural activity. The neural interface SOCs have since developed impressive set of performance standards that is expected to be maintained for the next few years. By cross-referencing the expected advances in neural recording technology a projection can be made on system requirements in the next 3 years [^26].
Table 2: Performance overview of the most recent state-of-the-art work on neural interfaces.
| | 2009 [^27] | 2010 [^28] | 2010 [^29] | 2011 [^30] | 2011 [^31] | 2012 [^32] |
|----|----|----|----|----|----|----|
|Technology | $0.35\mu m$ | $0.35\mu m$ | $0.35\mu m$ | $0.13\mu m$ | $0.18\mu m$ | $0.13\mu m$ |
|Channels | 1 | 128 | 128 | 1 | 32 | 96 |
|max BW (Hz) | 0.3k | 20k | 5k | 11.5k | 12k | 10k |
|ADC Resolution | 12b | 9b | 8b | 8b | 8b | 10b|
|ADC Sampling Rate (kS/s) | 1 | 640 | 111 | 10-100 | 125 | 31 |
|Data Rate per Channel (kb/s) | 12 | 360 | 111 | 100 | 250 | 313 |
|Power per Channel (W) | 895n | 344u | 190u | 75u | 10u | 68u |
|Power to Transmitter | - | 1.6mW | - | 400uW | - | - |
From the references in table one can observe that although the effective power consumption per channel is steadily decreasing below $100 \mu W$. The sample resolutions and channel bandwidths tend to be slightly over 8b and 10kHz respectively as it appears to be the sweet spot that maximizes SNR with minimal power requirements. Given the expection to see 512+ channel neural SOCs in the coming 3 years it theoretically corresponds to an uncompressed data rate of 82Mb/s that needs to be transmitted through the reverse RF link. A similar analysis would estimate the required system power budget to be an optimistic 5mW system or a more pessimistic 15mW prototyping system that considers systems that have demonstrated neural recording from animal trails with more significant weighting.
In summary, this chapter has given way for the target specification given in table 3 with the corresponding topology given by figure 12.
{{< figure src="/images/msc-thesis/s3.png" title="Figure 12: System level abstraction of the proposed biotelemetry topology." width="500" >}}
Table 3: Performance requirements for the implantable biotelemetry system.
|Parameter | Specification |
|----|----|
|Power Delivered to load | 15mW |
|Forwardlink Data rate | 300kb/s |
|Modulation Scheme | BPSK |
|Reverselink Data rate | 80Mb/s |
|Power to Transmitter | $\textless100\mu W$ |
# 10 Forwardlink
The forward link has been the primary focus of biotelemetry systems as the induction of wireless power into the body is a challenge that has been receiving attention since the 1960s and has continued to develop alongside the innovations made in power electronics and the more recent RFID technology [^8]. However, regardless of the modulation techniques presented in chapter 2, there is a very inherent limitation that the inductive link imposes in terms of data transmission.
{{< figure src="/images/msc-thesis/s5.png" title="Figure 13: System block diagram of the forward link channel." width="500" >}}
With reference to figure 13, the system of interest here may be abstracted into four separate sections; the power amplifier, the inductive link, the demodulator, and the rectifier. Each of which substantiates a complete technical topic on its own and in association with the technical specifications given. This chapter will focus on first presenting an analytical description of the coil link in order to formulate target figures of merit followed by the employed power amplifier design with the associated simulation results. Techniques that minimize the loss introduced by phase transitions from BPSK modulation will be a very particular consideration that will be made at the end of this chapter together with the corresponding low complexity BSPK demodulator.
# 11 Inductive Link Design
{{< figure src="/images/msc-thesis/pa4.png" title="Figure 14: Circuit model of the inductive link driven by an ideal source." width="500" >}}
With particular focus on maximizing the induced power onto the rectifier load which has be reduced to the ac equivalent \\(R_{AC}\\). With the reduced circuit illustrated in figure 14 one may be able to identify the two loss mechanisms that govern the power transmission transfer function. The first being the reflection coefficient associated with the resistive loading of inductor \\(L_1\\) due the secondary coil that is in series with the parasitic resistance of the inductor itself \\(R_1\\). The second loss mechanism abstractly lies with the self-loading of secondary inductor due to the parasitic resistor \\(R_2\\). Both of these parasitics are directly related to the Q-factor of the two inductive coils used to couple the two systems. In brief, the analytic expression for the efficiency of power induction may be derived at the resonant switching frequency, again that is $\omega_s = (C_{L2} \cdot L_2 )^{-1/2}$ , as [^33];
$$ \eta = \left[ \frac{V_L \cdot I_L}{V_s \cdot I_s} \right] = \frac{R_{eff}}{R_{eff} + R_{1}} \cdot \frac{L_2}{L_2 + R_{2} \cdot R_{AC} \cdot C_{L2}} $$
Where the effective impedance seen at the primary coil, \\(R_{eff}\\), is
$$ R_{eff} = k^2 \cdot \frac{\omega^2 \cdot L_1 \cdot L_2}{R_2 + \frac{L_2}{R_{AC} \cdot C_{L2}}} $$
Further expansion will show that this equation may be optimized for a given k in terms of the load \\(R_{AC}\\) with respect to the inductor Q of coils \\(L_1\\) & \\(L_2\\).
$$ R_{AC} \bigg|_{\eta=\eta_{max}} = \frac{\omega_s \cdot L_2}{k} \cdot √{\frac{R_1 \cdot L_2}{R_2 \cdot L_1}} = \frac{\omega_s \cdot L_2}{k} \cdot √{\frac{Q_2 }{Q_1}} $$
Such that the peak efficiency, \\(\eta_{max}\\) may be expressed as
$$ \eta_{max} = \frac{k^2 \cdot Q_{L1} \cdot Q_{L2}}{(1+ k \cdot Q_{L1})(1+ k \cdot Q_{L2})} $$
The limiting factor associated with the coils is primarily the total chip area hence the coil geometry should maximize the coupling quality factor product per unit area. Previous systems will either opt for a coil integrated on to the PCB which allows improves the ability manufacture the end result or a coil that is implemented by a wrapped linz wire which makes scalable prototyping challenging but provides much better performance in terms of inductor Q-factors [^34]. PCB integrated inductors tend to be more lossy for a given inductance primarily because of the space requirements on the traces which prevent the dense inductance one may expect from a wire wrapped coil. The majority of published literature tends to prefer using circular geometries as their properties are accurately predicted by analytic formulas, it should be noted however that rectangular coils achieve higher coupling coefficients per unit area. With this in mind, the coils that tested in the laboratory were based on copper wire wrapped rectangular geometries. In analogy to closely space circular coils where it has been demonstrated that the mutual inductance is maximized when the primary and secondary coils have the same geometry we expect the same from the rectangular coils [^35].
{{< figure src="/images/msc-thesis/l3.png" title="Figure 15: (left) Circular Coil geometry. (center) Square coil geomerty. (right) in plane view of coils." width="500" >}}
Using EM simulation tools a simple study was conducted to confirm these findings. Using a single turn circular loop with a diameter normalized to the parameter r and a square loop with the side length also normalized to the parameter r, we studied the behavior of the coupling coefficient k with respect the out of plane distance, d, from two identical coils and the lateral in plane displacement a. The results illustrated in figure 16 confirmed that, although circular coils achieve better quality factor, the square coils achieve better coupling coefficients implying with reference to equation 24 that square coils achieve higher peak efficiency .
\\(\\) \frac{Q_{circle}}{Q_{square}} = 1.87 & \frac{k_{circle}}{k_{square}} = 1.88 \\(\\)
{{< figure src="/images/msc-thesis/KUPL.eps" title="Figure 16: EM simulation results of the coupling coefficient with respect to the in-plane and out-of-plane normalized displacements." width="500" >}}
In accordance to the above considerations and estimates on the ac load expected to be loading the secondary coil a two coil rectangular link was prototyped. The primary coil and secondary coil were measured in the lab to evaluate the mutual inductance values where the mutual inductance was evaluated through a differential measurement [^36].
Table 4: Measured characteristics of the two inductive coils measured at coil distance of 10mm.
|Parameter | Primary Coil (L_1) | Secondary Coil (L_2)|
|----|----|----|
|Turns | 29 | 15 |
|Dimensions (mm) | 12 x 24 | 12 x 24 |
|Inductance (uH) | 46.59 | 12.67 |
|(R_s) ((\Omega) at 1MHz) | 7.49 | 3.19 |
|(k_{21}) | 0.134|
{{< figure src="/images/msc-thesis/loop.png" title="Figure 17: Photograph of the prototype rectangular coil used for power induction." width="500" >}}
Given the measured coil characteristics, the Class-E PA was designed in accordance with the method presented in chapter 2. By introducing the simulation models of commercially available components the design was fine tuned to achieve a power transmission efficiency of 46%. The derived system delivers 15mW to a 600 ohm load corresponding to an unregulated supply of 3V. The losses from the primary and secondary contribute to 30% and 14% of the total power dissipation respectively. The off chip rectifier dissipated 8% of the total power which actually correspond to a marginal efficiency of 85%. The remaining 3% is dissipated by the RF choke and the power transistor.
{{< figure src="/images/msc-thesis/pa0.png" title="Figure 18: Detailed circuit schematic of the complete power transmission system with the component names/models annotated." width="500" >}}
Note that a the power transistor in figure 18 is a 2N7000 Fairchild N-Channel Enhancement Mode Field Effect Transistor with a maximum drain voltage rating of 60V.
{{< figure src="/images/msc-thesis/power.png" title="Figure 19: Simulation results of the power induction system in operation illustrating a average 46% PTE." width="500" >}}
# 12 Switch mode BPSK Modulation
In one respect the input waveform of the Class E amplifier is no longer trivially related to the waveform driving the load in time domain and strictly speaking the degrees of freedom at the driving transistor are now limited to two states; open circuit, and closed circuit. As a result the dynamic range of this class of amplifier is limited to the unit gain circle on the constellation diagram. This inherently presents a problem for BPSK modulation as the state transitions through the zero crossing as shown in figure 20 which for many amplifier topologies is undesirable due the fact that is strains the dynamic range requirement. In the RF domain regulating the transition behavior is rather strict as state transitions that lie beyond the capability of the amplifier result in spurious frequency components from distortion that lie outside of the designated frequency band. In the case of biomedical telemetry we shall observe that such a careless transition results a significant amount of loss in the system. To alleviate this problem we shall introduce an intermediate state to allow a smoother transition without introducing additional system complexity.
{{< figure src="/images/msc-thesis/cnst2.png" title="Figure 20: (left) Standard BPSK constellation diagram. (right) Constellation diagram of the proposed BPSK modulation scheme." width="500" >}}
Figure 21 shows the simulation results of phase transition of two BPSK modulation techniques, the first in blue being the simple BPSK modulation of a square wave and the second in red being the proposed BPSK modulation of a square wave with an intermediate state. It is obvious that there is a dramatic difference with respect to the voltage waveform seen at the rectifier input. The simple modulation technique not only results in a slow transition but there is no energy induced for a number of cycles which is detrimental to the system PTE \\(\eta\\). The proposed modulation scheme first transitions to \\(+\pi/2\\) for half a cycle before completing the phase shift towards \\(+\pi\\). It is important to note that open circuit state of the RF switch maintains its temporal duration as this is the mechanism that provides harmonic termination to the higher order harmonics that are reflected by the LC tank.
{{< figure src="/images/msc-thesis/MOD.eps" title="Figure 21: Simulation results illustrating the gain in average PTE and the destructive inteference of the two phase states during the phase transition without the intermediate state." width="500" >}}
Even with this modulation technique a linear trade off with respect to the carrier frequency and the forward data rate is still to be expected as one cycle for every phase transition fails to induce power. The expected power transfer efficiency, \\(\eta\\), during modulation is asymptotic to and approximated by the following expression.
$$ E \left[ \eta \right] = \eta_{s} \cdot ( 1 - N \cdot \frac{f_{data}}{f_{carr}} ) $$
Where \\(\eta_{s}\\), \\(f_{carr}\\), \\(f_{data}\\) are the un-modulated PTE, carrier frequency, and data rate respectively. N is the model parameter that corresponds to the number of cycles skipped as a result of a phase transition which our fitting estimates to be approximately 1 for the proposed modulation scheme. It is now clear that faster switching frequencies driving the PA will also allow for proportionally faster data rates without having to sacrifice efficiency.
{{< figure src="/images/msc-thesis/swtmd.eps" title="Figure 22: Simulation results of the PTE with respect to different data rates and the fitting parameters of the extracted model." width="500" >}}
# 13 Integrated BPSK Demodulator
To reduce overhead, the demodulator illustrated in figure 23 recovers the transmitted data stream is not based on a delay locked loop topology but based on detecting the cycle skipping of phase transitions. Although it is arguable that this type of detection is prone to failure due to coil displacement when the designated patient moves these kind of environmental factors influence the induced voltage waveform in the very low frequency spectrum that typically do not exceed 100Hz. Hence a high-pass filter behavior is introduced to the peak voltage detector using the parasitic capacitance and leakage current of the transistor M9.
{{< figure src="/images/msc-thesis/bddd.png" title="Figure 23: (left) Transistor level schematic of the threshold based phase detector. (right) Digital State machine that detects phase changes in the induced voltage waveform." width="500" >}}
The remaining operation of the circuit is intuitive, M1 shifts the voltage wave at the input of the rectifier down so that is falls below the supply voltage and the transistors M5-M7 determine & compare the voltage \\(V_{bias}\\) and the peak voltage which is $max(V_{in}-V_{thm1} - V_{thm8})$. Due to the over driving effects the output is approximately digital in characteristic where Vclk is low then Vin is larger than \\(V_{bias}\\) and \\(V_{sig}\\) is low when Vin larger than the stored peak value. These signals are processed by some simple digital circuitry to detect when \\(V_{in}\\) drops below its peak value by more than one NMOS threshold voltage. The near digital operation of this circuit the power consumption is just under $1.5 \mu W$ and simulation results of phase detection is shown below in figure 24.
{{< figure src="/images/msc-thesis/DBPSK.eps" title="Figure 24: Simulation results showing the operation of the threshold based phase detector" width="500" >}}
# 14 System Summary
In this chapter a class-E based forward transmission link was presented that couples power and transmits data. To engage the discussion on system design a common framework for coupled coils was presented to formulate a objective that brought forth the efficiency figure of merit. In addition to the schematic specifications of the transmitter, the modulation scheme was considered in detail with respect to the switch mode amplifier by identifying the underlying phase transition inefficiencies. By introducing an intermediate state the power transmission efficiency during modulation was improved an a accurate model describing the trade off between modulation rates and carrier frequency was presented. Finally the a low power BPSK demodulator was proposed.
# Reverselink
The reverse link of the biotelemetry system primarily pertains to the RF communication link that sends large amounts of data acquired in vivo by the sensory instrumentation devices to a receiver external to the body. The focus of this chapter will revolve around how this reverse link achieves a very high data rate with the minimum amount of power consumption, that is minimizing the energy per bit transmitted, and proposing a scalable modulation technique for low power applications. Followed by the design considerations of a digitally calibrated oscillator as well as an energy efficient bi-phasic UWB pulse generator, a UWB antenna design shall be presented with considerations towards near field pulse transmission. Finally a energy detection based UWB receiver topology is proposed for testing purposes.
{{< figure src="/images/msc-thesis/s4.png" title="Figure 25: System level abstraction of the UWB transceiver." width="500" >}}
# 15 UWB Pulse Modulation
Let us first consider the two principle modulation techniques illustrated figure 26 that have been the most successful in UWB communication systems, which are binary phase shift keying (BPSK) and pulse position modulation (PPM). BPSK can be directly associated with the continuous wave modulation techniques and has shown to be a good alternative for pulse modulation that does not distort the output spectrum significantly [^37]. PPM is based on temporal delays and advances of the UWB pulse to modulate the signal. Current PPM systems are based on modulation with reference to a receiver oscillator that is locked through a digital Costas loop equivalent that requires transmitter dead time for synchronization. As current pulse generators consume at least several pJ per pulse we may assume that over 80% of the system's power consumption will be due to the actual output pulse driving the antenna.The interest here lies with encoding a single pulse with multiple bits to maximize efficiency. Simply combining the two modulation techniques is the easy way to boost efficiency but may not be worth the increase in system complexity.
{{< figure src="/images/msc-thesis/cnst.png" title="Figure 26: (left) Time-domain representation of BPSK & PPM modulation schemes. (right) Constellation diagrams of BPSK & PPM modulation schemes illustrating the inherent SNR reduction for PPM." width="500" >}}
The bottle neck that prevents a scalable system that encodes multiple pulse positions lies with how the temporal delay are generated in contemporary designs. For non-coherent detection systems these delays must be relatively small and accurate to maintain correct detection on the receiver end which if scaled up would result in too much calibration overhead to tune each pulse position. For coherent based UWB receivers the pulses must be orthogonal with respect to the detection window which is even more challenging for detecting multiple phase states. Instead if the delay of a fixed period is used from a calibrated digital oscillator (DCO) and multiple pulses are allowed within a short reference frame, the scaling of the position encoding mechanism can be improved in a fundamental way while maintaining system simplicity. More importantly, using a DCO allows us to dedicate a lot of resources for fine tuning the delay of a single element where if multiple delay elements need to be used the restricted resources would limit the tuning of the resulting delay and introduce unwanted phase noise.
{{< figure src="/images/msc-thesis/n2.png" title="Figure 27: (left) Simple delay encoded pulses with reference to a DCO clock. (right) Pulses encoded by the cascading of two delay symbols in a single data word." width="500" >}}
As illustrated above in figure 27, the data is essentially encoded in the delay between pulses. More importantly, note that the pulse package is encoded with reference to the first pulse which allows for accurate receiver phase locking. The implications of this type of ‘delay encoding’ are quite significant. First and foremost the energy detection receiver can now actually be asynchronous negating the need for startup dead time. Since efficiency improves only by the logarithm of the maximum delay it is not area efficient to encode large delays but by cascading multiple encoded delays after one another bit rate, area, and efficiency can be traded off with a significant amount of flexibility. Moreover by omitting the last pulse of the package a delay of 0 can be encoded for improved efficiency.
It should also be apparent that this approach has two main draw backs, the first being that it is particularly sensitive to the DCO frequency off sets for long delays that integrate to large amount of phase noise over the signal window. The other drawback is to maintain FCC mask compliance the peak output power of the UWB pulse must be reduced which degrades the signal to noise ratio. On the other hand however this modulation technique can tolerate a temporal equivalent of phase noise equal to half the DCO’s period.
To give further insight to the expected degradation in the bit error rate (BER), let us consider the absolute worst case scenario where the entire word needs to be detected by a linear receiver. That is, each symbol transmitted needs to be detected at the receiver and is subject to the same AWGN from the channel. For simplicity a threshold detection receiver model has been adopted that integrates the incident RF power waveform by self mixing and samples the accumulated energy before resetting the integrator for the next reference window at a period of \\(T_w\\). In addition, let us assume the signal band with is known such that the probability of detecting a pulse, \\(P_{bit}\\), for \\(\frac{E_b}{N_0}\\)\textless $\frac{T_w BW}{2}$ is given by [^17];
$$ P_{bit}=Q\left( \frac{E_b / N_0}{√{2T_w \cdot BW + 2E_b / N_0}} \right) where Q(x)=\int^{\infty}_x \frac{exp(\frac{-t^2}{2})}{√{2\pi}} dt $$
Here \\(E_b\\) and \\(N_0\\) denote the energy in the pulse and AWG noise over the integration window \\(T_w\\). In extension the expected value of the BER for this particular modulation scheme may be evaluated by considering the probability of detecting the whole word correctly, the probability of sending that particular word, and the number of bits transmitted per word. For simplicity assume each word is equiprobable, which is sub-optimal source coding but regardless, then for the simple case of non-cascaded delay encoding the BER may be expressed as;
$$ BER_1 = \frac{1 - \sum\limits_{i=1}^{D_{max}} \left[ \frac{(1-P_{bit})^{i+1}}{D_{max}}\right] }{2+log_2(D_{max})} $$
Where \\(D_{max}\\) is the maximum delay encoded by the transmitter. If the BER of a N times cascaded delay system is to be evaluated then the previous expression is simply adjusted in the same regard to recomputing the expected value and the number of bits per word.
$$ BER_N = \frac{1}{1 + N + \sum\limits_{j=1}^{N} log_2(A_j)} \cdot \left\{ 1 - \frac{1 - \sum\limits_{i=N}^{D_{max}} \left[a_i \cdot (1-P_{bit})^{i+1}\right] } {(\sum\limits_{i=N}^{D_{max}} a_i)} \right\} $$
Here the series \\(a_i\\) denoted the number of ways one can encode a word in the cascaded system with \\(i\\) delays, note that for each cascade of delays the minimum number of delays is 1. The series \\(A_j\\) denotes the maximum possible delay ecoded by the \\(j^{th}\\) cascaded delay and N denotes the number of cascaded delays. To find a closed form expression for th series \\(a_i\\) one must consider the problem of sorting i elements in N sets that are constrained to the carnality given by the series \\(A_j\\). For the proposed system where \\(N=2\\), the series is given by;
$$ a_i \bigg|_{N=2}= (1+ i) - \sum\limits_{j=1}^{2} \left[ \sum\limits_{k=Aj+1}^{i} 1 \right] $$
Where $A_j=\{8 , 4\}$. These results confirm our previous statement that the expected BER worsens as the maximum possible encoded delay is increased but by increasing N this degredation can be aleviated by as the bit rate is increased by N and the N sum over the log maximum delay of each cascaded delay.
# 16 System Architecture
The system architecture abstraction illustrated in figure 28 is the proposed integrated UWB transmitter which consists of three main components; DCO, Delay Modulator, and Pulse shaper. Although the previous discussion has pointed out the general purpose of using an on-chip oscillator it should also be noted that such high frequency oscillators can dissipate a significant amount of power. To alleviate the power hungry behavior of the DCO a feedback loop is introduced into the system that enables very exact duty cycles such that the oscillator is only switched on to generate the required number of delays and is turned off once the delay encoded package is generated saving a significant amount of power as the complete package duration is on average only half the maximum encoded delay for single delay encoded equiproportional set of words.
{{< figure src="/images/msc-thesis/mod.png" title="Figure 28: System level abstraction of the UWB transmitter architecture." width="500" >}}
The proposed system uses a 10MHz reference input clock generated by an accurate crystal oscillator and will be used to both calibrate the DCO trough a frequency locked loop (FLL) as well as being the reference for the first pulse of the data package that partly acts as a preamble. The delay modulator is essentially a pulse swallow circuit where the decision to swallow a pulse (i.e. introduce a delay) is encoded in a shift register feeding the D flip flop.
# 17 Digitally Calibrated Oscillator
The main challenge in designing the DCO lies with the fact the digital oscillators are very prone to variation in the oscillation frequency as a result of variation in supply, process parameters, and layout parasitics/mismatch. The Monte Carlo simulation in figure 29 shows that, if the presented DCO topology were uncalibrated, the oscillation frequency would have a standard deviation of 45MHz which as discussed previously results in large amounts of phase noise at the receiver. To alleviate this problem a two stage calibration mechanism has introduced with a total resolution of 8 bit to assure a large and accurate tunability range of the oscillation center frequency. The 4 most significant bits calibrate the main capacitive load of the DCO which is a binary weighted Metal-Insulator-Metal capacitive array, with unit capacitance of 5fF, by connecting an arbitrary combination of capacitors to ground and leaving the rest floating. The 4 least significant bits calibrate the NMOS driving capability of an inverter which inherently allows for tuning at a much more precise scale as the transistors can be well matched without taking up a considerable amount of area with only fractional differences in their size.
{{< figure src="/images/msc-thesis/MC.eps" title="Figure 29: Monte-Carlo simulation result of the uncalibrated Oscillation frequency." width="500" >}}
The DCO also includes a Frequency Locked Loop (FLL) that during the calibration phase will tune the DCO output frequency to match that of an accurate reference clock. A fully digital implementation was chosen so minimize area and so that the self-calibration loop can be switched off during normal operation. Although Phase Locked Loops (PLLs) are generally preferred for this particular kind of functionality due to their quicker lock-on time, the all-digital FLL in figure 30 surpasses the all-digital PLL in simplicity as no digital loop filter is required.
The principle of operation of the FLL is based on detecting which clock has a faster rate of rising edges by using a simple set reset latch that is set by reference clock and reset by the DCO clock. If the DCO is resetting the latch more often than the reference lock is setting the latch a pulse is generated at the output of the frequency detector that increments or decrements an 8 bit counter that calibrates the DCO proportionally. Similarly if the latch is set more often than reset a pulse is also generated such that the rate of pulses at the output of the frequency detector is directly equal to the absolute difference in frequency between the reference and DCO clock. The state that persists while these pulses are generated indicates whether the DCO frequency must increase or decrease. Note that the generated DCO clock is divided by a factor of 50 such that the 500MHz clock can be calibrated with respect to a low cost off the shelf 10MHz crystal.
{{< figure src="/images/msc-thesis/dco.png" title="Figure 30: Schematic of the Frequency locked loop used to enable self-calibration of the DCO" width="500" >}}
Figure 31 Illustrates that the presented DCO exceeds a 3 sigma tunability range with respect to the expected standard deviation in DCO frequency with a resolution of 1.58MHz which corresponds to oscillation period that is accurate to ±4ps. The DCO consumes an average of $72 \mu W$ during continuous operation.
{{< figure src="/images/msc-thesis/DCO.eps" title="Figure 31: Simulation result of the frequency range capability of the DCO." width="500" >}}
{{< figure src="/images/msc-thesis/step.eps" title="Figure 32: Transient simulation illustrating the response of the FLL due to a step decrease in reference frequency." width="500" >}}
# 18 Bi-phasic UWB Pulse Generator
In order to satisfy the FCC regulations for UWB communication [^12], two different approaches have been presented in previous literature. One approach is based on modulating the envelope of a RF oscillator output which allows for simultaneous UWB communication in multiple frequency bands [^22]. The other approach is based on maximizing the spectral efficiency by fitting the UWB pulse shape to a Gaussian derivative that optimally fits the FCC mask by piecewise modulation of multiple current pulses [^38]. The design proposed here is a hybrid between these two approaches employing a simple all-digital architecture that generates a UWB pulse with improved energy efficiency using an oscillator output shaped by piece wise current pulses.
The pulse generation techniquest presented are has been partly adopted from previous work that used integrated LC components to filter out the unwanted spectrum to meet the FCC mask requirements [^39]. However instead of dissipating the unwanted spectral energy, a lossy LC resonator is used to recycle the unwanted spectral energy and modulate this to its resonant frequency. Abstractly speaking, the inductor is pulsed with current over 180ps. This induces energy that is stored in the magnetic field and is gradually dissipated in the load (over 1ns while the LC pair resonates in response to the impulse). This integrated pulse generator designed is based on a 0.18\\(\mu\\)m CMOS technology using a 1.2V supply and assuming a 50\\(\Omega\\) termination.
{{< figure src="/images/msc-thesis/puls.png" title="Figure 33: Schematic Illustration of the Digital pre-shaping. Note that the relative temporal delays are not to scale." width="500" >}}
The Digital pre-shaper is shown in figure 33. This uses a popular glitch generator to generate 180ps long Gaussian like pulses, which are demultiplexed to two inverter chains to boost the driving capability of the output. It is important to note that these chains have a different output polarity but both output the buffered pulse together with a delayed and inverted pulse, driving the transistors sourcing the inductor with pulsed current (shown in figure 34). The purpose of the delayed pulse is to cancel the DC component generated by the transient impulse response of the lossy LC resonator, by injecting an equal but complementary pulse at the opposite port of the inductor. By driving either the end connected to the load, or the \\(C_{res}\\) end of the inductor first, the polarity of the UWB pulse is well controlled.
The illustration in figure 33 also shows how a simple shift register can interface the UWB transmitter with a parallel input data stream. With reference to fig, it is interesting to note that since the transistor pairs M1, M4, M2, and M3 are matched in terms of driving capability this particular topology is immune to variation in pulse length which may easily distort the performance of aggressive UWB pulse generators that use multiple glitch generators to shape the pulse.
{{< figure src="/images/msc-thesis/rf.png" title="Figure 34: Circuit schematic of the RF section (parasitics not shown) - Lres = 4nH; Cres = 200fF." width="500" >}}
Since both the total pulse energy and pulse width (due to ringing) is directly proportional to the Q of the resonator, one must trade off pulse length for amplitude where a higher Q results in longer ringing but also larger peak to peak values. In this particular case, a single layer 6-turn 8-sided spiral 4nH inductor with poly-silicon ground plane was used with the dimensions 4\\(\mu\\)m, 2:8\\(\mu\\)m, 96\\(\mu\\)m corresponding to the trace width, trace spacing, and outer radius respectively. The pulse energy was tuned to fall below 5% within 1ns to avoid inter symbol interference corresponding to the resonant capacitance of 200fF.
{{< figure src="/images/msc-thesis/TRAN.eps" title="Figure 35: Simulation Results of the bi-phase UWB temporal response illustrating a 350mVpp Amplitude" width="500" >}}
{{< figure src="/images/msc-thesis/DFT.eps" title="Figure 36: Simulated PSD of the designed UWB pulse & the indoor UWB FCC mask as annotated" width="500" >}}
It can be observed in figure 36 that the current output spectrum does not meet the sub 2GHz FCC mask specifications and thus future work based on this UWB pulse generator will filter this particular spectrum using the geometric resonance of the UWB antenna which can efficiently implement a high Q high pass filter and has already been demonstrated feasible [^24]. On that note, this system consumes 1.65pJ/pulse, which corresponds to an average of 16.5\\(\mu\\)W with a pulse rate frequency of 10MHz and has a competitive edge over many previous publications in terms of the energy per pulse figure of merit shown in table.
Table 5: Performance summary and comparison of UWB transmitter.
|Reference | Output (V_{pp}) | Pulse width/BW | Power (pJ/pulse)|
|----|----|----|----|
|[^14] | 700mV | 0.38ns/7.2GHz | 15.4|
|[^40] | 600mV | 0.4ns/7.5GHz | 26.4 |
|[^15] | 500mV | 0.8ns/2GHz | 4.7 |
|[^41] | 180mV | 3.5ns/0.5GHz | 18|
|[^38] | 165-710 mV | 2.4ns/300MHz | 17.5 |
|This Work | 350mV | 1ns/4GHz | 1.65|
# 19 UWB Antenna
With fresh insights from the UWB pulse shaper presented in the previous section, there are a number of observations that can be made with respect to the requirements of the antenna with respect to bandwidth and input impedance. In particular, we require a 22dB rejection of the sub 1.6GHz band with respect to the pass band and a 50 ohm impedance across the 3-7GHz band that needs to be radiated out to the environment. The remaining standard requirements of an antenna are primarily associated with the directionality and gain of the radiation pattern which for the biotelemetry system depend on the orientation of the two antennas which is illustrated below. The antennas will essentially be coupled in the near field which is not ideal in terms of radiation efficiency but sufficient for simple SOC applications where the receiver end is not limited as strictly by power requirements such that additional gain in the RF band can be attained.
{{< figure src="/images/msc-thesis/chnl.png" title="Figure 37: Illustration showing orientation of the antennas with reference to the inductive coils and skin barrier." width="500" >}}
A planar antenna that is directional with one lobe tangential to the plane would be the most desirable for the proposed antenna orientation but the compactness of the antenna is a far more valued requirement. Note that this particular orientation avoids capacitive loading on the antenna where current densities at the highest and allows the UWB antennas to be conveniently distanced from one another without compromising the implant size. Another challenging antenna property that is required is that the radiation pattern must be stable across the ultra-wide band and more importantly that the radiated energy maintains a constant group delay at the receiver side to avoid excessive distortion of the UWB pulse. The last requirement is ultimately the most challenging as it requires the single mode of radiation retained over a bandwidth of several GHz for simple electrically small antenna structures.
A comment should be made with regard to the fundamental limitation of electrically small dipole antennas, as it can be shown that the fractional bandwidth of the antenna explicitly inverse to the quality factor of the antenna and hence it is theoretically possible to achieve UWB specification using these structures. However, the quality factor is directly related to the radiation efficiency by the Chu-Harrington limitations which inhibits the use of compact quarter wavelength dipole structures [^42]. Instead a class of “fat” monopole antennas has been introduced that provide a similar foundation for simple geometric structures that show adequate performance for UWB applications. The success of these structures lie with the many overlapping resonant modes that the geometries exhibit and hence appear to resonate over a large bandwidth. The most successful planar structure according to the demonstrated radiation efficiencies presented in literature has been the elliptical monopole off which we have based our primitive antenna design as well [^43].
{{< figure src="/images/msc-thesis/ant.jpg" title="Figure 38: (left) illustration of the UWB antenna geometric variables. (right) Photo of the exposed prototype UWB antenna. Note the darker gray rectangle indicates high dielectric substrate on both sides of the metalization." width="500" >}}
In addition to the matching requirements of the antenna, it is highly desirable if the antenna is scaled down to the smallest possible size. UWB antennas from literature are primarily based on off the self FR4 substrate have a radiating patch is on the order of $16 cm^2$. In order to scale down the antenna to around the \\(1cm^2\\) area a high dielectric substrate, RO3010, was used. More specifically, the elliptic lobe that is used to match the $50 \Omega$ co-planar transmission line is enclosed by the high dielectric substrate on both sides of the metalization leaving the radiating gap between the ground plane and the ellipse partly exposed on one face in order to avoid deteriorating the radiation efficiency.
{{< figure src="/images/msc-thesis/PROT.eps" title="Figure 39: EM simulation results illustrating the degeneration of the first resonant mode to improve performance." width="500" >}}
The basic geometry in figure 38 illustrates the addition of a elliptic lobe that is placed protruding from the ground plane towards the elliptic patch which was found to give the antenna the desired in-plane directivity of 3dB and improved wide band matching. The ground plane extension generally reduced the Q-factor of the first mode such that its resonance overlaps more continuously with the second mode as may be observed in figure 39 by the gradual improvement in the reflection coefficient as the lobe is extended towards the antenna.
{{< figure src="/images/msc-thesis/A1.eps" title="Figure 40: EM simulation of the \\(S_{11}\\) reflection coefficient for the finalized UWB antenna geometry." width="500" >}}
{{< figure src="/images/msc-thesis/TRNSM.eps" title="Figure 41: Preliminary side-by-side \\(S_{21}\\) transmission characteristic." width="500" >}}
The preliminary EM simulation results in figure 40 show adequate performance over the 3-7 GHz band in terms of a reflection coefficient below -10dB with a constant group delay that only varies by several tens of degrees. Figure 41 illustrates a more insightful the transmission characteristic of the near field coupling that the two antennas would experience placed side by side 1cm apart. The designated bandwidth of interest, 3GHz to 7GHz, has an insertion loss of 20dB and exhibits near negligible fluctuation in the group delay, that is less than 50 ps. The corresponding finalized parameters describing the antenna geometry are listed in table 6.
Table 6: UWB antenna parameters
|Parameter | Length $(\mu m)$|
|----|----|
|R | 5000|
|(R_g) | 400|
|(R_t) | 800|
|G | 290|
|W | 440|
|C | 260|
{{< figure src="/images/msc-thesis/MA.eps" title="Figure 42: (top) Comparison of the measured and simulated \\(S_{11}\\) characteristic. (bot) PSD generated by the UWB pulse shaper for reference." width="500" >}}
The first set of prototype UWB antennas were developed through manual photo chemical etching whose reflection characteristics are shown in figure 43. The sub 5GHz band appears to match the simulation results relatively well while there are some hints of over etching. The band above 5GHz however is characteristically very different from simulations. The author believes this to be the result of edge roughness introduced by uneven distribution of spray-on photo resist that was used in the development stage as a number of other antenna samples had miniature holes in the ground plane indicating a non-homogeneous etch. There is still a level of adequacy for the measured antenna as the UWB pulse PSD covers the entire band that exhibits the ability to radiate. The high Q notch at 5.5GHz however may significantly distort UWB pulses due the corresponding fluctuation in group delay. The prototype antenna does present a respectable 2GHz bandwidth.
{{< figure src="/images/msc-thesis/chmbr.png" title="Figure 43: Photograph of the UWB antenna under test in the Imperial College anechoic chamber." width="500" >}}
# 20 Reciever
The receiver presented in this section is primarily aimed at system completeness and the testability of the power optimized UWB transmitter system as many of the strict constraints that concern the implanted system no longer apply to the external system. UWB receiver architectures generally consist of almost completely digital architectures including RF ADCs with the exception of front end tunable low noise amplifiers for pre-acquisition gain. Pulse detection methods are very much translated into the DSP domain where channel approximation algorithms have proven to be very successful at filtering and detective UWB pulses mainly because of critical and overly complex filtering requirement that needs to adapt to both the channel and the effectively unknown input spectrum of the pulse that highly distorted after transmission [^44].
{{< figure src="/images/msc-thesis/rec.png" title="Figure 44: System level abstraction of the reciever architechture." width="500" >}}
Since both the most basic coherent and non-coherent UWB receiver architectures are beyond the scope of this project a very simple energy detection system has been derived that assumes no strong interferer is transmitting in the UWB spectrum such that the UWB pulse can easily be detected by energy thresholding.
Based on this detection, a set of trigger pulses are generated ideally identical to those generated at the output of the delay modulator. Using the same DCO, the delay between these triggers can be counted by a set of registers such that the encoded information is extracted from trigger circuit recovering all data sent from the transmitter.
{{< figure src="/images/msc-thesis/dly.png" title="Figure 45: (left) Schematic of the implemented delay-locked loop. (right) Analog tuned delay element." width="500" >}}
To synchronize the two systems a delay locked loop is introduced at the receiver that uses analog delay elements in combination with a charge pump phase detector[^45]. The control loop illustrated in figure 45 synchronizes the output of the delay line \\(V_{sync}\\) with the reference clock \\(V_{ref}\\) by continuously integrating the phase difference of the two signals. As charge accumulates onto \\(C_p\\), the resulting voltage biases four cascaded delay elements that each can efficiently introduce delays up to 25ns. The actual mechanism of the analog delay element is based on around the current starving the inverter structure of M5 M4 such that the time it takes to reach the switching point of the output inverter M12 M13 is controlled. Note that once the switching point is achieved the state rapidly regenerates itself due to M8 M9 assuring a fast transition. More importantly the structure negates short circuit currents that may be introduced by the slow switching of the first stage through the transistors M14 and M11.
# 21 UWB System Summary
Transient simulations of the UWB transmitter, illustrated in figure 46, have confirmed the general operation of the delay modulator and extracted simulation of the whole system have indicated a power consumption of $68.9\mu W$ for a PRF of 10MHz. Since the transmitter is encoding the pulses with an effective data rate of 77.5 Mb/s these results correspond to a energy per bit FOM of 890fJ per bit. By extrapolating these results to find the power consumption of the system excluding the UWB pulse shaper, it can be stated that the modulator consumes 470fJ per DCO oscillation and corresponds to 34% of the over power consumption.
{{< figure src="/images/msc-thesis/POWER.eps" title="Figure 46: System level simulation results of the DCO, Modulator, and pulse shaper outputs as well as the accumulated power consumption." width="500" >}}
Although the total phase noise expected at the output of the delay modulator still needs to be characterized, the complete UWB system presents respectable performance in terms of power consumption. And from figure 42 it can be observed that there is an expected -20dB rejection in the sub 2GHz band with reference to the 3-6GHz pass band which implies that the radiated spectrum should meet the FCC requirements accordingly. It can be observed from figure 46 that for closely spaced pulses the pulse amplitude is slightly degraded due to ISI at the transmitter. This type of hysteresis is generally unwanted but can be improved by either shortening the pulse or by reducing the DCO oscillation frequency, both of which degrade the over all system power performance.
Table 7: Performance overview of recent UWB transmitters
|Reference | [^16] | [^46] | [^47] | [^25] | [^48] | [^38] | This Work |
|----|----|----|----|----|----|----|----|
|Technology (nm) | 65 | 90 | 90 | 65 | 65 | 65 | 180 |
|Modulation | Delay | PPM | BPSK | PPM | OOK | PPM | Delay |
|Avg. Power (W) | 660n | 718u | 3.3m | 600u | 217u | 4.36m | 68.9u |
|PRF (Hz) | 1.3M | 16.7M | 100M | 50M | 24M | 15.6M | 10M |
|Energy per bit (J/bit) | 300f | 37p | 33p | 12p | 8.5p | 17p | 890f|
|FCC compliant | No | Yes | Yes | Yes | Yes | Yes | Yes |
With reference to table 7 it can be noted that the delay modulation generally achieves respectable energy per bit FOMs in comparison to other modulation schemes as the highly energetic pulses are encoded with multiple bits. Note that even though our design was based on a less aggressive \\(180nm\\) process the UWB pulse generator allowed us to achieve comparable performance to designs that were implemented in \\(65nm\\) technologies for which the transistors achieve a transition frequency (\\(F_T\\)) that extends far beyond the UWB bandwidth which is essentially a prerequisite for employing the piece-wise reconstruction of analytically optimal wavelets.
The two figures 47 & 48 show the full custom layout that was designed for the proposed UWB transceiver. The actual transistor level layout of transmitter and receiver combined occupy approximately $100\mu m$ by $200\mu m$ with a separate self calibrated DCO for each section. The overall area is increased by 300% due to the on-chip inductor that was integrated for the UWB pulse generator. The figure 48 also shows a large array of decoupling capacitors (in yellow) that remove noise from the supply pads that may influence the DCO operation and introduce additional phase noise.
{{< figure src="/images/msc-thesis/die1.png" title="Figure 47: Detail of the Full custom Digital layout of UWB, counter clockwise, TX [DCO(red), Delay Modulator(l. blue), UWB Pulse Generator(orange)] & UWB RX [DCO(purple), Demodulator(green), DLL(yellow), RF Energy detector(d. blue)]" width="500" >}}
{{< figure src="/images/msc-thesis/die2.png" title="Figure 48: Layout sent for tape out illustrating the guard-ring (blue), RF pads (red), Integrated Inductor (green), and UWB TX/RX (green)." width="500" >}}
# 22 Conclusion
This thesis has addressed the design considerations of an implantable biotelemetry system with respect system level optimizations and presented the circuit level innovation that focused on optimizing power requirements.
During the development of the forward link in particular the modulation techniques of contemporary literature were evaluated and, with respect to the projected system requirements, BPSK modulation was found to be the most promising. This was illustrated by the fact that BPSK modulation minimizes the off-chip components and by employing the proposed modulation scheme relatively high bit rates were achieved without degrading the overall power transfer efficiency of the forward link. Moreover, the efficiency achieved illustrates that the class-E amplifier operation shows a good synergy with the BPSK modulation mechanism without the need to supply modulation techniques or additional filtering components.
Since UWB application for biomedical implants is a relatively new and emerging field a significant amount of effort was put toward developing a scalable delay encoding system that could give way for systems that maximize efficiency FOMs like sub 100fJ energy dissipation per bit transferred. The presented work allows numerous bits to reliably be encoded into a single energetic pulse with a good control over how robust the encoding scheme is towards phase noise as only one element is required to be tuned. The delay modulator presented here is for that reason integrated with a self-calibration frequency locked loop that keeps chip area to a minimum. A conservative estimate bit error rates due to channel induced AWG noise was also presented to given insight to how higher order delay encoding effects the transmission of data. With the theoretical basis covered, circuit specific elements were developed such as a widely tunable digital oscillator and a particularly energy efficient UWB pulse generator based off the impulse response of a LC resonator. In extension to the transmitter, an UWB antenna was designed where a significant improvement in the low-frequency group-delay and reflection co-efficient was found if the first resonant mode was degenerated by an asymmetric extension of the ground plane. The antenna was fabricated but fine tuning of the etching process was still required for the EM simulation results to match the measured response at the frequencies above 5GHz. Finally a simple energy detection receiver is developed that will allow testing of the full custom digital layout that was designed for fully integrated the UWB transceiver system.
# 23 Future Work
Due to the broad scope telemetry systems there are a wide range of possible future developments that can be considered in extension to what has been presented here. First and foremost it would be important to develop a more standardized receiver that is based on GHz sample acquisition through FPGA and uses a channel estimation adaptive filter to detect the delay encoded words sent by the implanted device. Secondly the UWB antenna needs to go through several process development cycles under a automated fabrication process until the antenna is well characterized. In addition the antenna need to be tuned to match the impedance of the human body right under the skin for maximum radiation efficiency which may even allow for the system to be placed deeper within the body and may be of interest for future work in association to RF powered implants. The final aspect that should be a worthwhile investment lies with developing an integrated rectifier and regulator for the forward transmission link.
# Refernces:
[^1]: D.D. Wentzloff, ''Pulse-based ultra-wideband transmitters for digital communication,'' PhD in Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Aug. 2007.
[^2]: K.Wise, D.Anderson, J.Hetke, D.Kipke, and K.Najafi, ''Wireless implantable microsystems: high-density electronic interfaces to the nervous system,'' Proceedings of the IEEE, vol.92, no.1, pp. 76 -- 97, jan 2004.
[^3]: A.Eftekhar, S.Paraskevopoulou, and T.Constandinou, ''Towards a next generation neural interface: Optimizing power, bandwidth and data quality,'' in Biomedical Circuits and Systems Conference (BioCAS), 2010 IEEE, nov. 2010, pp. 122 --125.
[^4]: S.D. M.G. Olivo, J.;Carrara, ''Optimal frequencies for inductive powering of fully implantable biosensors for chronic and elderly patients,'' in Sensors, 2010 IEEE, nov. 2010, pp. 99 --103.
[^5]: P.C. Y.Luo, C.Winstead, ''125mbps ultra-wideband system evaluation for cortical implant devices,'' in Engineering in Medicine and Biology Society,EMBC, 2012 Annual International Conference of the IEEE, Sept. 2012, pp. 779--782.
[^6]: S.M.T. Poon, A.S.Y.;O'Driscoll, ''Optimal operating frequency in wireless power transmission for implantable devices,'' in Engineering in Medicine and Biology Society, 2007. EMBS 2007. 29th Annual International Conference of the IEEE, aug. 2007, pp. 5673 --5678.
[^7]: D.Laqua, T.Just, and P.Husar, ''Measuring the attenuation characteristics of biological tissues enabling for low power in vivo rf transmission,'' in Engineering in Medicine and Biology Society (EMBC), 2010 Annual International Conference of the IEEE, 31 2010-sept. 4 2010, pp. 1437 --1440.
[^8]: J.C. Schuder, J.H. Gold, and H.E. Stephenson, ''An inductively coupled rf system for the transmission of 1 kw of power through the skin,'' Biomedical Engineering, IEEE Transactions on, vol. BME-18, no.4, pp. 265 --273, july 1971.
[^9]: M.Ghovanloo and K.Najafi, ''A wideband frequency-shift keying wireless link for inductively powered biomedical implants,'' Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.51, no.12, pp. 2374 -- 2383, dec. 2004.
[^10]: K.Finkenzeller, RFID Handbook: Fundamentals and Applications in Contactless Smart Cards and Identification, 2nded.\hskip 1em plus 0.5em minus 0.4em elax New York, NY, USA: John Wiley & Sons, Inc., 2003.
[^11]: G.Marconi, Transatlantic Wireless Telegraphy, ser. Pamphlets on electricity.\hskip 1em plus 0.5em minus 0.4em elax New York, NY, USA: E. Eastwood, editor, Wiley, march 1908.
[^12]: ''Federal communications commission (fcc), first report and order in the matter of revision of part 15 of the commission's rules regarding ultra wideband transmission systems, et-docket 98-153, fcc 02-48, released 22 april 2002.''
[^13]: T.M. Cover and J.A. Thomas, Elements of Information Theory (Wiley Series in Telecommunications and Signal Processing).\hskip 1em plus 0.5em minus 0.4em elax Wiley-Interscience, 2006.
[^14]: H.Kim, D.Park, and Y.Joo, ''All-digital low-power cmos pulse generator for uwb system,'' Electronics Letters, vol.40, no.24, pp. 1534 -- 1535, nov. 2004.
[^15]: T.-A. Phan, V.Krizhanovskii, S.-K. Han, S.-G. Lee, H.seo Oh, and N.-S. Kim, ''4.7pj/pulse 7th derivative gaussian pulse generator for impulse radio uwb,'' in Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, may 2007, pp. 3043 --3046.
[^16]: M.Mark, Y.Chen, C.Sutardja, C.Tang, S.Gowda, M.Wagner, D.Werthimer, and J.Rabaey, ''A 1mm3 2mbps 330fj/b transponder for implanted neural sensors,'' in VLSI Circuits (VLSIC), 2011 Symposium on, june 2011, pp. 168 --169.
[^17]: J.Proakis, Digital Communications, 4thed.\hskip 1em plus 0.5em minus 0.4em elax McGraw-Hill, Aug. 2000.
[^18]: J.Agbinya and H.Truong, ''A comparison of ultra wideband signal functions for wireless ad hoc networks,'' in Information Technology and Applications, 2005. ICITA 2005. Third International Conference on, vol.2, july 2005, pp. 677 -- 682 vol.2.
[^19]: M.Abtahi, M.Mirshafiei, J.Magne, L.Rusch, and S.LaRochelle, ''Ultra-wideband waveform generator based on optical pulse-shaping and fbg tuning,'' Photonics Technology Letters, IEEE, vol.20, no.2, pp. 135 --137, jan.15, 2008.
[^20]: J.Moll and S.Hamilton, ''Physical modeling of the step recovery diode for pulse and harmonic generation circuits,'' Proceedings of the IEEE, vol.57, no.7, pp. 1250 -- 1259, july 1969.
[^21]: I.Immoreev and P.Fedotov, ''Ultra wideband radar systems: advantages and disadvantages,'' in Ultra Wideband Systems and Technologies, 2002. Digest of Papers. 2002 IEEE Conference on, 2002, pp. 201 -- 205.
[^22]: A.T. Phan, J.Lee, V.Krizhanovskii, Q.Le, S.-K. Han, and S.-G. Lee, ''Energy-efficient low-complexity cmos pulse generator for multiband uwb impulse radio,'' Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.55, no.11, pp. 3552 --3563, dec. 2008.
[^23]: M.Mirshafiei, M.Abtahi, P.Larochelle, and L.Rusch, ''Pulse shapes that outperform traditional uwb antenna/waveform combinations,'' in Global Telecommunications Conference (GLOBECOM 2010), 2010 IEEE, dec. 2010, pp. 1 --5.
[^24]: K.Li, ''Uwb bandpass filter: structure, performance and application to uwb pulse generation,'' in Microwave Conference Proceedings, 2005. APMC 2005. Asia-Pacific Conference Proceedings, vol.1, dec. 2005, p. 4 pp.
[^25]: Y.Park and D.Wentzloff, ''An all-digital 12pj/pulse 3.1 - 6.0ghz ir-uwb transmitter in 65nm cmos,'' in Ultra-Wideband (ICUWB), 2010 IEEE International Conference on, vol.1, sept. 2010, pp. 1 --4.
[^26]: H.S. Ian and P.K. Konrad, ''How advances in neural recording affect data analysis,'' pp. 139 -- 142, Feb. 2011.
[^27]: X.Xu, X.Zou, L.Yao, and Y.Lian, ''A 1-v 450-nw fully integrated biomedical sensor interface system,'' in VLSI Circuits, 2008 IEEE Symposium on, june 2008, pp. 78 --79.
[^28]: M.S. Chae, Z.Yang, M.Yuce, L.Hoang, and W.Liu, ''A 128-channel 6 mw wireless neural recording ic with spike feature extraction and uwb transmitter,'' Neural Systems and Rehabilitation Engineering, IEEE Transactions on, vol.17, no.4, pp. 312 --321, aug. 2009.
[^29]: F.Shahrokhi, K.Abdelhalim, D.Serletis, P.Carlen, and R.Genov, ''The 128-channel fully differential digital integrated neural recording and stimulation interface,'' Biomedical Circuits and Systems, IEEE Transactions on, vol.4, no.3, pp. 149 --161, june 2010.
[^30]: S.Rai, J.Holleman, J.Pandey, F.Zhang, and B.Otis, ''A 500 $\mu$ w neural tag with 2 $\mu$ vrms afe and frequency-multiplying mics/ism fsk transmitter,'' in Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International, feb. 2009, pp. 212 --213,213a.
[^31]: W.Wattanapanitch and R.Sarpeshkar, ''A low-power 32-channel digitally programmable neural recording integrated circuit,'' Biomedical Circuits and Systems, IEEE Transactions on, vol.5, no.6, pp. 592 --602, dec. 2011.
[^32]: R.Walker, H.Gao, P.Nuyujukian, K.Makinwa, K.Shenoy, T.Meng, and B.Murmann, ''A 96-channel full data rate direct neural interface in 0.13 $\mu$ m cmos,'' in VLSI Circuits (VLSIC), 2011 Symposium on, june 2011, pp. 144 --145.
[^33]: \BIBentryALTinterwordspacingR.Sarpeshkar, Ultra Low Power Bioelectronics: Fundamentals, Biomedical Applications, and Bio-Inspired Systems, ser. Ultra Low Power Bioelectronics: Fundamentals, Biomedical Applications, and Bio-inspired Systems.\hskip 1em plus 0.5em minus 0.4em elax Cambridge University Press, 2010. [Online]. Available: \urlhttp://books.google.co.uk/books?id=eYPBAyDRjOUC\BIBentrySTDinterwordspacing
[^34]: U.-M. Jow and M.Ghovanloo, ''Design and optimization of printed spiral coils for efficient transcutaneous inductive power transmission,'' Biomedical Circuits and Systems, IEEE Transactions on, vol.1, no.3, pp. 193 --202, sept. 2007.
[^35]: C.Zierhofer and E.Hochmair, ''Geometric approach for coupling enhancement of magnetically coupled coils,'' Biomedical Engineering, IEEE Transactions on, vol.43, no.7, pp. 708 --714, july 1996.
[^36]: A guide to measurement technology and techniques, 4thed.\hskip 1em plus 0.5em minus 0.4em elax Agilent Technologies, Ltd., 2009.
[^37]: M.Welborn, ''System considerations for ultra-wideband wireless networks,'' in Radio and Wireless Conference, 2001. RAWCON 2001. IEEE, 2001, pp. 5 --8.
[^38]: P.Mercier, D.Daly, and A.Chandrakasan, ''An energy-efficient all-digital uwb transmitter employing dual capacitively-coupled pulse-shaping drivers,'' Solid-State Circuits, IEEE Journal of, vol.44, no.6, pp. 1679 --1688, june 2009.
[^39]: L.Moreira, W.van Noije, D.Silveira, S.Kofuji, and C.Sassaki, ''A small area 2.8pj/pulse 7th derivative gaussian pulse generator for ir-uwb,'' in Microwave Conference Proceedings (CJMW), 2011 China-Japan Joint, april 2011, pp. 1 --4.
[^40]: S.Bourdel, Y.Bachelet, J.Gaubert, M.Battista, M.Egels, and N.Dehaese, ''Low-cost cmos pulse generator for uwb systems,'' Electronics Letters, vol.43, no.25, pp. 1425 --1427, 6 2007.
[^41]: T.-A. Phan, J.Lee, V.Krizhanovskii, S.-K. Han, and S.-G. Lee, ''A 18-pj/pulse ook cmos transmitter for multiband uwb impulse radio,'' Microwave and Wireless Components Letters, IEEE, vol.17, no.9, pp. 688 --690, sept. 2007.
[^42]: W.Geyi, ''Physical limitations of antenna,'' Antennas and Propagation, IEEE Transactions on, vol.51, no.8, pp. 2116 -- 2123, aug. 2003.
[^43]: C.-Y. Huang and W.-C. Hsia, ''Planar elliptical antenna for ultra-wideband communications,'' Electronics Letters, vol.41, no.6, pp. 296 -- 297, march 2005.
[^44]: C.Carbonelli and U.Mengali, ''Synchronization algorithms for uwb signals,'' Communications, IEEE Transactions on, vol.54, no.2, pp. 329 -- 338, feb. 2006.
[^45]: M.Kurchuk and Y.Tsividis, ''Energy-efficient asynchronous delay element with wide controllability,'' in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 30 2010-june 2 2010, pp. 3837 --3840.
[^46]: D.Wentzloff and A.Chandrakasan, ''A 47pj/pulse 3.1-to-5ghz all-digital uwb transmitter in 90nm cmos,'' in Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, feb. 2007, pp. 118 --591.
[^47]: B.Qin, H.Chen, X.Wang, A.Wang, Y.Hao, L.Yang, and B.Zhao, ''A single-chip 33pj/pulse 5th-derivative gaussian based ir-uwb transmitter in 0.13 $\mu$m cmos,'' in Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, may 2009, pp. 401 --404.
[^48]: H.Miranda and T.Meng, ''A programmable pulse uwb transmitter with 34% energy efficiency for multichannel neuro-recording systems,'' in Custom Integrated Circuits Conference (CICC), 2010 IEEE, sept. 2010, pp. 1 --4.

580
content/publications/2011/implantable-biotelemetry.md_bk Normal file
View File

@ -0,0 +1,580 @@
---
title: "Implantable Biotelemetry"
date: 2012-09-13T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
- chapter
- wireless
- CMOS
- biomedical
- implants
---
Supervised by: Dr Timothy G. Constandinou
A Thesis submitted in fulfilment of requirements for the degree of Master of Science Analogue and Digital Integrated Circuit Design of Imperial College
London, Department of Electrical and Electronic Engineering.
# Introduction
Recent developments in the field of neuroscience and health monitoring have identified the need for biotelemetry systems based around a ultra efficient power standard to allow for next generation biomedical implants and distributed en-vivo sensory networks. The work presented here engages the design of the biotelemetry forward and reverse links with a top down perspective exploring the loss mechanics and inefficiencies of concern. This development has led to the design of an optimized class-E based inductive link that includes a improved modulation scheme specific to the operation of the power amplifier as well as a integrated low complexity BPSK demodulator. In addition a frame work was developed around a scalable UWB delay modulation scheme that improves transmitter efficiency as well as circuit level designs for a widely tuneable digital oscillator and a particularly energy efficient UWB pulse generator based off the impulse response of a LC resonator. In extension an UWB antenna is designed with significant improvements in the low-frequency group-delay and reflection co-efficient and a simple energy detection receiver is developed that will allow testing of the full custom digital layout that is designed for fully integrated the UWB transceiver system in 0.18 um CMOS technology. The presented forward link achieves achieve a power transmission efficiency of 46% and 34% while transmitting 250 kb/s. The UWB transmitter consumed 68.9 uW of power for a PRF of 10 MHz that corresponds to a data rate of 77.5 Mb/s.
## Motivation
It has been slightly over 100 years since the advent of the world’s first ‘transistor’ and even more now than a decade ago, revolution has almost become synonymous with the advancement of the microelectronics industry with impacts that change the very backbone of society. The revolution of the last decade surely belonged to that of mobile devices industry which experienced an increase in user end data demand by over a hundred fold. On the other end of the spectrum however this surge of wireless connectivity of the past decade has synergized and inspired a new foundation of ideas for biomedical systems.
These novel systems are based around digitizing the medical diagnosis and treatment trough wireless en-vivo sensory networks for true personalized medicine. By employing electronic implants that have demonstrated incredible potential due to the dense functionality of CMOS technology, the implantable system on chip have shown potential for restoring vision, treating paralysis, severe epilepsy and Parkinson’s disease \cite{1258173}. In addition to applications for novel heath monitoring systems and home-stay medication, bio-telemetry links to implanted devices have enabled the simultaneous study of several hundreds of functioning neurons in a localized area through multi electrode arrays (MEAs). These studies have given crucial insight to behavioural models of the brain for fields such as neuroscience. Recent advances have allowed patients with a spinal impairment to interact with the world through a brain machine interface bringing society closer to visions such as J. C. R. Licklider’s Man-Computer Symbiosis.
Although the idea of wireless powering of implanted devices has been around since the early 1960s for long term artificial cardiac pacemakers, the focus of current generation bio-telemetry systems has shifted from a functional orientation to building a framework for reliability and performance directed at commercial applications. As a result of new applications finding their way to employing bio-telemetry links where there are a net set challenges associated with handling the transmission of substantial data rates. The more recent neural recording system-on-chip (SOC) in particular has presented very challenging power requirements for the radio frequency (RF) transmitter driven by the restriction on heat dissipation in order to prevent cell damage. As the demand for number of simultaneously neurons recorded exponentially increases every year, a significant amount of interest has been directed at finding more efficient alternatives for transmitting data out of the implant wirelessly and exploiting specialized encryption algorithms that reduce data rate requirements such as inter-spike-interval figures & spike-feature extraction \cite{5709586}.
In similitude to the miniaturization principle of microelectronics, biomedical system miniaturization is also seen as an important merit that improves the comfort of the subject. Consequently the size of radiating elements inherent to the telemetry system is also an important topic for consideration that with recent demonstrations has brought to light the viability of power and data transmission via GHz radiation and may change bio-telemetry to a more specialized RFID tag based medical system in the future.
This thesis presents various system level reductions and efficiency optimizations on both the forward transmission link, from the external system towards the implant, as well as the reverse transmission link, from the implant to the external system. The overall focus revolves around presenting scalable topologies that may allow significant improvements in power consumption of the overhead transmission components which is key in enabling future neural studies and ultra-low power telemetry systems that can be incorporated with RF energy harvesting technologies to give way for next generation biomedical implants based on multi-element sensory networks. All schematic designs presented in this document are based on a 0.18 um CMOS technology using a 1.2 V supply. Circuit level simulations were carried out using Cadence IC5.1.41 with foundry provided PSP models. 2D & 3D electromagnetic simulations were carried out using the CST MICROWAVE STUDIO package.
## Contributions
The main contribution presented by this thesis are outlined below
- A complete wireless power transmission link trough coupled coil that achieves a net 45% efficiency with the measured coil characteristics as well study on the trade offs of circular and rectangular coil geometries.
- With the developed class E power amplifier an energy efficient BPSK modulation technique is introduced that not require additional supply modulation techniques in addition to a low power BPSK demodulator that consumes 1.5 uW from the unregulated supply.
- Framework for the UWB delay modulation scheme with conservative estimated on BER values and a scalable architecture for implementation.
- Complete UWB transceiver architecture is developed that transmits data at 890 fj/bit for which a full custom digital layout is designed that occupies 200 um by 300 um.
- Miniaturized UWB antenna design that occupies 1.3 cm² and achieves -12 dB reflection coefficient and sub 50 ps group delay over a bandwidth of 4GHz.
# Background
The neural sensory implants of interest is generally located in a vital location such as under the skull and characteristically needs to process large aggregates of data as a multitude of neurons are recorded simultaneously for prolonged periods of time. As a result it is particularly challenging to power the implant as monthly operations to replace a battery can severely endanger the subject to infection. Moreover power requirements of several milliwatt would require a large battery. The inductive link in principle allows for a relatively efficient transmission of power without puncturing the skin while giving room for data transmission.
The overall design of telemetry systems pertains to the field of radio frequency electronic circuit design with the inclusion of a few essential aspects from power electronics. The biomedical telemetry application however tends to relax the high frequency requirements and focus more on efficient power induction that is more suitable below the 100 MHz frequency range for maximizing power gain \cite{5690847}. Although elaborate antenna systems are still designed to allow for full system-on-chip (SOC) integration the trend towards ubiquitous adoption of integrated UWB transmitters in implants seems to have given a different spin on the RF design aspect. As most bio-telemetry communication links are enabled trough near field coupling there is little gained for high antenna directivity and un-optimized RF coils have been demonstrated sufficient for UWB trough-skin boundary transmission \cite{60956}. Moreover design theory behind UWB is more based on time-domain analysis aimed at minimizing pulse distortion where the traditional harmonic frequency analysis fails to give sufficient insight.
In this chapter, a review of the various system level topologies that have been used in recent bio-telemetry systems is presented by evaluating the strengths and weaknesses of each design methodology. In extension, a design methodology is briefly presented for the class-E power amplifier that is ubiquitous in inductively coupled power links. In addition, an introduction to UWB technology is presented together with a review of state-of-the-art neural interface systems to project our system requirements and topology.
## Bio-Telemetry Schemes
Abstractly speaking, modern telemetry systems can be seen as a 3-channel system. As illustrated in figure 1 these channels correspond to power transmission, forward data transmission, and reverse data transmission. Although 3-channel systems have been reported where each channel is optimized for a single function in terms of carrier frequency and coil/antenna designs the component count is very high. In accordance to the characteristic of the reverse link where a fast bit rate is generally desired, the reverse link is often designed with explicit RF considerations by introducing a far field antenna but it has been demonstrated that single loop coils have considerable potential for near field coupling of RF radiation through the skin \cite{4353634}. The power transmission is generally done through inductive coupling at a frequency where the Q-factor of the coils is maximized and losses from the environment are kept to a minimum \cite{5626705}. The forward link may very similarly be designed trough inductive coupling but a higher carrier frequency is preferred to allow for more substantial data rates while trading off losses induced by the coils which have been shown to dominate over tissue absorption for frequencies above 100 KHz \cite{4502849}.
{{< figure src="/images/msc-thesis/s1.png" title="Figure 1: Generalized system architecture of a bi-directional telemetry system for medical implants." width="500" >}}
Contemporary implant systems have mainly focused on improving the system by choosing the right modulation techniques that allow two channels to by combined into one while still achieving similar performance and there by significantly reducing the number of off chip components on the implant side. In some sense this also relaxes the inter-channel interference as the as the interaction between power forward data transmission, for example, is modelled much more explicitly when combined without interference being prone to variations in the coupling coefficients.
The simplest implementation for data modulation is amplitude modulation, ASK, of power wave form, where the DC-DC regulator driving the supply of the PA is directly adjusted according to a binary bit stream. However a supply regulation control loop is generally implemented on a system level that fixes the average induced power such that the supply at the implant side maintains a stable voltage. This control loop is rather essential as the coils may misalign or move during operation such that the supply must be recalibrated to avoid component damage or injuries due to overheating hence it is not desirable to introduce modulation noise directly into the control loop.
The alternative to ASK is FSK or PSK which allow for much faster data rates due to the fact that the detection of the phase/frequency shift is not limited by the relaxation time of the resonant pair at the implant side and since the Q-factors of the inductors is desirably large to minimize losses this response time limits modulation speeds \cite{1364109}. FSK generally doubles the number of resonant components required for power transmission to be efficient at both frequencies and may be considered undesirable but, unlike ASK and PSK, modulation does not degrade the power transmission efficiency. A binary phase shift keying can achieve faster uplink data rates than ASK without the need of additional passives but as will be discussed in chapter 3 the resonant modes of the two phase states are complementary to one another such that during phase transition a significant amount of power lost which results in the degradation in transmission efficiency when data is being transmitted trough the link. Technically speaking, inefficiency during modulation is not a major concern as data sent through the forward link is primarily used during system set up and remains inactive for the majority of the implant’s lifetime but it requires additional consideration to avoid system failure during the transmission of large amount of calibration data.
More recently the reverse link has also been integrated into the power transmission channel as well by using Load Shift Keying (LSK). This modulation technique is based on the fact that the current drained from the secondary power coil L2 is coupled to the total power drained from the power amplifier. A common implementation of this illustrated in figure 2 where a simple transistor driven by a OOK modulated data stream pulses a short circuit current from L2 which can be detected at the primary power coil. Note that the PA can still be modulated with the forward link data stream. This approach introduces a significant amount of simplicity into the design as power and bi-directional data is transmitted through a single coil potentially eliminating all off-chip components. In addition power hungry driver circuitry required for driving the antenna/coil of the reverse link has also been eliminated. The drawback naturally lies with the fact that the two data channels interfere with one another more severely than with separate coils regardless of the modulation schemes and moreover all data rates are limited by the bandwidth the inductive link. In addition, a significant amount of strain is put on the requirements of the on-chip supply regulator as the average power induced from the coil is continuously being modulated with higher frequency components from the OOK switching characteristic and may require the high-performance analogue instrumentation components to have differential architectures that require more power and area.
{{< figure src="/images/msc-thesis/s2.png" title="Figure 2: LSK based telemetry system architecture." width="500" >}}
## Power Amplifiers for Biomedical Applications
A quintessential aspect of power induction is minimizing losses at all stages of the power transmission link where the power amplifier used to be at the centre of attention but with the introduction of switch mode power amplifiers the near lossless operation has now become standard for MHz PA applications. The more classical load driving techniques that use class B or class C modes of operation made achieving over 70\% efficiency with a varying load such as an implant challenging due to the matching requirements. Switch mode power amplifiers generally refer to amplifier topologies where the main driving transistor is severely over driven to the extent that the output is far into the non-linear domain by clipping effects such that the transistor can essentially be treated as an ideal switch. The basis of lossless switch mode operation lies with making sure the power transistor does not dissipate power and disregarding how nonlinear the intermediate waveforms are as long as a high-Q LC components are used to terminate all unwanted harmonics an ideal efficiency is expected at the load as all the sources of loss are negated. Since the switch mode structure inherently requires a LC pair it is ideal for driving an inductive load as the coil can be absorbed into the network without additional design considerations.
In order to gain further insight to the operation of switch mode amplifiers we shall present a time domain analysis of the switch mode Class E amplifier topology which allows us to mitigate nearly all losses by absorbing the power transistor paracitics into the network.
{{< figure src="/images/msc-thesis/pa1.png" title="Figure 3: Detailed Class-E PA schematic and the inductive link." width="500" >}}
The topology illustrated in figure 3 shows a power transistor biased by a choke inductor driving the primary coil which is coupled to the secondary coil that drives a half-wave rectifier. It is assumed that the DC load, coil Q-factor, and coil inductance is known for this analysis as well as \\( C_{L2} \\) being chosen according to the required switching frequency such that it forms a resonant tank with \\( L_2 \\). The actual Class-E operation is derived trough the biasing condition of the transistor with a over-driven digital input which allows the transistor to be approximated by an ideal switch. More over it can be assumed that the current driving the primary & secondary coils is purely sinusoidal as the \\( L_1 C_{L1} \\) tank is used to filter out non linearities introduced by the switching operation of the transistors. Before going into analytical details, the overall circuit needs to be reduced to a simple PA structure driving a single complex load. Note that the effective AC load that the rectifier presents to the secondary coil can be approximated in term of expected voltage drop across the diode bridge and the DC load resistor, that is;
$$ R_{AC} = \frac{1}{2} \frac{(V_{Load} + V_{Diode})^2}{P_{Load} P_{Diode}} || R_{Q2} $$
Now, using simple circuit techniques the circuit can be further reduced at the resonant switching frequency \\( \omega_s = (C_{L2} \cdot L_2 )^{-1/2} \\) where the resonant tank at the secondary coil provides the largest reduction in coil losses \cite{861917}.
{{< figure src="/images/msc-thesis/pa2.png" title="Figure 4a: Circuit schematic illustrating circuit reductions." width="500" >}}
{{< figure src="/images/msc-thesis/pa3.png" title="Figure 4b: Schematic of the reduced circuit representing a Class-E PA with inductive load." width="500" >}}
Note that the series resistance of \\( L_1 \\) may directly be absorbed by the effective real load \\( R_{EL} \\) and the series resistance of \\( L_2 \\) is absorbed trough equivalent loss of the unloaded Q-factor corresponding to the resonant \\( L_2 C_{L2} \\) tank. Formally, it has been assumed that the ac current observed at the resistive load purely sinusoidal and expressed as follows;
$$ i_{R}(\theta) = I_{rf} \cdot cos( \omega_s t ) = m I_{dc} \cdot cos( \theta ) $$
Where m is the ratio between \\( I_{rf} \\) and \\( I_{dc} \\) and \\( \omega_s t \)) is normalized to \\( \theta \\) as the system is periodic over \\( T = 2\pi \backslash \omega_s \\). Furthermore, let the switch be closed for some arbitrary reference frame defined by \\( -a_1 \\) and \\( a_2 \\) centred around 0, such that;
$$ i_{sw} = \begin{cases} I_{dc} \left[1+m\cdot cos( \theta ) \right], & \mbox{for } -a_1 \textless \theta \textless a_2 \\ 0, & \mbox{ otherwise} \end{cases} $$
Note that the parameter $m$ may be found be evaluating the charge conservation at the node $V_d$ of the capacitor \\( C_{ds} \\) by;
$$ I_{dc} = \frac{I_{dc}}{2\pi} \int \limits_{-a_1}^{a_2} \left[1+m\cdot cos( \theta ) \right] d\theta $$
Similarly by integration the at the node \\( V_d \\) is given by;
$$ v_d (\theta) = \begin{cases} 0 , & \mbox{for } -a_1 \textless \theta \textless a_2 \\ \frac{I_{dc}}{\omega C_{ds}} [ \theta - m \cdot sin(\theta) - a_2 - m \cdot sin ( a_2 ) ], & \mbox{ otherwise} \end{cases} $$
Given these waveforms one may perform a transform integral to find the power of the fundamental quadrature components which is expected to drive the load with the sinusoidal current \\( I_{rf} \\).
$$ V_{di} = \frac{I_{dc}}{\pi \cdot \omega C_{ds}} \cdot \frac{1}{2m} [ m \cdot sin^2 ( a_1 ) - m \cdot sin^2 (a_2) + 2 \cdot cos^2 ( a_1 ) - 2 \cdot cos^2 ( a_2 )] $$
$$ V_{dq} = \frac{m \cdot I_{dc}}{2 \pi \cdot \omega C_{ds}} \left[ m \left( sin^2 ( a_1 ) + sin^2 (a_2) \right) + \frac{ sin (2 a_1 ) - sin (2 a_2 ) }{2} + 2 \cdot cos ( a_1 ) sin ( a_2 ) \right] $$
With these components the phasor at the \\( V_d \\) side of \\( C_{L1} \\) must be match to the phasor at the known load \\( X_L + R_{EL} \\) which specifies the coupling capacitor \\( C_{L1} \\) by impedance matching.
$$ R_{EL} =\frac{ - V_{di}}{m \cdot I_{dc}} $$
$$ C_{L1} =\frac{ V_{dq}}{m \cdot I_{dc}} - X_{L} $$
Finally we need to consider the conduction angle of the transistor, that is \\( a_1 + a_2 \\) in degrees. Intuitively, the larger the conduction angle (bounded by a maximum value of 180 degrees) of the transistor the more dynamic current oscillating trough the primary tank of the circuit for a given capacitance \\( C_{ds} \\) but this also results in a very large peak voltage at the drain of the power transistor inducing a significant amount of stress at the pinch-off region in the channel. For high power applications a conduction angle of 110 degrees is generally suggested for trading off driving capability and component lifetime but since bio-telemetry power requirements are small and a direct interface with digital control components is desirable, the PA presented in chapter 3 has a conduction angle of 180 degrees.
Note that one can also extract the DC component through using a transform integral which illustrates explicitly the linear scaling associated with the supply voltage and current load at the inductor. This characteristic is particularly useful for fine tuning the final PA configuration as it is initially difficult to specify the exact waveform at the rectifier, hence minimizing the power dissipated by the diodes remains challenging from the first cut design but is done at ease with simulation support.
## Ultra Wide Band Technology
The UWB system is historically based on the spark gap transmitters developed by Marconi in the 1900s \cite{marconi}. Although there was potential for ground breaking data rates, the ability to control the UWB spectrum at the time was still in its infancy and made inter channel and multi user interference a serious problem. This ultimately resulted in the disregard for wide band communication in favour for the narrowband technology that was easier to regulate with respect to multiple end-users. The more recent 3.1 GHz to 10.6 GHz spectrum allocation for UWB applications that occupy at least 500 MHz by the Federal Communications Commission (FCC) of United States in 2002 has sparked new interests in the field as commercial use is now permitted with a limited power spectral density of -41.3 dBm/MHz \cite{RFCC}.
The recent developments in ultra-wideband (UWB) technology have made a significant impact on a broad range of applications because it presents a set of relatively unique advantages: very short duty cycles, low power consumption and simple architectures which are ideal for modern cost efficient SOC miniaturizations that are often the focus of state-of-the-art research projects. In this respect, UWB has promised phenomenal performance for short range wireless channels allowing up to 100Mb/s data rates under very strict sub-mili watt power budgets with all-digital transmitter architectures that are much more robust in performance than their analogue wave-mixing counterpart that can often not be integrated on the same chip due to substrate interference issues from other system components.
{{< figure src="/images/msc-thesis/spec.png" title="Illustration of the spectral characteristics for the three main classes of communication technologies and the associated modulation schemes." width="500" >}}
The foundation of UWB systems based around the characteristic low spectral density that results from very short pulses of energy but embody a very wide signal bandwidth. This characteristic allows the transmission of a signal with spectral energy distributed below the noise floor eliminating the chance of interference with coherent narrowband systems. The basis on which UWB is assured to attain the phenomenal bit rates suggested earlier comes from the well-known Shannon-Nyquist criterion that dictates the maximum channel capacity, $C$, which can be achieved with arbitrarily small but nonzero probability of error and is given by \cite{BKSS};\\
$$ C = BW \cdot log_2 \left( 1 + \frac{E_{signal}}{E_{noise}} \right) $$
Where \\( BW \\), \\( E_{signal} \\), \\( E_{noise} \\) are the channel bandwidth, received in-band signal energy, received in-band noise energy respectively. Recognizing that SNR, \\( E_{signal} \\) / \\( E_{noise} \\) scales almost linearly with the total system power on both the transmitter and receiver side we observe that improving SNR by dissipating more power will, as disappointing as it is for high SNR environments such as nearfield biotelemetry, only improve the channel capacity in logarithmic fashion. However with a given bandwidth of several GHz we can still assure ourselves a Mb/s bit rate even with poor SNR ratios due to ultra low power transmitter operation from the linear dependency of bandwidth.
Some of the most significant developments in this field lie with the fully integrated CMOS pulse shapers that adhere to the FCC mask regulations \cite{1363659}. Pulse shapers not pertaining to the field of biomedical implants generally quote the energy dissipated per pulse FOM which ranges from 2 nJ/pulse to some of the more recent work that nearly achieves 4 pJ/pulse \cite{4253320}. There have been several publication have proposed using a UWB reverse link data transmission for biomedical telemetry with much success in terms of low power operation and have achieved 900 fJ/pulse but did not present spectral compliance\cite{5986090}.
There are three performance metrics of the UWB pulse that are of interest for commercial applications as they allow complete specification of the signal to noise and interference ratios for linear receivers \cite{474590}. These three metrics correspond to spectral efficiency, out-of-band emissions, and time-bandwidth product \cite{1489046}.
The first of which being the most intuitive, that is the spectral efficiency, which indicates how efficiently the designated spectrum is used in terms of how well all the radiated energy is confined within the 10dB ultra-wide bandwidth. This is expressed as;
$$ \eta_{ch} = \frac{E_{ch}}{BW_{-10dB} \cdot max ( PSD_{W / MHz})} $$
Where the total in band spectral energy, \\( E_{ch} \\), is given by
$$ E_{ch} = \frac{1}{2 \pi} \int_{BW_{-10dB}} PSD ( \omega ) d\omega $$
The second figure of merit for UWB pulses evaluates the normalized amount of spurious spectral energy is generated by the pulse. That is;
$$ \eta_{0} = \frac{E_{tot} - E_{ch}}{E_{ch}} $$
Where the total radiated energy, \\( E_{tot} \\), is given by the time-domain integral
$$ E_{tot} = \int^{\infty}_{-\infty} p(t)^2 dt $$
Finally, the time-bandwidth product primarily indicates the utility of the pulse in terms of being able to carry information. Consider for example the Sinc function which precisely has 0% out of band emissions however its time domain square power is unbounded indicated by the divergent integral for \\( d^2 \\). This implies that modulation based on a ideal Sinc wavelet is non-realizable by a causal system. The time-bandwidth product being related to the standard deviation in the spectral intensity and time domain intensity which is formulated as follows;
$$ D^2 = \frac{1}{2 \pi \cdot E_s} \int^{\infty}_{-\infty} \omega^2 \cdot | PSD(\omega)|^2 d \omega $$
Where the total radiated spectral energy, \\( E_{s} \\), is given by the frequency-domain integral:
$$ E_s = \frac{1}{2\pi} \int^{\infty}_{-\infty} | PSD(\omega)|^2 d \omega $$
$$ d^2 = \frac{1}{E_{tot}} \int^{\infty}_{-\infty} t^2 \cdot | f(t) |^2 dt $$
Such that the time-bandwidth product is summarized as;
$$ B_{t \omega} = D \cdot d $$
\begin{table}[h!]
\begin{center}
\begin{tabular}{l c c c}
& Spectral Efficiency & Out-of-Band Emissions & Time-BW Product\\
\hline
Sinc & 100\% & 0\% & $\infty$ \\
Square & 60\% & 12.8\% & $\infty$ \\
$2^{nd}$ order & 59.2\% & $2.8\%$ & 0.55 \\
Root-Raised cosine & 84.6\% & $0.4\%$ & 0.85 \\
Gaussian & 56.5\% & $3.3\%$ & 0.50 \\
Tanh & $58.4\%$ & $2.7\%$ & 0.53 \\
\end{tabular}
\end{center}
\caption{Summary of the UWB FOM performance for different classes of analytic pulses\cite{thsis}.}
\ context.TABLE: 1
\end{table}
A significant amount of progress has already been made towards to maximizing these figures of merit in a more general UWB framework by means of photonics and microwave systems \cite{4427280}. Only a select few of these advances are fully integrated systems and since compact integrability is the strict requirement for the implant side system there is a still lot of room for improvement for current implant-compatible UWB transceivers.
## UWB Pulse Generation
Fully integrated UWB technology is a relatively recent breakthrough, as previous pulse generation systems were primarily based on step recovery and tunnel diodes that under pulsed excitation produced a very different radiation spectrum that carrier based modulation schemes \cite{1449159}. Interestingly the spectrum used for time domain UWB encoding was essentially the modulated impulse response of the diode in operation. Moreover these wideband spectrums were found to allow much more accurate special resolution as well as exhibit some degree of immunity to passive interference \cite{1006348}. The integrated UWB framework bases its pulse generation on a more synthetic approach as the GHz operation of current CMOS technology allows pulse modulation with pulse width far below the average temporal UWB pulse duration which is around 1ns. This in many cases has allowed for piece wise reconstruction of a theoretically derive pulse shape such as those mentioned in table 1.
{{< figure src="/images/msc-thesis/pl0.png" title="Figure 5a: Spectral representation of the oscillator and modulation waveforms" width="500" >}}
{{< figure src="/images/msc-thesis/pl2.png" title="Figure 5b: Resulting UWB spectrum due to mixing." width="500" >}}
The most elementary form of fully integrated UWB pulse generation is derived from sub GHz OOK modulation of the GHz oscillator \cite{4526201}. With the frequency domain transforms are illustrated in figure 5, since digital and analogue oscillators are relatively disposable in the FCC UWB band this approach is arguably the most elementary topology that can achieve relatively good performance if the start-up and dead times are well calibrated. The challenging aspect of this topology is it is difficult to both suppress the spurious frequency sidebands as well as the DC component at the output.
{{< figure src="/images/msc-thesis/pl1.png" title="Figure 6: Illustration of the spectral characteristic of $1^{st}$, $5^{th}$, and $7^{th}$ derivative based gaussian UWB pulses." width="500" >}}
An alternative approach to generating UWB pulses is based on the spectrum of Gaussian derivatives \cite{1363659}. The family of Gaussian functions are generally well known for their transform limited behaviour and as illustrated in the previous section the Gaussian pulse has the most optimal time bandwidth product out of all analytic reference pulses. Since the actual Gaussian pulse has a strong DC component the derivatives are more realizable in RF systems.
$$ g^{(n)}(t) = \frac{d^n}{d t^n} \left( \frac{ A }{ \sqrt{2\pi} \cdot \sigma} \cdot exp \left\{ \frac{-t^2}{2 \sigma^2} \right\} \right) $$
$$ |G^{(n)} (\omega) | = A \cdot (\omega)^n \cdot exp \left\{ \frac{-( \omega \cdot \sigma )^2}{2} \right\} $$
From the expression of the Gaussian UWB spectrum it can be observed that there are two parameters for spectral tunability that allow fitting under the FCC mask which has been done extensively \cite{5683697}. These two parameters are \\( \sigma \\) and the n which correspond to the temporal pulse width and the derivative order of the Gaussian pulse. By increasing the derivative order of the generated gaussian pulse the overall spectrum is expected to shift to the higher frequencies while simultaneously becoming more concave at the fundamental lobe. By reducing \\( \sigma \\) the spectrum also shifts towards the higher frequency spectrum but in contrast does not affect the fractional bandwidth of the fundamental lobe. The \\( 1^{st} \\), \\( 4^{th} \\), \\( 5^{th} \\), and \\( 7^{th} \\) order Gaussian derivatives have been demonstrated to fit the FCC mask in literature and are their allocation under the FCC mask is illustrated in figure 6 for a relative comparison.
{{< figure src="/images/msc-thesis/pls1.png" title="Schematic of a simple Gaussian Pulse shaper." width="500" >}}
{{< figure src="/images/msc-thesis/pls2.png" title="Ultra short pulse control signals driving the Gaussian pulse shaper." width="500" >}}
{{< figure src="/images/msc-thesis/pls3.png" title="Piece wise constructed gaussian output pulse fed to the antenna." width="500" >}}
The integrated circuit implementation of these Gaussian pulse generators are typically fitted by a series of consecutive current pulses feeding into a coupling capacitor toward the antenna load. The pulses are typically under a 100ps long depending on the CMOS technology and by adjusting the driving capability of the MOSFET that is active during a particular phase the amplitude of the corresponding pulse can be adjusted according to the configuration that best fits the target Gaussian model. This topology has demonstrated some of the most energy efficient pulse generators yet, achieving a spectral energy density that nearly matches the FCC mask while consuming more than 4 pJ per pulse.
In extension to the Gaussian pulse generator topologies, a more generalized structure has also been introduced which focuses on efficiently generating a very board band pulse and filtering out the unwanted spectral components after amplification trough by an RF power amplifier. The filter can be implemented as an integrated on-chip LC filter or using a microwave distributed element filter topology \cite{1606192}. A particularly challenging aspect of this topology is that, although the implementation is the most robust, the filter is required to have a near constant group delay over the pass band to maintain ultra-short pulse durations and avoid pulse distortion.
{{< figure src="/images/msc-thesis/pls4.png" title="Schematic illustrating a RF PA amplifying a Broad band pulse that is then filtered by a lumped LC network." width="500" >}}
{{< figure src="/images/msc-thesis/pl3.png" title="Illustration showing how the broad band pulse is filtered to meet the FCC mask requirements by using a high pass filter." width="500" >}}
Overall these three topologies allows for fully integrated systems where often the implementation can be translated into a completely digital architecture where only the transistors driving the RF output need to be considered in analogue terms. This benefit allow for rapid prototyping with very small chip area requirements, complete generation of a UWB transmitter by digital synthesis has also been demonstrated \cite{5615627}.
## Projecting System Requirements
Due to the very rich physiological information neural signals carry, an overwhelming amount of interest has been seen in the monitoring of en-vivo neural activity. The neural interface SOCs have since developed impressive set of performance standards that is expected to be maintained for the next few years. By cross-referencing the expected advances in neural recording technology a projection can be made on system requirements in the next 3 years \cite{nat}.
\begin{table}[h!]
\begin{center}
\begin{tabular}{p{3cm} | c c c c c c}
& 2009 \cite{s5} & 2010 \cite{s7} & 2010 \cite{s9} & 2011 \cite{s2} & 2011 \cite{s10} & 2012 \cite{s11} \\
\hline
Technology & $0.35\mu m$ & $0.35\mu m$ & $0.35\mu m$ & $0.13\mu m$ & $0.18\mu m$ & $0.13\mu m$ \\
Channels & 1 & 128 & 128 & 1 & 32 & 96 \\
max BW (Hz) & 0.3k & 20k & 5k & 11.5k & 12k & 10k \\
ADC Resolution & 12b & 9b & 8b & 8b & 8b & 10b\\
ADC Sampling Rate (kS/s) & 1 & 640 & 111 & 10-100 & 125 & 31 \\
Data Rate per Channel (kb/s) & 12 & 360 & 111 & 100 & 250 & 313 \\
Power per Channel (W) & 895n & 344u & 190u & 75u & 10u & 68u \\
Power to Transmitter & - & 1.6mW & - & 400uW & - & - \\
\end{tabular}
\end{center}
\caption{Performance overview of the most recent state-of-the-art work on neural interfaces.}
\end{table}
From the references in table one can observe that although the effective power consumption per channel is steadily decreasing below 100 uW. The sample resolutions and channel bandwidths tend to be slightly over 8 bits and 10 kHz respectively as it appears to be the sweet spot that maximizes SNR with minimal power requirements. Given the expectation to see 512+ channel neural SOCs in the coming 3 years it theoretically corresponds to an uncompressed data rate of 82 Mb/s that needs to be transmitted through the reverse RF link. A similar analysis would estimate the required system power budget to be an optimistic 5 mW system or a more pessimistic 15 mW prototyping system that considers systems that have demonstrated neural recording from animal trails with more significant weighting.
In summary, this chapter has given way for the target specification given in table 2 with the corresponding topology given by figure 7.
{{< figure src="/images/msc-thesis/s3.png" title="Figure 7: System level abstraction of the proposed biotelemetry topology." width="500" >}}
\begin{table}[h!]
\begin{center}
\begin{tabular}{l | c }
Parameter & Specification \\
Power Delivered to load & 15mW \\
Forwardlink Data rate & 300kb/s \\
Modulation Scheme & BPSK \\
Reverselink Data rate & 80Mb/s \\
Power to Transmitter & $\textless100\mu W$ \\
\end{tabular}
\end{center}
\caption{ Performance requirements for the implantable biotelemetry system.}
\ context.TABLE: 2
\end{table}
# Forward Link
## System Abstraction
The forward link has been the primary focus of biotelemetry systems as the induction of wireless power into the body is a challenge that has been receiving attention since the 1960s and has continued to develop alongside the innovations made in power electronics and the more recent RFID technology \cite{4502849}. However, regardless of the modulation techniques presented in chapter 2, there is a very inherent limitation that the inductive link imposes in terms of data transmission.
{{< figure src="/images/msc-thesis/s5.png" title="Figure 8: System block diagram of the forward link channel." width="500" >}}
With reference to figure 8, the system of interest here may be abstracted into four separate sections; the power amplifier, the inductive link, the demodulator, and the rectifier. Each of which substantiates a complete technical topic on its own and in association with the technical specifications given. This chapter will focus on first presenting an analytical description of the coil link in order to formulate target figures of merit followed by the employed power amplifier design with the associated simulation results. Techniques that minimize the loss introduced by phase transitions from BPSK modulation will be a very particular consideration that will be made at the end of this chapter together with the corresponding low complexity BSPK demodulator.
## Inductive Link Design
{{< figure src="/images/msc-thesis/pa4.png" title="Figure 9: Circuit model of the inductive link driven by an ideal source." width="500" >}}
With particular focus on maximizing the induced power onto the rectifier load which has be reduced to the ac equivalent \\( R_{AC} \\). With the reduced circuit illustrated in figure 9 one may be able to identify the two loss mechanisms that govern the power transmission transfer function. The first being the reflection coefficient associated with the resistive loading of inductor \\( L_1 \\) due the secondary coil that is in series with the parasitic resistance of the inductor itself \\( R_1 \\). The second loss mechanism abstractly lies with the self-loading of secondary inductor due to the parasitic resistor \\( R_2 \\). Both of these parasitics are directly related to the Q-factor of the two inductive coils used to couple the two systems. In brief, the analytic expression for the efficiency of power induction may be derived at the resonant switching frequency, again that is \\( \omega_s = (C_{L2} \cdot L_2 )^{-1/2} \\), as \cite{sarpes};
$$ \eta = \left[ \frac{V_L \cdot I_L}{V_s \cdot I_s} \right] = \frac{R_{eff}}{R_{eff} + R_{1}} \cdot \frac{L_2}{L_2 + R_{2} \cdot R_{AC} \cdot C_{L2}} $$
Where the effective impedance seen at the primary coil, \\( R_{eff} \\), is
$$ R_{eff} = k^2 \cdot \frac{\omega^2 \cdot L_1 \cdot L_2}{R_2 + \frac{L_2}{R_{AC} \cdot C_{L2}}} $$
Further expansion will show that this equation may be optimized for a given k in terms of the load \\( R_{AC} \\) with respect to the inductor Q of coils \\( L_1 \\) & \\( L_2 \\).
$$ R_{AC} \bigg|_{\eta=\eta_{max}} = \frac{\omega_s \cdot L_2}{k} \cdot \sqrt{\frac{R_1 \cdot L_2}{R_2 \cdot L_1}} = \frac{\omega_s \cdot L_2}{k} \cdot \sqrt{\frac{Q_2 }{Q_1}} $$
Such that the peak efficiency, \\( \eta_{max} \\) may be expressed as
$$ \eta_{max} = \frac{k^2 \cdot Q_{L1} \cdot Q_{L2}}{(1+ k \cdot Q_{L1})(1+ k \cdot Q_{L2})} $$
The limiting factor associated with the coils is primarily the total chip area hence the coil geometry should maximize the coupling quality factor product per unit area. Previous systems will either opt for a coil integrated on to the PCB which allows improves the ability manufacture the end result or a coil that is implemented by a wrapped linz wire which makes scalable prototyping challenging but provides much better performance in terms of inductor Q-factors \cite{4432391}. PCB integrated inductors tend to be more lossy for a given inductance primarily because of the space requirements on the traces which prevent the dense inductance one may expect from a wire wrapped coil. The majority of published literature tends to prefer using circular geometries as their properties are accurately predicted by analytic formulas, it should be noted however that rectangular coils achieve higher coupling coefficients per unit area. With this in mind, the coils that tested in the laboratory were based on copper wire wrapped rectangular geometries. In analogy to closely space circular coils where it has been demonstrated that the mutual inductance is maximized when the primary and secondary coils have the same geometry we expect the same from the rectangular coils \cite{503178}.\\
{{< figure src="/images/msc-thesis/l1.png" title="Circular Coil geometry." width="500" >}}
{{< figure src="/images/msc-thesis/l2.png" title="Square coil geometry." width="500" >}}
{{< figure src="/images/msc-thesis/l3.png" title="In plane view of coils." width="500" >}}
Using EM simulation tools a simple study was conducted to confirm these findings. Using a single turn circular loop with a diameter normalized to the parameter r and a square loop with the side length also normalized to the parameter r, we studied the behaviour of the coupling coefficient k with respect the out of plane distance, d, from two identical coils and the lateral in plane displacement a. The results illustrated in figure 10 confirmed that, although circular coils achieve better quality factor, the square coils achieve better coupling coefficients implying with reference to equation 23 that square coils achieve higher peak efficiency.
$$ \frac{Q_{circle}}{Q_{square}} = 1.87 \hspace{10mm} \& \hspace{10mm} \frac{k_{circle}}{k_{square}} = 1.88 $$
{{< figure src="/images/msc-thesis/KUPL.png" title="Figure 10: EM simulation results of the coupling coefficient with respect to the in-plane and out-of-plane normalized displacements." width="500" >}}
In accordance to the above considerations and estimates on the ac load expected to be loading the secondary coil a two coil rectangular link was prototyped. The primary coil and secondary coil were measured in the lab to evaluate the mutual inductance values where the mutual inductance was evaluated through a differential measurement \cite{AGI}.
\begin{table}[h!]
\begin{center}
\begin{tabular}{l | c | c}
Parameter & Primary Coil $L_1$ & Secondary Coil $L_2$\\
\hline
Turns & 29 & 15 \\
Dimensions (mm) & 12 x 24 & 12 x 24 \\
Inductance (uH) & 46.59 & 12.67 \\
$R_s$ ($\Omega$ at 1MHz) & 7.49 & 3.19 \\
$k_{21}$ * & 0.134\\
\end{tabular}
\end{center}
\caption{Measured characteristics of the two inductive coils.}
\begin{flushleft}
* measured at coil distance of 10mm\\
\end{flushleft}
\end{table}
{{< figure src="/images/msc-thesis/loop.png" title="Photograph of the prototype rectangular coil used for power induction." width="500" >}}
Given the measured coil characteristics, the Class-E PA was designed in accordance with the method presented in chapter 2. By introducing the simulation models of commercially available components the design was fine tuned to achieve a power transmission efficiency of 46%. The derived system delivers 15mW to a 600 ohm load corresponding to an unregulated supply of 3V. The losses from the primary and secondary contribute to 30% and 14% of the total power dissipation respectively. The off chip rectifier dissipated 8% of the total power which actually correspond to a marginal efficiency of 85%. The remaining 3% is dissipated by the RF choke and the power transistor. Note that a the power transistor in figure 11 is a 2N7000 Fairchild N-Channel Enhancement Mode Field Effect Transistor with a maximum drain voltage rating of 60 V.
{{< figure src="/images/msc-thesis/pa0.png" title="Figure 11: Detailed circuit schematic of the complete power transmission system with the component names/models annotated." width="500" >}}
{{< figure src="/images/msc-thesis/power.png" title="Simulation results of the power induction system in operation illustrating a average 46% PTE." width="500" >}}
## Switch mode BPSK Modulation
In one respect the input waveform of the Class E amplifier is no longer trivially related to the waveform driving the load in time domain and strictly speaking the degrees of freedom at the driving transistor are now limited to two states; open circuit, and closed circuit. As a result the dynamic range of this class of amplifier is limited to the unit gain circle on the constellation diagram. This inherently presents a problem for BPSK modulation as the state transitions through the zero crossing as shown in figure 12 which for many amplifier topologies is undesirable due the fact that is strains the dynamic range requirement. In the RF domain regulating the transition behaviour is rather strict as state transitions that lie beyond the capability of the amplifier result in spurious frequency components from distortion that lie outside of the designated frequency band. In the case of biomedical telemetry we shall observe that such a careless transition results a significant amount of loss in the system. To alleviate this problem we shall introduce an intermediate state to allow a smoother transition without introducing additional system complexity.
{{< figure src="/images/msc-thesis/cnst2.png" title="Figure 12: (left) Standard BPSK constellation diagram. (right) Constellation diagram of the proposed BPSK modulation scheme." width="500" >}}
Figure 13 shows the simulation results of phase transition of two BPSK modulation techniques, the first in blue being the simple BPSK modulation of a square wave and the second in red being the proposed BPSK modulation of a square wave with an intermediate state. It is obvious that there is a dramatic difference with respect to the voltage waveform seen at the rectifier input. The simple modulation technique not only results in a slow transition but there is no energy induced for a number of cycles which is detrimental to the system PTE $\eta$. The proposed modulation scheme first transitions to $+\pi/2$ for half a cycle before completing the phase shift towards $+\pi$. It is important to note that open circuit state of the RF switch maintains its temporal duration as this is the mechanism that provides harmonic termination to the higher order harmonics that are reflected by the LC tank.
{{< figure src="/images/msc-thesis/mod_tran.png" title="Figure 13: Simulation results illustrating the gain in average PTE and the destructive interference of the two phase states during the phase transition without the intermediate state." width="500" >}}
Even with this modulation technique a linear trade off with respect to the carrier frequency and the forward data rate is still to be expected as one cycle for every phase transition fails to induce power. The expected power transfer efficiency, \\( \eta \\), during modulation is asymptotic to and approximated by the following expression.
$$ E \left[ \eta \right] = \eta_{s} \cdot ( 1 - N \cdot \frac{f_{data}}{f_{carr}} ) $$
Where \\( \eta_{s} \\), \(( f_{carr} \\), \\( f_{data} \\) are the un-modulated PTE, carrier frequency, and data rate respectively. N is the model parameter that corresponds to the number of cycles skipped as a result of a phase transition which our fitting estimates to be approximately 1 for the proposed modulation scheme. It is now clear that faster switching frequencies driving the PA will also allow for proportionally faster data rates without having to sacrifice efficiency.
{{< figure src="/images/msc-thesis/swtmd.png" title="Simulation results of the PTE with respect to different data rates and the fitting parameters of the extracted model." width="500" >}}
## Integrated BPSK Demodulator
To reduce overhead, the demodulator illustrated in figure 14 recovers the transmitted data stream is not based on a delay locked loop topology but based on detecting the cycle skipping of phase transitions. Although it is arguable that this type of detection is prone to failure due to coil displacement when the designated patient moves these kind of environmental factors influence the induced voltage waveform in the very low frequency spectrum that typically do not exceed 100 Hz. Hence a high-pass filter behaviour is introduced to the peak voltage detector using the parasitic capacitance and leakage current of the transistor M9.
{{< figure src="/images/msc-thesis/bdmd.png" title="Figure 14a: Transistor level schematic of the threshold based phase detector." width="500" >}}
{{< figure src="/images/msc-thesis/bddd.png" title="Figure 14b: Digital State machine that detects phase changes in the induced voltage waveform." width="500" >}}
The remaining operation of the circuit is intuitive, M1 shifts the voltage wave at the input of the rectifier down so that is falls below the supply voltage and the transistors M5-M7 determine & compare the voltage \\( V_{bias} \\) and the peak voltage which is \\( max(V_{in}-V_{thm1} - V_{thm8}) \\). Due to the over driving effects the output is approximately digital in characteristic where \\( V_{clk} \\) is low then \\( V_{in} \\) is larger than \\( V_{bias} \\) and \\( V_{sig} \\) is low when \\( V_{in} \\) larger than the stored peak value. These signals are processed by some simple digital circuitry to detect when \\( V_{in} \\) drops below its peak value by more than one NMOS threshold voltage. The near digital operation of this circuit the power consumption is just under 1.5 uW and simulation results of phase detection is shown below in figure 15.
{{< figure src="/images/msc-thesis/DBPSK.png" title="Figure 15: Simulation results showing the operation of the threshold based phase detector." width="500" >}}
## System Summary
In this chapter a class-E based forward transmission link was presented that couples power and transmits data. To engage the discussion on system design a common framework for coupled coils was presented to formulate a objective that brought forth the efficiency figure of merit. In addition to the schematic specifications of the transmitter, the modulation scheme was considered in detail with respect to the switch mode amplifier by identifying the underlying phase transition inefficiencies. By introducing an intermediate state the power transmission efficiency during modulation was improved an a accurate model describing the trade off between modulation rates and carrier frequency was presented. Finally the a low power BPSK demodulator was proposed.
# Reverse Link
The reverse link of the biotelemetry system primarily pertains to the RF communication link that sends large amounts of data acquired in vivo by the sensory instrumentation devices to a receiver external to the body. The focus of this chapter will revolve around how this reverse link achieves a very high data rate with the minimum amount of power consumption, that is minimizing the energy per bit transmitted, and proposing a scalable modulation technique for low power applications. Followed by the design considerations of a digitally calibrated oscillator as well as an energy efficient bi-phasic UWB pulse generator, a UWB antenna design shall be presented with considerations towards near field pulse transmission. Finally a energy detection based UWB receiver topology is proposed for testing purposes.
{{< figure src="/images/msc-thesis/s4.png" title="System level abstraction of the UWB transceiver." width="500" >}}
## UWB Pulse Modulation
Let us first consider the two principle modulation techniques illustrated figure 16 that have been the most successful in UWB communication systems, which are binary phase shift keying (BPSK) and pulse position modulation (PPM). BPSK can be directly associated with the continuous wave modulation techniques and has shown to be a good alternative for pulse modulation that does not distort the output spectrum significantly \cite{947480}. PPM is based on temporal delays and advances of the UWB pulse to modulate the signal. Current PPM systems are based on modulation with reference to a receiver oscillator that is locked through a digital Costas loop equivalent that requires transmitter dead time for synchronization. As current pulse generators consume at least several pJ per pulse we may assume that over 80% of the system's power consumption will be due to the actual output pulse driving the antenna.The interest here lies with encoding a single pulse with multiple bits to maximize efficiency. Simply combining the two modulation techniques is the easy way to boost efficiency but may not be worth the increase in system complexity.
{{< figure src="/images/msc-thesis/mmd.png" title="Figure 16a: Time-domain representation of BPSK & PPM modulation schemes." width="500" >}}
{{< figure src="/images/msc-thesis/cnst.png" title="Figure 16b: Constellation diagrams of BPSK & PPM modulation schemes illustrating the inherent SNR reduction for PPM." width="500" >}}
The bottle neck that prevents a scalable system that encodes multiple pulse positions lies with how the temporal delay are generated in contemporary designs. For non-coherent detection systems these delays must be relatively small and accurate to maintain correct detection on the receiver end which if scaled up would result in too much calibration overhead to tune each pulse position. For coherent based UWB receivers the pulses must be orthogonal with respect to the detection window which is even more challenging for detecting multiple phase states. Instead if the delay of a fixed period is used from a calibrated digital oscillator (DCO) and multiple pulses are allowed within a short reference frame, the scaling of the position encoding mechanism can be improved in a fundamental way while maintaining system simplicity. More importantly, using a DCO allows us to dedicate a lot of resources for fine tuning the delay of a single element where if multiple delay elements need to be used the restricted resources would limit the tuning of the resulting delay and introduce unwanted phase noise.
{{< figure src="/images/msc-thesis/n1.png" title="Figure 17a: Simple delay encoded pulses with reference to a DCO clock." width="500" >}}
{{< figure src="/images/msc-thesis/n2.png" title="Figure 17b: Pulses encoded by the cascading of two delay symbols in a single data word." width="500" >}}
As illustrated above in figure 17, the data is essentially encoded in the delay between pulses. More importantly, note that the pulse package is encoded with reference to the first pulse which allows for accurate receiver phase locking. The implications of this type of ‘delay encoding’ are quite significant. First and foremost the energy detection receiver can now actually be asynchronous negating the need for start-up dead time. Since efficiency improves only by the logarithm of the maximum delay it is not area efficient to encode large delays but by cascading multiple encoded delays after one another bit rate, area, and efficiency can be traded off with a significant amount of flexibility. Moreover by omitting the last pulse of the package a delay of 0 can be encoded for improved efficiency.
It should also be apparent that this approach has two main draw backs, the first being that it is particularly sensitive to the DCO frequency off sets for long delays that integrate to large amount of phase noise over the signal window. The other drawback is to maintain FCC mask compliance the peak output power of the UWB pulse must be reduced which degrades the signal to noise ratio. On the other hand however this modulation technique can tolerate a temporal equivalent of phase noise equal to half the DCO’s period.
To give further insight to the expected degradation in the bit error rate (BER), let us consider the absolute worst case scenario where the entire word needs to be detected by a linear receiver. That is, each symbol transmitted needs to be detected at the receiver and is subject to the same AWGN from the channel. For simplicity a threshold detection receiver model has been adopted that integrates the incident RF power waveform by self mixing and samples the accumulated energy before resetting the integrator for the next reference window at a period of $T_w$. In addition, let us assume the signal band with is known such that the probability of detecting a pulse, \\( P_{bit} \\), for \\( \frac{E_b}{N_0} \)) < \\( \frac{T_w BW}{2} \\) is given by \cite{474590};
$$ P_{bit}=Q\left( \frac{E_b / N_0}{\sqrt{2T_w \cdot BW + 2E_b / N_0}} \right) \hspace{10mm} where \hspace{5mm} Q(x)=\int^{\infty}_x \frac{exp(\frac{-t^2}{2})}{\sqrt{2\pi}} dt $$
Here \\( E_b \\) and \\( N_0 \\) denote the energy in the pulse and AWG noise over the integration window \\( T_w \\). In extension the expected value of the BER for this particular modulation scheme may be evaluated by considering the probability of detecting the whole word correctly, the probability of sending that particular word, and the number of bits transmitted per word. For simplicity assume each word is equiprobable, which is sub-optimal source coding but regardless, then for the simple case of non-cascaded delay encoding the BER may be expressed as;
$$ BER_1 = \frac{1 - \sum\limits_{i=1}^{D_{max}} \left[ \frac{(1-P_{bit})^{i+1}}{D_{max}}\right] }{2+log_2(D_{max})} $$
Where \\( D_{max} \\) is the maximum delay encoded by the transmitter. If the BER of a N times cascaded delay system is to be evaluated then the previous expression is simply adjusted in the same regard to recomputing the expected value and the number of bits per word.
$$ BER_N = \frac{1}{1 + N + \sum\limits_{j=1}^{N} log_2(A_j)} \cdot \left\{ 1 - \frac{1 - \sum\limits_{i=N}^{D_{max}} \left[a_i \cdot (1-P_{bit})^{i+1}\right] } {(\sum\limits_{i=N}^{D_{max}} a_i)} \right\} $$
Here the series \\( a_i \\) denoted the number of ways one can encode a word in the cascaded system with \\( i \\) delays, note that for each cascade of delays the minimum number of delays is 1. The series \\( A_j \\) denotes the maximum possible delay ecoded by the \\( j^{th} \\) cascaded delay and N denotes the number of cascaded delays. To find a closed form expression for th series \\( a_i \\) one must consider the problem of sorting i elements in N sets that are constrained to the carnality given by the series \\( A_j \\). For the proposed system where \\( N=2 \\), the series is given by;
$$ a_i \bigg|_{N=2}= (1+ i) - \sum\limits_{j=1}^{2} \left[ \sum\limits_{k=Aj+1}^{i} 1 \right] $$
Where \\( A_j=\{8 , 4\} \\). These results confirm our previous statement that the expected BER worsens as the maximum possible encoded delay is increased but by increasing N this degradation can be alleviated by as the bit rate is increased by N and the N sum over the log maximum delay of each cascaded delay.
## System Architecture
The system architecture abstraction illustrated in figure 18 is the proposed integrated UWB transmitter which consists of three main components; DCO, Delay Modulator, and Pulse shaper. Although the previous discussion has pointed out the general purpose of using an on-chip oscillator it should also be noted that such high frequency oscillators can dissipate a significant amount of power. To alleviate the power hungry behaviour of the DCO a feedback loop is introduced into the system that enables very exact duty cycles such that the oscillator is only switched on to generate the required number of delays and is turned off once the delay encoded package is generated saving a significant amount of power as the complete package duration is on average only half the maximum encoded delay for single delay encoded equi-proportional set of words.
{{< figure src="/images/msc-thesis/mod.png" title="Figure 18: System level abstraction of the UWB transmitter architecture." width="500" >}}
The proposed system uses a 10 MHz reference input clock generated by an accurate crystal oscillator and will be used to both calibrate the DCO trough a frequency locked loop (FLL) as well as being the reference for the first pulse of the data package that partly acts as a preamble. The delay modulator is essentially a pulse swallow circuit where the decision to swallow a pulse (i.e. introduce a delay) is encoded in a shift register feeding the D flip flop.
## Digitally Calibrated Oscillator
The main challenge in designing the DCO lies with the fact the digital oscillators are very prone to variation in the oscillation frequency as a result of variation in supply, process parameters, and layout parasitics/mismatch. The Monte Carlo simulation in figure 19 shows that, if the presented DCO topology were uncalibrated, the oscillation frequency would have a standard deviation of 45MHz which as discussed previously results in large amounts of phase noise at the receiver. To alleviate this problem a two stage calibration mechanism has introduced with a total resolution of 8 bit to assure a large and accurate tunability range of the oscillation centre frequency. The 4 most significant bits calibrate the main capacitive load of the DCO which is a binary weighted Metal-Insulator-Metal capacitive array, with unit capacitance of 5 fF, by connecting an arbitrary combination of capacitors to ground and leaving the rest floating. The 4 least significant bits calibrate the NMOS driving capability of an inverter which inherently allows for tuning at a much more precise scale as the transistors can be well matched without taking up a considerable amount of area with only fractional differences in their size.
{{< figure src="/images/msc-thesis/MC.png" title="Figure 19: Monte-Carlo simulation result of the uncalibrated Oscillation frequency." width="500" >}}
The DCO also includes a Frequency Locked Loop (FLL) that during the calibration phase will tune the DCO output frequency to match that of an accurate reference clock. A fully digital implementation was chosen so minimize area and so that the self-calibration loop can be switched off during normal operation. Although Phase Locked Loops (PLLs) are generally preferred for this particular kind of functionality due to their quicker lock-on time, the all-digital FLL in figure 20 surpasses the all-digital PLL in simplicity as no digital loop filter is required.
The principle of operation of the FLL is based on detecting which clock has a faster rate of rising edges by using a simple set reset latch that is set by reference clock and reset by the DCO clock. If the DCO is resetting the latch more often than the reference lock is setting the latch a pulse is generated at the output of the frequency detector that increments or decrements an 8 bit counter that calibrates the DCO proportionally. Similarly if the latch is set more often than reset a pulse is also generated such that the rate of pulses at the output of the frequency detector is directly equal to the absolute difference in frequency between the reference and DCO clock. The state that persists while these pulses are generated indicates whether the DCO frequency must increase or decrease. Note that the generated DCO clock is divided by a factor of 50 such that the 500 MHz clock can be calibrated with respect to a low cost off the shelf 10 MHz crystal.
{{< figure src="/images/msc-thesis/dco.png" title="Figure 20: Schematic of the Frequency locked loop used to enable self-calibration of the DCO." width="500" >}}
Figure 21 Illustrates that the presented DCO exceeds a 3 sigma tunability range with respect to the expected standard deviation in DCO frequency with a resolution of 1.58 MHz which corresponds to oscillation period that is accurate to ±4 ps. The DCO consumes an average of 72 uW during continuous operation.
{{< figure src="/images/msc-thesis/dco_sweep.png" title="Figure 21: Simulation result of the frequency range capability of the DCO." width="500" >}}
{{< figure src="/images/msc-thesis/step.png" title="Transient simulation illustrating the response of the FLL due to a step decrease in reference frequency." width="500" >}}
## Bi-phasic UWB Pulse Generator
In order to satisfy the FCC regulations for UWB communication \cite{RFCC}, two different approaches have been presented in previous literature. One approach is based on modulating the envelope of a RF oscillator output which allows for simultaneous UWB communication in multiple frequency bands \cite{4526201}. The other approach is based on maximizing the spectral efficiency by fitting the UWB pulse shape to a Gaussian derivative that optimally fits the FCC mask by piecewise modulation of multiple current pulses \cite{4982876}. The design proposed here is a hybrid between these two approaches employing a simple all-digital architecture that generates a UWB pulse with improved energy efficiency using an oscillator output shaped by piece wise current pulses.
The pulse generation techniques presented are has been partly adopted from previous work that used integrated LC components to filter out the unwanted spectrum to meet the FCC mask requirements \cite{5773985}. However instead of dissipating the unwanted spectral energy, a lossy LC resonator is used to recycle the unwanted spectral energy and modulate this to its resonant frequency. Abstractly speaking, the inductor is pulsed with current over 180 ps. This induces energy that is stored in the magnetic field and is gradually dissipated in the load (over 1ns while the LC pair resonates in response to the impulse). This integrated pulse generator designed is based on a 0.18 um CMOS technology using a 1.2 V supply and assuming a 50 ohms termination.
{{< figure src="/images/msc-thesis/puls.png" title="Figure 22: Schematic Illustration of the Digital pre-shaping. Note that the relative temporal delays are not to scale." width="500" >}}
The Digital pre-shaper is shown in figure 22. This uses a popular glitch generator to generate 180ps long Gaussian like pulses, which are demultiplexed to two inverter chains to boost the driving capability of the output. It is important to note that these chains have a different output polarity but both output the buffered pulse together with a delayed and inverted pulse, driving the transistors sourcing the inductor with pulsed current (shown in figure 23). The purpose of the delayed pulse is to cancel the DC component generated by the transient impulse response of the lossy LC resonator, by injecting an equal but complementary pulse at the opposite port of the inductor. By driving either the end connected to the load, or the $C_{res}$ end of the inductor first, the polarity of the UWB pulse is well controlled.
The illustration in figure 22 also shows how a simple shift register can interface the UWB transmitter with a parallel input data stream. With reference to fig, it is interesting to note that since the transistor pairs M1, M4, M2, and M3 are matched in terms of driving capability this particular topology is immune to variation in pulse length which may easily distort the performance of aggressive UWB pulse generators that use multiple glitch generators to shape the pulse.
{{< figure src="/images/msc-thesis/rf.png" title="Figure 23: Circuit schematic of the RF section (parasitics not shown) - Lres = 4 nH; Cres = 200 fF." width="500" >}}
Since both the total pulse energy and pulse width (due to ringing) is directly proportional to the Q of the resonator, one must trade off pulse length for amplitude where a higher Q results in longer ringing but also larger peak to peak values. In this particular case, a single layer 6-turn 8-sided spiral 4 nH inductor with poly-silicon ground plane was used with the dimensions 4 um, 2.8 um, 96 um corresponding to the trace width, trace spacing, and outer radius respectively. The pulse energy was tuned to fall below 5% within 1ns to avoid inter symbol interference corresponding to the resonant capacitance of 200 fF.
{{< figure src="/images/msc-thesis/TRAN.png" title="Figure 24a: Simulation Results of the bi-phase UWB temporal response illustrating a 350 mVpp Amplitude." width="500" >}}
{{< figure src="/images/msc-thesis/DFT.png" title="Figure 24b: Simulated PSD of the designed UWB pulse & the indoor UWB FCC mask as annotated." width="500" >}}
It can be observed in figure 24 that the current output spectrum does not meet the sub 2 GHz FCC mask specifications and thus future work based on this UWB pulse generator will filter this particular spectrum using the geometric resonance of the UWB antenna which can efficiently implement a high Q high pass filter and has already been demonstrated feasible \cite{1606192}. On that note, this system consumes 1.65 pJ/pulse, which corresponds to an average of 16.5 uW with a pulse rate frequency of 10 MHz and has a competitive edge over many previous publications in terms of the energy per pulse figure of merit shown in table.
\begin{table}[h!]
\centering
\begin{tabular}{c|c|c|c}
Reference & Output $V_{pp}$ & Pulse width/BW & Power (pJ/pulse)\\
\hline
\cite{1363659} & 700mV & 0.38ns/7.2GHz & 15.4\\
\cite{4405600} & 600mV & 0.4ns/7.5GHz & 26.4 \\
\cite{4253320} & 500mV & 0.8ns/2GHz & 4.7 \\
\cite{4295131} & 180mV & 3.5ns/0.5GHz & 18\\
\cite{4982876} & 165-710 mV & 2.4ns/300MHz & 17.5 \\
This Work & 350mV & 1ns*/4GHz & 1.65\\
\end{tabular}
\begin{flushleft}
\caption{ Performance summary and comparison of UWB transmitter. }
*time taken for pulse energy to fall below 5\%.\\
\end{flushleft}
\end{table}
## Ultra-Wide-Band Antenna
With fresh insights from the UWB pulse shaper presented in the previous section, there are a number of observations that can be made with respect to the requirements of the antenna with respect to bandwidth and input impedance. In particular, we require a 22dB rejection of the sub 1.6GHz band with respect to the pass band and a 50 ohm impedance across the 3-7GHz band that needs to be radiated out to the environment. The remaining standard requirements of an antenna are primarily associated with the directionality and gain of the radiation pattern which for the biotelemetry system depend on the orientation of the two antennas which is illustrated below. The antennas will essentially be coupled in the near field which is not ideal in terms of radiation efficiency but sufficient for simple SOC applications where the receiver end is not limited as strictly by power requirements such that additional gain in the RF band can be attained.
{{< figure src="/images/msc-thesis/chnl.png" title="Illustration showing orientation of the antennas with reference to the inductive coils and skin barrier." width="500" >}}
A planar antenna that is directional with one lobe tangential to the plane would be the most desirable for the proposed antenna orientation but the compactness of the antenna is a far more valued requirement. Note that this particular orientation avoids capacitive loading on the antenna where current densities at the highest and allows the UWB antennas to be conveniently distanced from one another without compromising the implant size. Another challenging antenna property that is required is that the radiation pattern must be stable across the ultra-wide band and more importantly that the radiated energy maintains a constant group delay at the receiver side to avoid excessive distortion of the UWB pulse. The last requirement is ultimately the most challenging as it requires the single mode of radiation retained over a bandwidth of several GHz for simple electrically small antenna structures.
A comment should be made with regard to the fundamental limitation of electrically small dipole antennas, as it can be shown that the fractional bandwidth of the antenna explicitly inverse to the quality factor of the antenna and hence it is theoretically possible to achieve UWB specification using these structures. However, the quality factor is directly related to the radiation efficiency by the Chu-Harrington limitations which inhibits the use of compact quarter wavelength dipole structures \cite{1219625}. Instead a class of “fat” monopole antennas has been introduced that provide a similar foundation for simple geometric structures that show adequate performance for UWB applications. The success of these structures lie with the many overlapping resonant modes that the geometries exhibit and hence appear to resonate over a large bandwidth. The most successful planar structure according to the demonstrated radiation efficiencies presented in literature has been the elliptical monopole off which we have based our primitive antenna design as well \cite{1421157}.
{{< figure src="/images/msc-thesis/geo.png" title="Figure 25a: Illustration of the UWB antenna geometric variables." width="500" >}}
{{< figure src="/images/msc-thesis/ant.jpg" title="Figure 25b: Photo of the exposed prototype UWB antenna. Note the darker grey rectangle indicates high dielectric substrate on both sides of the metallization." width="500" >}}
In addition to the matching requirements of the antenna, it is highly desirable if the antenna is scaled down to the smallest possible size. UWB antennas from literature are primarily based on off the self FR4 substrate have a radiating patch is on the order of $16 cm^2$. In order to scale down the antenna to around the $1cm^2$ area a high dielectric substrate, RO3010, was used. More specifically, the elliptic lobe that is used to match the $50 \Omega$ co-planar transmission line is enclosed by the high dielectric substrate on both sides of the metallization leaving the radiating gap between the ground plane and the ellipse partly exposed on one face in order to avoid deteriorating the radiation efficiency.
{{< figure src="/images/msc-thesis/PROT.png" title="Figure 26: EM simulation results illustrating the degeneration of the first resonant mode to improve performance." width="500" >}}
The basic geometry in figure 25 illustrates the addition of a elliptic lobe that is placed protruding from the ground plane towards the elliptic patch which was found to give the antenna the desired in-plane directivity of 3dB and improved wide band matching. The ground plane extension generally reduced the Q-factor of the first mode such that its resonance overlaps more continuously with the second mode as may be observed in figure 26 by the gradual improvement in the reflection coefficient as the lobe is extended towards the antenna.
{{< figure src="/images/msc-thesis/A1.png" title="Figure 27: EM simulation of the \\( S_{11} \\) reflection coefficient for the finalized UWB antenna geometry." width="500" >}}
{{< figure src="/images/msc-thesis/TRNSM.png" title="Figure 28: Preliminary side-by-side \\( S_{21} \\) transmission characteristic." width="500" >}}
The preliminary EM simulation results in figure 27 show adequate performance over the 3-7 GHz band in terms of a reflection coefficient below -10dB with a constant group delay that only varies by several tens of degrees. Figure 28 illustrates a more insightful the transmission characteristic of the near field coupling that the two antennas would experience placed side by side 1cm apart. The designated bandwidth of interest, 3-7 GHz, has an insertion loss of 20 dB and exhibits near negligible fluctuation in the group delay, that is less than 50 ps. The corresponding finalized parameters describing the antenna geometry are listed in table 3.
\begin{table}[h!]
\begin{center}
\begin{tabular}{ c | c }
Parameter & Length $(\mu m)$\\
R & 5000\\
$R_g$ & 400\\
$R_t$ & 800\\
G & 290\\
W & 440\\
C & 260\\
\end{tabular}
\end{center}
\caption{UWB antenna parameters}
\ context.TABLE: 3
\end{table}
{{< figure src="/images/msc-thesis/MA.png" title="Figure 29: (top) Comparison of the measured and simulated $S_{11}$ characteristic. (bot) PSD generated by the UWB pulse shaper for reference." width="500" >}}
The first set of prototype UWB antennas were developed through manual photo chemical etching whose reflection characteristics are shown in figure 30. The sub 5GHz band appears to match the simulation results relatively well while there are some hints of over etching. The band above 5GHz however is characteristically very different from simulations. The author believes this to be the result of edge roughness introduced by uneven distribution of spray-on photo resist that was used in the development stage as a number of other antenna samples had miniature holes in the ground plane indicating a non-homogeneous etch. There is still a level of adequacy for the measured antenna as the UWB pulse PSD covers the entire band that exhibits the ability to radiate. The high Q notch at 5.5GHz however may significantly distort UWB pulses due the corresponding fluctuation in group delay. The prototype antenna does present a respectable 2GHz bandwidth.
{{< figure src="/images/msc-thesis/chmbr.png" title="Figure 30: Photograph of the UWB antenna under test in the Imperial College anechoic chamber." width="500" >}}
## Reciever
The receiver presented in this section is primarily aimed at system completeness and the testability of the power optimized UWB transmitter system as many of the strict constraints that concern the implanted system no longer apply to the external system. UWB receiver architectures generally consist of almost completely digital architectures including RF ADCs with the exception of front end tuneable low noise amplifiers for pre-acquisition gain. Pulse detection methods are very much translated into the DSP domain where channel approximation algorithms have proven to be very successful at filtering and detective UWB pulses mainly because of critical and overly complex filtering requirement that needs to adapt to both the channel and the effectively unknown input spectrum of the pulse that highly distorted after transmission \cite{1599606}.
{{< figure src="/images/msc-thesis/rec.png" title="System level abstraction of the reciever architechture." width="500" >}}
Since both the most basic coherent and non-coherent UWB receiver architectures are beyond the scope of this project a very simple energy detection system has been derived that assumes no strong interferer is transmitting in the UWB spectrum such that the UWB pulse can easily be detected by energy thresholding.
Based on this detection, a set of trigger pulses are generated ideally identical to those generated at the output of the delay modulator. Using the same DCO, the delay between these triggers can be counted by a set of registers such that the encoded information is extracted from trigger circuit recovering all data sent from the transmitter.
{{< figure src="/images/msc-thesis/dll.png" title="Figure 31a: Schematic of the implemented delay-locked loop." width="500" >}}
{{< figure src="/images/msc-thesis/dly.png" title="Figure 31b: Analog tuned delay element." width="500" >}}
To synchronize the two systems a delay locked loop is introduced at the receiver that uses analogue delay elements in combination with a charge pump phase detector\cite{5537714}. The control loop illustrated in figure 31 synchronizes the output of the delay line $V_{sync}$ with the reference clock $V_{ref}$ by continuously integrating the phase difference of the two signals. As charge accumulates onto $C_p$, the resulting voltage biases four cascaded delay elements that each can efficiently introduce delays up to 25ns. The actual mechanism of the analogue delay element is based on around the current starving the inverter structure of M5 M4 such that the time it takes to reach the switching point of the output inverter M12 M13 is controlled. Note that once the switching point is achieved the state rapidly regenerates itself due to M8 M9 assuring a fast transition. More importantly the structure negates short circuit currents that may be introduced by the slow switching of the first stage through the transistors M14 and M11.
## UWB System Summary
Transient simulations of the UWB transmitter, illustrated in figure 32, have confirmed the general operation of the delay modulator and extracted simulation of the whole system have indicated a power consumption of 68.9 uW for a PRF of 10 MHz. Since the transmitter is encoding the pulses with an effective data rate of 77.5 Mb/s these results correspond to a energy per bit FOM of 890fJ per bit. By extrapolating these results to find the power consumption of the system excluding the UWB pulse shaper, it can be stated that the modulator consumes 470 fJ per DCO oscillation and corresponds to 34% of the over power consumption.
{{< figure src="/images/msc-thesis/power.png" title="Figure 32: System level simulation results of the DCO, Modulator, and pulse shaper outputs as well as the accumulated power consumption." width="500" >}}
Although the total phase noise expected at the output of the delay modulator still needs to be characterized, the complete UWB system presents respectable performance in terms of power consumption. And from figure 29 it can be observed that there is an expected -20 dB rejection in the sub 2 GHz band with reference to the 3-6 GHz pass band which implies that the radiated spectrum should meet the FCC requirements accordingly. It can be observed from figure 32 that for closely spaced pulses the pulse amplitude is slightly degraded due to ISI at the transmitter. This type of hysteresis is generally unwanted but can be improved by either shortening the pulse or by reducing the DCO oscillation frequency, both of which degrade the over all system power performance.
\begin{table}[h!]
\begin{center}
\begin{tabular}{ p{3cm} | c | c | c | c | c | c | c }
Reference & \cite{5986090} & \cite{4242293} & \cite{5117770} & \cite{5615627} & \cite{5617608} & \cite{4982876} & This Work \\
Technology (nm) & 65 & 90 & 90 & 65 & 65 & 65 & 180 \\
Modulation & Delay & PPM & BPSK & PPM & OOK & PPM & Delay \\
Avg. Power (W) & 660n & 718u & 3.3m & 600u & 217u & 4.36m & 68.9u \\
PRF (Hz) & 1.3M & 16.7M & 100M & 50M & 24M & 15.6M & 10M \\
Energy per bit (J/bit) & 300f & 37p & 33p & 12p & 8.5p & 17p & 890f\\
FCC compliant & No & Yes & Yes & Yes & Yes & Yes & Yes* \\
\end{tabular}
\end{center}
\caption{Performance overview of recent UWB transmitters}
\ context.TABLE: 4
\begin{flushleft}
*to be confirmed with measurements\\
\end{flushleft}
\end{table}
With reference to table 4 it can be noted that the delay modulation generally achieves respectable energy per bit FOMs in comparison to other modulation schemes as the highly energetic pulses are encoded with multiple bits. Note that even though our design was based on a less aggressive 180 nm process the UWB pulse generator allowed us to achieve comparable performance to designs that were implemented in 65 nm technologies for which the transistors achieve a transition frequency \\( F_T \\) that extends far beyond the UWB bandwidth which is essentially a prerequisite for employing the piece-wise reconstruction of analytically optimal wavelets.
The two figures 33 & 34 show the full custom layout that was designed for the proposed UWB transceiver. The actual transistor level layout of transmitter and receiver combined occupy approximately 100 um by 200 um with a separate self calibrated DCO for each section. The overall area is increased by 300% due to the on-chip inductor that was integrated for the UWB pulse generator. The figure~ \ref{LL2} also shows a large array of decoupling capacitors (in yellow) that remove noise from the supply pads that may influence the DCO operation and introduce additional phase noise.
{{< figure src="/images/msc-thesis/die1.png" title="Figure 33: Detail of the Full custom Digital layout of UWB, counter clockwise, TX [DCO(red), Delay Modulator(l. blue), UWB Pulse Generator(orange)] & UWB RX [DCO(purple), Demodulator(green), DLL(yellow), RF Energy detector(d. blue)]." width="500" >}}
{{< figure src="/images/msc-thesis/die2.png" title="Figure 34: Layout sent for tape out illustrating the guard-ring (blue), RF pads (red), Integrated Inductor (green), and UWB TX/RX (green)." width="500" >}}
# Conclusion
This thesis has addressed the design considerations of an implantable biotelemetry system with respect system level optimizations and presented the circuit level innovation that focused on optimizing power requirements.
During the development of the forward link in particular the modulation techniques of contemporary literature were evaluated and, with respect to the projected system requirements, BPSK modulation was found to be the most promising. This was illustrated by the fact that BPSK modulation minimizes the off-chip components and by employing the proposed modulation scheme relatively high bit rates were achieved without degrading the overall power transfer efficiency of the forward link. Moreover, the efficiency achieved illustrates that the class-E amplifier operation shows a good synergy with the BPSK modulation mechanism without the need to supply modulation techniques or additional filtering components.
Since UWB application for biomedical implants is a relatively new and emerging field a significant amount of effort was put toward developing a scalable delay encoding system that could give way for systems that maximize efficiency FOMs like sub 100 fJ energy dissipation per bit transferred. The presented work allows numerous bits to reliably be encoded into a single energetic pulse with a good control over how robust the encoding scheme is towards phase noise as only one element is required to be tuned. The delay modulator presented here is for that reason integrated with a self-calibration frequency locked loop that keeps chip area to a minimum. A conservative estimate bit error rates due to channel induced AWG noise was also presented to given insight to how higher order delay encoding effects the transmission of data. With the theoretical basis covered, circuit specific elements were developed such as a widely tuneable digital oscillator and a particularly energy efficient UWB pulse generator based off the impulse response of a LC resonator. In extension to the transmitter, an UWB antenna was designed where a significant improvement in the low-frequency group-delay and reflection co-efficient was found if the first resonant mode was degenerated by an asymmetric extension of the ground plane. The antenna was fabricated but fine tuning of the etching process was still required for the EM simulation results to match the measured response at the frequencies above 5 GHz. Finally a simple energy detection receiver is developed that will allow testing of the full custom digital layout that was designed for fully integrated the UWB transceiver system.
## Future Work
Due to the broad scope telemetry systems there are a wide range of possible future developments that can be considered in extension to what has been presented here. First and foremost it would be important to develop a more standardized receiver that is based on GHz sample acquisition through FPGA and uses a channel estimation adaptive filter to detect the delay encoded words sent by the implanted device. Secondly the UWB antenna needs to go through several process development cycles under a automated fabrication process until the antenna is well characterized. In addition the antenna need to be tuned to match the impedance of the human body right under the skin for maximum radiation efficiency which may even allow for the system to be placed deeper within the body and may be of interest for future work in association to RF powered implants. The final aspect that should be a worthwhile investment lies with developing an integrated rectifier and regulator for the forward transmission link.

146
content/publications/2013/a-890-fj-bit-uwb-transmitter-for-soc-integration-in-high-bit-rate-transcutaneous-bio-implants.md Normal file
View File

@ -0,0 +1,146 @@
---
title: "A 890 fj bit UWB Transmitter for SOC Integration in High Bit-Rate Transcutaneous Bio-Implants"
date: 2013-05-19T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
- publication
- wireless
- CMOS
- biomedical
- telemetry
---
Lieuwe B. Leene, Song Luan, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
The paper presents a novel ultra low power UWB transmitter system for near field communication in transcutaneous bio-telemetries. The system utilizes an all-digital architecture based on minimising the energy dissipated per bit transmitted by efficiently encoding a packet of pulses with multiple bits and utilizing oscillator referenced delays. This is achieved by introducing a novel bi-phasic 1.65 pJ per pulse UWB pulse generator together with a 72 μW DCO that provide a transmission bandwidth of 77.5 Mb/s with an energy efficiency of 890 fJ per bit from a 1.2 V supply. The circuit core occupies a compact silicon footprint of 0.026 mm² in a 0.18 μm CMOS technology.
# 2 Introduction
Since Pulsed Ultra Wide Band (UWB) technology has become available for unlicensed communication, a broad spectrum of ideas have been presented over the past decade with regard to UWB pulse modulation, generation and detection techniques[^1]. Recent literature has primarily demonstrated the potential all-digital UWB transmitters have in achieving ultra low power budgets by operating with aggressive duty cycles while maintaining substantial data rates. These developments are of considerable interest to biomedical applications, for example in neural interfaces estimates indicate that state-of-the-art systems already require data rates up to 40Mb/s without compression and a power budget of several mili-watt[^2]. Moreover, based on the recent projection regarding the steady exponential growth in number of neurons recorded[^3], we expect a considerable demand for a ultra low power wireless link that is capable of transmitting 80 Mb/s and is viable for integration on chip with the neural sensory devices in the coming years.
The UWB transmitter presented here is based on developing a transcutaneous biotelemetry system where the transmitter is coupled to a receiver trough a near field communication channel across the skin boundary. The adoption of near field transmission for power and data is nearly ubiquitous in biotelemetry systems because it alleviates the challenge of coping with the lossy radiation environment of the human body and power restrictions due to thermal dissipation constraints. Moreover, near field communication should allow high SNR values with respect to interfering UWB devices such that a simple energy detection based receiver can fully detect the individual transmitted UWB pulses.
This work presents an UWB transmitter architecture for asynchronous communication that achieves ultra low power consumption by minimising the energy dissipated per bit transmitted (EPB). This is achieved through circuit level optimizations in addition to encoding a packet of pulses with multiple bits. Furthermore scalable PPM modulation is achieved with significant improvements in both resource requirements and phase integrity over conventional techniques that either use a tuneable delay element or multiple delay lines[^4].
This paper is organized as follows. Section 3 presents a discussion on the operation of the proposed architecture. Section 4 presents the transistor level implementations of a Digitally Calibrated Oscillator (DCO) and an novel UWB pulse shaper. Section 7 completes the design aspects of the transmitter by presenting the employed UWB antenna. Sections 8 & 13 demonstrate the performance of the proposed system and conclude upon this paper's findings.
# 3 UWB Transmitter System Concept
The system architecture of the UWB transmitter is shown in Fig. 1. This is based on using a DCO as a reference for the encoded delays intermediate to the pulse positions. This approach allows accurate definition of all relative pulse positions by calibrating a single element thereby reducing the system's resource requirement while maintaining scalability. The bi-phasic pulse generator extends this flexibility by allowing pulses to be modulated in terms of position and phase simultaneously.
{{< figure src="/images/iscas2012/s1.png" title="Figure 1: System level architecture of the UWB Transmitter capable of M-arry PPM and BPSK modulation" width="500" >}}
The PPM modulation mechanism relies on the removal or 'swallowing' of extraneous clock pulses generated by the DCO, hence introducing inter-pulse delays quantized by the DCO's period. This is achieved by disconnecting the power supply from the inter-stage buffer driving the pulse generator for specific intervals. These intervals are specified by a synchronized D flip-flop fed by a shift register with decisions to swallow or transmit the incoming pulse. Exact duty cycles are achieved by enabling the DCO on the rising edge of the input for a burst of clock cycles and disabling the DCO when the shift register detects the end of the pulse package.
A high speed all-digital frequency locked loop is used on system start up to calibrate the DCO to a fixed oscillation frequency. Calibration is an important consideration as DCO frequency off-sets for this topology results in increasingly larger temporal off-sets for increasingly longer pulse packages and amounts to significant phase noise at the receiver.
In order to maximize the efficiency of the transmitter, this system essentially cascades two delay-hopped time-reference (DHTR) pulse pairs where the second pulse is the reference pulse for the third pulse [^5]. The phase of each pulse is given by a 3-bit word, D<sub>2<sub> - D<sub>0<sub>. The implemented design allows the second pulse to be delayed to 8 different positions. The third pulse can then be delayed to 4 different positions with reference to the second pulse including a null position where the pulse is omitted. Note that when the third pulse is omitted standard DHTR modulation is achieved and the bit D0 is ignored. As a result each pulse package encodes 7.75 effective number of bits (ENOBs) with an average of 2.75 pulses per package for a equiprobable code book. The transmitted package may be represented analytically as
$$ s(t)= a_{i} w(t) + b_{i} w(t - A_i \cdot T_{DCO}) + c_i w( t - (A_i + B_i) \cdot T_{DCO} ) $$
where i is the package index, w(t) is the UWB pulse shape, and T<sub>DCO<sub> is the unit delay introduced by the DCO's period. a<sub>i<sub>, b<sub>i<sub>, c<sub>i<sub> in { +1, -1 } are the respective first, second, and third pulse phases. A<sub>i<sub> & B<sub>i<sub> are the respective delays of the first and second pulse pairs. Fig. 2 exemplifies two pulse packets with reference to the DCO clock whose encoding is given by; A<sub>1<sub>, B<sub>1<sub>, D(2-0)<sub>1<sub> = [010, 10, 010] and A<sub>2<sub>, B<sub>2<sub>, D(2-0)<sub>2 = [001, 01, 110].
{{< figure src="/images/iscas2012/ex.png" title="Figure 2: Waveforms illustrating two different DHTR modulated pulse packages. a) DCO reference, b) package index 1 [010, 10, 010], c) package index 2 [001, 01, 110]$. " width="500" >}}
# 4 Circuit Implementation
The circuit has been implemented in a commercially available 0.18 μm CMOS technology provided by AMS/IBM (C18A4/7sf) and has been designed to operate from a 1.2 V supply. This section details the circuit level design and implementation.
## 5 Digitally Calibrated Oscillator
The DCO employed by the UWB transmitter is an 8-bit calibrated 5-stage ring oscillator as shown in Fig. 3. The five most significant bits of the calibration state C<sub>7<sub> to C<sub>3<sub> adjust the main capacitive load by shorting a select set of capacitors from a binary weighted array to ground and leaving others floating. The lower 3 bits C<sub>2<sub> to C<sub>0<sub> fine tune the oscillation frequency by adjusting the NMOS side driving capability of an the inverter stage achieving a resolution in the order of tens of pico-seconds by making fractional changes in aspect ratio for different matched transistors. Since the transistor 'on' resistance is inversely proportional to the tuned driving capability of the inverter, a 3-input look-up-table-based remapping is introduced. This improves the performance of the fine calibration bits by linearizing the tuneable delay with respect to the control bits. Note that the main delay elements are primarily dependent on the NMOS devices and the parasitic capacitance which by reducing the dependence on PMOS devices improves the sensitivity to process variation.
{{< figure src="/images/iscas2012/s2.png" title="Figure 3: Circuit schematic of the 5-stage digitally calibrated Ring oscillator" width="500" >}}
## 6 UWB Pulse Shaper
The pulse shaper presented here has been partly adopted from previous work that used integrated LC components to filter out the unwanted spectrum to meet the FCC mask requirements[^6]. An integrated inductor is differentially pulsed with current over 180 ps which perturbs the LC resonator to start oscillating with the induced energy. This resonating energy is leaked towards the resistive load of the antenna over a longer time frame of 1ns. There is an explicit capacitive impedance mismatch at the bond-pad such that most of the energy induced by the driving transistors is fed into the inductor.
The circuit consists of a two part design, including digital and RF sections. The Digital pre-shaper is shown in Fig. 4. This uses a popular glitch generator to generate 180ps long Gaussian like pulses, which are demultiplexed to two inverter chains to boost the driving capability of the output. It is important to note that these chains have a different output polarity but both output the buffered pulse together with a delayed and inverted pulse. The driving transistors in Fig. 5 source the inductor with pulsed current proportional to the glitch duration. The purpose of the delayed pulse is to cancel the DC component generated by the transient impulse response of the lossy LC resonator, by injecting an equal but complementary pulse at the opposite port of the inductor. By driving either the end connected to the load, or the C<sub>res<sub> end of the inductor first, the polarity of the UWB pulse is well controlled.
The circuit shown in Fig. 4 also illustrates how a shift register can interface the UWB transmitter with a parallel input data stream. In the RF section (Fig. 5), it is interesting to note that since the transistor pairs M1, M4, M2, and M3 are matched in terms of driving capability this particular topology is immune to variations in pulse length. This would easily distort the output spectrum of aggressive UWB pulse generators that use multiple glitch generators to shape the pulse. The integrated 4 nH inductor is a single layer 6-turn 8-sided spiral with poly-silicon ground plane and dimensions 4 μm, 2.8 μm, 66 μm corresponding to the trace width, trace spacing, and outer radius respectively.
{{< figure src="/images/iscas2012/s3.png" title="Figure 4: Circuit Schematic of the digital pre-shaping" width="500" >}}
{{< figure src="/images/iscas2012/s4.png" title="Figure 5: Circuit schematic of the RF section with L = 4nH; C<sub>res<sub> = 200fF; - Note that the relative temporal delays of the driving signals are not to scale." width="500" >}}
# 7 Miniaturized UWB Antenna
An omni-directional UWB antenna that radiates in the plane of the skin boundary is used for near field coupling instead of an RF coil to reduce the potential interference from echos and other UWB sources. The antenna here is based on a generic elliptic co-planar mono-pole geometry which has been shown to have good non-dispersive radiation characteristics over the entire bandwidth[^7]. To assure that the radiated pulse meets the FCC requirements in the sub 2 GHz band, the antenna is required to reject this band by at least 20 dB with respect to the insertion loss in the 3.1 GHz - 10.6 GHz band.
{{< figure src="/images/iscas2012/gg.png" title="Figure 6: Illustration of the antenna geometry and a high contrast photograph of a prototype next to a British pound with dielectric cover removed." width="500" >}}
The antenna geometry is shown in Fig. 6, with the various antenna dimensions designed as follows; R = 5mm, R<sub>G<sub> = 400 μm, R<sub>T<sub> = 800 μm, G = 290 μm, W = 440 μm, C = 260 μm, t<sub>d<sub> = 635 μm, t<sub>m<sub> = 35 μm.
The antenna uses an asymmetric extended ground plane to damp the first strong resonance that is usually centred around 3-4GHz and can introduce significant pulse distortion. To improve the viability of the antenna for an implanted system a high dielectric laminate with copper metallization, RO1030, was used on both sides of the metallization to scale down the dimensions to allow an off-chip imprint below 2 cm².
# 8 Results
The design was simulated in Cadence IC 5.141 ISR with foundry-supplied PSP models. This section details the DCO, pulse generator, antenna and system performance.
## 9 Digitally Calibrated Oscillator
Monte Carlo simulation revealed the proposed DCO has a standard deviation in oscillation frequency of 44.9 MHz. The calibration mechanism allows the DCO to sweep through from 750 MHz to 390 MHz with a resolution of approximately 4.5 MHz as shown in Fig. 7. The DCO consumes an average of 72 μW during continuous operation at 500MHz.
{{< figure src="/images/iscas2012/swp.png" title="Figure 7: Transient simulation of the DCO sweeping through all calibration states" width="500" >}}
## 10 Pulse Generator
The transient simulation of the UWB pulse generator is illustrated in Fig. 8. This demonstrated a power dissipation of 1.65 pJ per pulse with a 344 mVpp Amplitude. Spectral analysis further shows a peak power spectral density of -50.6 dBm/MHz and FCC mask compliance over the 3.1 GHz - 10 GHz band.
{{< figure src="/images/iscas2012/tr.png" title="Figure 8a: bi-phasic UWB temporal response." width="500" >}}
{{< figure src="/images/iscas2012/dfs.png" title="Figure 8b: Simulated PSD of the designed UWB pulse & the indoor UWB FCC mask as annotated." width="500" >}}
## 11 UWB antenna
{{< figure src="/images/iscas2012/a1.png" title="Figure 9: Simulated reflection co-efficient S11 for the UWB antenna radiating in free space." width="500" >}}
Preliminary EM simulations were carried out using CST MICROWAVE STUDIO package with a 50 ohm port impedance. Fig. 9 shows the UWB antenna achieves a -10 dB reflection over the 3.66 GHz to 7 GHz band without significant phase distortion.
## 12 System Performance
The complete system level simulation is shown in Fig. 10. This demonstrates the transmitter operating with a package frequency rate (PRF) of 20 MHz transmitting a 155 Mb/s bit stream of pseudo random data while consuming less than 40 pJ under 300 ns. For the target 10MHz PRF, the system consumes an average of 68.9 μW corresponding to a 890 fJ of energy dissipated per bit transmitted. The custom digital layout is shown in Fig. 11. This measures 135 μm by 60 μm excluding the 132 μm by 132 μm integrated inductor, giving a total core area of 0.026 mm².
{{< figure src="/images/iscas2012/ps.png" title="Figure 10: Simulation result illustrating the voltage waveforms generated by the different components with a 20 MHz PRF and a random input data stream." width="500" >}}
{{< figure src="/images/iscas2012/tx.png" title="Figure 11: Core Layout of the UWB transmitter with each block annotated as; a) UWB Pulse shaper b) Pulse Swallowing c) Serial Interface d) DCO." width="500" >}}
# 13 Conclusion
An all-digital UWB transmitter architecture has been presented for biomedical SOC integration that seeks to improve system efficiency by achieving asynchronous ultra low power operation for arbitrary bit rates. A DCO based modulation scheme is introduced that significantly reduces the on-chip resource requirements for PPM modulation and allowed efficient 8-bit encoding onto 3 UWB pulses. The novel low power bi-phasic UWB pulse generator further allows this system to achieve 890 fJ EPB on a 0.18 μm CMOS process to make integration with state of the art neural interfaces viable. The overall system achieves very aggressive performance in terms of power consumption for 10MHz PRF as illustrated in table 1. Future work will focus on tuning the UWB antenna to match the tissue impedance and characterizing the near field communication channel.
Table 1: Performance overview of recent UWB transmitters
|Reference | [^8] | [^9] | [^10] | [^11] | [^12] | This Work |
|----|----|----|----|----|----|----|
|Tech. (nm) | 65 | 130 | 65 | 65 | 65 | 180 |
|Modulation | DHTR | BPSK | PPM | OOK | BPSK | DHTR |
|Power (W) | 660n | 3.3m | 820u | 217u | 4.36m | 68.9u |
|PRF (Hz) | 0.6M | 100M | 50M | 24M | 15.6M | 10M |
|EPB (J/bit) | 300f | 33p | 12p | 8.5p | 17.5p | 890f|
|FCC compliant | - | Yes | Yes | Yes | Yes | Yes |
# Refernces:
[^1]: A.Chandrakasan, F.Lee, D.Wentzloff, V.Sze, B.Ginsburg, P.Mercier, D.Daly, and R.Blazquez, ''Low-power impulse uwb architectures and circuits,'' Proc. IEEE, vol.97, no.2, pp. 332 --352, 2009.
[^2]: A.Eftekhar, S.Paraskevopoulou, and T.Constandinou, ''Towards a next generation neural interface: Optimizing power, bandwidth and data quality,'' in Proc. IEEE BioCAS, 2010, pp. 122 --125.
[^3]: I.Stevenson and K.Kording, ''How advances in neural recording affect data analysis,'' Nature neuroscience, vol.14, no.2, pp. 139--142, 2011.
[^4]: T.Buchegger, G.Ossberger, A.Reisenzahn, A.Stelzer, and A.Springer, ''Pulse delay techniques for ppm impulse radio transmitters,'' in Proc. IEEE Conf. UWB Syst. Tech., 2003, pp. 37 -- 41.
[^5]: R.Hoctor and H.Tomlinson, ''Delay-hopped transmitted-reference rf communications,'' in Proc. IEEE Conf. UWB Syst. Tech., 2002, pp. 265--269.
[^6]: L.Moreira, W.van Noije, D.Silveira, S.Kofuji, and C.Sassaki, ''A small area 2.8pj/pulse 7th derivative gaussian pulse generator for ir-uwb,'' in Proc. CJMW, 2011, pp. 1 --4.
[^7]: J.Liang, C.Chiau, X.Chen, and C.Parini, ''Study of a printed circular disc monopole antenna for uwb systems,'' IEEE Trans. Antennas and Propagation, vol.53, no.11, pp. 3500 -- 3504, 2005.
[^8]: M.Mark, Y.Chen, C.Sutardja, C.Tang, S.Gowda, M.Wagner, D.Werthimer, and J.Rabaey, ''A 1mm$^3$ 2mbps 330fj/b transponder for implanted neural sensors,'' in Proc. IEEE VLSIC, 2011, pp. 168--169.
[^9]: B.Qin, H.Chen, X.Wang, A.Wang, Y.Hao, L.Yang, and B.Zhao, ''A single-chip 33pj/pulse 5th-derivative gaussian based ir-uwb transmitter in 0.13$\mu$m cmos,'' in Proc. IEEE ISCAS, 2009, pp. 401--404.
[^10]: Y.Park and D.Wentzloff, ''An all-digital 12pj/pulse 3.1 - 6.0ghz ir-uwb transmitter in 65nm cmos,'' in Proc. IEEE ICUWB, vol.1, 2010, pp. 1--4.
[^11]: H.Miranda and T.Meng, ''A programmable pulse uwb transmitter with 34% energy efficiency for multichannel neuro-recording systems,'' in Proc. IEEE CICC, 2010, pp. 1--4.
[^12]: P.Mercier, D.Daly, and A.Chandrakasan, ''An energy-efficient all-digital uwb transmitter employing dual capacitively-coupled pulse-shaping drivers,'' IEEE JSSC, vol.44, no.6, pp. 1679--1688, 2009.

131
content/publications/2013/a-compact-recording-array-for-neural-interfaces.md Normal file
View File

@ -0,0 +1,131 @@
---
title: "A Compact Recording Array for Neural Interfaces"
date: 2013-09-13T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
- publication
- instrumentation
- CMOS
- biomedical
- sensor
---
Lieuwe B. Leene, Yan Liu, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
This paper presents a 44-channel front-end neural interface for recording both Extracellular Action Potentials (EAPs) and Local Field Potentials (LFPs) with 60 dB dynamic range. With a silicon footprint of only 0.011 mm² per recording channel this allows an unprecedented order of magnitude area reduction over state-of-the-art implementations in 0.18 μm CMOS. This highly compact configuration is achievable by introducing an in-channel Sigma Delta assisted Successive Approximation Register (\\(\Sigma\Delta\\)-SAR) hybrid data converter integrated into the analogue front-end. A pipelined low complexity FIR filter is distributed across 44-channels to resolve a 10-bit PCM output. The proposed system achieves an input referred noise of 6.41 μVrms with a 6 kHz bandwidth and sampled at 12.5 kS/s, with a power consumption of 2.6 μW per channel.
# 2 Introduction
The recent trend in on-chip instrumentation for neural electrophysiological recording has largely been motivated by the growing interest in observing large scale neuronal activity using small chronic implants. Such tools are crucial in the quest to better understand the brain, but also in revealing fundamental mechanisms behind neurological and psychiatric diseases for developing new diagnostics and therapeutic devices. Microelectronic bio-instrumentation systems currently have the capacity for profoundly impact such key scientific efforts [^1].
State-of-the-art neural recording systems have made significant progress over past years by objectively improving figures of merit, most notably that of the Noise Efficiency Factor (NEF) [^2]. This progress has not however generally had the same impact on silicon footprint, which is also critical for the long term increase in recording capacity and System-on-Chip (SOC) platforms. Although a number of compact circuits including analogue amplifiers and data converters have been proposed for biomedical applications, less attention has been given to area reduction from a system perspective apart from the typical multiplexing of the Analogue-to-Digital Converter (ADC). This is partly due to the challenge in multiplexing ultra low power analogue without significantly degrading performance (i.e. due to parasitics and inter-channel interference). The work presented herein applies a number of ideas aimed at collectively reducing the silicon area towards highly scalable systems. Through a combination of novel structures and circuit level implementations that allow for hardware reuse (and thus area reduction), this work demonstrates the capacity for unprecedented area efficiency at the system level.
The target system specifications herein apply to a Brain Machine Interface (BMI) recording the (raw) signal including both LPFs and EAPs. Furthermore, such a system can provide undistorted EAP recordings which are typically due to a high pass filter centred around 100--500 Hz. This implies an input-referred signal amplitude ranging from 10 μV to 10 mV, which has a dynamic range equivalent to that of a10-bit converter with a frequency bandwidth of 100 mHz to 3 kHz for optimal data post processing [^1]. This system aims towards a robust SOC platform, utilising a fully-differential structure to reject supply noise, as well as even order distortion harmonics, for the integration of a very large number of recording channels with wireless and digital post-processing systems.
This organisation of this paper is as follows: Section 3 outlines the proposed system-level architecture; Section 4 details the circuit level implementation; Section 9 presents simulated system and circuit level results; and finally, Section 10 compares the overall system characteristics to the current state-of-the-art and concludes the paper.
# 3 System Architecture
{{< figure src="/images/biocas2013/I1.png" title="Figure 1: Top level architecture of the proposed system." width="500" >}}
The top level system is illustrated in Fig 1, showing the in-channel architecture consisting of two multiplexed low noise amplifiers, a hybrid data converter, and two ultra compact digital filters. The system integrates 44-channels together with the primary objective being to combine state-of-the-art instrumentation techniques to achieve a substantial reduction in area through a novel implementation. The Front End Amplifier (FEA) utilises a chopper technique to alleviate the need for very large transistors and a Sigma Delta assisted Successive Approximation Register (\\(\Sigma\Delta\\)-SAR) is developed to significantly reduce the size of the capacitor bank typically required for a 10-bit resolution output. This capacitor bank is also used to implement a switched-capacitor digital filter to reject the unwanted chopper harmonics thus avoiding the requirement for additional analogue filter blocks. Finally, the filter needed to decimate the \\(\Sigma\Delta\\)-SAR modulator output is shared in the digital domain through a pipeline structure that require only a low resolution accumulator, thereby mitigating the computational costs typically associated with \\(\Sigma\Delta\\) decimation.
# 4 Circuit Implementation
## 5 Chopper Modulated Analog Front End
{{< figure src="/images/biocas2013/I2.png" title="Figure 2:FEA structure illustrating the feedback and chopper configuration." width="500" >}}
The AFE is illustrated in Fig. 2. This Capacitively-Coupled Chopper Instrumentation Amplifier (CCIA) [^3] consists of a Miller compensated 2-stage design with capacitive feedback. Using a single analogue block for amplification naturally has its trade-off as the high gain requirement implies a large input capacitance C<sub>in<sub> = 6.5 pF) but at the same time reduces the value of the Miller capacitor that introduces the dominant pole of the system for a given thermal noise floor. The feedback network is configured to introduce 34 dB of differential gain and improve the input impedance of the amplifier through positive feedback where C<sub>fp<sub> = C<sub>fb<sub>, Zin=\\( \frac{Gain}{2 \cdot f_{chop} \cdot C_{in}}\\) = 77 MΩ, and f<sub>chop<sub> = 50 kHz.
{{< figure src="/images/biocas2013/I5.png" title="Figure 3:Circuit level schematic of the FEA." width="500" >}}
The circuit level schematic of the FEA is shown in Fig. 3. This implementation uses the complementary input pair to allow good current efficiency for the 1.8 V analogue supply together with a class-AB, low output resistance, cascade gain stage to drive the large switching capacitance loading the output from the feedback network. The circuit also includes the common mode feedback and ADC sampling capacitors. A MOS capacitor is used to introduce the dominant pole at 6 kHz while the feedback network is implemented using MIM capacitors. The overall high pass behaviour of this structure is implemented through the periodic reset of the input and the output which also auto-zeros the input pair offset. This offset compensation is maintained outside the reset phase by biasing the gate of the reset switch at the mid-rail voltage such that it behaves as a traditional MOS-based pseudo-resistor. This reset mechanism benefits due to the improved noise characteristic over a DC-servo loop implementation that also requires a significant amount of additional area. However, the signal distortion introduced though this technique can be compensated in the digital domain [^4]. All current sourcing transistors (M5-M10) have cascode implementations (not shown in Fig. 3) to provide adequate common mode rejection and common mode input range of \\(\pm\\)200 mV, which is biased and filtered through the reset switch.
## 6 Hybrid \\(\Sigma\Delta\\) assisted SAR ADC
The data converter is based on extending the resolution of a small 6-bit SAR ADC with a continuous time \\(\Sigma\Delta\\) modulator that resolves the remaining quantisation error residue from the SAR algorithm. The primary components of the modulator are integrated into the pre-gain stage structure of the comparator as illustrated in Fig. 4. During initial SAR operation the gm-C filter is switched out and the input pair directly feeds into a diode-connected load for wideband operation while the filter capacitors are reset. Once the last SAR bit is resolved the loop filter is enabled implementing a second-order chain of integrators with a weighted feedforward summation modulator topology that allows low power operation with minimised signal distortion. Note that in Fig. 4 during SAR operation V\\(\Sigma\Delta\\) is at the common mode and is then modulated between ±V<sub>ref<sub> such that the feedback is necessarily always twice as large as the residue error to ensure modulator stability and optimal residue quantisation.
{{< figure src="/images/biocas2013/I3.png" title="Figure 4: Circuit level schematic of the hybrid \\(\Sigma\Delta\\)-SAR converter." width="500" >}}
The general organisation and operation of the ADC is illustrated in Fig. 7. Given that N=6 is the resolution of the SAR DAC and OSR=44 is the conventional oversampling ratio of the modulator. It can be observed that both SAR and \\(\Sigma\Delta\\) operation is at 5 MHz and takes N+OSR cycles to finish or a total of 10 μs for a sampling rate of 25 kHz at the 25 % duty cycle. In addition to using 5 reference voltages this topology makes a extreme reduction in size by a factor of 32 and will allow large 8 by 8 μm² unit capacitors to reduce the sensitivity of process variation thereby achieving a 10-bit resolution without any in-channel calibration.
## 7 Chopper Rejection
In order to reject chopper harmonics introduced by the up-modulated offset aggressors, the capacitive array is used as a switched capacitor network to implement a notch filter centred around the odd harmonics of the chopper frequency when the data converter is not operational. The output of the AFE is sampled in the time domain and weighted using different sets of capacitors to implement a 3<sup>rd<sup> order Bartlett window filter before ADC conversion. This technique avoids the need for a ripple reduction loop which typically also requires an analogue filter with large capacitors. Fig. 5 shows the 4-phase sampling sequence that operates at 50 kHz. The net charge, Q<sub>total<sub>, quantised by the converter is expressed as follows.
$$ \frac{Q_{total}}{C_{unit}} = 8 V_{diff} \left[ n-1 \right] + 16 V_{diff} \left[ n-2 \right] + 8 V_{diff} \left[ n-3 \right] $$
Where V<sub>diff<sub> is the sampled differential output voltage of the amplifier and C<sub>unit<sub> is the 120 fF unit capacitance of the converter that also averages sampling noise during conversion. This allows the notch filter characteristic illustrated in Fig. 5, to reject a significant amount of high frequency aggressors.
{{< figure src="/images/biocas2013/F2.png" title="Figure 5:Switched capacitor filter timing diagram (left) and frequency response (right)" width="500" >}}
## 8 Digital Filter
The filter structure used to process the \\(\Sigma\Delta\\) output is illustrated in Fig. 6. This structure distributes the overall structure across all channels such that each channel requires only a 7-bit register, a 12-bit registered add/subtract accumulator as well as the two 7-bit registers from the SAR to implement the hybrid functionality demonstrated here. The filter coefficients are hardwired into each channel's 7-bit register such that it is loaded during reset and circulated through all channels.
{{< figure src="/images/biocas2013/I6.png" title="Figure 6:Implementation of the pipelined FIR structure." width="500" >}}
The \\(\Sigma\Delta\\) output sign modulates the accumulator which integrates over a 44-point hanning window, implementing a FIR filter without multipliers. A more traditional decimation filter implemented using a cascaded integrator comb (CIC) filter is much less effective here. This is because the structures cannot be shared (across channels) and will require a larger number of samples than the OSR to evaluate the residue error which due to the intermediate SAR process being continuously disrupted. Fortunately the resolution only needs to be extended by 4-bits to achieve the required 60 dB dynamic range. Therefore a compact 44<sup>th<sup> order window at 7-bit unsigned resolution suffices. The structure has shown to make a good estimate of the stationary input to the modulator even with high levels of quantisation noise allowing us to decrease to resolution of the stored coefficients that are given by the following expression.
$$ w[n] = C \cdot \left[ 1 - cos \left( \frac{2 \pi n}{N-1}\right) \right]^{0.7} $$
The coefficients, w[n], represent a modified hanning window that results in a better Differential Non-Linearity (DNL) characteristic over other FIR windows when quantised to 7-bits. Note that C=0.024, N=46, and $n \in \left[1, 2, ..., N-2 \right]$ represent the normalisation constant, effective filter order, and the non-zero coefficient index respectively.
{{< figure src="/images/biocas2013/example.png" title="Figure 7: Transient operation of the ADC conversion." width="500" >}}
{{< figure src="/images/biocas2013/os.png" title="Figure 8: Output of the analogue channel with a 19 mV peak to peak 1 kHz input." width="500" >}}
# 9 Simulation Results
Preliminary validation of the proposed implementation has been done through schematic level simulations in the Cadence IC 6.1.5 Design Environment using industry provided PSP models for the commercially available 6 Metal 0.18 μm CMOS technology (AMS/IBM C18A6/7SF). The entire channel has been stimulated with 19 mV peak to peak 1 kHz differential signal for full swing at the ADC input of which a single ADC conversion is illustrated in Fig. 7. The quantised output spectrum of this simulation is shown in Fig. 8 which indicates a 1.2% total harmonic distortion for a full swing output that is due to the AFE. Fig. 10 illustrates the characteristics of the FIR filter in time and frequency domain respectively. Fig. 11 presents 10.2 ENOB performance through the 0.5 LSB bounded integral and differential non-linearities of the converter. The channel level layout is shown in Fig. 12 indicating a 440 μm by 50 μm area requirement for 2 recording channels.
{{< figure src="/images/biocas2013/noise.png" title="Figure 9: Noise density simulated at the output of the FEA" width="500" >}}
{{< figure src="/images/biocas2013/F1.png" title="Figure 10: 7-bit quantised Hanning FIR filter showing frequency (top) and time (bottom) domain responses." width="500" >}}
{{< figure src="/images/biocas2013/F3.png" title="Figure 11: \\(\Sigma\Delta\\)SAR non-linearities showing INL (top), DNL (bottom)" width="500" >}}
{{< figure src="/images/biocas2013/Area2.png" title="Figure 12: Layout of 4 Channels integrated together with CMIM capacitors overlaying the 440 μm by 100 μm silicon footprint." width="500" >}}
# 10 Conclusion
The ultra compact topology presented has demonstrated the means by which the recording channel can scale down below a 0.01 mm² area while maintaining its recording fidelity and advanced spectral filtering characteristics. In addition the proposed 10 bit hybrid data converter achieves a factor of 32 reduction in area over equivalent data converters through pipelining and \\(\Sigma\Delta\\) modulation. With an input referred noise of 6.4 μVrms this system consumes 2.6 μW resulting in excellent Noise Area product of 0.007 μVrms mm². The overall system characteristics are shown in Table 1 demonstrating respectable performance particularly with respect to the order of magnitude reduction in area per channel and the 60 dB dynamic range for the given power budget.
Table 1: Performance per channel of Neural Recording Arrays
|Reference | [^5] | [^6] | [^7] | [^8] | This work |
|----|----|----|----|----|----|
|Year | 2011 | 2012 | 2012 | 2012 | 2013 |
|Tech. [nm] | 180 | 250 | 130 | 130 | 180 |
|Power [μW] | 10.1 | 3.96 | 68 | 5.9 | 2.59 |
|High Pass [Hz] | 126m | 100m | 1 | 200 | 100m |
|Low Pass [Hz] | 12k | 17k | 10K | 6.9K | 6K |
|Noise [μVrms] | 5.4 | 4.8 | 2.2 | 3.8 | 6.41 |
|NEF | 4.4 | 2.9 | 4.5 | 2.16 | 2.27 |
|Area [mm²] | 0.31 | 0.07 | 0.19 | 0.16 | 0.011 |
|ADC Res. | 8 | 9 | 10 | 8 | 10 |
|Sample [kS/s] | 125 | 60 | 31 | 27 | 12.5 |
# 11 Acknowledgment
This work was supported by the UK EPSRC (grants EP/I000569/1 and EP/K015060/1).
# Refernces:
[^1]: F.K. etal., ''Drug discovery: A jump-start for electroceuticals,'' Nature, vol. 496, pp. 159--161, 2013.
[^2]: R.Rieger, Y.-Y. Pan, and J.Taylor, ''Design strategies for multi-channel low-noise recording systems,'' in Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, 2007, pp. 561--564.
[^3]: Q.Fan, F.Sebastiano, J.Huijsing, and K.Makinwa, ''A 1.8 w 60 nv hz capacitively-coupled chopper instrumentation amplifier in 65 nm cmos for wireless sensor nodes,'' Solid-State Circuits, IEEE Journal of, vol.46, no.7, pp. 1534--1543, 2011.
[^4]: Y.Chen, A.Basu, and M.Je, ''A digitally assisted, pseudo-resistor-less amplifier in 65nm cmos for neural recording applications,'' in Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on, 2012, pp. 366--369.
[^5]: W.Wattanapanitch and R.Sarpeshkar, ''A low-power 32-channel digitally programmable neural recording integrated circuit,'' Biomedical Circuits and Systems, IEEE Transactions on, vol.5, no.6, pp. 592--602, 2011.
[^6]: K.Al-Ashmouny, S.-I. Chang, and E.Yoon, ''A 4 $\mu$w/ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-d neural microsystems,'' in Biomedical Circuits and Systems Conference (BioCAS), 2011 IEEE, 2011, pp. 1--4.
[^7]: H.Gao, R.Walker, P.Nuyujukian, K.Makinwa, K.Shenoy, B.Murmann, and T.Meng, ''Hermese: A 96-channel full data rate direct neural interface in 0.13 m cmos,'' Solid-State Circuits, IEEE Journal of, vol.47, no.4, pp. 1043--1055, 2012.
[^8]: A.Rodriguez-Perez, J.Masuch, J.Rodriguez-Rodriguez, M.Delgado-Restituto, and A.Rodriguez-Vazquez, ''A 64-channel inductively-powered neural recording sensor array,'' in Biomedical Circuits and Systems Conference (BioCAS), 2012 IEEE, 2012, pp. 228--231.

144
content/publications/2014/an-adaptive-16-64-khz-9-bit-sar-adc-with-peak-aligned-sampling-for-neural-spike-recording.md Normal file
View File

@ -0,0 +1,144 @@
---
title: "An adaptive 16/64 kHz, 9-bit SAR ADC with peak-aligned sampling for neural spike recording"
date: 2014-06-01T15:26:46+01:00
draft: false
toc: true
math: true
type: posts
tags:
- publication
- instrumentation
- CMOS
- biomedical
- sampling
---
Lirong Zheng, Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
This paper presents a novel method and circuit for feature-driven data acquisition in single neuron recording. By dynamically adjusting the phase of the sampling clock in a Successive Approximation Register (SAR) Analogue to Digital Converter (ADC), the samples can be maximally aligned to the spike extrema (peaks). This is achieved by using spike detection to switch from a 'coarse' to 'fine' sampling clock, and triggering a peak-search algorithm to determine the offset between the peak occurrence and the coarse clock. Subsequent samples are then aligned to the peak by shifting the coarse clock by the measured offset. This adaptive sampling scheme thus allows for improved temporal precision on features of interest (i.e. peaks) whilst maintaining a coarse effective sampling rate, also minimising power consumption. The proposed method reduces the output data bandwidth by approximately 70% in comparison to a fixed-sampling rate data converter that would achieve similar precision in peak alignment. The circuit implementation achieves 9-bit resolution with a 93 fJ/conversion-step energy efficiency in a standard 0.35\\( \mu\\)m CMOS technology.
# 2 Introduction
In the quest towards understanding the human brain, neuroscientists are now using 'new' research tools to record single neuron activity in-vivo. Neural probes consisting of micro-fabricated multi-electrode arrays (MEAs) together with supporting recording electronics are providing the opportunity to observe the extracellular activity of an increasing number of neurons in real-time [^1]. To this end, the Neural Engineering and BioCAS communities have made significant progress in the past decade, developing countless integrated, multi-channel neural recording interfaces, Eg. \cite{harrison2007low, bonfanti2010multi, gao2012hermese}. These amplify, filter and digitise the Extracellular Action Potentials (EAPs) with hardware specifications carefully selected so as to maintain signal integrity for post-processing or offline analysis [^5].
Spike sorting allows the decomposition of extracellular recordings into single unit EAP activities. This process typically involves spike detection, alignment, feature extraction and clustering. Although neural interfaces maintain the signal bandwidth in front-end conditioning and comply to Nyquist criteria in digitisation, the temporal precision of spike features can still be compromised in quantisation. Specifically, spike peaks can be 'missed' if incident between sampling cycles, and can then be prone to sampling error causing the peak magnitude be undersampled. The precise detection of spike peaks is critical in ensuring good alignment for spike sorting [^6]. In methods such as template matching it has been shown that spike sorting accuracy degrades significantly with poor alignment [^5]. However, if good alignment can be maintained, then decreasing the template size (i.e. using a reduced sampling rate to provide fewer samples for a fixed spike window) has a negligible impact on spike sorting accuracy. In practice, good alignment can be achieved either by: (1) increasing the sampling rate, thus increasing the temporal resolution, or (2) reducing the sampling rate and interpolating (i.e. upsampling) to 'reconstruct' the peak. Both these methods however are undesirable, as they increase complexity and thus hardware resource (power and area) requirements.
This paper presents a novel data converter design that aligns its samples to the spike peak by adapting its sampling rate, thus combining the good alignment accuracy of a high sampling rate, with the reduced data bandwidth (and power consumption) of a low sampling rate. The core is based on a SAR charge redistribution ADC, which is the topology used in all integrated neural interfaces due to low area and power requirements for low to medium resolution converters. Although adaptive SAR ADCs have previously been reported for neural recording applications \cite{o2011adaptive, huang20121}, these adapt the resolution rather than sampling rate and therefore would not provide benefit to spike alignment as presented herein.
The paper is organised as follows: Section 3 introduces the concept and system architecture; Section 4 details the circuit implementation; Section 10 describes the simulated results and target specifications; and Section 11 concludes the paper.
{{< figure src="/images/iscas2014/concept.svg" title="Figure 1: Proposed concept of fine (high sampling rate) peak alignment with coarse (low sampling rate) data output. Shown is: (a) fixed uniform sampling; and (b) proposed adaptive sampling method." width="500" >}}
# 3 Concept and System Architecture
The basic idea is to use fine sampling at 64 kHz to locate the spike peak, and then sample the rest of the spike using coarse sampling at 16 kHz. It is essential however, that the coarse sampling is peak-aligned (by adjusting sampling clock phase. The adaptive sampling rate is controlled using threshold-based spike detection. This concept is illustrated in Fig. 1. The system architecture is shown in Fig. 2. This consists of two main sub-systems: the core SAR ADC, and the digital alignment controller; responsible for the spike detection, peak search and detection, and timing/sampling alignment.
{{< figure src="/images/iscas2014/architecture.svg" title="Figure 2: System architecture of the proposed peak-aligned ADC with adaptive sampling rate." width="500" >}}
# 4 Circuit Implementation
The circuit has been implemented as a mixed-signal design in a commercially available 0.35\\( \mu\\)m 2P4M CMOS technology provided by AMS.
## 5 Digital Alignment Control
The adaptive sampling algorithm has been implemented in Verilog using a digital design flow. A standard cell based circuit implementation has been realised using Cadence RTL compiler for synthesis and Encounter for place & route.
The controller, which operates at the 64 kHz clock frequency, consists of 3 main blocks to first detect the spike, then search for and detect the peak and finally to provide the aligned samples to the output register.
## 6 Spike Detection
This is achieved using a double threshold detection method as previously illustrated in Fig. 1. This provides the system sensitivity to both positive and negative peaks. The thresholds are externally calibrated after recording and analysing a training dataset.
## 7 Peak Search & Detection
The state diagram for the peak search and detection is shown in Fig. 3. Here the concern lies with the noise corrupted neural spike that will present fluctuations around the peak maximum. To avoid detecting these artifacts as multiple peaks, a 4 sample window is used that succeeds the peak sample. Analyzing these samples will indicate whether the signal is still increasing or if the peak maximum has been detected.
{{< figure src="/images/iscas2014/state2.svg" title="Figure 3: State diagram of the Peak-Search and Detection Algorithm." width="500" >}}
## 8 Timing Control
Once the a peak location in confirmed, the data steam is then re-aligned by updating the valid data phase off-set of the down sampled stream and the logic returns to a to the low frequency data monitoring state. In coherence with the spike detection algorithm, data points are continuously throughput at the 16 kS/s rate. Only upon the re-alignment event does the sampling phase at of the data shift. This implies that when the ADC is driven to record at 64kS/s the extraneous data used for aligning will need to be removed from the output steam by means of latching the digital data buffer at valid data times.
## 9 Analog To Digital Converter
{{< figure src="/images/iscas2014/sar_adc.svg" title="Figure 4: 9-bit Differential SAR ADC." width="500" >}}
{{< figure src="/images/iscas2014/clk.png" title="Figure 5: Time Sequencing for a 9-bit Successive Approximation." width="500" >}}
Fig. 4 illustrated the SAR ADC structure. The topology presented here employs a fully differential binary weighted capacitor array that allows for a highly linear 9-bit output that is driven by standard FSM logic. Moreover the top plate sampling technique will minimize the number of buffered voltage sources required for operation. The fully differential configuration is key for mixed signal systems as a significant amount of noise is rejected from the voltage supplies particularly the common mode of the differential input. The typical timing sequence of 10 cycles for the data converter is illustrated in Fig. 5. The basic binary weighter array is highly insensitive towards mismatch and process variation relative to split cap and C2C structures as parasitics load less significant charge with respect to the net capacitance. This justifies the use of minimum feature size $5 \mu m \times 5 \mu m$ poly-poly unit capacitors that have a capacitive value of 23.22fF.
The successive approximation is initiated by sampling the differential input on the top plate of the two capacitor banks and tying the bottom plates the the respective positive and negative reference supplies \\(GND\\) & \\(V_{ref}\\). This is followed by disconnecting the input from the top plate to allow charge redistribution due to changing the polarity of most significant bit (MSB). Each successive evaluation of the comparator will determine in logical value of the quantization bits in decreasing magnitude. The resulting voltage at the input of the comparator due to digital feedback on the bottom plates may be evaluated by use of charge balance equations.
A positive evaluation of the comparator after sampling with the MSB set high will imply the differential input is positive and hence the MSB changes polarity and the second to most significant bit is now 1. The following will be true for both differential and single ended signals;
\\(\\) V_{x} = V_{in} - \frac{V_{ref}}{4} \\(\\)
A negative evaluation of the comparator implies the differential input is positive and hence both the MSB and the second to most significant bit are now 1. Similarly the following will be true for both differential and single ended signals;
\\(\\) V_{x} = V_{in} + \frac{V_{ref}}{4} \\(\\)
Where \\(V_{x}\\) is the resulting voltage at which the input of the comparator settles. It is important to note that due to sampling with the MSB as high this value will is bounded between $GND & Vref$ which is important to prevent forward biasing any diode to substrate. This can be confirmed by considering the input either as slightly higher than \\(V_{ref}/2\\) or as GND.
{{< figure src="/images/iscas2014/comp.svg" title="Figure 6: Schematic Illustration of Comparator." width="500" >}}
The edge triggered comparator structure used in this design is illustrated in Fig. 6. This dynamic latch structure allows good trade offs with respect to speed and the off-set as speed is limited by the gate to drain capacitive component on the input transistors (M1 & M2). These transistors are required to be large in order to minimize off-set components while the latching transistor can be minimum feature size to maximize evaluation speed. The kick back noise of the comparator is alleviated as the feed through capacitance of the input pair is not coupled to the differential output and the differential structure of the DAC cancels the common mode switching components of the comparator. The output is buffered by a latch that will absorb the glitches on the evaluation transitions when both outputs float around the middle of the rail.
The sampling switches are driven by a boot strap circuit [^9] that will drive the gate voltage of the transistor to \\(V_{dd}+V_{s}\\) for a constant over drive voltage of \\(V_{dd}-V_{th}\\). This allow a full dynamic range on the input signal while preventing signal dependent charge injection to be sampled on the top plate. The switch network for the capacitor array employs stacked transmission gates [^10] on the top plates that minimize leakage components which is important for low frequency operation and single complementary transmission gates on the bottom plates that connect the supplies for rapid charge settling.
# 10 Simulation Results
Preliminary validation of the proposed implementation has been done through schematic level simulations in the Cadence IC 6.1.5 Design Environment using industry provided PSP models.
{{< figure src="/images/iscas2014/dnlinl.png" title="Figure 7: Simulated DNL & INL results." width="500" >}}
The ADC INL & DNL performance in Fig. 7 illustrates the 8.9 effective number of bits (ENOB) accuracy of the converter where the INL is limiting figure of merit. This result was produced using a slow input ramp on the ADC input that is sampled 2048 times across the full 3.3V scale and is aligned with the critical sampling points. The excelent DNL figure is a consequence of not using a split capacitor in the capacitor array.
The performance of this system is summarized in Table 1. The average power dissipation of the data converter from the 3.3V supply is $3 \mu W$ when processing typical neural activity that contain 200 spikes per second. This results in a respectable 93.3 fJ per conversion Figure of Merit (FOM) for the $0.35 \mu m$ CMOS technology given the control overhead for timing both the ADC and data buffer. Where the FOM is given by;
\\(\\) \frac{power}{F_{sample} \cdot 2^{ENOB}}\\(\\)
{{< figure src="/images/iscas2014/result2.svg" title="Figure 8: Simulation Results (top) Analog (bottom) Digital output." width="500" >}}
The simulated transient results in Fig. 8 demonstrate the dynamic sampling of a neural signal that has been measured in-vivo at both 16kHz as well as 64kHz. It can be observed that both positive and negative peaks are sampled with fine temporal resolution and their respective peak amplitude & position are also recorded accurately. Note that if a second peak is detected outside of the 4 sample window this peak will also be registered as a maxima ans will realign the data according to the last peak event. Although in this case these positions are very close to one another, a larger window buffer may be required for better tolerance towards spikes that occur consecutively.
Table 1: Data converter Performance Summary}\label{summary
|Reference | [^11] | [^12] | This work |
|----|----|----|----|
|Year | 2007 | 2011 | 2013 |
|Tech. [nm] | 90 | 130 | 350 |
|Power [(\mu)W] | 700 | 1580 | 3.06 |
|Supply [V] | 1 | 1.2 | 3.3 |
|Rate [S/s] | 50M | 50M | 16k (64k) |
|INL [LSB] | \textless 0.6 | - | +0.55/-0.59 |
|DNL [LSB] | \textless 0.6 | - | +0.25/-0.25 |
|FOM [fJ/bit] | 4.5 | 55 | 93.3 |
|Data Reduction | - | - | 70% |
# 11 Conclusion
In this paper, we have presented the design of a novel, resource-efficient, 9-bit SAR ADC with adaptive (16/64 kHz) rate for peak-aligned sampling. This strategy has been adopted to improve alignment precision to enable high performance spike sorting. Furthermore, by combining high precision peak-alignment with a reduced (effective) sampling rate in this way, good efficiency is achieved in both power consumption and data bandwidth utilisation. The design reported achieves a FOM of 93.3 fJ/conversion-step in a standard 0.35\\( \mu\\)m CMOS technology which is comparable to the state-of-the-art. Future work will focus on also achieving adaptive spike detection in addition to further optimisation of the peak search and detection algorithm.
# 12 Acknowledgment
This work was in part funded by EPSRC grants EP/I000569/1 and EP/K015060/1. The authors would like to thank Song Luan for useful discussion and technical support.
# References:
[^1]: I.H. Stevenson and K.P. Kording, ''How advances in neural recording affect data analysis,'' Nature neuroscience, vol.14, no.2, pp. 139--142, 2011.
[^12]: S.-J. Cho, Y.Hong, T.Yoo, and Kwang-Hyun-Baek, ''A 10-bit, 50 ms/s, 55 fj/conversion-step sar adc with split capacitor array,'' in IEEE ASICON, 2011, 2011, pp. 472--475.
[^11]: J.Craninckx and G.Vander Plas, ''A 65fj/conversion-step 0-to-50ms/s 0-to-0.7mw 9b charge-sharing sar adc in 90nm digital cmos,'' in IEEE ISSCC, 2007., 2007, pp. 246--600.
[^9]: A.Abo and P.Gray, ''A 1.5-v, 10-bit, 14.3-ms/s cmos pipeline analog-to-digital converter,'' IEEE JSSC, vol.34, no.5, pp. 599--606, 1999.
[^10]: D.Zhang, A.Bhide, and A.Alvandpour, ''A 53-nw 9.12-enob 1-ks/s sar adc in $0.13 \mu m$ cmos for medical implant devices,'' in Proc. ESSCIRC, 2011, 2011, pp. 467--470.
[^7]: S.O'Driscoll, K.V. Shenoy, and T.H. Meng, ''Adaptive resolution adc array for an implantable neural sensor,'' Biomedical Circuits and Systems, IEEE Transactions on, vol.5, no.2, pp. 120--130, 2011.
[^6]: M.S. Lewicki, ''A review of methods for spike sorting: the detection and classification of neural action potentials,'' Network: Computation in Neural Systems, vol.9, no.4, pp. 53--R7, 1998.
[^8]: G.-Y. Huang, S.-J. Chang, C.-C. Liu, and Y.-Z. Lin, ''A 1-$\mu$w 10-bit 200-ks/s sar adc with a bypass window for biomedical applications,'' Solid-State Circuits, IEEE Journal of, vol.47, no.11, pp. 2783--2795, 2012.
[^2]: R.R. Harrison, P.T. Watkins, R.J. Kier, R.O. Lovejoy, D.J. Black, B.Greger, and F.Solzbacher, ''A low-power integrated circuit for a wireless 100-electrode neural recording system,'' Solid-State Circuits, IEEE Journal of, vol.42, no.1, pp. 123--133, 2007.
[^4]: H.Gao, R.M. Walker, P.Nuyujukian, K.A. Makinwa, K.V. Shenoy, B.Murmann, and T.H. Meng, ''Hermese: A 96-channel full data rate direct neural interface in 0.13< formula formulatype=,'' IEEE JSSC, vol.47, no.4, pp. 1043--1055, 2012.
[^3]: A.Bonfanti, M.Ceravolo, G.Zambra, R.Gusmeroli, T.Borghi, A.Spinelli, and A.Lacaita, ''A multi-channel low-power ic for neural spike recording with data compression and narrowband 400-mhz mc-fsk wireless transmission,'' Proc. IEEE ESSCIRC, pp. 330--333, 2010.
[^5]: D.Y. Barsakcioglu, A.Eftekhar, and T.G. Constandinou, ''Design optimisation of front-end neural interfaces for spike sorting systems,'' Proc. IEEE ISCAS, pp. 2501--2504, 2013.

115
content/publications/2014/ultra-low-power-design-strategy-for-two-stage-amplifier-topologies.md Normal file
View File

@ -0,0 +1,115 @@
---
title: "Ultra-low power design strategy for two-stage amplifier topologies"
date: 2014-05-08T15:26:46+01:00
draft: false
toc: true
math: true
type: posts
tags:
- publication
- instrumentation
- analogue
- circuits
---
Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# Abstract
This letter presents a novel two stage amplifier topology and ultra low power design strategy for two stage amplifiers that utilises pole zero cancellation to address the additional power requirements for stability. For a 288nA total bias, the presented amplifier achieves a 1.07 MHz unity gain frequency with a 8560 pF MHz/mA figure of merit.
# 1 Introduction
Power efficient amplifier topologies are fundamental analogue processing both in the continuous and discrete time domains. The feasibility of a system is often established using a relevant figure of merit (FOM) that quantifies performance. The prevalence of limited power budgets in medical sensors indicates that advances in low power analogue are critical for the future of implantable biomedical systems that are constrained through battery life and wireless telemetry [^1] [^2]. Ultra low power analogue design is best motivated through aggressively maximising a FOM that indicates how effectively power is used to achieve a desired performance characteristic such as noise, speed, or linearity in order to reveal the underlying limitation.
Taking the differential pair in Fig. 1 for example to illustrate the driving motivation behind sub-threshold operation. The FOM with all transistors in strong inversion can reduced to a single operational parameter;
$$ FOM_{si} \left[ \frac{pF \cdot MHz} {mA} \right] = \frac{UGF \cdot C_{L}}{I_{total}} = \frac{10^{3}}{2 \pi V_{ov}} $$
Where \\(UGF\\), \\(C_{L}\\), \\(I_{total}\\), and \\(V_{ov}\\) are the unity gain frequency, load capacitance, total bias current, and over drive voltage of the input transistors respectively. With the input transistors biased in weak inversion however the FOM is derived as;
$$ FOM_{wi} = \frac{10^{3}}{4 \pi \cdot \eta U_{T}} $$
With \\(\eta\\) & \\(U_{T}\\) being the sub-threshold slope factor and thermal voltage respectively. With \\(V_{ov}\\) usually being 200mV, operation in weak inversion can directly improve the FOM by 6 times. In addition to sub-threshold biasing a number of current recycling techniques can be applied to further gain in FOM [^3]. By coupling the input signal to biasing transistors \\(M_{3-4}\\) for instance, a larger transconductance can be achieved with the same bias current. This allows a simple reduction in power by a factor of two for single stage systems, but a second stage is often required in switched capacitor (SC) applications for high gain and wide output swing. The constraint of the second stage lies with the non-dominant pole at the output that needs to lie beyond the unity gain frequency. The output load capacitance dictates the minimum transconductance of the second stage and will often result in the second stage dissipating significantly more power than the first stage. In this letter, we propose zero cancellation of this non-dominant pole in order to minimise power dissipation in the second stage. Secondly, we identify appropriate scaling factors for the FOM such as to make this applicable to two stage amplifiers.
{{< figure src="/images/el-opamp/TB.png" title="Figure 1: circuit schematics for: (a) simple differential pair with differential output; (b) unity feedback configuration used for testing the transient step response of a fully differential amplifier. " width="500" >}}
# 2 Proposed amplifier
The circuit configuration is shown in Fig. 2. This differential topology extends the complementary input stage with a current conveyor (CC) structure to achieve high gain and wide output swing. The high open loop gain is provided by the cross coupled PMOS devices \\(M_{11-14}\\) in addition to the traditional gain stage \\(M_{19-22}\\) that also allows for a rail to rail output swing. The circuit is configured to drain the same amount of current in the output branch as in the input transistor pair such that the transistors \\(M_{1-6}\\) \& \\(M_{19-22}\\) have a transconductance \\(gm_{1}\\). The cross coupled PMOS branch drains a fraction (1/M = 0.25) of this same current such that the total current dissipated by the amplifier is \\(2I_{M1} \cdot (2 + 1/M)\\). The NMOS current mirror \\(M_{15-18}\\) implements a wideband positive feedback loop with a ratio of 1:N-1 where N = 1.5 to boost the bandwidth of the structure. Note that transistors \\(M_{23-24}\\) bias the input stage through common mode feedback and transistors \\(M_{7-10}\\) bias the output stage. The input transistors \\(M_{1-6}\\) are biased with a drain current \\(I_{input}\\) of 50nA with a 1.2V supply. This biasing current in addition to the ratio \\(M\\) determine the observed single ended slew rate (SR) at the output as it is limited by the low gain path in the NMOS current mirror. In the step response scenario the current drained by \\(M_{23}\\) sources entirely into \\(M_{15}\\) \\(M_{18}\\) which is multiplied to \\(M_{19}\\) \\(M_{20}\\) by a factor \\(M\\), that is;
$$ SR = M \cdot \frac{2 I_{input}}{C_{L}} $$
{{< figure src="/images/el-opamp/CC.png" title="Figure 2: Circuit schematic of the proposed amplifier topology including the input stage (on left) and CC stage (on right). Vp & Vn are externally provided DC biasing voltages. " width="500" >}}
For preliminary design considerations it is useful to assess the dependence of different component parameters through the open loop gain, unity gain frequency, pole and zero locations with simple approximations. First it should be noted the bandwidth product is twice as large as a conventional amplifier though current recycling in the complementary input transistor pairs and evaluated as;
$$ UGF = \frac{gm_{1} }{ \pi \cdot C_{F}} $$
Where \\(C_{F}\\) is a 500 fF compensation capacitor that couples the output to the input stage via a low impedance node in the NMOS differential pair utilising split length indirect compensation, thus avoiding the right hand plane pole [^4]. With \\(\lambda\\) as the channel length modulation parameter the open loop DC gain is evaluated as;
$$ A_{dc} \approx NM \left( \frac{1}{\eta U_{T} \lambda} \right)^{2} $$
Furthermore in the midband frequencies the Miller capacitor \\(C_{F}\\) performs pole splitting both poles in the CC stage through the feedback loop. This will move the pole at the cross coupled PMOS outside the UGF, more specifically \\(\omega_{p2}\\), and move the pole due to \\(C_{L}\\) towards;
$$ \omega_{p1} \approx \frac{2M \cdot gm_{1}}{C_{L} + C_{z}} $$
If \\(gm_{1}\\) is kept small this pole will remain in-band of the amplifier. For adequate phase margin that is larger than \\(65^{\circ}\\), to prevent excess ringing at the output, we use pole zero cancellation. With \\(\omega_{p1} = \omega_{z}\\), \\(C_{z}\\) is determined according to;
$$ \omega_{z} \approx \frac{gm_{M15} \cdot (2-N)}{ C_{z}} $$
\noindent Past the zero location, the signal path loads into the diode-connected NMOS \\(M_{15}\\) that now drives both \\(M_{21}\\) & \\(M_{19}\\) pushing out the unity gain frequency. With \\(C_{gs}\\) as the total gate capacitance from both NMOS & PMOS current mirrors and taking \\(C_{z}\\) as a short circuit, the pole location \\(\omega_{p2}\\) can be confirmed to lie outside the unity gain frequency;
$$ \omega_{p2} \approx \frac{2 gm_{1}}{C_{gs}} $$
$$ FOM \approx \frac{10^{3}}{4 \pi \cdot \eta U_{T}} \cdot \frac{2 \cdot C_{F}/C_{L}}{2 + 1/M} = 3.56 \times FOM_{wi} $$
As a result, when the FOM is reformulated (see above) for this particular configuration, it can be observed that this is increased, compared to the conventional single stage topology. A significant contribution of this improvement in FOM naturally comes from the factor \\(C_{F}/C_{L}\\) as a reduction in the dominant capacitive load allows a overall reduction in bias current to achieve a given bandwidth. This also illustrates that relative to a single stage, a two stage configuration may trade off noise for a better FOM by adjusting the \\(C_{F}/C_{L}\\) ratio. As the total input referred integrated thermal noise \\(e^{2}_{in}\\) for a single pole system is related to the capacitor \\(C\\) that introduces the dominant pole of the system through:
$$ e^2 = \frac{ kT }{C} \frac{ kT NEF^{2} \cdot I_{input}}{ \eta A_{cl} I_{total} } $$
Which is directly derived from the definition of the noise efficiency factor (NEF) [^5] by substituting the expression for bandwidth as the closed loop gain \\(A_{cl}\\) multiplied by UGF.
{{< figure src="/images/el-opamp/results4.png" title="Figure 3: Simulation Results: (a) open loop frequency response (b) closed loop step response of differential signals (c) input referred noise density." width="500" >}}
Table 1: Performance Summary
|Reference |[^6] |[^7] |[^4] | This work |
|----|----|----|----|----|
|Year |2009 |2010 |2010 | 2013 |
|Tech. [nm] |180 |180 |500 | 180 |
|Power [W] |5.5m |600μ |1.2m | 345n |
|Supply Voltage [V] |1.2 |1.5 |3 | 1.2 |
|DC Gain [dB] |85 |59 |82 | 96 |
|UGF [MHz] |450 |111 |20 | 1.07 |
|Slew Rate [V/μs] |- |233 |8 | 0.12 |
|Load/Miller [pF] |-/3 |5 |5, 0.2/500 | 2/0.5 |
|Phase Margin [°] | 68 | 80 | 72 | 64 |
|Noise Floor [V/√Hz] |- |125n | - | 60n |
|FOM [MHz pF/mA] |295 |1267 |8333 | 8560 |
# 3 Simulation Results
Preliminary validation of the proposed implementation has been achieved using schematic level simulations in the Cadence IC 6.1.5 Design Environment using industry provided transistor models for the commercially available 6 Metal 0.18 μm CMOS technology (AMS/IBM C18A6/7SF). Fig. 3 shows key simulation results, including small signal, transient, and noise characteristics. The common mode feedback configuration used in these simulations is a conventional differential difference amplifier with a current mirror to drive both M23 & M24 transistors biasing the input stage simultaneously. In order to normalise performance with respect to requirements on the common mode feedback circuit its 45nW power contribution is excluded in FOM calculations. The simulated frequency characteristics were close to the analytical expectation achieving a 1.07MHz unity gain frequency and a phase margin of 64 degrees. The step response indicates settling of the output to <0.1 % within 10 μs with the feedback configuration illustrated in Fig. 1. The configuration also demonstrates good noise performance as the input transistors have a larger transconductance than the first active load by a factor of M for a smaller input referred noise figure. The 60 nV/√Hz input referred thermal noise floor from 100kHz to 1MHz is good for auto zeroing SC topologies that rejects the flicker noise and low frequency aggressors.
# 4 Conclusion
The application of pole zero cancellation for achieving ultra low power in two stage amplifier has been demonstrated. In addition the Miller to load capacitor ratio and current recycling have been discussed as techniques to improve the FOM with the respective trade off. The overall performance characteristics are summarized in table 1. This demonstrates comparable performance to state of the art three stage nested miller systems in terms of FOM in addition to a 345nW power budget that is well within the power constraints of many biomedical analogue processing applications. The proposed topology achieves a 3.56 times improvement in FOM over conventional single stage structures.
# 5 Acknowledgment
This work was supported by the UK EPSRC (grants EP/I000569/1 and EP/K015060/1).
# Refernces:
[^1]: A.Eftekhar, E.P. Sivylla, and G.C. Timothy, ''Towards a next generation neural interface: Optimizing power, bandwidth and data quality,'' in IEEE Proc. BIOCAS, 2010, pp. 122--125.
[^2]: W.Wattanapanitch and R.Sarpeshkar, ''A low-power 32-channel digitally programmable neural recording integrated circuit,'' IEEE Trans. Biomed. Circuits Syst., vol.5, no.6, pp. 592--602, 2011.
[^3]: R.Assaad and J.Silva-Martinez, ''Enhancing general performance of folded cascode amplifier by recycling current,'' IET Elec. Letters, vol.43, no.23, 2007.
[^4]: V.Saxena and R.J. Baker, ''Indirect compensation techniques for three-stage fully-differential op-amps,'' in IEEE Proc. MWSCAS, 2010, pp. 588--591.
[^5]: R.Harrison and C.Charles, ''A low-power low-noise cmos amplifier for neural recording applications,'' IEEE J. Solid-State Circuits, vol.38, no.6, pp. 958--965, 2003.
[^6]: M.Fan, J.Ren, Y.Guo, Y.Li, N.Li, F.Ye, and J.Xu, ''Low-voltage low-power operational amplifier for sc circuits,'' IET Elec. Letters, vol.45, no.25, pp. 1274--1276, 2009.
[^7]: M.Yavari, ''Single-stage class ab operational amplifier for sc circuits,'' IET Elec. Letters, vol.46, no.14, pp. 977--979, 2010.

14
content/publications/2015/a-novel-neural-recording-system-utilising-continuous-time-energy-based-compression.md Normal file
View File

@ -0,0 +1,14 @@
---
title: "A novel neural recording system utilising continuous time energy based compression"
date: 2015-05-24T15:26:46+01:00
draft: true
toc: true
type: posts
math: true
tags:
- publication
- instrumentation
- CMOS
- biomedical
- sampling
---

173
content/publications/2015/continuous-time-micropower-interface-for-neural-recording-applications.md Normal file
View File

@ -0,0 +1,173 @@
---
title: "Continuous-time micropower interface for neural recording applications"
date: 2015-10-16T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
- publication
- instrumentation
- CMOS
- biomedical
---
Marios Elia, Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
This paper presents a novel amplifier architecture intended for low power neural recording applications. By using continuous-time signal representation, the proposed topology predominantly leverages digital circuits and is thus well-suited for scaling to new technologies.
This includes digital integration providing direct quantization of the input voltage and superior filtering. Schematic-level simulations demonstrated the amplifier's bandwidth to be 6 kHz, with highly linear full dynamic range output. Achieving a static power consumption of 1.145 μW from a 0.5V supply voltage with an input referred thermal noise of 7.7 μVrms.
# 2 Introduction
Recent advancements in neuroscience have enabled simultaneous activity monitoring from multiple neurons, creating the need for fully implantable multi-neuron recording. Next-generation implanted systems must be able to simultaneously monitor between 100 and 1000 neurons [^1]. With neural signals being as small as 30 μV, a dedicated low-noise amplifier (LNA) is required for each electrode. However, implantable devices have restricted power budget so that tissue cells are not destroyed by the generated heat. It is therefore suggested that front-end amplifiers should dissipate no more than 2 μW. Thus, a trade-off between noise performance and power consumption emerges as thermal noise is directly related to bias current.
Utilising a current-mirror OTA topology with weakly-inverted PMOS inputs, authors of [^1] where able to achieve an input referred noise of 2.2 μV integrated over 0.25 Hz - 7 kHz. However, the amplifier dissipated 80 μW of power, potentially exceeding thermal-dissipation safe limits if scaling to hundreds of channels.
Extracellularly recorded neural action potentials have amplitudes in the range of 30 μV - 500 μV and frequency content in 100 Hz- 7kHz spectrum. On the other hand, local-field potentials can be as large as 5mV with energy present in sub-Hz frequencies, putting a system's dynamic range (DR) to the test. Moreover, electrodes demonstrate DC offsets up to 2 V [^1], requiring the integration of a sub-Hz high-pass filter. The design is further challenged by technological scaling; shrinking devices lead to reduced transistor impedances requiring higher power to maintain intrinsic gain and linearity.
Reduced DC gain can be effectively mitigated by the use of voltage controlled oscillator (VCO) based integrators [^3], [^4]. Furthermore, VCO-based topologies preserve signal information in the time domain allowing for very large dynamic range (DR). Similarly, authors of [^5] propose a switched-mode Op-Amp with a class-D output stage. The two-level operation renders the system inherently more linear, alleviating the linearity-power consumption trade-off. It is therefore beneficial to devise architectures based on these digital circuits, suited to fabrication using digitally-oriented CMOS technology. This is further motivated by the fact that biomedical instrumentation applications make extensive use of Digital-Signal Processing (DSP).
This paper presents the implementation of a low-power, VCO-based amplifier for neural recording applications. The system encodes information in time domain by utilising differential oscillators. A Phase-Frequency Detector (PFD) detects relative phase/frequency variations and generates high-frequency UP/DN pulses. An up/down binary counter integrates the PFD output and tracks the quantization of the signal; the binary value is now ready for digital processing.
The remainder of the paper is organised as follows. Section II introduces and analyses the proposed system architecture with circuit implementation presented in section III. Section IV demonstrates simulated results followed by conclusions in Section V.
# 3 Concept and System Architecture
The proposed amplifier architecture is shown in Fig 1. A fully differential Gm-cell integrates the residue signal, on the Miller-equivalent capacitance, and drives the VCO blocks.
A digitally registered integrator rejects high frequency harmonics and produces the system's quantized output. This integrator is implemented with a 9-bit binary up/down counter that is driven by events generated by the PFD. The asynchronous behaviour prevents down modulation of coherent noise in the system and quantization from producing strong tones in band. Finally all active integration nodes feedback to through a charge-scaling capacitive array. Utilizing multi-pathing of signal components, this topology attempts to reject out of band noise in the GM-VCO signal loop such that the band limited counter output contains a clean signal band without needing in large band limiting capacitors.
## 4 Amplifier Compensation
A pole is contributed to the transfer function, by each of the following stages; Gm-cell, VCO and counter integrator. Feed-forward compensation is achieved by capacitively coupling the PFD output to the charge-scaling array output with gain A<sub>v<sub>. As such, a zero is introduced in the transfer function, cancelling the effect of the counter-contributed pole. The amplifier is then approximated by a two-pole system allowing for Miller compensation. The Miller equivalent of C<sub>M<sub> places a DC pole at the output of the Gm-cell and pushes the VCO pole to higher frequencies. Laplace-domain analysis yields the system's transfer function; Eq. 1.
$$ H(s) = Gm\frac{1+\frac{s}{\omega_{z}}}{s(1+\frac{s}{\omega_{p2}})} $$
$$ \omega_z = A_{v}K_{INT},\ \omega_{p1} = DC $$
$$ \omega_{p2} = \frac{1+C_{M}A_{v}K_{VCO}K_{PFD}K_{INT}}{C_{M}K_{VCO}K_{PFD}} $$
The amplifier has sufficient phase margin (PM) if \\(\omega\\)<sup>p2<sup> and \\(\omega\\)<sub>z<sub> are very close in the frequency response, cancelling each other out. This will be satisfied if C<sub>M<sub>A<sub>v<sub>K<sub>VCO<sub>K<sub>PFD<sub>K<sub>INT<sub> >> 1, reducing \\(\omega\\)\textsubscript{p2} to A<sub>v<sub>K<sub>INT<sub>. The transfer function can then be approximated to \\(\frac{Gm}{s}\\) suggesting a single pole system and ideal integrator behaviour near DC.
{{< figure src="/images/iscas2016/system.svg" title="Figure 2: System Architecture with unit capacitor as 4 fF." width="500" >}}
It should be noted that K<sub>INT<sub> is input-dependent, in other words the integrator's gain dynamically changes when the amplifier is slewing. Nonetheless, both \\(\omega\\)\textsubscript{p2} and \\(\omega\\)<sub>z<sub> are a function of K<sub>INT<sub> thus, the system's overall transfer function is not affected.
## 5 Topological Advantages
The amplifier's digital nature offers a number of benefits compared to the analogue equivalent. As technology scales, propagation delays and power consumption are also expected to scale down offering increased performance. Moreover, reduced input capacitance yields higher input impedance. This is particularly useful in biomedical LNAs, as tissue built-up increases the electrode's impedance with time [^7].
Another key advantage, is that the binary counter continuously quantizes the input signal. As such the system's output is compatible with arbitrary & event-based processing rates. The circuit contains a minimal number of analogue nodes; the input node and the Gm-cell's output node. External and internal feedback ensure negligible voltage swing on all nodes. Resulting in minimal linearity restrictions by the power rails allowing the use of very low supply voltage.
Signal quantisation is performed in closed-loop. As such, quantization noise and non-linearities, induced by the counter-DAC combination, are shaped and pushed to higher frequencies. With distortion being suppressed by the internal feedback, aggressive reduction of the capacitors used in the charge-scaling array is allowed.
Another mechanism that improves noise performance results from the feed-forward stage Av. As it bypasses the counter circuit, any high frequency noise, generated by the Gm-cell and VCO circuits, will bypass the counter and propagate through the feedback loop. Thus, only low frequency noise components will reach the system's digitised output. As such, it is essential to maintain signal specific counter bandwidth.
# 6 Circuit Implementation
The circuit has been designed and simulated in a 0.18 μm CMOS process provided by AMS (H18A4). A circuit-level analysis of the system blocks follows.
## 7 Gm-cell
The first stage is implemented using a differential pair topology, Fig. 2.
{{< figure src="/images/iscas2016/1.svg" title="Figure 3: Gm-cell" width="500" >}}
For DC signals, devices M1 and M3 behave as diode-connected transistors, providing a well-defined output biasing as well as the high-pass DC off-set rejection cut off at 1 Hz. Noise analysis reveals that thermal noise is inversely proportional to device transconductance. By AC coupling the input signal to both NMOS and PMOS devices, the circuit's transconductance efficiency is significantly boosted. Small-signal analysis yields the circuit's transfer function; Eq. 2.
$$ H(s) = Gm\frac{r_{O}}{1 + sr_{O}C^{eq}_{M}} $$
$$ Gm = g_{m1} + g_{m2},\ r_O = r_{O1}//r_{O2} $$
$$ C^{eq}_{M} = C_{M} \frac{K_{VCO}}{s} K_{PFD} ( \frac{K_{INT}}{s} + \frac{1}{A_{v}} ) $$
Eq. 2 reveals that the finite output impedance of MOSFET devices, pushes the first stage pole to frequencies higher than DC. However, owed to the nearly infinite gain provided by the second stage integrators, the Miller capacitor will appear very large, pushing the pole back to very low frequencies.
## 8 Voltage-Controlled Oscillator
The implemented VCO circuit is shown in Fig. 3. Devices M2 and M3 form an inverter-based ring-oscillator. The oscillator's frequency is a linear function of the current it sinks and it is given by Eq. 3 [^8].
$$ f_{OSC} = \frac{I_{DS}}{N C_{TOT} VDD} $$
N being the number of inverter stages and C<sub>TOT<sub> the total capacitance per inverter stage. Device M1 directly controls the oscillator's frequency by modulating the current available to it. The circuit's gain is then given by
$$ K_{VCO} = 2\pi \frac{g_{m1}}{N C_{TOT} VDD} [radians V^{-1} s^{-1}] $$
{{< figure src="/images/iscas2016/4.svg" title="Figure 4: Voltage-Controlled Oscillator" width="500" >}}
Transistor M4 is biased in the triode region acting as a level shifter. It serves a dual purpose by ensuring correct biasing of device M6 and isolating the oscillator from high frequency noise present on the ground rail.
## 9 Phase-Frequency Detector
The circuit of the 3-state PFD utilised is shown in Fig. 4(a) [^9]. It is based on True-Single Phase Logic and its operation principle follows. Assuming VCO1 and VCO2 are low, nodes U1 and D1 are pre-charged to VDD via M1. On the rising edge of VCO1, M5 turns ON, and the dynamic inverter formed by M4 and M6 pull node U2 down causing UP signal to rise. On the rising edge of VCO2, DN signal also rises. M2 and M3 discharge nodes UI and D1 thus UP and DN signals are also pulled down. The circuit has returned to its initial condition [^9]. It should however be noted that to ensure reset of UP/DN signals at equal instances, I<sub>DS2,3<sub> >> I<sub>DS1<sub> must be satisfied.
Maximum output voltage is produced when the two input signals are perfectly out-of-phase; that is, they are 2\\(\pi\\) apart. The circuit's gain is then defined as K<sub>PFD<sub> = 1/2\\(\pi\\).
{{< figure src="/images/iscas2016/pfd_2.svg" title="Figure 5: (a) PFD circuit (b) SIGN bit generation" width="500" >}}
## 10 Counter Driving Circuit
Clock generation is achieved by the circuit in Fig. 5(a). Two edge-detector circuits generate pulses of well-defined width, at every rising edge generated by the VCOs. The pulses propagate through the OR, driving the DFF, to the divide-by-two circuit. Thus, the generated clock's frequency is the average of the two VCOs'.
{{< figure src="/images/iscas2016/clk_circuit.svg" title="Figure 6: (a) CLK circuit generation (b) 2-state to 3-state signal conversion" width="500" >}}
The circuit of Fig. 4(b) illustrates the PFD implementation. DFF1 detects the leading signal and accordingly registers a logic output. DFF2 ensures that the SIGN bit can only change after the clock's rising edge. As such, the SIGN bit is always stable when the counter registers its value, avoiding metastability issues.
The SIGN bit is also used to convert the 2-state UP/DN outputs to 3-state signals. This is achieved by using the SIGN bit to determine whether the signal oscillates between -1 and 0 or 0 and +1. By increasing the available logic levels, the maximum quantisation noise present on the signals is reduced improving system dynamics. The circuit implementing this function is shown in Fig. 5(b). The 3-state signals are now fed forward to the output node in order to introduce a zero in the transfer function and satisfy the stability requirements mentioned in Section II. %cancelling the effect of the output pole. %State +1 is represented by the binary value 11, zero by 01 and -1 by 00.
## 11 Integrator
The binary counter's building element is a Toggle Flip-Flop and a multiplexer; the multiplexer being controlled by the SIGN bit. Each TFF will toggle or hold its state, depending on the value presented to it by the multiplexer.
The counter's binary value is converted to an analogue signal by a charge-scaling capacitive array. The integrator's transfer function can be derived as follows. Each time the counter increments its value, the output voltage increases by V<sub>DD<sub>/2<sup>N<sup>; N being the number of binary bits. Approximating the output voltage by a ramp, it is given by
$$ V_{out}(t) = \frac{V_{DD}}{2^{N}}t\times u(t)\times f_{OSC} $$
yielding the following transfer function
$$ \frac{\Delta V_{out}}{\Delta\Phi_{in}}(s) = \frac{V_{DD}}{2^N}\times \frac{f_{OSC}}{\Delta\Phi_{in}}\times \frac{1}{s} $$
Eq. 6 suggests that the integrator's transfer function is input dependent as stated in Section II.
# 13 Simulated Results
The design was simulated in Cadence IC 6.1.5 Design Environment, using foundry-supplied PSP models. Owed to the circuit's dynamic time domain behaviour, only transient noise simulations can correctly predict system performance. As such, the provided bode plots were generated by simulating the linearized system transfer function.
{{< figure src="/images/iscas2016/bode.svg" title="Figure 8: Frequency response of linearised model" width="500" >}}
Fig. 6 demonstrates the system's frequency response revealing a closed loop 40dB voltage gain. The system's static current consumption is measured to be 2.29 μA from a 0.5V supply voltage yielding a power dissipation of 1.145 μW. Spectrum analysis of the output for a 2kHz, 5mV peak-to-peak input signal is shown in Fig. 7. The input referred noise floor of the transconductance state evaluated at 100nV/√Hz with the corner frequency at 1 kHz. High levels of flicker noise can be mitigated with common signal chopping techniques. Table I summarises system performance and compares with a typical analogue design. The used figure-of merit is defined by Eq. 7.
$$ FoM = v_{ni,RMS}\sqrt{\frac{2I_{TOT}V^2_{DD}}{\pi U_{T} 4KT\times BW}} $$
Table 1: Performance Comparison
| Parameter | This work |[^1]|
|----|----|----|
|Power [μW] | 1.14 | 80 |
|Supply [V] | 0.5 | ±2.5 |
|Bandwidth [Hz] | 1- 6k | 25m-7.2k |
|THD [%] | 1.05 | 1 |
|Noise [μVrms] | 7.7 | 2.2|
|Figure of Merit | 2.25 | 20|
# 14 Conclusion
A novel amplifier architecture is proposed, that makes extensive use of digital circuits attempting to overcome the issues resulting from technological scaling. By encoding and processing the information in time-domain, the system's DR is no longer restricted by the power rails. As such the entire system operates from a supply voltage of 0.5V consuming 2.29 μA of current.
The complementary input stage increases the circuit's transconductance efficiency while the capacitive feedback applied to the second stage ensures superior low voltage integration characteristics owed to the feedback mechanics. The output capacitive DAC, artificially increases closed loop gain of the second stage, further relaxing the noise-bandwidth trade-off as both depend on input transconductance. Lastly, the noise shaping on the output guarantees relaxed requirements in supply noise, capacitor matching while retaining linearity under very low supply voltages. Based on an event driven design, utilisation of Continuous-Time DSP could prove especially advantageous for this particular system [^6].
# Refernces:
[^1]: R.R. Harrison and C.Charles, ''A Low-Power Low-Noise CMOS Amplifier for Neural Recording Applications,'' IEEE JSSC, vol.38, no.6, pp. 958--965, 2003.
[^2]: S.I. Chang and E.Yoon, ''A 1$\mu$W 85nV/√Hz pseudo open-loop preamplifier with programmable band-pass filter for neural interface system,'' Proc. IEEE EMBS Conf., pp. 1631--1634, 2009.
[^3]: B.Drost, M.Talegaonkar, and S.Member, ''Analog Filter Design Using Ring Oscillator Integrators,'' IEEE JSSC, vol.47, no.12, pp. 3120--3129, 2012.
[^4]: C.-w. Hsu and P.R. Kinget, ''A 40MHz 4th-order Active-UGB-RC Filter using VCO-Based Amplifiers with Zero Compensation,'' pp. 359--362, 2014.
[^5]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-Mode Operational Amplifiers and Their Application to Continuous-Time Filters in Nanoscale CMOS,'' IEEE JSSC, vol.49, no.12, pp. 2758--2772, 2014.
[^6]: Y.Tsividis, ''Continuous-time digital signal processing,'' Electronics Letters, vol.39, 2003.
[^7]: J.Xu, T.Wu, W.Liu, and Z.Yang, ''A frequency shaping neural recorder with 3 pF input capacitance and 11 plus 4.5 bits dynamic range,'' IEEE BIOCAS, vol.8, no.4, pp. 510--527, 2014.
[^8]: R.J. Baker, CMOS Circuit Design, Layout and Simulation, 3rded.\hskip 1em plus 0.5em minus 0.4em elax JOHN WILEY & SONS, 2010.
[^9]: B.Lee and L.Siek, ''A CMOS Phase Frequency Detector for Charge Pump Phase-Locked Loop,'' Electronic Engineering, pp. 5--8, 1999.

119
content/publications/2016/a-0-45-v-continuous-time-domain-filter-using-asynchronous-oscillator-structures.md Normal file
View File

@ -0,0 +1,119 @@
---
title: "A 0.45 V continuous time-domain filter using asynchronous oscillator structures"
date: 2016-12-11T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
- publication
- instrumentation
- CMOS
- time-domain
- asynchronous
---
Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
This paper presents a novel oscillator based filter structure for processing time-domain signals with linear dynamics that extensively uses digital logic by construction. Such a mixed signal topology is a key component for allowing efficient processing of asynchronous time encoded signals that does not necessitate external clocking. A miniaturized primitive is introduced as analogue time-domain memory that can be modelled, synthesized, and incorporated in closed loop mixed signal accelerators to realize more complex linear or non-linear computational systems. This is contextualized by demonstrating a compact low power filter operating at 0.45 V in 65 nm CMOS. Simulation results are presented showing an excess of 50 dB dynamic range with a FOM of 7 fJ/pole which promises an order of magnitude improvement on state-of-the-art filters in nanometre CMOS.
# 2 Introduction
The challenges for advancing digital devices and energy constrained computation no longer exhibit the coherent virtues dictated by Moore's Law[^1]. Instead current research is driven to find new solutions inspired by the natural world for solving problems that are dissonant with today's computational paradigm. This has led to the re-emergence of processing in the analogue domain as accelerator to the digital framework [^2]. Motivated by the fact that when tailored to a specific computational problem analogue efficiency can be vastly superior to its digital equivalent [^3][^4]. However there remain many challenges that prevent a clear advantage for such architectures in practice. Current state-of-the-art demands fully integrated SOCs in nanometre CMOS for a cost effective solution. This substantially degrades analogue performance in addition to the difficulty in miniaturizing analogue elements. More importantly analogue tends to drastically lose fidelity for near threshold supply voltages which is an essential aspect to ultra low power digital systems [^5]. To address such challenges oscillator based topologies have been proposed in association with a new computational paradigm [^6][^7]. There are two critical advantages that such an approach can leverage. The first is that the signals pertaining to these systems are digital in nature where the information is encoded with respect to the timing between logical events equivalent to clock edges. This implies that a single binary bit stream can represent multiple bits of information artificially increasing the density of CMOS interconnect. Moreover such signals allow them selves to be manipulated by standard logic gates and asynchronous digital controllers for very rich yet highly efficient signal control[^8]. The second aspect is that voltage controlled oscillators suffer very little performance degradation from aggressive technology scaling or poor transistor characteristics. In fact the perpetual improvement f<sub>T<sub> increases the maximum temporal resolution achievable using time-domain quantizers for unparalleled dynamic range.
{{< figure src="/images/icecs2016/td_system.svg" title="Figure 1: Oscillator based computing to realize linear and non-linear dynamics that utilize a phase domain state as memory." width="500" >}}
In an effort to explore the potential of such a modality this work considers the use of oscillator structures for processing neural activity in extension to a previously developed oscillator based instrumentation system in [^9]. As implantable brain machine interfaces present one of the most demanding applications for realizing power efficient structures that acquire and classify neural activity to treat neurophysiological disorders. The ring oscillator concept shown in Fig. 1. This oscillator plays the role of analogue memory by retaining a state in the phase domain. A transconductive element adjusts the phase subject to the digital control signals. The digital logic dictates the overall response of the structure by using single or multiple phases of the oscillator. This presents negative feedback that stabilizes the operation of the system by rejecting frequency off-sets and noisy aggressors external to the circuit. As will be demonstrated this closed loop dynamic has true analogue aliasing properties due to the nature of VCO based integration. This implies that any logical approximations that induce errors or distortion at high frequency can be rejected. This paper is organized as follows. The basic aspects of the filter architecture is introduced in Sec. 3. This is followed by the circuit level implementation that is detailed in Sec. 4. Sec. 5 presents preliminary simulation results which are concluded upon in Sec. 7.
# 3 Ring Oscillator based Filter
{{< figure src="/images/icecs2016/TD_L1.svg" width="500" >}}
{{< figure src="/images/icecs2016/TD_L1.svg" title="Figure 2: Proposed Single pole ROF structure where V<sub>R<sub> represents the only analogue node in the system. " width="500" >}}
A first order realization of this Ring Oscillator based Filter (ROF) is presented in Fig. 2. This simpler structure will allow the discussion to give insight the elementary operation. Here the digital signals D and Q are pulse width modulated (PWM) encoded time domain signals and are typically not modulated using the same carrier frequency. In essence a digital adder injects current into the oscillator such that the phase recedes or advances with respect another local oscillator by comparing the two pulse width components of D & Q. By using a differential structure the phase can be encoded as self referenced timing events that do not require global frequency synchronization to decode phase information. It is also important to note this structure differs characteristically from classic literature examples [^10] but remain very useful for analysis. This discrepancy arises from sub-threshold and current starved operation of the oscillator which implies that the conduction phases of the NMOS and PMOS transistors for each inverter are non-overlapping. In a general sense however the output voltage V<sub>out<sub> of the structure is often modelled as:
$$ V_{out} (t) = A(t) \cdot f\left[ \omega_0 t + \phi(t) \right] $$
$$ \phi (t) = \int_{-\infty}^{\infty} h_{\phi}(t,\tau) i(\tau) \: d\tau = \int_{-\infty}^{t} \Gamma(\omega_0 , \tau) i(\tau) \: d\tau $$
In Eq. 1 A and \pphi represent the amplitude and phase state variables of the system as a function of time. \\(f\\) describes the limit cycle of the oscillation that captures the non-linearities of V<sub>out<sub> as a function of phase. Our primary interest lies with Eq. 2 which captures the dependency of phase with respect to the impulse response h<sub>\pphi<sub> and the cyclo stationary impulse sensitivity function (ISF) \gGamma. \gGamma is evaluated with respect to a specific small signal source. This dependency is what gives rise to the inherent integral behaviour of oscillators where parasitics diminish the integration constant but will not effect the ideal loop gain of the circuit. The transconductance Gm is introduced to translate the digital output to currents injected into the oscillator represented by I<sub>\dDelta<sub>. The resulting behaviour can be summarized in the s-domain by assuming \gGamma <sub>Gm<sub> is approximately independent of the phase[^11]:
$$ H_{\phi}(s)=\frac{1}{s} \frac{Gm}{2\pi q_{max}} \text{where} q_{max} = N V_R C_{T} $$
$$ V_R = V_{th} + \eta U_T \ln \left( \frac{2 I_B}{2\eta U_T^2 \mu C_{ox}} \frac{L}{W} \right) $$
In Eq. 3 N, V<sub>R<sub>, and C<sub>T<sub> represent the number of inverter stages, voltage across the oscillator, and total capacitance seen as load to each gate in the oscillator. Note q<sub>max<sub> physically represents the total charge that is dissipated each period which implies a frequency of oscillation in terms of f<sub>osc<sub>=I<sub>B<sub>/q<sub>max<sub>. For simplicity the carrier mobility \mmu and V<sub>th<sub> for both PMOS and NMOS are taken as equivalent such that their conductivity is equal. In practice W must be adjusted to compensate this difference but will typically lead to improved supply noise rejection. Fig. 3 shows the phase dependency of \gGamma with respect to I<sub>B<sub> and constituent NMOS & PMOS devices of all gates together for a 5 stage ring oscillator. Although H<sub>\pphi<sub> due to I<sub>B<sub> exhibits some dependency with respect to phase it is well estimated by Eq. 3. The phase information is extracted using an XOR gate which has a gain of 1/\ppi.
{{< figure src="/images/icecs2016/ISF.svg" title="Figure 3: Impulse sensitivity function for a 5-stage ring oscillator with respect to the bias current and NMOS/PMOS contributions from all stages together. " width="500" >}}
Although the first order structure has very low complexity the drawback is that the bandwidth is directly related to the the frequency of oscillation when H<sub>\pphi<sub> is put into feedback. This coupling is undesirable for two reasons. The first is from a noise perspective which is that for a fixed frequency decreasing I<sub>\dDelta<sub> increases the input-referred noise power (e²<sub>n<sub>) of this circuit approximately as (U<sub>T<sub>\\(\cdot\\)I<sub>B<sub>/I<sub>\dDelta<sub>)² which may become very pronounced. This forces the structure to dissipate excessive amounts of power to maintain adequate dynamic range. The second aspect is that the capability to control the oscillator frequency independent of loop bandwidth is useful to adjusting digital power dissipation and its interaction with other system blocks.
{{< figure src="/images/icecs2016/TD_L2.svg" title="Figure 4: Proposed two-pole ROF structure with the digital output Q represented by K PWM phases for reduced analogue distortion." width="500" >}}
For this reason the second order structure is introduced in Fig. 4. This has equivalent characteristics to that of a miller compensated amplifier where the switched current loads into a capacitor across a high gain stage which is realized by the first order structure. As a result noise/bandwidth and oscillator characteristics are decoupled by being represented through two different capacitors C<sub>L<sub> and C<sub>T<sub>. The additional consideration required here is that the digital feedback Q over C<sub>L<sub> can cause large signal swings on the gate of M<sub>B<sub> degrading transconductive linearity. Generally if M<sub>B<sub> is also in sub threshold operation its input range is limited to 2U<sub>T<sub> before excessive distortion is introduced. However capacitively coupling M phases of Q in parallel the quantization levels are reduced to V<sub>DD<sub>/M. Each phase is simply represented by taking more taps from the ring oscillator in parallel. Moreover if M is chosen proportional to V<sub>DD<sub>/2U<sub>T<sub> this structure actually reduces in complexity and improves efficiency as the supply voltage decreases. Note that for high frequency operation the switched current DAC exhibit poor switching dynamics due to the reduced supply voltage. In such a case it is sufficient to replace this block with parallel resistors equivalent to active RC integrators. As such it may be expected that this configuration implies the 3dB frequency equivalent to f<sub>3dB<sub>=I<sub>\dDelta<sub>/C<sub>L<sub> where C<sub>L<sub> is approximated as U<sub>T<sub> kT/e²<sub>n<sub> to match the required noise levels. In extension the oscillator spurs can be set to match this noise floor by considering the filter response and quantizer level dependency such that f<sub>osc<sub>\textgreater f<sub>3dB<sub> SNR/N for a first order system.
# 4 Circuit Implementation
The presented implementation realizes a 0.45 V second order ROF using commercially available TSMC \cmostech LP MS RF technology (1P9M\_6X1Z1U\_RDL). Fig. 5 shows transistor level implementation of the transconductor and oscillator structure that retains the phase state of the system. Here a bias current is simply switched differentially into the capacitive load while M\tss{1-2} provide common mode feedback. The transistors M\tss{3-4} realize a current mirror that biases the ring oscillators proportionally to I<sub>B<sub>. The control switches S<sub>A<sub>/S<sub>C<sub>/S<sub>B<sub> correspond to +1/0/-1 transconductive gains that realize a 1.5 bit current DAC. The oscillators are floating in the middle the supplies due to M<sub>5<sub> which has its body connected to source. This improves the switching behaviour of the proceeding XOR gate by providing good high/low voltage levels while also reducing the noise coupling from ground/substrate if the oscillator is allowed to use isolated P/N-wells. The capacitor C<sub>L<sub> is split into 11 MIM fringe capacitors for a total of 100 fF load on each terminal.
{{< figure src="/images/icecs2016/TD_sch1.svg" width="500" >}}
{{< figure src="/images/icecs2016/TD_sch2.svg" title="Figure 5: The proposed transistor level implementation of the second order ROF" width="500" >}}
The digital logic used to realize unity gain feedback is presented in Fig. 6. Three out of the 11 phases are used in the feedback logic for demonstration. Typically this number of phases is directly related to the frequencies of D & Q or their intermodulation products that will introduce spurs outside of the filter bandwidth. Increasing the number of phases used reduces distortion components while increasing the effective carrier frequencies. This can and should be reconfigurable in addition to tuning I<sub>B<sub> to accommodate the typical process variance for transistor characteristics. While other types of phase detectors beside the XOR gate can be used it is important to realize its impact on distortion due to the finite bandwidth of digital gates. The XOR realization grantees that for near zero input Q will exhibit the smallest bandwidth requirement due to its 50 % duty cycle which gradually increases as the phase difference approaches 0 or \ppi.
{{< figure src="/images/icecs2016/TD_logic.svg" title="Figure 6: Boolean operator used that allows a unity gain configuration of the ROF." width="500" >}}
# 5 Simulation Results
In practice the primary difficulty with time domain structures is their associated simulation effort because the bandwidth of operation is many orders larger than the signals of interest. For this reason the analytic model is also presented to perform behavioural simulations and guide the design effort. The results presented here are based on transient noise simulations using industry provided PSP models for completeness. Fig. 7 shows these simulation results where a 1 kHz PWM encoded input signal is driving the system at 95 % of the full input range. V<sub>R<sub> shows the oscillator providing capacitive feedback on the miller integration node while the phase difference of the two ring oscillators tracks the pulse width of the input. Fig. 9 presents the frequency content when three of the phases are summed together and Fig. 8 shows the oscillator phase difference as a function of time. The 56 dB THD shown is critically related to the current DAC characteristics near the cut-off frequency as it not adequately shaped by the integration loop which is challenging to enhance with limited voltage overhead. Table 1 compares the performance presented here using a figure of merit defined where SINAD<sub>MAX<sub> is the maximum signal to noise and distortion ratio as: FOM = Power/(N<sub>poles<sub> BW SINAD<sub>MAX<sub>).
{{< figure src="/images/icecs2016/visual.svg" title="Figure 7: Digital input (D) & output (Q) components together with the integration node V<sub>R<sub> and oscillator outputs internal to the system. " width="500" >}}
{{< figure src="/images/icecs2016/Delta.svg" title="Figure 8: Phase difference of the oscillator structure measured as time delay." width="500" >}}
{{< figure src="/images/icecs2016/Spectrum.svg" title="Figure 9: Spectral power densities of the multi-phase PWM signal Q" width="500" >}}
Table 1: Performance summary and comparison with state of the art
| Specification | This Work | [^6] | [^12] | [^13] |
|----|----|----|----|----|
| modality | Time | Time | Volt. | Volt. |
| Order | 1 | 4 | 3 | 3 |
| Technology | 65nm | 90nm | 0.5\mmu | 0.5\mmu |
| Supply [V] | 0.45 | 0.55 | 3.3 | 1.8 |
| Supply [A] | 35n | 5.3m | 1.4m | 2m |
| Bandwidth [Hz] | 6k | 7M | 1.5M | 500k |
| SINAD [dB] | 52 | 61 | 60 | 65 |
| FoM [fJ] | 7.4 | 93 | 1026 | 1350 |
| Area [mm²] | 0.001 | 0.29 | 2.2 | 0.68 |
# 6 Acknowledgement
This work was supported by EPSRC grants EP/K015060/1 and EP/M020975/1.
# 7 Conclusion
The model and implementation of a oscillator based filter has been demonstrated to complement that of FIR structures [^14] for asynchronous time domain structures. High linearity is demonstrated at full input dynamic range while operating with a 0.45 V supply voltage. The extensive use of digital logic in its construction allows highly synthesizable oscillator based computing for future ultra low power systems in nanometre CMOS. Preliminary simulation result indicates a FOM of 7.4 fJ/pole for the 6 kHz bandwidth which is a substantial improvement over previous time-domain implementations. While it remains to be seen if the efficiency can be maintained in more complex systems the proposed topology shows much promise for ultra low power systems. Moreover we expect that both the first & second order primitives proposed here will find many other applications like \\(\Delta\Sigma\\) ADCs due to its simplicity and flexibility towards process parameters for low voltage operation.
# Refernces:
[^1]: I.L. Markov, ''Limits on fundamental limits to computation,'' Nature, vol. 512, pp. 147--154, August 2014.
[^2]: N.Guo etal., ''Energy-efficient hybrid analog/digital approximate computation in continuous time,'' IEEE J. Solid-State Circuits, vol.51, no.7, pp. 1514--1524, July 2016.
[^3]: M.Verhelst and A.Bahai, ''Where analog meets digital: Analog-to-information conversion and beyond,'' IEEE Solid-State Circuits Mag., vol.7, no.3, pp. 67--80, September 2015.
[^4]: R.Sarpeshkar, ''Analog versus digital: Extrapolating from electronics to neurobiology,'' Neural Computation, vol.10, no.7, pp. 1601--1638, Oct 1998.
[^5]: M.Alioto, ''Understanding dc behavior of subthreshold cmos logic through closed-form analysis,'' IEEE Trans. Circuits Syst. I, vol.57, no.7, pp. 1597--1607, July 2010.
[^6]: B.Drost, M.Talegaonkar, and P.K. Hanumolu, ''Analog filter design using ring oscillator integrators,'' IEEE J. Solid-State Circuits, vol.47, no.12, pp. 3120--3129, December 2012.
[^7]: W.Y. Tsai etal., ''Enabling new computation paradigms with hyperfet - an emerging device,'' IEEE Trans. Multi-Scale Comput. Syst., vol.2, no.1, pp. 30--48, Jan 2016.
[^8]: T.S. Lande etal., ''Running cross-correlation using bitstream processing,'' Electronics Letters, vol.43, no.22, Oct 2007.
[^9]: M.Elia, L.B. Leene, and T.G. Constandinou, ''Continuous-time micropower interface for neural recording applications,'' in IEEE Proc. ISCAS, May 2016.
[^10]: A.Hajimiri and T.Lee, ''A general theory of phase noise in electrical oscillators,'' IEEE J. Solid-State Circuits, vol.33, no.2, pp. 179--194, February 1998.
[^11]: A.Hajimiri, S.Limotyrakis, and T.Lee, ''Phase noise in multi-gigahertz cmos ring oscillators,'' in IEEE Proc. CICC, May 1998, pp. 49--52.
[^12]: C.Garcia-Alberdi etal., ''Tunable class ab cmos gm-c filter based on quasi-floating gate techniques,'' IEEE Trans. Circuits Syst. I, vol.60, no.5, pp. 1300--1309, May 2013.
[^13]: J.Galan etal., ''A very linear low-pass filter with automatic frequency tuning,'' IEEE Trans. VLSI Syst., vol.21, no.1, pp. 182--187, Jan 2013.
[^14]: M.Kurchuk etal., ''Event-driven ghz-range continuous-time digital signal processor with activity-dependent power dissipation,'' IEEE J. Solid-State Circuits, vol.47, no.9, pp. 2164--2173, September 2012.

119
content/publications/2016/a-2-7-rmu-w-mips-0-88-gops-mm-tsqrd-distributed-processor-for-implantable-brain-machine-interfaces.md Normal file
View File

@ -0,0 +1,119 @@
---
title: "A 2.7 μW/MIPS, 0.88 GOPS/mm² distributed processor for implantable brain machine interfaces"
date: 2016-10-17T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
- publication
- processor
- CMOS
- biomedical
---
Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
This paper presents a scalable architecture in 0.18 um CMOS for implantable brain machine interfaces (BMI) that enables micro controller flexibility for data analysis at the sensor interface. By introducing more generic computational capabilities the system is capable of high level adaptive function to potentially improve the long term efficacy of invasive implants. This topology features a compact ultra low power distributed processor that supports 64-channel neural recording system on chip (SOC) with a computational efficiency of 2.7 \\( \mu\\)W/MIPS with a total chip area of 6.2 mm². This configuration executes 1024 instructions on each core at 20 MHz to consolidate full spectrum high precision recordings from 4 analogue channels for filtering, spike detection, and feature extraction in the digital domain.
# 2 Introduction
A key challenge for state-of-the-art neuroscience is real-time data analysis at a massive scale for the diagnosis, treatment and recovery of incapacitating neurological conditions[^1]. While this field has advanced substantially in the realization of signal acquisition and methods for decoding activity. Current systems show a disconnect between implantable devices and the development of algorithms. The initiatives for next generation BMIs focus on scaling recording capabilities and do not consider a strategy for providing highly efficient processing which is imperative implantable SOCs. Moreover it is rare to see methods actively utilize the reconfigurability of modern sensor systems while maximizing the integrity of decoding spike train activity. Numerous aspects with regard to the signal integrity cannot be anticipated and thus assuming a specific method or signal modality will lead to conservative design because an excessively noisy environment is a potentiality. This reveals that chronic instrumentation have yet to be take advantage of more generic real-time processing to improve the efficacy of these invasive devices. Implantable systems predominantly struggle in finding compact and power efficient architectures for signal decomposition. Moving towards fully packaged millimetre scale devices that can support wireless spike train analysis of hundreds of neurons is a highly contested target for many research groups[^2][^3]. As a result high level reconfigurability is yet to be adopted in the current state-of-the-art.
The approach to specialized DSP in the literature reflects two problems pertaining to neural recording systems. The first is signal extraction from recordings that consists of spike detection to extract compressed spike train data. The other is associated with accelerating adaptive filters that map these spike trains to estimate cognitive dynamics or invoked limb movement. Typical examples for acquiring neural activity are fully synthesized cores [^4] [^4]\cite\{2\} that have been successful in realizing implantable solutions. In contrast high level decoding is predominantly performed by FPGAs as integration makes less sense at the system level [^6]. However highly reconfigurable instrumentation have been suggested to leverage both adaptive noise shaping or artefact removal [^7] [^8].
In line with such work this paper presents a distributed processor architecture. Sec. 3 motivates the direction taken here and models the principle constraints for processing at the sensor interface. The proposed system is introduced in Sec. 4 and contextualized by a software development driven platform. The execution unit implementation is detailed in Sec. 5 and accompanied with performance results in Sec. 6.
# 3 On-Node Processing
In order anticipate how future processing methods can be accomodated in SOCs it is essential to capture high level trends with respect to processing capacity of neural implants. Here digital resource requirements are normalized in terms of state variables for evaluating technology dependency. The number of state variables in a dynamic process is a good indicator for complexity whether is a digital classifier or an analogue filter. Here the focus is exclusively on processing such that the signal of interest is idealized with respect amplitude and representation. Consider \\(L\\) as a normalized feature size that allows the evaluation of parameters for a particular technology and extrapolate them based on constant field scaling factors. This remain adequate considering BMIs are fabricated using wide range of 65 nm to 1 \mmu m CMOS technologies.
$$ R_{D} = \underbrace{ \alpha f_s C_{g} V_{dd}^2 L^2 \log_2(SNR) }_{power} \cdot \underbrace{ \alpha \log_2(SNR) A_{g} L^2}_{Area} $$
Eq. 1 represents the power area product for a digital state variable. \\(C_{g}\\), \\(A_{g}\\), \\(\alpha\\) parametrise typical gate capacitance, area, and overhead for each register respectively [^9]. Similarly \\(f_s\\), \\(V_{DD}\\) reflect the sampling frequency and supply voltage. Generally the scaling of \\(R_D\\) constituents are well known and guide maximizing system efficiency in an abstract sense [^10]. For the sake of this discussion we assert that analogue instrumentation is limited to a large extent to having an area power product \\(R_A\\) larger than $10^{-15} Wm^2$ when considering an SNR of 60 dB for a 1.2V system. The derivation comes from the fact that neural signal levels require a specific current dissipation associated with the thermal noise levels and filtering & sampling imply a certain capacitor size according to the supply voltage. The later two terms trade off power with area that can be improved by optimization of the instrumentation topology but will be bounded by signal dynamic range and minimum capacitor sizes.
{{< figure src="/images/biocas2016/Operations.svg" title="Figure 1: Analytic number of digital operations available with respect to different technologies (red) with references to the normalized performance of image processors (blue)." width="500" >}}
With this understanding Fig. 1 illustrates the expected number of digital state variables that aggregate to an equivalent power area product to that of the instrumentation circuit. This shows standard logic in 0.18 um CMOS allows 100 state variables or equivalently 100 operations per sample taken. As reference specialized image processors that similarly rely heavily on data intensive operations are normalized in Fig. 1 to illustrate how technology scaling exhibits the predicted characteristics. As a result it is expected that even for ultra low power BMIs digital processing capacity will be an abundant resource in future systems.
# 4 Neuron-Processor Interface
The high level objective for this system is illustrated in Fig. 2. The application of a generic IoT platform is used to support an unconstrained software stack for networking, data analysis, or system interrogation that best described by high-level languages. This simplifies the development with non-hardware specific software abstractions and accommodates the ease incorporating other modules. The proposed Neuron-Processor Inteface (NPI) device may directly be integrated with the sensor as ASIC and receive configuration commands from this platform to adjust its operation. In extension it follows that peripherals for regulating power and distributing clocks must be integrated on chip. This conforms the interface towards simply providing power and bi-directional data in terms of a SPI protocol.
{{< figure src="/images/biocas2016/Sys_iP.svg" title="Figure 2: Proposed development platform for highly reconfigurable neural recording systems." width="500" >}}
The proposed architecture introduces a large number of on-chip DRAM macros to support the retention of 1024x32-bit instructions. This represents program that is pipelined to each execution unit to instruct filtering coefficients or feature extraction in a manner that can be extended to an arbitrary the number of processing units. Local to each unit is another 1 kbit macro that enables memory intensive methods such as template matching to take place. Four analogue instrumentation channels with a 12 bit ADC is multiplexed to the 8 b processing unit with 68 dB SNDR maximal precision. This is an extension to prior work in [^15] which details the analogue recording implementation.
{{< figure src="/images/biocas2016/NPI_TLT.svg" title="Figure 3: Implemented Neuron-Processor Interface (NPI) system architecture for realizing high performance reconfigurable processing." width="500" >}}
The system is illustrated in Fig. 3, there are multiple layers from system peripheral to the internal units where average data rates progressively increase. We adopt an in-data processing methodology such that the signal is maximally reduced to its principle components at the sensor interface with high-performance digital methods. This mitigates any redundant energy dissipation for data telecommunication. The primary mechanism of operation is the program memory that continuously feeds the stored instructions into the array of processors that operate locally on the recorded data. The execution of these instructions are handled with what is essentially a instruction decoder, memory module and an arithmetic operator. Inherently this implementation will sacrifice the availability of more intricate functionality found in DSPs since the data is not funnelled into one processing unit that can be very elaborate in complexity. The distributed structure is rationalized by the fact that typical methods such as clustering operate at a much lower speed due to the sporadic spiking activity which makes statistical convergence slow. Furthermore these adaptations need to be performed on the order of minutes by which such functions may also be implemented through the redundancy of elementary operations. It is important to mention that multiplexing loses its effectiveness in memory intensive applications such as neural decoding. This is because it does not mitigate the power & area scaling associated with memory allocation and in fact becomes less efficient.
## 5 Execution Unit
It is clear that although all recording channels should execute the same algorithm they will typically not share the same state of operation. This state dependency is exemplified with respect to intermittent processing during bursting neural activity and idling during quiet periods. This is an inherent limitation to sharing the program memory as the dynamic execution of the code where each core has its own program counter or a top level scheduler is not feasible for an arbitrary number of channels. The quasi-out-of-order execution makes it challenging for us to adopt scalable tile structures found in image processing [^11].
Instead branch control or conditional execution is mediated by skipping a section of the incoming instructions if a condition is not met. In this context individual cores may need to execute any section code and branching will only be limited by the dissipation related to the registers pipe-lining the instructions across the chip. As a result any resources associated with cycling through the program has a diminishing contribution to system requirements as the number of channels is increased. This implies that as more sensors are integrated the complexity in algorithm can also increase proportionally which will not be characteristic of conventional implementations that do not pipeline high-level control signals.
{{< figure src="/images/biocas2016/Sys_uC.svg" title="Figure 4: Functional connectivity of the embedded execution unit and sub-blocks" width="500" >}}
The individual components of the execution unit are shown in Fig. 4 and details the main data buses used for exchanging data. The majority operations revolve around manipulating data in the registers R1-R16 as A operand in association with any other data sources that can be used as B operand. In terms of instructions there are always two components where the first is simply the operation executed by the ALU in addition to the two memory sources. The second component optionally extends this simple functionality by writing these intermediate values to multiple other locations or arbitrary branching operations that will take the unit out of sleep.
# 6 Results & Discussion
{{< figure src="/images/biocas2016/Lay_sH.png" title="Figure 5: Fabricated NPI SOC using a 6-metal $0.18 \mu m$ CMOS process showing the system block annotation and top metal routing. " width="500" >}}
This system has been fabricated using a commercially available 6 Metal \cmostech technology (AMS/IBM C18A6/7SF) for validation. The chip micrograph is shown in Fig. 5 measuring 6.2mm² including test circuits and pad ring. While the architecture is capable of achieving very dense configurations at the system level we emphasize that the sensor interface plays an crucial role for noise isolation and chip area overhead.
{{< figure src="/images/biocas2016/TPhw.svg" title="Figure 6: Realization of the development platform used for characterization system functionality." width="500" >}}
The testing platform is photographed in Fig. 6 which interfaces the NPI system with a raspberry pi module. This set-up supports a embedded Linux operating system with low level device control to meed a diverse set of needs. By monitoring the internal data-bus of one core the specialized processing structure has been exhaustively validated at the design point for operating frequencies of 5 MHz to 20 MHz with varying sampling rates on the ADC. Currently the synthesis of instructions remain tailored in associated to the hardware specific compiler because the low level control is crucial for active ADC and amplifier control.
{{< figure src="/images/biocas2016/uC_PS.svg" title="Figure 7: Measured power dissipation with respect to specific operations for the same operand A=113 & B=114 in randomized order." width="500" >}}
The results in Fig. 7 shows the dependency of power dissipation with respect to different operators for the same operand A and B. It should be expected that the is a strong operand dependency with respect to power consumption but these results follow post layout simulations closely. When the unit is in a sleep or branching state the power dissipation is mainly associated with the instruction pipeline. As this 32-bit pipeline transverses the entire execution unit it represents a considerable baseline power contribution. While typical power consumption for full activity lies around 45\\( \mu\\)A at 20 MHz. The reduced complexity local to each channel allows this configuration to achieve \\(2.7 pJ/Cycle\\) or $2.7 \mu W/MIPS$. The specifications given in Table 1 summarize the main features associated with this system on chip for processing neural data at the sensor interface.
Table 1: Comparison of performance specifications for the NPI system.
| Specification | This Work | 2011 [^11] | 2011 [^4] |
|----|----|----|----|
| Scaling | Fine | Fine | Coarse |
| Tech. [nm] | 180 | 65 | 65 |
| Supply [V] | 1.2 | 1.2 | 0.27|
| Units | 64 | 2048 | 16|
| Freq. [MHz] | 20 | 300 | 0.48 |
| Sys. Power [mA] | 1.42 | 300 | 0.28 |
| Sys. Memory [kb] | 32 | - | 50 |
| Tile Memory [kb] | 1 | 1 | - |
| Processor Area [mm(^2)] | 1.37 | 5.10 | 2.09 |
| P-Merit [GOPS/mW] | 1.52 | 0.31 | - |
| A-Merit [GOPS/mm(^2)] | 0.88 | 36.1 | -|
# 7 Acknowledgement
This work was supported by EPSRC grants EP/K015060/1 and EP/M020975/1.
# 8 Conclusion
A scalable processing architecture is proposed in effort to realize compact and efficient neural recording arrays. The topology reflects the nature of processing neural data in the context of extracting signal components and we expect the application of this architecture to be relevant to many high channel count neural SOCs. This discussion details both low-level and system level considerations that look towards better software integration. The proposed system power consumption is on the order of \\(1.5 mW\\) with a power density \\(26 mW/cm^2\\). However this figure is subject to the physical & software reconfiguration that allows extensive optimization for different neural recording applications using the same fabricated device. This work aims to realize long term solution for neural recording implants directed at validating neural decoding methods with in-vivo settings. Importantly standardization off-chip interfacing protocols with self-sustained operation should grantee the ease of integrating existing wireless solutions in extension to this system.
# Refernces:
[^1]: I.H. Stevenson and K.P. Kording, ''How advances in neural recording affect data analysis,'' Nature neuroscience, vol.14, no.2, pp. 139--142, February 2011.
[^2]: A.Khalifa etal., ''A compact, low-power, fully analog implantable microstimulator,'' in IEEE Proc. ISCAS, May 2016, pp. 2435--2438.
[^3]: J.S. Ho etal., ''Midfield wireless powering for implantable systems,'' Proc. IEEE, vol. 101, no.6, pp. 1369--1378, June 2013.
[^4]: V.Karkare etal., ''A 75- $\mu$w, 16-channel neural spike-sorting processor with unsupervised clustering,'' IEEE J. Solid-State Circuits, vol.48, no.9, pp. 2230--2238, September 2013.
[^5]: A.M. Sodagar etal., ''A fully integrated mixed-signal neural processor for implantable multichannel cortical recording,'' IEEE Trans. Biomed. Eng., vol.54, no.6, pp. 1075--1088, June 2007.
[^6]: Y.Xin etal., ''An fpga based scalable architecture of a stochastic state point process filter (ssppf) to track the nonlinear dynamics underlying neural spiking,'' Microelectronics Journal, vol.45, no.6, pp. 690 -- 701, June 2014.
[^7]: C.Qian etal., ''A low-power configurable neural recording system for epileptic seizure detection,'' IEEE Trans. Biomed. Circuits Syst., vol.7, no.4, pp. 499--512, August 2013.
[^8]: Y.Xin etal., ''An application specific instruction set processor (asip) for adaptive filters in neural prosthetics,'' IEEE/ACM Trans. Comput. Biol. Bioinformatics, vol.12, no.5, pp. 1034--1047, September 2015.
[^9]: T.N. Theis and P.M. Solomon, ''In quest of the "next switch" prospects for greatly reduced power dissipation in a successor to the silicon field-effect transistor,'' Proc. IEEE, vol.98, no.12, pp. 2005--2014, December 2010.
[^10]: M.Verhelst and A.Bahai, ''Where analog meets digital: Analog-to-information conversion and beyond,'' IEEE Solid-State Circuits Mag., vol.7, no.3, pp. 67--80, September 2015.
[^11]: T.Kurafuji etal., ''A scalable massively parallel processor for real-time image processing,'' IEEE J. Solid-State Circuits, vol.46, no.10, pp. 2363--2373, October 2011.
[^12]: H.Noda etal., ''The design and implementation of the massively parallel processor based on the matrix architecture,'' IEEE J. Solid-State Circuits, vol.42, no.1, pp. 183--192, Jan 2007.
[^13]: J.Y. Kim etal., ''A 201.4 gops 496 mw real-time multi-object recognition processor with bio-inspired neural perception engine,'' IEEE J. Solid-State Circuits, vol.45, no.1, pp. 32--45, Jan 2010.
[^14]: C.C. Cheng etal., ''ivisual: An intelligent visual sensor soc with 2790 fps cmos image sensor and 205 gops/w vision processor,'' IEEE J. Solid-State Circuits, vol.44, no.1, pp. 127--135, Jan 2009.
[^15]: L.B. Leene etal., ''A compact recording array for neural interfaces,'' in IEEE Proc. BIOCAS, October 2013, pp. 97--100.

1429
content/publications/2016/brain-machine-interfaces-low-power-techniques-for-cmos-based-system-integration.md Normal file
View File

File diff suppressed because it is too large Load Diff

663
content/publications/2016/brain-machine-interfaces-neural-recording-front-end-design.md Normal file
View File

@ -0,0 +1,663 @@
---
title: "Brain machine interfaces: Neural Recording Front End Design"
date: 2016-08-08T15:26:46+01:00
draft: false
toc: true
math: true
type: posts
tags:
- chapter
- thesis
- CMOS
- biomedical
---
Lieuwe B. Leene, Yan Liu, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
This chapter focuses on the multitude of questions associated with the mixed signal design for multi channel integrated neural recording systems. As a result, a significant section will be directed at developing an abstract understanding of how design parameters influence the various design challenges. This discussion will clarify the key limitations for these systems and propose how they can be mitigated or efficiently designed for. In the scope of integrating a large number of recording channels together, clearly understanding how each resource trades for another is crucial for optimizing a complex system. Optimization methods found in the literature typically assume a certain configuration which limits to what extent improvements can be made [^109]. However here we specifically identify abstractions that allow us to consider the impact of different topologies and filter structures simultaneously. This should enable a much boarder sense of optimization that will reflect in the improved performance characteristics demonstrated here.
We will focus on elaborately evaluating the dominant resource requirements with respect to noise, mismatch, quantization, and functional aspects for signal conditioning together that is mostly implementation independent. In addition we propose several circuit implementations based on this analysis that present highly efficient and compact instrumentation. The corresponding abstractions that we use attempt to realize clarity respect to underlying dependencies. This should allow better analytic models that make the limiting factors appear obvious and reveal means to circumvent specific constraints with alternative techniques. For example we may be interested to know when it is worthwhile to put certain functions in the digital domain in terms of the CMOS technology parameters. Approaching the ideal instrumentation structure in such a scenario remains highly desirable for constrained applications. Thus conforming to the technology parameters could reveal that conventional methods do not deliver the most effective solution.
The chapter is organized as follows; Section 17 describes the general problem statement related to the analogue front end which is followed by the associated amplifier design considerations in Section 19. The method for improving the analogue to digital conversion is outlined in Section \ref{ch:T1_converter}. These results are then collected in Section \ref{ch:T1_model} to evaluate the impact of system level parameters as a function of resource requirements.
# 17 Architecture for Neural instrumentation
The analogue dimension of neural recording system can be broken down into two objectives for signal conditioning that will maximize the performance of the proceeding digital signal processing. The first is related to getting adequate signal quantization by amplifying the signals to full input range of the data converter without corrupting the signal of interest. The second objective is performing some kind of filtering that removes noisy or irrelevant components in the recording and only captures the relevant signals of interest.
{{< figure src="technical_1/T1_SIG_Spectrum.pdf" title="Figure 20: Illustration of the spectral power density characteristic for a typical neural recording with the associated frequency bins. " width="500" >}}
As depicted in Figure 20, the input spectrum of a typical \text{in-vivo} electrode recording can be classified using a few frequency bands. The energy from extracellular spiking activity is primarily concentrated around \\(300 Hz\\) to \\(6 kHz\\) and is characteristically intermittent resulting in a distinct difference between the average and instantaneous spectral power [^110]. This characteristic is also present in the LFP band to a lesser extent. From an electrical standpoint the design constraints are derived from the tolerated noise levels in each frequency band to maintain a proper signal to noise ratio. As a consequence it important to specify the signal to noise ratio in terms of noise density opposed to integrated noise figures as digital processing accuracy is not limited by the later term. Here we should also note that the electrode spectral noise power $N^2_{electrode} = 4 kT R_{en} \Delta f$ depends on the resistive component of the electrode impedance. This is typically matched by that of the amplifier noise characteristic \\(N_{amp}\\) so that no excess power is wasted and is expressed in terms of the electrode resistance \\(R_{en}\\), Boltzmann energy \\(kT\\), and the frequencies of interest $\Delta f$.
## 18 Instrumentation Requirements
This kind of electrical sensing can be broken down in the a number of system blocks each of which perform an essential operation to this process. These are shown in Figure 21 and consist of an amplifier, a filter, a sampler, and a quantizer. Occasionally one circuit can combine multiple of these operations together depending on the construction. Table 3 presents the overall performance requirements that should be demonstrated when these components are integrated together. These are also the specifications that we will target as the design is being considered in the following discussion. The reasoning behind these specific requirements are mainly related to conventional signal acquisition given the bandwidth and noise requirements. Moreover these seem to be sufficient for most decoding/characterization methods hence similar figures can be found in most BMI publications.
{{< figure src="technical_1/ISYS.pdf" title="Figure 21: " width="500" >}}
Table 3: Summary of the target specifications for the analogue instrumentation system.
| Parameter | Symbol | Specification |
|----|----|----|
| Integrated Channels | | 64 |
| Supply Voltage | (V_{DD})| (<)1.8V |
| Power Dissipation | (P_{SYS}) | (<)5 (\mu)W |
| Diff. Signal | | 5 (\mu) - 5 mVpp |
| Common Signal | | 50 mVpp |
| CMRR/PSRR | | (>)80 dB |
| Input Referred Noise | (e^2_{in}) | (<)5 (\mu)Vrms |
| Total Gain | (A_T) | (>)40 dB |
| THD at max input | | (>)40 dB |
| 3dB Bandwidth | (f_{3dB}) | 6 kHz |
| High pass frequency | (f_{hp}) | (<)1 Hz |
| Sampling rate | (f_{smp}) | 25 kS/s |
| Input Impedance | (R_{IN}) | (>)50$ M \Omega$ @( 1 )kHz |
| ADC Resolution | (ENOB) | 12 bits |
| Active Area | | 0.01 mm(^2) |
# 19 Amplifier Principles for Miniaturization
{{< figure src="technical_1/Harrison.pdf" title="Figure 22: " width="500" >}}
The principle design considerations for neural instrumentation have been well established particularly with regard to the Harrison topology [^111] that been widely adopted in many systems and shown in Figure 22. Objectively the optimization techniques have become both more specialized and specific for maximizing the average signal to noise ratio in the LFP or EAP bandwidth with the absolute minimum power budget. Interestingly due to the use of more advanced CMOS technologies there is a persistent trend towards sub-threshold operation. This is motivated by trading in the excess transistor bandwidth for improved current efficiency that measured in terms of the achieved transconductance per dissipated ampere of current. In fact this is purely a result of maximizing the individual transistor performance with respect to the speed efficiency product [^112]. This is expressed in Eq 4 using \\(f_T\\), \\(U_T\\), \\(v_sat\\), \\(\mu\\) as the transition frequency, thermal voltage, velocity saturation voltage, and carrier mobility respectively.
$$ \max\limits_{IC} \left\lbrace f_{T} \frac{gm}{I_{DS}} \right\rbrace = \frac{v_{sat}^2}{4\pi \mu \eta U_{T}^2} \: \frac{1}{IC_{max}} \approx \frac{22}{IC_{max}} \left[ \frac{THz}{V} \right] Where IC_{max} = \left( \frac{L_{sat}}{L_{tech}} \right)^2 $$
Here \\(L_{sat}\\) is a technology independent BSIM6 parameter that reflects the impact of ballistic carrier transport during velocity saturation and normalizes the minimum feature length \\(L_{tech}\\) for a specific technology as an effective length. The implication of Equation 4 is that the transistors for optimized low frequency instrumentation amplifiers are exclusively in the sub-threshold regime because \\(f_T\\) is always in excess with respect to the signals of interest. The subthreshold operation results in each transistor's transconductance being defined as $gm = \frac{I_{DS}}{\eta U_{T}}$ which only depends on drain current. Instead of noise optimization though the overdrive voltage, \\(V_{ov}\\), the topology can only reduce noise by removing non-amplifying transistors or biasing them with reduced drain current when compared to the input transistor(s). This reflects the need for a different design methodology as the input referred contribution is dominated by how the total amplifier current distributed to all the transistors. At least in the small signal sense the key requirement is that the amplifying transistors dissipate all the current while biasing/non-amplifying transistors dissipate relatively very little.
In principle due to the under-determined nature of transistor level design the optimization methodology is initially constrained by one of the most important objective characteristics. This could be low noise, wide bandwidth, good linearity, etc. Hence this discussion will digress by distinguishing the design considerations for noise or bandwidth limited amplifiers as separate cases. This should reveal some key relations with respect how power efficiency is achieved. For each case we evaluate the implications with respect to different resource requirements.
## 20 Noise limited Amplifiers
This discussion is guided by the leading challenge for instrumentation systems which is maximizing efficiency while maintaining good linearity. For this reason a noise efficiency factor (NEF) was first introduced in [^113] and is expressed in Equation 5.
$$ NEF^2 = e^2_{in} \frac{I_{tot}}{ U_T 4kT \omega_{3db}} $$
This figure represents a normalized efficiency or in other words it evaluates how much extra current is dissipated by a particular circuit when compared to an ideal bipolar junction transistor for the same noise performance. Here \\(e^2_{in}\\), \\(I_{tot}\\) and \\(\omega_{3db}\\) represent the input referred noise power, the total current dissipation and the -3dB bandwidth in radians respectively. NEF reflects how well a particular topology achieves efficient amplification for a particular noise floor and thus it inherently trades off with a multitude of other parameters. Here we shall use it as design parameter that reflects the chosen transistor level topology. With this in mind, we propose the following reformulation from Equation 5:
$$ e^2_{in} = \frac{kT}{C} \frac{NEF^2}{\eta A_{cl}} \frac{I_{in}}{I_{tot}} \text{where} C = \frac{gm}{\omega_{3db} A_{cl}} \text{and} gm=\frac{I_{in}}{\eta U_T} $$
This result leads to:
$$ gm = \omega_{3db} \frac{kT}{e^2_{in}} \frac{\zeta}{\eta} Equivalently I_{in} = \omega_{3db} \frac{q U_T^2}{e^2_{in}} \zeta \text{where} \zeta = NEF^2 \frac{I_{in}}{I_{tot}} $$
Note that this relation is exclusive to noise limited characteristics and implies nothing with regard to the output load or linearity conditions. Moreover there is a fundamental requirement for transconductance with respect to noise and an implementation related factor \\(\zeta\\). This factor represents the noise efficiency of the topology and the slope factor \\(\eta\\) that tells us about the transistor performance as a fundamental process parameter. Numerous techniques for improving NEF can be found in the literature. As a generalization these can be put into two categories. The first reducing the transconductance of non-signal amplifying transistors using degeneration such that their input referred noise is minimized [^114]. The second approach is AC coupling the amplifier's input signal to biasing transistors such that the total transconductance is increased and the current efficiency is improved. Interestingly because this factor relates to current efficiency the NEF can be smaller than 1 or exceed the efficiency of a BJT using a stacked mixer structure that reuses the same biasing current for multiple amplifiers [^115]. This hints at the fact that NEF should be normalized to the voltage supply but in some sense these structures trade off dynamic range for power efficiency. Theoretical NEF figures for some of the primitive low noise topologies are listed in Table 4 assuming biasing transistors have negligible contribution and taking \\(V_{th}\\) as the NMOS & PMOS threshold voltage.
Table 4: Theoretical figures for NEF for various amplifier topologies. \\(^\star\\) N is the number of stages sharing the structure.
| Topology | NEF | Minimum (Vdd) | Reference |
|----|----|----|----|
| Single Transistor | $\eta $ | (V_{th}) | - |
| Differential Pair | $\eta √{2}$ | $V_{ds} + V_{th}$ | [^116] |
| Complementary Pair | $\eta $ | $2 V_{th}+2 V_{ds}$ | [^117] |
| Common Reference(^\star) | $ \eta √{\frac{1+N}{N}}$ | $V_{ds} + V_{th}$ | [^118] |
| Common Bias(^\star) | $ \eta √{\frac{2}{N}}$ | $(1+N) V_{ds} + V_{th}$ | [^115] |
These relations highlight the fact NEF primarily dependent on the chosen topology and less sensitive to the actual transistor design after optimization. Choosing a topology for the instrumentation amplifier with respect to its ideal NEF performance is significantly more effective than starting with a particular structure and introducing resistive degeneration on transistors that should not contribute noise.
Also notice that the expression for noise in Equation 6 only has one degree of freedom and that is the ratio between the closed loop gain and capacitive load of the amplifier. This implies the 3dB bandwidth of the amplifier is fixed but its unity gain frequency is arbitrary. In fact by satisfying the relation for Equation 7 it is automatically the case the the equivalent noise density requirement is also satisfied. This is significant because we could allow the first stage to provide wide band gain and rely on a second stage to perform filtering. The second stage will have a capacitor gain product that is \\(A_1^2\\) times smaller than if the fist stage had to perform filtering. This can has a large impact on analogue circuit area that is typically dominated by capacitors used for filtering and setting closed loop gain.
{{< figure src="technical_1/flickker.png" title="Figure 23: " width="500" >}}
So far we have only considered the implication thermal noise requirements on the design. We must also address the flicker noise sources because neural signals have a lot of low frequency content. Moreover because flicker noise sources concentrate the noise power at the lower frequencies, the total noise profile inside the LFP frequency band can be dominated by this type of noise. The nature of flicker noise from transistor physics can be due to a number of phenomena; mobility fluctuation $\Delta \mu$, carrier density fluctuation $\Delta N$, and changes in access resistances $\Delta R$. Each of these phenomena will exhibit a \\(1/f\\) frequency dependence when computing the input referred power spectrum. Typically for a given inversion coefficient IC only one of these phenomena will dominate the overall noise characteristic of a transistor. This is illustrated in Figure 23 which shows that $\Delta N$ is typically the leading cause for flicker noise generated additively to the drain current. IC is a factor that indicates to what extent a transistor is operating in the subthreshold region by using the definition IC=I<sub>D<sub>/($2\mu C_{ox} W/L U^2_T$). This uses The more general parameters \\(q\\), \\(W\\), \\(L\\), \\(C_{ox}\\) that represent electron charge, transistor width, transistor length, and gate oxide sheet capacitance respectively. The region of interest for biomedical circuits is typically when \\(IC<1\\) which exhibits good current efficiency and subthreshold operation. The phenomenological model corresponding to carrier density fluctuation $\Delta N$ component is expressed in Equation 8 after being referred to the transistor gate as an equivalent voltage noise density [^119].
$$ e^2_{fl} \Delta f = \frac{q^2 kT \lambda N_T}{W L C^2_{ox} f} \cdot K_{G} \text{where} K_{G} \approx (1 + \frac{\alpha \mu}{2})^2 \text{for} IC < 1 $$
Here \\(\alpha\\) and \\(\lambda\\) represent the coulomb scattering coefficient and tunnelling attenuation distance respectively. Notice that this expression has relatively weak biasing dependency in weak inversion contrast to the strong inversion region as shown in Figure 23. This trend follows very closely to the \\((gm/I_D)^2\\) characteristic which implies a fixed SNR for varying IC. The parameter \\(N_T\\) reflects the density of trapped charges at the oxide interface inside the transistor's conducting channel. Whether this parameter is consistent across various technology nodes is naturally put into question [^120] but similarly there is evidence supporting that indeed this factor is process independent [^121]. Now we should keep in mind that increasing the input transistor size will accommodate lower flicker noise but also result in increased noise. This is because of the signal loss when coupling \\(C_{in}\\) to \\(C_{fb}\\) that is loaded by the parasitic input capacitance of the amplifier \\(C_{g}\\) (see Figure 22). Keeping the ratio \\(C_{g}/C_{fb}\\) fixed as a \\(\delta\\), we can express the required input capacitance in Equation 9 in terms of general amplifier requirements using \\(A_{cl}\\), \\(K_F\\), \\(f_{cor}\\) as the closed loop gain, flicker charge density, corner frequency respectively.
$$ C_{in} = \delta A_{cl} C_{g} = \frac{3}{4} \delta A_{cl} C_{ox} W L = \frac{3}{4} \frac{K_F A_{cl} \delta }{C_{ox} e^2_{in} f_{cor}} \text{where} K_F = q^2 kT \lambda N_T K_G $$
This expression indicates that attempting to achieve all desirable characteristics; small \\(e^2_{in}\\), small \\(f_{cor}\\), large \\(A_{cl}\\) simultaneously in a single amplifier structure comes at the cost of a very large input capacitance that scales proportionally to all factors. This representation suggests the Harrison topology has limited flexibility for improving input capacitance as the only solution appears to be minimising \\(\frac{KF}{C_{ox}}\\) through CMOS process selection. Moreover \\(\delta\\) cannot be made arability small as it will more typically be bounded by the minimum feedback capacitor \\(C_{fb}\\). This need to be large enough to set the high pass pole location at sufficiently small frequency to prevent the resistor \\(R_{fb}\\) from introducing noise inside the signal band which has a integrated power of \\(\frac{kT}{C_{fb}}\\) [^111]. Not to mention that the resulting size of the input transistors can be very large for this particular topology.
## 21 Chopper Stabilized Amplifiers
Alternatively we can apply chopping techniques to deal with these noise requirements which is used extensively in bio-signal instrumentation systems [^69]. By up modulating the signal to a higher frequency before amplification, the flicker noise is added to the usual near-DC band which no longer coincides with out input signal. The output is then demodulated to recover the input. The difference is that the flicker components now lie at the chopper frequency \\(f_{chp}\\) which is typically out of band and can be rejected easily. This eliminates the requirements from Eq 9 on the input capacitance and shifts the focus to rejecting up modulated aggressors at higher frequencies. We suggest using keeping the sampling and chopper frequency coherent because it allows low order FIR filter reject all up modulated harmonics. For instance by chopping at the half the Nyquist frequency (\\(f_s/2\\)) or odd multiples of it (i.e. \\([2n+1] f_s/2\\) $|$ $n \in \mathbb{Z}$) will fold chopper harmonics onto \\(f_s/2\\). The resulting filter are quite relaxed because of the large fractional bandwidth in the transition band that separates our signal bandwidth \\(f_{3dB}\\) from \\(f_{chop}\\). In this particular case we employ a sampling frequency of \\(25 kS/s\\) and use a chopping frequency at \\(37.5 kHz\\) to achieve this functionality [^122]. Conveniently any common mode signals from the sensor or analogue supplies are also rejected using this configuration because they will appear at the chopper frequency.
In addition to basic chopping functionality, the performance can be further improved by providing closed loop feedback to actively cancel aggressors on top of filtering the resulting up modulated aggressors. This can be achieved in multiple ways and in some cases could improve linearity. One possible technique is using a DC-servo loop and another is performing ripple rejection both of which remove different components [^123]. Here we will consider the implementation of three such techniques that improve chopping performance that specifically have negligible power and area requirements. The considerations made here will be similar to that of [^124] [^125] but with explicit focus on area reduction.
{{< figure src="technical_1/T1_CAMP.pdf}" width="500" >}}
{{< figure src="technical_1/T1_CAMP_T.pdf}" title="Figure 24: Proposed compact chopper stabilized neural amplifier topology. " width="500" >}}
Figure 24 shows the proposed configuration that promises a significant reduction in input capacitance and the required silicon area. This configuration has two gain stages where the first stage A1 is a wideband low noise stage and the second provides A2 low pass filtering as motivated by Section 20. This enables the rejection of flicker noise from the first stage completely and effectively shifts the corner frequency of the second stage by gain of first stage squared. Moreover this the configuration does not require auxiliary integrators provide feedback on the capacitive feedback network around A1 that would lead to increased complexity.
The pseudo resistor across A1 in this configuration provides closed loop rejection of low frequency noise below the high pass pole with the time constant $\tau_{HP} = C_{F1} R_{HP}$. The noise components in the band from \\(f_{HP}\\) to \\(f_{CHP}\\) will be a mixture of flicker and thermal noise that are up-modulated by the chopper proceeding A1. This is because A1's corner frequency will lie inside of this band after sizing the input transistors such that \\(C_G\\) is about 5% of \\(C_{IN}\\) which usually leads to a target area of about 100 $\mu m^2$.
It is important that the gains of A1 and A2 are carefully selected because this configuration only provides a first order role off in terms of analogue filtering. It could be that \\(f_{CHP}\\) is not sufficiently outside of the \\(6kHz\\) filter bandwidth resulting in some aggressors to appear on the output of A2. For this reason we require an aggressive high pass pole location to minimize this total up modulated power. More specifically we can say that the total noise contribution below the \\(f_{HP}\\) is mainly from \\(R_{HP}\\) which has a noise power of $\frac{kT}{A1^2 C_{F1}}$ when referred to the input of A1. The main concern here is that we have to sacrifice a small amount of dynamic range on A2 to prevent distortion. Although this power is quite limited, we need make sure the FIR filter can reject up-modulated noise components effectively.
In addition we take advantage of the reduced output referred sampling noise a the input of the second stage that scales by \\(f_{3dB}/f_{CHP}\\). This is because most of the sampling noise will lie outside of the filter bandwidth. The size of \\(C_{I2}\\) can be reduced to alleviate the slewing errors due to the band limited behaviour of A1. In addition the parasitics at the output of A1 will pre-charge before \\(C_{I2}\\) is connected reducing the settling error due to the active nodes switching at the input and output.
A common concern for chopper stabilized circuits is the resistive element of each chopper which in this case is seen at the input of the amplifier. This resistance is due to the switching capacitor \\(C_{I1}\\) that is continuously dissipating dynamic current. This can partially be compensated for by performing positive feedback from the output to assist in cancelling the dynamic current through \\(C_{PF}\\) [^123]. However this will rely on the matching of the capacitor ratios $\frac{C_{I1}}{C_{F1}} \frac{C_{I2}}{C_{F2}}$ to be equal to \\(\frac{C_{I1}}{C_{PF}}\\). This can be quite challenging if small configurations are desired that do not need exhaustive calibration. The use of a high precision ADC makes this somewhat easier because the total gain A1\\(\cdot\\)A2 does not need to be as large implies smaller ratios and better matching. Evaluating this resistance in terms of the switching capacitance will result in the expression in Equation 10.
$$ R_{in} = \frac{1}{2 f_{CHP} \cdot (C_{I1} + C_{par} - \frac{C_{I1}}{C_{F1}} \frac{C_{I2}}{C_{F2}} C_{PF})} $$
This dependency should indicate that if the dynamic switching current cannot be well matched due to parasitics or variability the next objective would be to reduce the total switching capacitance. From our discussion however it appears that reducing the input capacitance is limited by the psuedo resistive noise that induces aggressors at the chopper frequency. This constraint can be mitigated using a distributed amplifier structure that splits A1 into two identical sections. This should be configured such that the second stage has its high pass pole and corner frequency proportionally larger than the first stage but scaled the gain of the prior stage. However such a topology is more constrained by parasitics that worsen the settling errors in $0.18 \mu m$ CMOS. In addition the poor control of psuedo resistive characteristics does not allow this to be convincing solution [^126]. The feasibility may be more favourable in more advanced technology nodes. Considering a value of \\(1 pF\\) for \\(C_{I1}\\) we expect slightly over \\(20 M\Omega\\) without positive feedback and approximately \\(200 M\Omega\\) with \\(10%\\) matching. This may be acceptable in either cases depending which type of electrode is used but generally any thing above \\(100 M\Omega\\) is satisfactory for most scenarios.
## 22 Bandwidth Limited Amplifiers
Biomedical instrumentation has the advantage that the slowly varying signals prevent most implementations from facing problems due to limited bandwidth. The exception however lies with the stage that drives the input capacitance of the ADC and the settling time during sampling can be quite challenging[^127]. Particularly when multiple channels are multiplexed to the same data converter. In some sense there is an similarity when we look at NEF and bandwidth efficiency because they are strongly dependent on maximizing transconductance efficiency.
$$ FOM \left[ \frac{MHz \: pF}{mA} \right] = \frac{f_{UGF} \cdot C_{L}}{I_{tot}} \text{for diff. pair} FOM = \frac{10^{3}}{4 \pi \eta U_{T}} $$
{{< figure src="technical_1/MCAmp.pdf" title="Figure 25: " width="500" >}}
Strictly stated in Equation 11, a bandwidth constrained circuit should minimize the total current consumption \\(I_{tot}\\) for a given unity gain bandwidth \\(f_{UGF}\\) and capacitive load \\(C_L\\). It is typical to find dedicated structures out side of the signal processing chain that drive the ADC input capacitance and focus specifically on maximizing the FOM by employing current recycling, adaptive biasing, and positive feedback techniques. The challenge here is efficiently introducing these techniques while also preserving the capability for full output swing, stability and particularly low distortion. The later is likely the most challenging and demands high loop gain that is generally not found in adaptive single pole structures if full output swing is also required. With that said, two stage Miller compensated topologies can provide an excellent solution to this problem because high gain in the second stage will suppress a number nonlinearities excited by the input stage. Further more the capacitive coupling of the output to the input of the second stage implies the settling speed is limited by bandwidth of the second stage. This allows the configuration to simultaneously provide filtering and settling while sharing many of the biasing and feedback elements. Using the model shown in Figure 25. We can show that sampling induced kick back from the ADC at \\(V_{out}\\) has negligible in pact on internal integration node as it is inversely proportional to the product $A_{cl}\cdot \frac{gm2}{gm1}$ where \\(gm1\\) and \\(gm2\\) are the transconductance of the first and second stage. This is derived from evaluating a step response due to discharging the output load \\(C_{L}\\) which has the Laplace domain response as Equation 12.
$$ H_{step}(s) = \frac{s^2}{s^2 + (\omega_2 - \frac{\omega_1 C_{M}}{A_{cl} C_{L}} ) s + \frac{\omega_{1} \omega_{2}}{A_{cl}}} \text{where} \omega_{1} = \frac{gm_1}{C_{M}} \: \: , \: \: \omega_{2} = \frac{gm_2}{C_{L}} $$
{{< figure src="technical_1/T1_T2AMP.pdf" title="Figure 26: " width="500" >}}
Figure 26 shows the proposed circuit implementation of the two-stage amplifier used inside the second instrumentation stage in Figure 24. This structure has the advantage of providing very high loop gain across the Miller capacitor and allows full output swing due to the positive feed back structures in the current mirrors. The PMOS mirror provides high gain by cancelling the \\(1/gm\\) transresistance of from the diode connected pair leaving the high impedance node and the NMOS mirror provides positive feedback to speed up the transient behaviour on the PMOS side. When this structure provides closed loop gain larger than 20 dB it is sufficient to rely on the NMOS current mirror for stability. In fact this is equivalent to a feed-forward stabilization technique that by passes high frequency signal lag induced by the pole at the PMOS side. However when good phase margin is required at the unity gain frequency stability becomes more stringent. In this case we suggest introducing an additional capacitor across \\(V_n\\) & \\(V_p\\) to realize a zero that cancels the pole in the PMOS branch [^128]. The zero will in fact boost the effective \\(\omega_{2}\\) from $N M \frac{gm_{M5}}{C_{L}}$ to $\frac{N M + M }{2-N} \frac{gm_{M5}}{C_{L}}$. The factor M in this structure has a rather interesting implication with respect to NEF. If M is large enough this topology will have a NEF equivalent to the complementary structure. However in effect the biasing current of the intermediate branch is reduced when M is large which can move the parasitic poles in side the amplifier bandwidth. The apparent trade off between stability and NEF is unique to this structure but it is not challenging to have M=8 for low power applications.
$$ FOM = \frac{10^3}{4\pi \eta U_{T}} \cdot \frac{2 C_L }{ C_M (1+M/K+1/K)} $$
The components that improve bandwidth efficiency are detailed in Equation 13. Referring this back to Equation 6 however implies the noise is dominated by the capacitor that introduces the dominant pole of the system. The observation made here is that unlike the single stage topologies, the two stage configuration can trade off input referred noise for a better speed FOM by adjusting the \\(\frac{C_M}{C_L}\\) ratio. The high level methodology applied here is replacing the \\(C_L\\) with a smaller capacitor that requires less power with the hope that stability can still be maintained by boosting transconductance power with positive feedback and current recycling.
## 23 Circuit Implementation
{{< figure src="technical_1/T1_T1AMP.pdf}" width="500" >}}
{{< figure src="technical_1/AMP_Feedback.pdf}" title="Figure 27: Schematic showing circuit implementation of the proposed compact neural amplifier. " width="500" >}}
Figure 27 shows the transistor level implementation of the topology used in Figure 24. The first gain stage is a highly compact complementary structure that exhibits exceptional noise performance. The second stage transistor implementation is the high gain two-stage topology discussed in Section 22. The variable gain configuration is facilitated by the digital controlled low leakage switches that connect a selected set of capacitors in feedback. This particular configuration provides more generic instrumentation of the 1 Hz to 6 kHz bandwidth. It is well known that the analogue filters introduce frequency dependent group delay near the pole locations which has been shown to degrade processing capabilities of spike sorting techniques [^129]. By placing the high pass pole well inside of the LFP band the spike wave-forms exhibit less distortion due to analogue filtering and is instead filtered using linear phase filters in the digital domain that do not suffer from such drawbacks.
The reset mechanism on instrumentation amplifiers using pseudo-resistive elements is essential. Either during stimulation, start-up, or amplifier saturation the charge across the feedback capacitor must be neutralized before correct operation can begin. This mechanism allows the rejection of various distortion components that would other wise corrupt the latent signal integrity or digital signal processing. However there is an inherent problem with these reset switches due to the parasitic charge injection induced on the intermediate semi-floating nodes. Moreover if these elements are cascaded to increase resistance or dynamic range these sensitive floating nodes are also increased thereby building up more residue charge. A significant amount of charge can introduce a permanent reset artefact after reset as this charge redistributes internally inside the resistor. The proposed solution to this problem is by minimizing the floating nodes and guarding the floating N-Well from injected noise. This should allow a very large pseudo resistance for a sub-Hz high pass cut off frequency while maintaining exceptional reset characteristics. We minimize the resulting charge residue by absorbing the leaky diode currents and residues into the guarding amplifier. Now there will be some instantaneous off-set as the reset signal injects charge directly onto the feedback capacitor but this can be quite small when using small switches. The drawback here is that there may exist a very slow drift on the order of \\(V/sec\\) from the guarding amplifiers due to $V_{os} R_{diode}$. But simple digital assistance will suffice in eliminating this concern by periodically resetting the structure and cancelling the residue off-set. This re-introduces the high pass pole at a well defined location depending on the periodicity of the reset signal and reconstructing signal in the digital domain [^130].
{{< figure src="technical_1/AMP_Label.pdf}" width="500" >}}
{{< figure src="technical_1/AMP_Chip.pdf}" title="Figure 28: Physical implementation of amplifier using a 6-metal $0.18 \mu m$ CMOS process measuring $75 \times 82 \mu m^2$ in size. " width="500" >}}
The floor plan for this implementation is annotated in Figure 28. The typical focus for analogue layout is achieving good matching for the input transistors and capacitors to minimise off-set or undesirable signal coupling. In this case the chopper introduces a lot switching that is difficult isolate from the signal so instead we focused on minimising parasitics of the clocked nets. The common mode feedback on the second stage uses a switched capacitor and wide band amplifier to ensure accurate common mode settling without deteriorating linearity. This is important because the ADC can be quite sensitive to the sampled common mode resulting in a reduced precision if there is an unexpected offset on the sampled output. Simulated performance of the implemented topology is shown in Figure 29. This compact configuration can achieve an input referred noise of $5.6 \mu V_{rms}$ over the specified bandwidth with a noise corner frequency of 20 Hz. The performance is detailed with a clear reduction in size can be observed when compared to other chopper systems in Table 5. The total gain is \\(421 V/V\\) for this particular configuration which can be adjusted using the digital calibration bits integrated into the structure allowing different gain and power settings. The maximum available gain setting is shown in Figure 30.
{{< figure src="technical_1/Noise_PLO.pdf}" width="500" >}}
{{< figure src="technical_1/Amp_Thd.pdf}" title="Figure 29: Post layout simulated results of the proposed instrumentation circuit. " width="500" >}}
{{< figure src="technical_1/sim_gain.pdf" title="Figure 30: Post layout simulated results using periodic steady state analysis to evaluate the closed loop gain of the instrumentation circuit. " width="500" >}}
Table 5: Summary of performance specifications of the proposed instrumentation topology and other bio-signal chopper stabilized amplifiers found in the literature.
| Parameter | Units | This Work | Markovic [^125] | Makinwa [^123] |
|----|----|----|----|----|
| technology | [nm] | 180 | 40 | 65 |
| Supply Voltage | [V] | (1.2) | (1.2) | (1) |
| Total Current | [(\mu)A] | (1.05) | (1.67) | (2.1)|
| Bandwidth | [Hz] | (<1)-(6 k) | (1-5k) | (0.5-1k) |
| Filter Order \ Roll-off | [dB/Dec] | (20) | (20) | (20) |
| Noise Floor | [$nV / √{Hz}$] | (55) | (101) | (60)|
| Noise Corner | [Hz] | $20 Hz$ | (100) | (<1)|
| Dynamic Range | [dB] | (58) | (69) | (64) |
| Area | [(\mu)m(^2)] | $6.2\cdot 10^3 $ | $7.2\cdot 10^4$| $2\cdot 10^5$ |
| Area-Power-Product | [(\mu)W (\mu)m(^2)] | (7.3 10^3) | (141 10^3) | (420 10^3) |
| NEF | | (1.08) | (2.5) | (1.66) |
Overall the proposed implementation performs well for supply voltages larger than \\(1.1 V\\) where the limiting factor is due to the current biased complimentary input stage. This configuration necessitates a voltage overhead requirement of \\(2V_{TH}+2V_{ov}\\). However both of the gain stages are class-A which at exhibit relatively well behaved current transients on the supplies. Class-AB alternatives do not share this feature and are more prone to disturb neighbouring recording circuits. Minimizing the dynamic current dissipation should lead to better LDO performance and lower supply induced sensor noise when many channels are integrated together. This also motivates another aspect for using a wide-band amplifier configuration for the first amplification stage because it usually implies that the common mode will also have wide band regulation. This leads to better common mode rejection in the signal band due to additional loop gain.
# 24 Analogue Signal Conversion
\label{ch:T1_converter}
Analogue to digital conversion remains to a crucial component instrumentation, particularly for full signal characterization. Even when considering the demanding constraints for integrated neural sensors, the prevalence of full spectrum signal characterization is ubiquitous in the literature. This is motivated by the efficiency and reliability of various digital processing methods that require very efficient signal conversion to discreet samples instead of processing recordings in the analogue domain. Typically the most valued performance criteria for such a system is the ADC power consumption. A Successive Approximation Register (SAR) ADC is commonly used for quantizing biomedical signals because it only dissipates switching energy that can be very small for slow sampling rates. The SAR topology is depicted in 31 and can be found extensively in BMI recording publications.
{{< figure src="technical_1/Split_Cap_Schmtc.pdf" title="Figure 31: Schematic of a conventional N bit SAR ADC with the split capacitor at position M." width="500" >}}
## 25 Capacitive array miniaturization
This discussion pays special attention to acquiring neural recordings that include LFPs while minimizing the required silicon area per sensor. This is motivated by wanting to integrate many sensors on chip for large arrays and secondly reducing any capacitive switching noise that can be quite difficult to reject in fully integrated systems. Recording LFPs and EAPs simultaneously will require increased ADC resolution so that the instrumentation dynamic range exceeds 60dB. Equivalently this means 10 to 14 bit precision is needed depending on the nonlinearity tolerances of the proceeding processing methods. This can be quite difficult it terms of the SAR specifications because the capacitor mismatch and sampling noise can prevent aggressive sizing on the unit capacitor. For a given ADC precision N, the SAR capacitor array will require $M \cdot 2^{N/M}+M$ unit capacitors \\(C_{unit}\\) where M is the number of equally split sections. By splitting the array into sections it should be obvious that the total capacitor requirement \\(C_{Total}\\) can be reduced to some extent. The quantization errors resulting from capacitor mismatch on the other hand is also closely related to these parameters. For given standard deviation \\(\sigma\\) and confidence interval CI we can use Equation 14 to make a simple estimate for the expected quantization error \\(E_Q\\) [^131].
$$ E_Q = V_{ref} \frac{\sum \Delta Ci}{2^N C_{unit} - \Delta C_{Total}} = V_{ref} \cdot \alpha(N) \frac{√{2^N}-1}{√{2}-1} $$
The above expression assumes no split configuration is used where \\(\alpha\\) represents a scaling factor that is dependent on the number control bits for each sub-DAC, $\alpha(x)= \frac{CI \sigma}{2^x - CI \sigma √{2^x}}$. \\(V_{ref}\\) is the reference voltage by which the sampled input is normalized to arrive at the binary encoded result. Now extending this formulation to include the dependency of M and bounding $E_Q < LSB/2$ in accordance with the required ADC precision leads to the expression in Equation 15.
$$ \frac{1}{2^{N+1}} \geq \alpha(N/M) \sum_{k=0}^{M} \left[ \sum_{i=0}^{M} √{2^{i}} \right] \cdot \left( \frac{\alpha(N/M)}{2^{N/M}} \right)^k $$
There several higher order terms with respect \\(\sigma CI\\) not shown here because they have vanishing contribution as N is increased and require a numerical solution to the problem. Otherwise for M=2 and arbitrary placing the split capacitor K position in the array we can similarly reconstruct the equality from 14 in Equation 16.
$$ \frac{1}{2^{N+1}} \geq \frac{CI\sigma(√{2^{N-k}}-1)}{(2^{N-K} - CI \sigma 2^{\frac{N-K}{2}} )(√{2}-1)} + \frac{(√{2^{K}}-1) CI \sigma} {(√{2}-1) 2^K (2^K -CI \sigma 2^{\frac{K}{2}})} $$
The standard deviation \\(\sigma\\) is closely related to the exact requirements for the whole capacitive DAC in terms of the total area and unit capacitor size. The dependency of \\(E_Q\\) is mainly subject to the variance due to the MSB capacitors and for each less significant bit (from MSB to LSB) the expected variance increases by \\(√{2}\\) while its capacitive coupling decreases by 2. This is because $\sigma \propto 1/√{A_C}$ where \\(A_C\\) is the area of the capacitor. Clearly there is a process related figure of merit here that relates to the quality of capacitors since small capacitors with excellent matching will result in the best characteristics ADCs such that we minimize the % deviation per \\(\mu m^2\\).
{{< figure src="technical_1/Split_CAP.pdf" title="Figure 32: Numerical solution to Equation 16 relating the capacitive DAC area requirement with the DAC resolution (N) and the position of the split capacitor before capacitor K. " width="500" >}}
Figure 32 shows a numerical solution to the equality in Equation 16. This allows us to consider the effect of split capacitor positioning with respect to the optimal area allocation for the capacitor array. The visible plateau for small N represents the case when the design is bounded by the minimal unit capacitance. This is determined using the process documentation for the target 0.18 \\(\mu m\\) CMOS technology that gives its mismatch specifications and minimum sizing. Generally split capacitor configurations are more sensitive to parasitics they can lead to more pronounced nonlinearities. However in some cases that the unit capacitor size limits the array size such that splinting the array is an effective solution for improving power dissipation. We reiterate that this also indicates that the binary weighted configuration without splitting maximizes area efficiency if we are not limited by sampling noise or minimal capacitor sizing. In addition a fully differential DAC counter intuitively reduces the minimum size if the switching method first detects polarity before applying successive feedback [^132]. This is because the first quantization cycle does not depend on the capacitive division. This in turn means that the array can tolerate twice the mismatch error implying a 4 times smaller unit capacitance while only doubling the number of capacitors in the array.
## 26 Model based topology selection
From here there are multiple directions we can take in order to ensure efficient operation and simultaneously achieve a compact configuration. A common approach is to multiplex the SAR ADC to a large number of channels but this will also require the analogue stage driving the ADC to dissipate proportionally more power due to settling requirements on the sampling capacitance. From a high level perspective, distributing the quantization effort into a large array of ADCs with staggered operation should lead to much more systematic power dissipation due to their uncorrelated operation. Opposed to using a single high speed ADC that requires a much higher clock frequency with stronger tones in the generated supply noise. Another SAR based alternative using calibration for the capacitive array such that it can specifically be designed with the smallest possible unit capacitors. Then we could correct any nonlinearity or quantization errors that arise from capacitor mismatch if the array is characterized precisely enough. This does require either foreground or background calibration modules to extract the individual capacitor weights. Because we aim to perform a number of processing techniques in the digital domain for characterizing neural recording, it makes sense for us to consider effective means to perform calibration.
{{< figure src="technical_1/SDADC.pdf" title="Figure 33: Schematic of the proposed $\Sigma \Delta$ assisted SAR ADC topology for achieving a more compact configuration." width="500" >}}
The structure illustrated in 33 represents a hybrid topology based on SAR and sigma delta structures. The motivation is driven by the efficiency of SAR quantization for large signals and the compactness of high resolution quantization from sigma delta loops. The digital control will perform fully differential bottom plate sampling of the input which is then rapidly quantized to \\(2^N\\) levels using the typical binary search. After the SAR operation the resulting residue left on the capacitive array is quantized using a sigma delta control loop that feedback on the nodes \\(V\Sigma\Delta\pm\\).
There is a strict advantage over conventional sigma delta loops which is that the residue error that needs to be quantized is reduced to \\(\frac{V_{ref}}{2^{N}}\\) which can easily be designed to lie within the linear range of a differential pair. This negates having to use passive or active feedback to deal with transconductance nonlinearity and significantly improves the power efficiency by retaining a relatively simple control loop topology. Moreover as the feedback loop is typically responsible for small dynamic range of 30dB the requirements on clock jitter and decimation filtering is made more relaxed.
The more desirable advantage over a high resolution SAR is that the capacitive DAC may designed in a highly optimal configuration with as few bits as possible. This allows sizing that primarily focuses on suppressing parasitic effects with minimal sampling capacitance. As will be demonstrated this topology does not require an axillary calibration DAC or a pseudo random dithering source for performing mismatch correction. This is due to the capability that the internal sigma delta structure is in the same signal loop as the SAR operation and can trade-off bandwidth for increased noise rejection simply by adjusting the sampling frequency \\(f_s\\). Naturally because this topology inherently needs a pre-amp stage for SAR conversion we should not expect the FOM to do better than low resolution SARs.
Intuitively one can think that when combining the two topologies the individual sources for power dissipation now scale with \\(2^{\frac{N}{2}}\\). More specifically these sources come from the capacitive DAC and decimation filter. The components that do not have reduced scaling are related to the sampling noise and the thermal noise floor of the oversampling modulator. To demonstrate this quantitatively we will build an analytic model for the SAR and \\(\Delta\Sigma\\) SAR topologies to demonstrate some of the inherent characteristics. This will also reveal the techniques for optimizing of the proposed structure.
$$ FOM_{ADC} = \frac{P_{sys}}{2^{N} f_s} $$
Maximizing the performance indicator from Equation 17 will represent our objective function which reflects the efficiency by which each sample is converted into a digital code. Through the simplicity of this relation, any comparison primarily requires an accurate expectation for power budget in terms of the required resolution or precision requirements.
$$ P_{Ideal} = \underbrace{ E_{search} \cdot f_s C_{unit} V_{ref}^2 (2^{N-2}+2^2)}_{Capacitor Array} + \underbrace{2N (N+2) f_s E_{gate} }_{Register Logic} $$
Equation 18 Considers the primitive structure with an ideal comparator where \\(E_{search}\\) represents the average dissipation for binary search switching method and \\(E_{gate}\\) is the average gate dissipation per clock cycle. Both these parameters adjust to different core libraries or various switching methods that typically trade off efficiency for parasitic tolerance [^133]. This ideal structure is extended by the requirements of either a dynamic latch comparator or an analogue pre amplifier that allows negligible comparator requirements at the expense of consuming a static current. The classic pre-amplifier approach also tends to deal with mitigating kick back noise but in general the straightforward application of classic \\(kT/C\\) relations conveniently give;
$$ P_{amp} = 32 \pi \ln(2) \cdot \underbrace{\frac{(U_T N 2^N)^2}{V_{ref} \cdot \eta q}}_{Noise} \cdot \underbrace{A_{ol} f_s NEF^2}_{Bandwidth} $$
Here \\(A_{ol}\\) represents the gain provided by the pre-amplifier. Notice the very typical inverse relationship with respect to \\(V_{ref}\\) which motivates the use of the more efficient dynamic comparator structure. However evaluating the equivalent input referred noise of a dynamic structure accurately requires the a piece wise evaluation for different phases of operation and the respective stochastic integrals [^134]. The contribution can be associated with two dominant sources, that of sampled noise;
$$ \sigma_{S} = \frac{4 kT}{3 C_x F} + \frac{ kT}{3 C_x F^2 H} + \frac{ kT}{12 C_x F^2 H^2} $$
And noise contributed from transconductive elements;
$$ \sigma_{M} = \frac{kT}{C_x F^2} + \frac{kT}{2 C_x F^2 H} + \frac{kT}{8 C_x F^2 H^2} $$
$$ F = \frac{2 \rho V_{th}}{V_{ref} - V_{th} } \text{and} H = \frac{V_{ref}}{2 V_{ov}} \cdot {2 \rho }{1 + \rho} $$
As before, this must be bounded by the acceptable quantization noise, $ V_{ref} \cdot {2^{-N-2}} = √{\sigma_M + \sigma_S } $, which give the values for \\(C_x\\). Strictly there is a strong dependence on the input signal in order to evaluate the dissipated power but on average it is reasonable to approximate this to the capacitive switching energy of $P_{Latch} \approx f_{s} C_x V^2$.
Now consider the components of the \\(\Delta\Sigma\\) structure. Clearly it will follow closely to that of the pre-amplifier based relations with the exception that the primitive components from Equation 18. Instead this will scale with \\(N-K\\) where \\(K\\) is the number of bits resolved by the sigma delta loop. Here two additional components will be accounted for, the first is the integrator and the second is the digital FIR that decimates the modulated residue quantization. A second order feed forward integration topology is chosen for \\(H(s)\\) based on its efficacy of being applied to the configuration shown in Figure 33 and primarily minimizing the number of summing operators and coefficients prone to mismatch. For the sake of discussion we make the assertion that decimation noise rejection is bounded $K \leq (FIR)^{-1/2}$ in the case of a rectangular window for analytic clarity [^135]. Furthermore, note that as we increase the SAR quantization the first stage will proportionally see a reduction of the input signal that needs to be accounted for to achieve the correct integration constant.
$$ P_{int} = 32 \pi \cdot \underbrace{\frac{(U_T 2^{N} NEF)^2 }{ q V_{ref}}}_{Noise} \cdot \underbrace{FIR f_s (1+2^{N-K}) }_{Bandwidth} $$
And similarly the digital decimation filter will scale in the form of;
$$ P_{fir} = \underbrace{2^{K}}_{OSR} \underbrace{( K + \log_{2}(K))}_{Quantization} fs E_{gate} $$
Collecting these terms for each topology will equate to expressions that typically have scalar dependencies on technology or implementation which we must make a set of reasonable assumptions for. The literature will indicate numerous means by which each component can be reduced through specialized logic cells, adaptive comparator power allocation, or power saving switching methods. Our particular interest lies with the dependency on N that will imply the effectiveness of a certain topology for a given dynamic range requirement. In addition this familiarizes us with specific factors fundamental to power dissipation with respect to resolution.
{{< figure src="technical_1/P_TOP_N.pdf}" width="500" >}}
{{< figure src="technical_1/P_TOP_A.pdf}" title="Figure 34: Summary of the FOM (\\(P_{sys}/2^{N} f_s\\)) for each topology with respect to different resolution requirements. " width="500" >}}
Figure 34 presents the expected merit for each topology as the target resolution is varied. Without consideration for area, there is a clear power advantage for the dynamic SAR structure mediated primarily by the fact that the comparator does not have settling associated tolerance. This is the main reason why the pre-amp topology requires a proportionally increased bandwidth/power as resolution is increased. What stands out is that the \\(\Delta\Sigma\\) structure has a power dependency $\propto 2^{3N}$ for achieving the required input referred noise in contrast to more conventional dependency of \\(2^{2N}\\). The mechanism behind this is due to the SAR quantization that reduces the signal input range which needs to be recovered to achieve the correct integration factors. Moreover the over sampling ratio increases simultaneously which has an overall multiplicative effect. Clearly the resolution of the SAR quantizer should only perform a few conversion that put the residue in the linear range of the loop filter and let the modulator perform most of the quantization effort. When all topologies are using the same unit capacitor, this result demonstrates that for \\(N < 5\\) & \\(N > 14\\) the \\(\Delta\Sigma\\) topology becomes strictly unfavourable in terms of power but performs comparably with respect to power efficiency for \\(N \approx 10\\). Taking the FOM area product by considering the capacitors in terms of \\(\Box\\) units the advantage of the \\(\Delta\Sigma\\) topology becomes more obvious. For the precision significant to neural recording, \\(8<N<12\\), the hybrid structure consistently grantees a more compact configuration by a factor of 10.
{{< figure src="technical_1/FOM_Space.pdf" title="Figure 35: Figure of merit dependency of the proposed \\(\Delta\Sigma\\)SAR topology with respect to design parameters K1 & K2. " width="500" >}}
Considering the design space of the \\(\Delta\Sigma\\)SAR structure in more detail will expose a more optimal strategy for increasing FOM. Figure 35 exemplifies how the FOM behaves as either the SAR of sigma delta accuracy is increased. After the optimal basin at N = 9 & K=4 the best strategy for improving ADC resolution is by increasing SAR quantization at half the rate of the sigma delta increase in resolution. For reference a conventional $\Delta \Sigma$ modulator [^136] is designed with the same target specifications and using the same design method to configure the OPAMP integrators and resistive input network. Such a configuration achieves 167 dB FOM<sub>s<sub> irrespective of target resolution when we consider just the analogue power dissipation. In fact this figure is commonly achieved by state of the art [^137]. As shown in Figure 36 the \\(\Delta\Sigma\\)SAR configuration can theoretically achieve more than 4X better performance than conventional \\(\Delta\Sigma\\) modulators for resolutions above 12 bits even when operating at lower supply voltages. This is because of the improved noise efficiency. Please refer to Section 58 for additional details regarding derivations and topology comparisons that are omitted here for clarity.
{{< figure src="technical_1/AMD.pdf" title="Figure 36: Estimation on the expected figure of merit for a target resolution and varying SAR precision. The red star and blue circle indicate the target and measured performance respectively. " width="500" >}}
## 27 Circuit Implementation
Extending the conventional SAR structure to perform sigma delta modulation is achieved with relatively little changes to the overall topology. The main difference is that during the last phase of SAR conversion a register must be toggled that switches in the integrators intermediate to the comparator. Simultaneously the \\(V\Sigma\Delta\pm\\) capacitors are directly connected to the comparator bipolar output instead of the common mode voltage \\(VCM\\) for differential feedback. This configuration is integrated on chip and performs 7 bits of differential SAR quantization with another 5 bits resolved by the noise shaping modulator with an over sampling rate of 32. At the system level, 4 analogue recording channels will be multiplexed to the input of the ADC which implies sampling rate of \\(100 kS/s\\) is required to sample each output at \\(25 kS/s\\).
{{< figure src="technical_1/SAR_Arch.pdf}" width="500" >}}
{{< figure src="technical_1/SAR_Logic.pdf}" title="Figure 37: Schematic configuration of the top level control for the \\(\Delta\Sigma\\)SAR data converter." width="500" >}}
Figure 37 shows the top level configuration of this data converter. By using a specialized register logic slice a small reduction in complexity is achieved in addition to the mitigation of timing issues typical with the conventional self clocking register configuration. This topology uses a bottom plate sampling strategy to neutralize the effect of parasitics and common mode comparator nonlinearities while operating at 1.2V with a 10MHz clock frequency. Although there are only \\(N-K+OSR\\) active phases, settling the output of the recording amplifiers on to the capacitor array will require several cycles because of the band limited behaviour present in the driving stage.
The implementation of the capacitive DAC and second order feed-forward integrator are shown in Figure 37. This configuration also opts to scale the voltage reference for the LSB in order to reduce the total number of capacitor required. As the capacitor array is implemented using CMIM devices the 7 bit differential structure with a split capacitor for \\(M=3\\) will grantee 10.1b for a confidence interval of \\(3\sigma\\) using Equation 16 and process documentation parameters that show a $8\times8 \mu m$ has \\(0.23 %\\) mismatch induced standard deviation. The reasoning for this configuration is that we are guaranteed \\(>9.5 bits\\) without calibration and will allow \\(>12 bits\\) with calibration. For either case the accuracy is sufficient for recording LFP and EAP signals simultaneously. This result was also confirmed with monte-carlo analysis using foundry supplied PSP models.
{{< figure src="technical_1/T1_SDSAR_CDAC.pdf}" width="500" >}}
{{< figure src="technical_1/T1_SDSAR_INT.pdf}" title="Figure 38: Schematic implementation of the \\(\Delta\Sigma\\)SAR structure. " width="500" >}}
The integrator topology primarily deals with the contrasting bandwidth requirement of the SAR operation and the sigma delta integration for the first stage. Particularly when taking the SAR decisions at the oversampled clock the first stage can only provide wideband gain if the capacitor is switched out and a resistive element is used instead. The circuit complexity can be dramatically reduced by using triode region transistors that regulate the PMOS biasing current for a well defined common mode. Because these transistor can be large in area they could slow down the maximum SAR speed. To avoid this the CMFB circuit is semi open loop during the SAR quantization leading to an increase bandwidth by using the common mode voltage that preserved on the integration capacitor. Also by switching the biasing current of the analogue summing stage a constant common mode can be presented to the comparator input thereby reducing any off-set disparity between the two operation phases.
{{< figure src="technical_1/ADC_Label.pdf}" width="500" >}}
{{< figure src="technical_1/ADC_Chip.pdf}" title="Figure 39: Physical implementation of ADC using a 6-metal $0.18 \mu m$ CMOS process measuring $93 \times 147 \mu m^2$ in size." width="500" >}}
Figure 39 shows the fabricated structure of the ADC. Since the capacitors are placed on top of the active circuits this floor plan distances the integrators and the MSB capacitors to physically isolate the digital switching noise sources. A number of shielding structures are employed to improve post layout performance. There include various guard rings and isolating N-wells but due to the proximity of the digital switching the most effective strategy is appropriately orienting fully differential structures in order to equalize the coupling components. Here metal layers 1-3 are used for transistor interconnect, layers 5-6 for the capacitive DAC, and layer 4 is interposed in order to shield the two sections while connected to the common mode voltage. This is because the transient fluctuations on \\(V_{cm}\\) are only due to mismatch and should be the most quiet reference in the system with large capacitive loading.
In order to take advantage of this structure we reveal two distinguishing characteristics that can not be found in either conventional topologies or other hybrid topologies. When the capacitive DAC is considered as a set of weights that need to be determined we realize that the derivative for slow varying signals is predominantly quantized by the sigma delta loop. With the exception when the SAR bits switch the quantization is independent of the mismatch in these weights. As a result all the mismatch coefficients can be accounted for with respect to the $\Sigma \Delta C$ capacitor.
{{< figure src="technical_1/adc_cloop.pdf" title="Figure 40: Control loop used to perform calibration with a slow test signal at the ADC input." width="500" >}}
The calibration technique discussed is abstractly represented by Figure 40 where there are two IIR control loops with the coefficients \\(a_1\\) and \\(b_1\\). In part this loop performs normal operation by evaluating the signal quantization \\(Q_{sig}\\). This is done adding the SAR quantization with calibrated weights and decimating the oversampled residue with a \\(32^{nd}\\) order FIR window quantized with 8 bit coefficients for each sample. Here \\(a_{1}\\) simply has to be small enough to track the signal and reject noisy components to determine $\Delta Q$. $\Delta Q$ represents DNL nonlinearities that are used to adjust the coefficients \\(K_{DAC}\\). The multiplication operator is in fact a bitwise evaluation that indicates if a coefficient needs to be adjusted due to a correlation between $\Delta Q$ and a change in that bit. Hence \\(b_{1}\\) needs to be small enough to prevent level dependent tuning and \\(V_{test}\\) should be a full range slow varying signal.
{{< figure src="technical_1/adc_UC.pdf}" width="500" >}}
{{< figure src="technical_1/adc_CC.pdf}" title="Figure 41: INL Plots illustrating the mismatch artefact reduction due to calibration." width="500" >}}
The improvement in INL is evident in Figure 41 due to the calibration mechanism with \\(a_1=1/4\\) and \\(b_1=2^{-8}\\). The close interaction between INL & DNL errors over the full dynamic range for a capacitive array in addition to the sigma delta loop's capability of quantizing $\pm 2 LSB$ of the array allows this method to converge accurately. Here it is observed that the calibration improves the quantization accuracy by two additional bits.
{{< figure src="technical_1/adc_thdsnr.pdf" title="Figure 42: Measured THD and SNR of the fabricated data converter." width="500" >}}
{{< figure src="technical_1/ADC_TEST.jpg}" width="500" >}}
{{< figure src="technical_1/adc_TI.pdf}" title="Figure 43: Testing setup used for characterizing the ADC." width="500" >}}
Figure 43 shows the test bench used during device characterization. The saleae logic device is a digital probe that offers 100 MS/s digital signal acquisition for measurements of up to 10 seconds. Here the raspberry pi module simply provides real time interaction with the device configuration using automated spi control and a graphical user interface that will indicate ADC precision based on the selected operation. This allows us to tweak the operating conditions and find which noise sources are disturbing the configuration. The analogue bias \\(I_{BIAS}\\) is generated by a 2602A Keithley system source meter and fed in using a guarded triax cable. The differential input signals are generated using a Agilent 33522A arbitrary waveform generator and fed to the ADC input using BNC cables.
Table 6 outlines the characteristics of the implemented ADC configuration while comparing it to recent oversampling/noise shaping data converter publications. Figure 42 demonstrates the spectral characteristics of the quantization output for a input signal at half the full input range after calibration. In comparison to the analogue instrumentation, the resource related specifications are significantly larger. However note that there requirements are distributed over a number of channels as a result of multiplexing this structure.
Table 6: Summary of performance specifications for the \\(\Delta\Sigma\\)SAR data converter and other oversampling/noise shaping data converter structures found in the literature.
| Parameter | Units | This Work | Lo [^138] | Roermund [^139] |
|----|----|----|----|----|
| Technology | [nm] | 180 | 65 | 65 |
| Supply Voltage | [V] | (1.2) | (1.2) | (0.8) |
| Total Current |[(\mu)A] | (12) | (13) | (1.7) |
| Sampling Frequency | [kS/s] | $200 $ | (8) | (16) |
| ENOB | [bits] | (11.3) | (17.5) | (14.5) |
| SFDR | [dB] | (86) | (105) | $ 87 $ |
| Area | [$\mu m^2$] | $93 \times 147$ | $400 \times 180$ | $600 \times 300$|
| Power-Area-Product | [$\mu W \mu m^2$] | $1.9 \cdot 10^5$ | $1.1 \cdot 10^6$ | $2.4 \cdot 10^5$|
| $P/(fs + 2^N)$ | [fJ/conv] | (10) | (29) | (6.6) |
| (SNDR+10log(BW/P)) | [dB] | (166) | (180) | (177) |
The trade off with respect to residue over sampling in Figure 44 demonstrates that there is some flexibility with respect to sampling rate and SINAD performance. In addition this also clarifies that post-fabrication adjustments do not exhibit significant resolution improvements beyond the design point. This is related to the sampling noise of the capacitor array and the noise floor of the analogue integrators that need to be programmable for different oversampling ratios. At which point the decimation also has more strenuous requirements that may result in an inefficient resource overhead. Strictly stated it is significantly more efficient to reject noise with digital bandpass filtering selected frequency components than having the ADC resolve the signal beyond the target precision.
{{< figure src="technical_1/adc_fom.pdf" title="Figure 44: Measured Figure of Merit as a function of oversampling ratio." width="500" >}}
In the context of miniaturization the topology presented here follows closely to the expected improvement from the model for high resolution signal acquisition. We achieve nearly 12 bits of quantization with a 6 bit equivalent capacitive DAC which is reflected in the compact design foot print. When compared to similar compact ADC implementations found in recent publications we observe a competitive power budget with again significantly smaller area requirement. Some additional digital processing is required opposed to the simplicity of SAR converters to take full advantage of the topology. However such hardware is typically readily available in systems that also perform spike sorting and neural signal classification.
# 28 System Level Abstraction
\label{ch:T1_model}
Numerous specifications such as ADC resolution and input referred noise of the instrumentation amplifiers relate directly to signal specific parameters. Moreover a particular processing algorithm would favour certain filter configurations of others in terms of signal conditioning. In multi stage systems however there is a significant amount of flexibility related to choosing gain for individual stages or their filter parameters that is indifferent to the resulting transfer function. Here we consider such a primitive \\(N\\) stage analogue processing chain and discuss the allocation of resources to gain insight to some of the high level the optimization for selecting a specific configuration. Such a configuration is shown in Figure 45.
{{< figure src="technical_1/ACS.pdf" title="Figure 45: Multistage amplifier configuration using the series G to adjust the allocation power and area. " width="500" >}}
$$ G[n] = A_{g} \left( \beta + \alpha^{n} \right) \text{where} A_{g} = √[N]{\frac{G_{T}}{ \prod_{i=1}^{N} (\beta + \alpha^{n} )}} $$
Consider a geometric series for the gain of each stage as expressed in Equation 25. Here \\(G_{T}\\), \\(\alpha\\), \\(\beta\\) represent the total gain required, resource distribution factor, and a minimal contribution factor. The formulation is motivated by the fact that if \\(\alpha\\) is one resources are allocated equally. This means every stage has equal gain but it also implies that the sum of all gain factors is minimal leading to a minimum amount of area due to the feedback capacitors. More typically designs will choose a smaller \\(\alpha\\) such that most of the gain is situated at the first few stages. This allows some reduction in power in the proceeding stages because of the reduced noise requirement. \\(\beta\\) simply allows us to specify that a fraction of the total gain is uniformly distributed but is typically kept small in order to maximize the benefit from resource redistribution. This allows us to express the noise power requirement for a given set of parameters in Equation 26.
$$ P_{Amplifiers} = P_{unit} \left( 1 + \sum_{k=1}^{N-1}\left[\prod_{i=1}^{k} \frac{1}{A_{g} \beta + A_{g} \alpha^{i} } \right] \right)^2 $$
$$ A_{Gain}= A_{unit}\left( \sum_{k=1}^{N} \left[1 + A_{g} \beta + A_{g} \alpha^{k} \right] \right) $$
Here \\(P_{unit}\\) is simply evaluated from Equation 6 and leads to an area requirement that is simply expressed using Equation 27. Now taking some typical parameters we can evaluate a possible configuration of gains and thereby the associated allocation of resources. This is shown in Figure 46.
{{< figure src="technical_1/RDBG.pdf" title="Figure 46: Resource allocation for analogue power and area using the parameters \\(G_T=500\\), \\(\alpha=0.3\\), and \\(\beta=0.05\\). " width="500" >}}
Lets take \\(A_{unit}\\) as some unit capacitance size that allows the deviation of gain due to mismatch to fall inside the confidence interval. In order to realize Equation 26, each stage has its power and input referred noise reduced by accumulated gain for the preceding stages. This result presents us with the trend illustrated in Figure 47 where it appears that in many stage systems it is relatively beneficial to redistribute the resources to the front-end for a reduction in overall power. However when the number of stages is three or less we observe the increase in area can diminish this improvement for high gain system requirements.
{{< figure src="technical_1/NM_NP.pdf}" width="500" >}}
{{< figure src="technical_1/NM_PAP.pdf}" title="Figure 47: Normalized resource improvements for \\(\alpha\\) with respect the case when \\(\alpha=1\\) for each configuration. " width="500" >}}
So far we have neglected some aspects to the design consideration. The first is the multiplicative increase standard deviation as N is increases and the sensitivity to variance being inversely proportional to closed loop gain. Here we can account for the increased variance by proportionally increasing \\(A_{unit}\\) in order to neutralize this increase according to Equation 28.
$$ \Delta \sigma^2 =\frac{A_{\mu+\sigma}}{A_{Gain}} \approx \prod_{i=1}^{k} \left( 1 + \sigma CI \left[ 2 - \frac{2}{√{ A_{g} \beta + A_{g} \alpha^i }} \right] \right) $$
Again \\(\sigma\\) represents the deviation for a chosen unit capacitance and \\(CI\\) is our confidence interval. For completeness in estimating area we will also introduce the capacitance required for performing filtering on the last \\(K\\) stages. Rearranging Equation 6 in terms of output referred noise according to Equation 29.
$$ e^2_{out} = \frac{kT}{C} {NEF^2}{\eta} $$
Combining these terms lets us define a more accurate area requirement that is reformulated in Equation 30.
$$ A_{filt} = A_{unit} \cdot \frac{kT}{C_{unit}} \frac{NEF^2 SNR^2}{Vdd^2 \eta} \cdot \left( 1 + \sum_{k=1}^{K-1} \prod_{i=1}^{k} \left[A_{g} \beta + A_{g} \alpha^{N-i} \right] \right) $$
It is important to point out that SNR here refers to the SNR of the data converter as we have fixed the input referred noise of the system for a systematic comparison and we adjust \\(G_T\\) to fill this dynamic range. And extending this result with the requirements for signal conversion we can estimate system level power \\(P_{Total}\\) and area \\(A_{Total}\\) requirements as a sum of individual components according to Equation 31.
$$ A_{Total} = A_{filt} + A_{Gain} + A_{ADC} \text{and} P_{Total} = P_{Amplifiers} + P_{ADC} $$
Taking an appropriate set of parameter values, the system of relations is exemplified in Figure 48 with respect to the dependency on the supply voltage, \\(Vdd\\). As illustrated there are two domains when considering the area requirement. For small \\(Vdd\\) the sampling & filtering noise requirements overwhelm the design particularly in this case if \\(\alpha\\) is not taken small enough and a second order roll off is needed. When there is more voltage overhead available we observe reliably matching in input dynamic range of the ADC is the dominating factor.
{{< figure src="technical_1/NM_TSNA.pdf}" width="500" >}}
{{< figure src="technical_1/NM_TSNAP.pdf}" title="Figure 48: Analogue resource relations with respect to different supply voltages. " width="500" >}}
The area power product also tells an interesting story. When \\(Vdd\\) is larger than 1 V a clear proportional dependency on power is apparent that is mostly related to the total gain & noise requirements of the system because the ADC is not the limiting factor. However for small supply voltage the power dissipation requirement is more closely related to the lower noise quantization requirements presented by the SD-SAR topology. We should be careful because certain circuit topologies are simply not viable below specific supply voltages and as a result it would no be possible to achieve a NEF smaller than 2. Figure 48 also indicates when particular topologies are viable specific to the $0.18 \mu m$ CMOS process where $V_{th} \approx 350 mV$. That said it is likely a system can be designed with \\(0.6 V\\) supply in order to achieve significant power and area savings. The main challenge will be achieving acceptable total harmonic distortion as the supply will not easily allow cascoding transistors. Particularly sub-threshold transistors suffer from \\(Gm\\) nonlinearity as a function of \\(e^{\frac{-V_{DS}}{U_T}}\\) that can only be compensated by increased loop gain and multi-stage topologies. Since it is implementation dependent, it is difficult to quantify what this increase in area an power overhead this will result in. We can assert that \\(60 dB\\) precision with instrumentation has very significant diminishing returns when the conventional design approaches a \\(2 V_{th}\\) supply. The reader can find more details in regard to these comparisons in Section 60.
The approach taken here can be exhaustively extended towards including more detail in the system level design in order to leverage the capability of numerical methods. Higher order Gm-C filtering structures can be accounted for as a single stage by introducing new parameters that reflect the increase in \\(NEF\\) and filtering capacitors. Transistor area per amplifier can arguably be assumed static if chopping techniques are employed or alternatively this can accounted for by considering the flicker noise relations for the input transistors. However these contributions have negligible effect on changing the optimal resource destitution and will be more influenced by strategic positioning of poles to reject certain noise components. The most critical parameters on the systems level is the supply voltage as well as the requirement for channel to channel gain matching. As the power area product has a inverse square dependency as either \\(V_{DD}\\) or gain variance tends to zero. There are only a select number of scenarios where gain matching is of significance which is primarily in the case of distributed LFP recording and multi electrode (i.e. tetrode) recordings where exact coupling of neural circuitry is in question. The supply voltage has significance with respect to the expected power dissipation of the on chip digital processing and it is understandably advantageous to aggressively dissipate more power on the analogue side if the power saving in the digital domain indicate a overall improvement.
We note another aspect to technology selection in addition enabling voltage scaling is the increase in functional capacitor density. In fact we have shown that the dominant factor for area requirement in chopper stabilized structures is capacitance through the strong dependency on gain and filtering elements. More advanced processes have an increased number of metal layers and higher transistor gate capacitance. This ultimately leads to an increased capacitor density per square millimetre. In certain scenarios this should allow us to marginally shrink amplifier configurations while keeping the same filter characteristics. The main concern would be associated with capacitor nonlinearity that requires extra consideration or correction circuits.
# 29 Conclusion
This chapter has demonstrated the capacity for conventional analogue instrumentation with state-of-the-art circuit techniques. This presents capacity for achieving very compact performance that is sufficient for the full characterization of neural recordings. The fabricated system uses 0.03 mm\\(^2\\) size silicon footprint for 4 recording channels that can characterize 5 mVpp neural signals with over 11 bits of precision. In addition proposed $\Delta\Sigma SAR$ ADC topology demonstrates how oversampling converters can achieve 10fJ/conversion efficiency with minimal circuit complexity. The techniques applied here suggests chopping and sigma-delta modulation are key components for achieving better performance particularly for size constrained systems. In association we suggest immediate digitization & coherent mixed signal processing to leverage a number of advantages. Moreover we expect modern system will allow more processing capabilities in the digital baseband for BMI systems that needs to be used effectively.
The significance of minimizing the noise efficiency factor has been revealed in terms of having profound influence to power dissipation and area. In extension we have presented a number of topologies that excel at achieving excellent power and area efficiency in the case of single stage, two stage, and ADC structures. However we are left with little surprise when methodical optimization of various configurations is limited by the fundamental bounds in terms of noise and dynamic range. In fact various idealized configuration show little benefit with respect to one another if they have been optimized and exploited appropriately with the understanding presented. It is characteristic that improving resource efficiency for full bandwidth signal quantization is difficult because we simultaniously attempt to achieve lower supply voltages.
Although digitization is crucial to most neural recording systems for extracting the signal characteristics used to train and improve signal postprocessing. It is clear that improvements at the system level will lie very much in the domain of specialized instrumentation and analogue to information converters. This notion is motivated by the desire for the system to be limited by the law of equipartition and less so by the quantization process of the data converter. The direct classification of recordings in the analogue domain has significant implications on the responsibilities of the accompanied DSP on chip and the reduction of associated processing bandwidth.
# References:
[^1]: R.Q. Quiroga, Z.Nadasdy, and Y.Ben-Shaul, ''Unsupervised spike detection and sorting with wavelets and superparamagnetic clustering,'' Neural Computation, vol.16, pp. 1661--1687, April 2004. [Online]: http://dx.doi.org/10.1162/089976604774201631
[^2]: R.A. Normann, ''Technology insight: future neuroprosthetic therapies for disorders of the nervous system,'' Nature Clinical Practice Neurology, vol.3, pp. 444--452, August 2007. [Online]: http://dx.doi.org/10.1038/ncpneuro0556
[^3]: K.Birmingham, V.Gradinaru, P.Anikeeva, W.M. Grill, B.Pikov, VictorMcLaughlin, P.Pasricha, K.Weber, DouglasLudwig, and K.Famm, ''Bioelectronic medicines: a research roadmap,'' Nature Reviews Drug Discovery, vol.13, pp. 399--400, May 2014. [Online]: http://dx.doi.org/10.1038/nrd4351
[^4]: ''Bridging the bio-electronic divide,'' Defense Advanced Research Projects Agency, Arlington, Texas, January 2016. [Online]: http://www.darpa.mil/news-events/2015-01-19
[^5]: G.Fritsch and E.Hitzig, ''ber die elektrische erregbarkeit des grosshirns,'' Archiv für Anatomie, Physiologie und Wissenschaftliche Medicin., vol.37, pp. 300--332, 1870.
[^6]: G.E. Loeb, ''Cochlear prosthetics,'' Annual Review of Neuroscience, vol.13, no.1, pp. 357--371, 1990, pMID: 2183680. [Online]: http://dx.doi.org/10.1146/annurev.ne.13.030190.002041
[^7]: ''Annual update bcig uk cochlear implant provision,'' British Cochlear Implant Group, London WC1X 8EE, UK, pp. 1--2, March 2015. [Online]: http://www.bcig.org.uk/wp-content/uploads/2015/12/CI-activity-2015.pdf
[^8]: M.Alexander, ''Neuro-numbers,'' Association of British Neurologists (ABN), London SW9 6WY, UK, pp. 1--12, April 2003. [Online]: http://www.neural.org.uk/store/assets/files/20/original/NeuroNumbers.pdf
[^9]: A.Jackson and J.B. Zimmermann, ''Neural interfaces for the brain and spinal cord — restoring motor function,'' Nature Reviews Neurology, vol.8, pp. 690--699, December 2012. [Online]: http://dx.doi.org/10.1038/nrneurol.2012.219
[^10]: M.Gilliaux, A.Renders, D.Dispa, D.Holvoet, J.Sapin, B.Dehez, C.Detrembleur, T.M. Lejeune, and G.Stoquart, ''Upper limb robot-assisted therapy in cerebral palsy: A single-blind randomized controlled trial,'' Neurorehabilitation AND Neural Repair, vol.29, no.2, pp. 183--192, February 2015. [Online]: http://nnr.sagepub.com/content/29/2/183.abstract
[^11]: P.Osten and T.W. Margrie, ''Mapping brain circuitry with a light microscope,'' Nature Methods, vol.10, pp. 515--523, June 2013. [Online]: http://dx.doi.org/10.1038/nmeth.2477
[^12]: S.M. Gomez-Amaya, M.F. Barbe, W.C. deGroat, J.M. Brown, J.Tuite, Gerald F.ANDCorcos, S.B. Fecho, A.S. Braverman, and M.R. RuggieriSr, ''Neural reconstruction methods of restoring bladder function,'' Nature Reviews Urology, vol.12, pp. 100--118, February 2015. [Online]: http://dx.doi.org/10.1038/nrurol.2015.4
[^13]: H.Yu, W.Xiong, H.Zhang, W.Wang, and Z.Li, ''A parylene self-locking cuff electrode for peripheral nerve stimulation and recording,'' IEEE/ASME Journal of Microelectromechanical Systems, vol.23, no.5, pp. 1025--1035, Oct 2014. [Online]: http://dx.doi.org/10.1109/JMEMS.2014.2333733
[^14]: J.S. Ho, S.Kim, and A.S.Y. Poon, ''Midfield wireless powering for implantable systems,'' Proceedings of the IEEE, vol. 101, no.6, pp. 1369--1378, June 2013. [Online]: http://dx.doi.org/10.1109/JPROC.2013.2251851
[^15]: R.D. KEYNES, ''Excitable membranes,'' Nature, vol. 239, pp. 29--32, September 1972. [Online]: http://dx.doi.org/10.1038/239029a0
[^16]: A.D. Grosmark and G.Buzs\'aki, ''Diversity in neural firing dynamics supports both rigid and learned hippocampal sequences,'' Science, vol. 351, no. 6280, pp. 1440--1443, March 2016. [Online]: http://science.sciencemag.org/content/351/6280/1440
[^17]: B.Sakmann and E.Neher, ''Patch clamp techniques for studying ionic channels in excitable membranes,'' Annual Review of Physiology, vol.46, no.1, pp. 455--472, October 1984, pMID: 6143532. [Online]: http://dx.doi.org/10.1146/annurev.ph.46.030184.002323
[^18]: M.P. Ward, P.Rajdev, C.Ellison, and P.P. Irazoqui, ''Toward a comparison of microelectrodes for acute and chronic recordings,'' Brain Research, vol. 1282, pp. 183 -- 200, July 2009. [Online]: http://www.sciencedirect.com/science/article/pii/S0006899309010841
[^19]: J.E.B. Randles, ''Kinetics of rapid electrode reactions,'' Discuss. Faraday Soc., vol.1, pp. 11--19, 1947. [Online]: http://dx.doi.org/10.1039/DF9470100011
[^20]: M.E. Spira and A.Hai, ''Multi-electrode array technologies for neuroscience and cardiology,'' Nature Nanotechnology, vol.8, pp. 83 -- 94, February 2013. [Online]: http://dx.doi.org/10.1038/nnano.2012.265
[^21]: G.E. Moore, ''Cramming more components onto integrated circuits,'' Proceedings of the IEEE, vol.86, no.1, pp. 82--85, January 1998. [Online]: http://dx.doi.org/10.1109/JPROC.1998.658762
[^22]: I.Ferain, C.A. Colinge, and J.-P. Colinge, ''Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors,'' Nature, vol. 479, pp. 310--316, November 2011. [Online]: http://dx.doi.org/10.1038/nature10676
[^23]: I.H. Stevenson and K.P. Kording, ''How advances in neural recording affect data analysis,'' Nature neuroscience, vol.14, no.2, pp. 139--142, February 2011. [Online]: http://dx.doi.org/10.1038/nn.2731
[^24]: C.Thomas, P.Springer, G.Loeb, Y.Berwald-Netter, and L.Okun, ''A miniature microelectrode array to monitor the bioelectric activity of cultured cells,'' Experimental cell research, vol.74, no.1, pp. 61--66, September 1972. [Online]: http://dx.doi.org/0.1016/0014-4827(72)90481-8
[^25]: R.A. Andersen, E.J. Hwang, and G.H. Mulliken, ''Cognitive neural prosthetics,'' Annual review of Psychology, vol.61, pp. 169--190, December 2010, pMID: 19575625. [Online]: http://dx.doi.org/10.1146/annurev.psych.093008.100503
[^26]: L.A. Jorgenson, W.T. Newsome, D.J. Anderson, C.I. Bargmann, E.N. Brown, K.Deisseroth, J.P. Donoghue, K.L. Hudson, G.S. Ling, P.R. MacLeish etal., ''The brain initiative: developing technology to catalyse neuroscience discovery,'' Philosophical Transactions of the Royal Society of London B: Biological Sciences, vol. 370, no. 1668, p. 20140164, 2015.
[^27]: E.DAngelo, G.Danese, G.Florimbi, F.Leporati, A.Majani, S.Masoli, S.Solinas, and E.Torti, ''The human brain project: High performance computing for brain cells hw/sw simulation and understanding,'' in Proceedings of the Digital System Design Conference, August 2015, pp. 740--747. [Online]: http://dx.doi.org/10.1109/DSD.2015.80
[^28]: K.Famm, B.Litt, K.J. Tracey, E.S. Boyden, and M.Slaoui, ''Drug discovery: a jump-start for electroceuticals,'' Nature, vol. 496, no. 7444, pp. 159--161, April 2013. [Online]: http://dx.doi.org/0.1038/496159a
[^29]: K.Deisseroth, ''Optogenetics,'' Nature methods, vol.8, no.1, pp. 26--29, January 2011. [Online]: http://dx.doi.org/10.1038/nmeth.f.324
[^30]: M.Velliste, S.Perel, M.C. Spalding, A.S. Whitford, and A.B. Schwartz, ''Cortical control of a prosthetic arm for self-feeding,'' Nature, vol. 453, no. 7198, pp. 1098--1101, June 2008. [Online]: http://dx.doi.org/10.1038/nature06996
[^31]: T.N. Theis and P.M. Solomon, ''In quest of the "next switch" prospects for greatly reduced power dissipation in a successor to the silicon field-effect transistor,'' Proceedings of the IEEE, vol.98, no.12, pp. 2005--2014, December 2010. [Online]: http://dx.doi.org/10.1109/JPROC.2010.2066531
[^32]: G.M. Amdahl, ''Validity of the single processor approach to achieving large scale computing capabilities, reprinted from the afips conference proceedings, vol. 30 (atlantic city, n.j., apr. 18-20), afips press, reston, va., 1967, pp. 483-485, when dr. amdahl was at international business machines corporation, sunnyvale, california,'' in AFIPS Conference Proceedings, Vol. 30 (Atlantic City, N.J., Apr. 18-20), vol.12, no.3.\hskip 1em plus 0.5em minus 0.4em elax IEEE, Summer 2007, pp. 19--20. [Online]: http://dx.doi.org/0.1109/N-SSC.2007.4785615
[^33]: J.G. Koller and W.C. Athas, ''Adiabatic switching, low energy computing, and the physics of storing and erasing information,'' in IEEE Proceedings of the Workshop on Physics and Computation.\hskip 1em plus 0.5em minus 0.4em elax IEEE, October 1992, pp. 267--270. [Online]: http://dx.doi.org/10.1109/PHYCMP.1992.615554
[^34]: E.P. DeBenedictis, J.E. Cook, M.F. Hoemmen, and T.S. Metodi, ''Optimal adiabatic scaling and the processor-in-memory-and-storage architecture (oas :pims),'' in IEEE Proceedings of the International Symposium on Nanoscale Architectures.\hskip 1em plus 0.5em minus 0.4em elax IEEE, July 2015, pp. 69--74. [Online]: http://dx.doi.org/10.1109/NANOARCH.2015.7180589
[^35]: S.Houri, G.Billiot, M.Belleville, A.Valentian, and H.Fanet, ''Limits of cmos technology and interest of nems relays for adiabatic logic applications,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.62, no.6, pp. 1546--1554, June 2015. [Online]: http://dx.doi.org/10.1109/TCSI.2015.2415177
[^36]: S.K. Arfin and R.Sarpeshkar, ''An energy-efficient, adiabatic electrode stimulator with inductive energy recycling and feedback current regulation,'' IEEE Transactions on Biomedical Circuits and Systems, vol.6, no.1, pp. 1--14, February 2012. [Online]: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6036003&isnumber=6138606
[^37]: P.R. Kinget, ''Scaling analog circuits into deep nanoscale cmos: Obstacles and ways to overcome them,'' in IEEE Proceedings of the Custom Integrated Circuits Conference.\hskip 1em plus 0.5em minus 0.4em elax IEEE, September 2015, pp. 1--8. [Online]: http://dx.doi.org/10.1109/CICC.2015.7338394
[^38]: K.Bernstein, D.J. Frank, A.E. Gattiker, W.Haensch, B.L. Ji, S.R. Nassif, E.J. Nowak, D.J. Pearson, and N.J. Rohrer, ''High-performance cmos variability in the 65-nm regime and beyond,'' IBM Journal of Research AND Development, vol.50, no. 4.5, pp. 433--449, July 2006. [Online]: http://dx.doi.org/10.1147/rd.504.0433
[^39]: L.L. Lewyn, T.Ytterdal, C.Wulff, and K.Martin, ''Analog circuit design in nanoscale cmos technologies,'' Proceedings of the IEEE, vol.97, no.10, pp. 1687--1714, October 2009. [Online]: http://dx.doi.org/10.1109/JPROC.2009.2024663
[^40]: Y.Xin, W.X.Y. Li, Z.Zhang, R.C.C. Cheung, D.Song, and T.W. Berger, ''An application specific instruction set processor (asip) for adaptive filters in neural prosthetics,'' IEEE/ACM Transactions on Computational Biology and Bioinformatics, vol.12, no.5, pp. 1034--1047, September 2015. [Online]: http://dx.doi.org/10.1109/TCBB.2015.2440248
[^41]: G.Schalk, P.Brunner, L.A. Gerhardt, H.Bischof, and J.R. Wolpaw, ''Brain-computer interfaces (bcis): detection instead of classification,'' Journal of neuroscience methods, vol. 167, no.1, pp. 51--62, 2008, brain-Computer Interfaces (BCIs). [Online]: http://www.sciencedirect.com/science/article/pii/S0165027007004116
[^42]: Z.Li, J.E. O'Doherty, T.L. Hanson, M.A. Lebedev, C.S. Henriquez, and M.A. Nicolelis, ''Unscented kalman filter for brain-machine interfaces,'' PloS one, vol.4, no.7, pp. 1--18, 2009. [Online]: http://dx.doi.org/10.1371/journal.pone.0006243
[^43]: A.L. Orsborn, H.G. Moorman, S.A. Overduin, M.M. Shanechi, D.F. Dimitrov, and J.M. Carmena, ''Closed-loop decoder adaptation shapes neural plasticity for skillful neuroprosthetic control,'' Neuron, vol.82, pp. 1380 -- 1393, March 2016. [Online]: http://dx.doi.org/10.1016/j.neuron.2014.04.048
[^44]: Y.Yan, X.Qin, Y.Wu, N.Zhang, J.Fan, and L.Wang, ''A restricted boltzmann machine based two-lead electrocardiography classification,'' in IEEE Proceedings of the International Conference on Wearable and Implantable Body Sensor Networks.\hskip 1em plus 0.5em minus 0.4em elax IEEE, June 2015, pp. 1--9. [Online]: http://dx.doi.org/10.1109/BSN.2015.7299399
[^45]: B.M. Yu and J.P. Cunningham, ''Dimensionality reduction for large-scale neural recordings,'' Nature Neuroscience, vol.17, pp. 1500 -- 1509, November 2014. [Online]: http://dx.doi.org/10.1038/nn.3776
[^46]: S.Makeig, C.Kothe, T.Mullen, N.Bigdely-Shamlo, Z.Zhang, and K.Kreutz-Delgado, ''Evolving signal processing for brain: Computer interfaces,'' Proceedings of the IEEE, vol. 100, no. Special Centennial Issue, pp. 1567--1584, May 2012. [Online]: http://dx.doi.org/10.1109/JPROC.2012.2185009
[^47]: G.Indiveri and S.C. Liu, ''Memory and information processing in neuromorphic systems,'' Proceedings of the IEEE, vol. 103, no.8, pp. 1379--1397, August 2015. [Online]: http://dx.doi.org/10.1109/JPROC.2015.2444094
[^48]: Y.Chen, E.Yao, and A.Basu, ''A 128-channel extreme learning machine-based neural decoder for brain machine interfaces,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.3, pp. 679--692, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2483618
[^49]: V.Karkare, S.Gibson, and D.Marković, ''A 75- $\mu$w, 16-channel neural spike-sorting processor with unsupervised clustering,'' IEEE Journal of Solid-State Circuits, vol.48, no.9, pp. 2230--2238, September 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2264616
[^50]: T.C. Chen, W.Liu, and L.G. Chen, ''128-channel spike sorting processor with a parallel-folding structure in 90nm process,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2009, pp. 1253--1256. [Online]: http://dx.doi.org/10.1109/ISCAS.2009.5117990
[^51]: G.Baranauskas, ''What limits the performance of current invasive brain machine interfaces?'' Frontiers in Systems Neuroscience, vol.8, no.68, April 2014. [Online]: http://www.frontiersin.org/systems_neuroscience/10.3389/fnsys.2014.00068
[^52]: E.F. Chang, ''Towards large-scale, human-based, mesoscopic neurotechnologies,'' Neuron, vol.86, pp. 68--78, March 2016. [Online]: http://dx.doi.org/10.1016/j.neuron.2015.03.037
[^53]: M.A.L. Nicolelis and M.A. Lebedev, ''Principles of neural ensemble physiology underlying the operation of brain-machine,'' Nature Reviews Neuroscience, vol.10, pp. 530--540, July 2009. [Online]: http://dx.doi.org/10.1038/nrn2653
[^54]: Z.Fekete, ''Recent advances in silicon-based neural microelectrodes and microsystems: a review,'' Sensors AND Actuators B: Chemical, vol. 215, pp. 300 -- 315, 2015. [Online]: http://www.sciencedirect.com/science/article/pii/S092540051500386X
[^55]: N.Saeidi, M.Schuettler, A.Demosthenous, and N.Donaldson, ''Technology for integrated circuit micropackages for neural interfaces, based on gold–silicon wafer bonding,'' Journal of Micromechanics AND Microengineering, vol.23, no.7, p. 075021, June 2013. [Online]: http://stacks.iop.org/0960-1317/23/i=7/a=075021
[^56]: K.Seidl, S.Herwik, T.Torfs, H.P. Neves, O.Paul, and P.Ruther, ''Cmos-based high-density silicon microprobe arrays for electronic depth control in intracortical neural recording,'' IEEE Journal of Microelectromechanical Systems, vol.20, no.6, pp. 1439--1448, December 2011. [Online]: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6033040&isnumber=6075219
[^57]: T.D.Y. Kozai, N.B. Langhals, P.R. Patel, X.Deng, H.Zhang, K.L. Smith, J.Lahann, N.A. Kotov, and D.R. Kipke, ''Ultrasmall implantable composite microelectrodes with bioactive surfaces for chronic neural interfaces,'' Nature Materials, vol.11, pp. 1065--1073, December 2012. [Online]: http://dx.doi.org/10.1038/nmat3468
[^58]: D.A. Schwarz, M.A. Lebedev, T.L. Hanson, D.F. Dimitrov, G.Lehew, J.Meloy, S.Rajangam, V.Subramanian, P.J. Ifft, Z.Li, A.Ramakrishnan, A.Tate, K.Z. Zhuang, and M.A.L. Nicolelis, ''Chronic, wireless recordings of large-scale brain activity in freely moving rhesus monkeys,'' Nature Methods, vol.11, pp. 670--676, April 2014. [Online]: http://dx.doi.org/10.1038/nmeth.2936
[^59]: P.Ruther, S.Herwik, S.Kisban, K.Seidl, and O.Paul, ''Recent progress in neural probes using silicon mems technology,'' IEEJ Transactions on Electrical and Electronic Engineering, vol.5, no.5, pp. 505--515, 2010. [Online]: http://dx.doi.org/10.1002/tee.20566
[^60]: ibitem3d-printH.-W. Kang, S.J. Lee, I.K. Ko, C.Kengla, J.J. Yoo, and A.Atala, ''A 3d bioprinting system to produce human-scale tissue constructs with structural integrity,'' Nature Biotechnology, vol.34, pp. 312--319, March 2016. [Online]: http://dx.doi.org/10.1038/nbt.3413
[^61]: ibitemdistrib-electC.Xie, J.Liu, T.-M. Fu, X.Dai, W.Zhou, and C.M. Lieber, ''Three-dimensional macroporous nanoelectronic networks as minimally invasive brain probes,'' Nature Materials, vol.14, pp. 1286--1292, May 2015. [Online]: http://dx.doi.org/10.1038/nmat4427
[^62]: R.R. Harrison, P.T. Watkins, R.J. Kier, R.O. Lovejoy, D.J. Black, B.Greger, and F.Solzbacher, ''A low-power integrated circuit for a wireless 100-electrode neural recording system,'' IEEE Journal of Solid-State Circuits, vol.42, no.1, pp. 123--133, Jan 2007. [Online]: http://dx.doi.org/10.1109/JSSC.2006.886567
[^63]: J.Guo, W.Ng, J.Yuan, S.Li, and M.Chan, ''A 200-channel area-power-efficient chemical and electrical dual-mode acquisition ic for the study of neurodegenerative diseases,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.3, pp. 567--578, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2468052
[^64]: W.Biederman, D.J. Yeager, N.Narevsky, J.Leverett, R.Neely, J.M. Carmena, E.Alon, and J.M. Rabaey, ''A 4.78 mm 2 fully-integrated neuromodulation soc combining 64 acquisition channels with digital compression and simultaneous dual stimulation,'' IEEE Journal of Solid-State Circuits, vol.50, no.4, pp. 1038--1047, April 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2384736
[^65]: R.Muller, S.Gambini, and J.M. Rabaey, ''A 0.013mm$^2$, $5 \mu w$, dc-coupled neural signal acquisition ic with 0.5v supply,'' IEEE Journal of Solid-State Circuits, vol.47, no.1, pp. 232--243, Jan 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2163552
[^66]: H.Kassiri, A.Bagheri, N.Soltani, K.Abdelhalim, H.M. Jafari, M.T. Salam, J.L.P. Velazquez, and R.Genov, ''Battery-less tri-band-radio neuro-monitor and responsive neurostimulator for diagnostics and treatment of neurological disorders,'' IEEE Journal of Solid-State Circuits, vol.51, no.5, pp. 1274--1289, May 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2528999
[^67]: M.Ballini, J.Müller, P.Livi, Y.Chen, U.Frey, A.Stettler, A.Shadmani, V.Viswam, I.L. Jones, D.Jäckel, M.Radivojevic, M.K. Lewandowska, W.Gong, M.Fiscella, D.J. Bakkum, F.Heer, and A.Hierlemann, ''A 1024-channel cmos microelectrode array with 26,400 electrodes for recording and stimulation of electrogenic cells in vitro,'' IEEE Journal of Solid-State Circuits, vol.49, no.11, pp. 2705--2719, Nov 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2359219
[^68]: P.D. Wolf, Thermal considerations for the design of an implanted cortical brain--machine interface (BMI).\hskip 1em plus 0.5em minus 0.4em elax CRC Press Boca Raton, FL, 2008, pMID: 21204402. [Online]: http://www.ncbi.nlm.nih.gov/books/NBK3932
[^69]: T.Denison, K.Consoer, W.Santa, A.T. Avestruz, J.Cooley, and A.Kelly, ''A 2 $\mu$w 100 nv/rthz chopper-stabilized instrumentation amplifier for chronic measurement of neural field potentials,'' IEEE Journal of Solid-State Circuits, vol.42, no.12, pp. 2934--2945, December 2007. [Online]: http://dx.doi.org/10.1109/JSSC.2007.908664
[^70]: B.Johnson, S.T. Peace, A.Wang, T.A. Cleland, and A.Molnar, ''A 768-channel cmos microelectrode array with angle sensitive pixels for neuronal recording,'' IEEE Sensors Journal, vol.13, no.9, pp. 3211--3218, Sept 2013. [Online]: http://dx.doi.org/10.1109/JSEN.2013.2266894
[^71]: C.M. Lopez, A.Andrei, S.Mitra, M.Welkenhuysen, W.Eberle, C.Bartic, R.Puers, R.F. Yazicioglu, and G.G.E. Gielen, ''An implantable 455-active-electrode 52-channel cmos neural probe,'' IEEE Journal of Solid-State Circuits, vol.49, no.1, pp. 248--261, January 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2284347
[^72]: J.Scholvin, J.P. Kinney, J.G. Bernstein, C.Moore-Kochlacs, N.Kopell, C.G. Fonstad, and E.S. Boyden, ''Close-packed silicon microelectrodes for scalable spatially oversampled neural recording,'' IEEE Transactions on Biomedical Engineering, vol.63, no.1, pp. 120--130, Jan 2016. [Online]: http://dx.doi.org/10.1109/TBME.2015.2406113
[^73]: M.Han, B.Kim, Y.A. Chen, H.Lee, S.H. Park, E.Cheong, J.Hong, G.Han, and Y.Chae, ''Bulk switching instrumentation amplifier for a high-impedance source in neural signal recording,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.62, no.2, pp. 194--198, Feb 2015. [Online]: http://dx.doi.org/10.1109/TCSII.2014.2368615
[^74]: R.Muller, S.Gambini, and J.M. Rabaey, ''A 0.013$ $mm$^2$, 5$ \mu$w, dc-coupled neural signal acquisition ic with 0.5 v supply,'' IEEE Journal of Solid-State Circuits, vol.47, no.1, pp. 232--243, Jan 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2163552
[^75]: ''Rhd2164 digital electrophysiology interface chip - data sheet,'' Intan Technologies, Los Angeles, California, December 2013. [Online]: http://www.intantech.com/files/Intan_RHD2164_datasheet.pdf
[^76]: K.M. Al-Ashmouny, S.I. Chang, and E.Yoon, ''A 4 $\mu$w/ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-d neural microsystems,'' IEEE Transactions on Biomedical Circuits and Systems, vol.6, no.5, pp. 403--413, October 2012. [Online]: http://dx.doi.org/10.1109/TBCAS.2012.2218105
[^77]: D.Han, Y.Zheng, R.Rajkumar, G.S. Dawe, and M.Je, ''A 0.45 v 100-channel neural-recording ic with sub-$\mu$w/channel consumption in 0.18$\mu$m cmos,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.6, pp. 735--746, December 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2014.2298860
[^78]: S.B. Lee, H.M. Lee, M.Kiani, U.M. Jow, and M.Ghovanloo, ''An inductively powered scalable 32-channel wireless neural recording system-on-a-chip for neuroscience applications,'' IEEE Transactions on Biomedical Circuits and Systems, vol.4, no.6, pp. 360--371, Dec 2010. [Online]: http://dx.doi.org/10.1109/TBCAS.2010.2078814
[^79]: J.Yoo, L.Yan, D.El-Damak, M.A.B. Altaf, A.H. Shoeb, and A.P. Chandrakasan, ''An 8-channel scalable eeg acquisition soc with patient-specific seizure classification and recording processor,'' IEEE Journal of Solid-State Circuits, vol.48, no.1, pp. 214--228, Jan 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2221220
[^80]: M.A.B. Altaf and J.Yoo, ''A 1.83$ \mu$j/classification, 8-channel, patient-specific epileptic seizure classification soc using a non-linear support vector machine,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.1, pp. 49--60, Feb 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2014.2386891
[^81]: K.Abdelhalim, H.M. Jafari, L.Kokarovtseva, J.L.P. Velazquez, and R.Genov, ''64-channel uwb wireless neural vector analyzer soc with a closed-loop phase synchrony-triggered neurostimulator,'' IEEE Journal of Solid-State Circuits, vol.48, no.10, pp. 2494--2510, Oct 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2272952
[^82]: A.Bagheri, S.R.I. Gabran, M.T. Salam, J.L.P. Velazquez, R.R. Mansour, M.M.A. Salama, and R.Genov, ''Massively-parallel neuromonitoring and neurostimulation rodent headset with nanotextured flexible microelectrodes,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.5, pp. 601--609, Oct 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2281772
[^83]: H.G. Rhew, J.Jeong, J.A. Fredenburg, S.Dodani, P.G. Patil, and M.P. Flynn, ''A fully self-contained logarithmic closed-loop deep brain stimulation soc with wireless telemetry and wireless power management,'' IEEE Journal of Solid-State Circuits, vol.49, no.10, pp. 2213--2227, Oct 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2346779
[^84]: W.Biederman, D.J. Yeager, N.Narevsky, J.Leverett, R.Neely, J.M. Carmena, E.Alon, and J.M. Rabaey, ''A 4.78 mm 2 fully-integrated neuromodulation soc combining 64 acquisition channels with digital compression and simultaneous dual stimulation,'' IEEE Journal of Solid-State Circuits, vol.50, no.4, pp. 1038--1047, April 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2384736
[^85]: A.Mendez, A.Belghith, and M.Sawan, ''A dsp for sensing the bladder volume through afferent neural pathways,'' IEEE Transactions on Biomedical Circuits and Systems, vol.8, no.4, pp. 552--564, Aug 2014. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2282087
[^86]: T.T. Liu and J.M. Rabaey, ''A 0.25 v 460 nw asynchronous neural signal processor with inherent leakage suppression,'' IEEE Journal of Solid-State Circuits, vol.48, no.4, pp. 897--906, April 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2239096
[^87]: D.Han, Y.Zheng, R.Rajkumar, G.S. Dawe, and M.Je, ''A 0.45 v 100-channel neural-recording ic with sub-$\mu$w/channel consumption in 0.18$ \mu$m cmos,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.6, pp. 735--746, Dec 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2014.2298860
[^88]: R.Muller, H.P. Le, W.Li, P.Ledochowitsch, S.Gambini, T.Bjorninen, A.Koralek, J.M. Carmena, M.M. Maharbiz, E.Alon, and J.M. Rabaey, ''A minimally invasive 64-channel wireless $\mu$ecog implant,'' IEEE Journal of Solid-State Circuits, vol.50, no.1, pp. 344--359, Jan 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2364824
[^89]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational amplifiers and their application to continuous-time filters in nanoscale cmos,'' IEEE Journal of Solid-State Circuits, vol.49, no.12, pp. 2758--2772, December 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2354641
[^90]: V.Karkare, H.Chandrakumar, D.Rozgić, and D.Marković, ''Robust, reconfigurable, and power-efficient biosignal recording systems,'' in IEEE Proceedings of the Custom Integrated Circuits Conference, Sept 2014, pp. 1--8. [Online]: http://dx.doi.org/10.1109/CICC.2014.6946018
[^91]: L.B. Leene and T.G. Constandinou, ''A 0.45v continuous time-domain filter using asynchronous oscillator structures,'' in IEEE Proceedings of the International Conference on Electronics, Circuits and Systems, December 2016.
[^92]: R.Mohan, L.Yan, G.Gielen, C.V. Hoof, and R.F. Yazicioglu, ''0.35 v time-domain-based instrumentation amplifier,'' Electronics Letters, vol.50, no.21, pp. 1513--1514, October 2014. [Online]: http://dx.doi.org/10.1049/el.2014.2471
[^93]: X.Zhang, Z.Zhang, Y.Li, C.Liu, Y.X. Guo, and Y.Lian, ''A 2.89$ \mu$w dry-electrode enabled clockless wireless ecg soc for wearable applications,'' IEEE Journal of Solid-State Circuits, vol.51, no.10, pp. 2287--2298, Oct 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2582863
[^94]: M.Elia, L.B. Leene, and T.G. Constandinou, ''Continuous-time micropower interface for neural recording applications,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2016, pp. 534--537. [Online]: http://dx.doi.org/10.1109/ISCAS.2016.7527295
[^95]: N.Guo, Y.Huang, T.Mai, S.Patil, C.Cao, M.Seok, S.Sethumadhavan, and Y.Tsividis, ''Energy-efficient hybrid analog/digital approximate computation in continuous time,'' IEEE Journal of Solid-State Circuits, vol.51, no.7, pp. 1514--1524, July 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2543729
[^96]: B.Bozorgzadeh, D.R. Schuweiler, M.J. Bobak, P.A. Garris, and P.Mohseni, ''Neurochemostat: A neural interface soc with integrated chemometrics for closed-loop regulation of brain dopamine,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.3, pp. 654--667, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2453791
[^97]: E.B. Myers and M.L. Roukes, ''Comparative advantages of mechanical biosensors,'' Nature nanotechnology, vol.6, no.4, pp. 1748--3387, April 2011. [Online]: http://dx.doi.org/10.1038/nnano.2011.44
[^98]: R.Machado, N.Soltani, S.Dufour, M.T. Salam, P.L. Carlen, R.Genov, and M.Thompson, ''Biofouling-resistant impedimetric sensor for array high-resolution extracellular potassium monitoring in the brain,'' Biosensors, vol.6, no.4, p.53, October 2016. [Online]: http://dx.doi.org/10.3390/bios6040053
[^99]: J.Guo, W.Ng, J.Yuan, S.Li, and M.Chan, ''A 200-channel area-power-efficient chemical and electrical dual-mode acquisition ic for the study of neurodegenerative diseases,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.3, pp. 567--578, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2468052
[^100]: D.A. Dombeck, A.N. Khabbaz, F.Collman, T.L. Adelman, and D.W. Tank, ''Imaging large-scale neural activity with cellular resolution in awake, mobile mice.'' Neuron, vol.56, no.1, pp. 43--57, October 2007. [Online]: http://dx.doi.org/10.1016/j.neuron.2007.08.003
[^101]: T.York, S.B. Powell, S.Gao, L.Kahan, T.Charanya, D.Saha, N.W. Roberts, T.W. Cronin, J.Marshall, S.Achilefu, S.P. Lake, B.Raman, and V.Gruev, ''Bioinspired polarization imaging sensors: From circuits and optics to signal processing algorithms and biomedical applications,'' Proceedings of the IEEE, vol. 102, no.10, pp. 1450--1469, Oct 2014. [Online]: http://dx.doi.org/10.1109/JPROC.2014.2342537
[^102]: K.Paralikar, P.Cong, O.Yizhar, L.E. Fenno, W.Santa, C.Nielsen, D.Dinsmoor, B.Hocken, G.O. Munns, J.Giftakis, K.Deisseroth, and T.Denison, ''An implantable optical stimulation delivery system for actuating an excitable biosubstrate,'' IEEE Journal of Solid-State Circuits, vol.46, no.1, pp. 321--332, Jan 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2010.2074110
[^103]: N.Ji and S.L. Smith, ''Technologies for imaging neural activity in large volumes,'' Nature Neuroscience, vol.19, pp. 1154--1164, September 2016. [Online]: http://dx.doi.org/10.1038/nn.4358
[^104]: S.Song, K.D. Miller, and L.F. Abbott, ''Competitive hebbian learning through spike-timing-dependent synaptic plasticity,'' Nature Neuroscience, vol.3, pp. 919--926, September 2000. [Online]: http://dx.doi.org/10.1038/78829
[^105]: T.Kurafuji, M.Haraguchi, M.Nakajima, T.Nishijima, T.Tanizaki, H.Yamasaki, T.Sugimura, Y.Imai, M.Ishizaki, T.Kumaki, K.Murata, K.Yoshida, E.Shimomura, H.Noda, Y.Okuno, S.Kamijo, T.Koide, H.J. Mattausch, and K.Arimoto, ''A scalable massively parallel processor for real-time image processing,'' IEEE Journal of Solid-State Circuits, vol.46, no.10, pp. 2363--2373, October 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2159528
[^106]: J.Y. Kim, M.Kim, S.Lee, J.Oh, K.Kim, and H.J. Yoo, ''A 201.4 gops 496 mw real-time multi-object recognition processor with bio-inspired neural perception engine,'' IEEE Journal of Solid-State Circuits, vol.45, no.1, pp. 32--45, Jan 2010. [Online]: http://dx.doi.org/10.1109/JSSC.2009.2031768
[^107]: C.C. Cheng, C.H. Lin, C.T. Li, and L.G. Chen, ''ivisual: An intelligent visual sensor soc with 2790 fps cmos image sensor and 205 gops/w vision processor,'' IEEE Journal of Solid-State Circuits, vol.44, no.1, pp. 127--135, Jan 2009. [Online]: http://dx.doi.org/10.1109/JSSC.2008.2007158
[^108]: H.Noda, M.Nakajima, K.Dosaka, K.Nakata, M.Higashida, O.Yamamoto, K.Mizumoto, T.Tanizaki, T.Gyohten, Y.Okuno, H.Kondo, Y.Shimazu, K.Arimoto, K.Saito, and T.Shimizu, ''The design and implementation of the massively parallel processor based on the matrix architecture,'' IEEE Journal of Solid-State Circuits, vol.42, no.1, pp. 183--192, Jan 2007. [Online]: http://dx.doi.org/10.1109/JSSC.2006.886545
[^109]: M.S. Chae, W.Liu, and M.Sivaprakasam, ''Design optimization for integrated neural recording systems,'' IEEE Journal of Solid-State Circuits, vol.43, no.9, pp. 1931--1939, September 2008. [Online]: http://dx.doi.org/10.1109/JSSC.2008.2001877
[^110]: K.J. Miller, L.B. Sorensen, J.G. Ojemann, and M.den Nijs, ''Power-law scaling in the brain surface electric potential,'' PLoS Comput Biol, vol.5, no.12, pp. 1--10, 12 2009. [Online]: http://dx.doi.org/10.1371%2Fjournal.pcbi.1000609
[^111]: R.Harrison and C.Charles, ''A low-power low-noise cmos amplifier for neural recording applications,'' IEEE Journal of Solid-State Circuits, vol.38, no.6, pp. 958--965, June 2003. [Online]: http://dx.doi.org/10.1109/JSSC.2003.811979
[^112]: W.Sansen, ''1.3 analog cmos from 5 micrometer to 5 nanometer,'' in IEEE Proceedings of the International Solid-State Circuits Conference.\hskip 1em plus 0.5em minus 0.4em elax IEEE, February 2015, pp. 1--6. [Online]: http://dx.doi.org/10.1109/ISSCC.2015.7062848
[^113]: M.S.J. Steyaert and W.M.C. Sansen, ''A micropower low-noise monolithic instrumentation amplifier for medical purposes,'' IEEE Journal of Solid-State Circuits, vol.22, no.6, pp. 1163--1168, December 1987. [Online]: http://dx.doi.org/10.1109/JSSC.1987.1052869
[^114]: W.Wattanapanitch, M.Fee, and R.Sarpeshkar, ''An energy-efficient micropower neural recording amplifier,'' IEEE Transactions on Biomedical Circuits and Systems, vol.1, no.2, pp. 136--147, June 2007. [Online]: http://dx.doi.org/10.1109/TBCAS.2007.907868
[^115]: B.Johnson and A.Molnar, ''An orthogonal current-reuse amplifier for multi-channel sensing,'' IEEE Journal of Solid-State Circuits, vol.48, no.6, pp. 1487--1496, June 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2257478
[^116]: C.Qian, J.Parramon, and E.Sanchez-Sinencio, ''A micropower low-noise neural recording front-end circuit for epileptic seizure detection,'' IEEE Journal of Solid-State Circuits, vol.46, no.6, pp. 1392--1405, June 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2126370
[^117]: X.Zou, L.Liu, J.H. Cheong, L.Yao, P.Li, M.-Y. Cheng, W.L. Goh, R.Rajkumar, G.Dawe, K.-W. Cheng, and M.Je, ''A 100-channel 1-mw implantable neural recording ic,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.60, no.10, pp. 2584--2596, October 2013. [Online]: http://dx.doi.org/10.1109/TCSI.2013.2249175
[^118]: V.Majidzadeh, A.Schmid, and Y.Leblebici, ''Energy efficient low-noise neural recording amplifier with enhanced noise efficiency factor,'' IEEE Transactions on Biomedical Circuits and Systems, vol.5, no.3, pp. 262--271, June 2011. [Online]: http://dx.doi.org/10.1109/TBCAS.2010.2078815
[^119]: ibitemQ-basedC.C. Enz and E.A. Vittoz, Charge-based MOS transistor modeling: the EKV model for low-power AND RF IC design.\hskip 1em plus 0.5em minus 0.4em elax John Wiley & Sons, August 2006. [Online]: http://eu.wiley.com/WileyCDA/WileyTitle/productCd-0470855452.html
[^120]: Y.Yasuda, T.-J.K. Liu, and C.Hu, ''Flicker-noise impact on scaling of mixed-signal cmos with hfsion,'' IEEE Transactions on Electron Devices, vol.55, no.1, pp. 417--422, January 2008. [Online]: http://dx.doi.org/10.1109/TED.2007.910759
[^121]: S.-Y. Wu, C.Lin, M.Chiang, J.Liaw, J.Cheng, S.Yang, M.Liang, T.Miyashita, C.Tsai, B.Hsu, H.Chen, T.Yamamoto, S.Chang, V.Chang, C.Chang, J.Chen, H.Chen, K.Ting, Y.Wu, K.Pan, R.Tsui, C.Yao, P.Chang, H.Lien, T.Lee, H.Lee, W.Chang, T.Chang, R.Chen, M.Yeh, C.Chen, Y.Chiu, Y.Chen, H.Huang, Y.Lu, C.Chang, M.Tsai, C.Liu, K.Chen, C.Kuo, H.Lin, S.Jang, and Y.Ku, ''A 16nm finfet cmos technology for mobile soc and computing applications,'' in IEEE Proceedings of the International Electron Devices Meeting, December 2013, pp. 9.1.1--9.1.4. [Online]: http://dx.doi.org/10.1109/IEDM.2013.6724591
[^122]: L.B. Leene, Y.Liu, and T.G. Constandinou, ''A compact recording array for neural interfaces,'' in IEEE Proceedings of the Biomedical Circuits and Systems Conference, October 2013, pp. 97--100. [Online]: http://dx.doi.org/10.1109/BioCAS.2013.6679648
[^123]: Q.Fan, F.Sebastiano, J.Huijsing, and K.Makinwa, ''A $1.8 \mu w\:60 nv/√Hz$ capacitively-coupled chopper instrumentation amplifier in 65 nm cmos for wireless sensor nodes,'' IEEE Journal of Solid-State Circuits, vol.46, no.7, pp. 1534--1543, July 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2143610
[^124]: H.Chandrakumar and D.Markovic, ''A simple area-efficient ripple-rejection technique for chopped biosignal amplifiers,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.62, no.2, pp. 189--193, February 2015. [Online]: http://dx.doi.org/10.1109/TCSII.2014.2387686
[^125]: H.Chandrakumar and D.Markovic, ''A 2$\mu$w 40mvpp linear-input-range chopper-stabilized bio-signal amplifier with boosted input impedance of 300mohm and electrode-offset filtering,'' in IEEE Proceedings of the International Solid-State Circuits Conference.\hskip 1em plus 0.5em minus 0.4em elax IEEE, January 2016, pp. 96--97. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7417924
[^126]: H.Rezaee-Dehsorkh, N.Ravanshad, R.Lotfi, K.Mafinezhad, and A.M. Sodagar, ''Analysis and design of tunable amplifiers for implantable neural recording applications,'' IEEE Transactions on Emerging and Selected Topics in Circuits and Systems, vol.1, no.4, pp. 546--556, December 2011. [Online]: http://dx.doi.org/10.1109/JETCAS.2011.2174492
[^127]: X.Zou, X.Xu, L.Yao, and Y.Lian, ''A 1-v 450-nw fully integrated programmable biomedical sensor interface chip,'' IEEE Journal of Solid-State Circuits, vol.44, no.4, pp. 1067--1077, April 2009. [Online]: http://dx.doi.org/10.1109/JSSC.2009.2014707
[^128]: L.Leene and T.Constandinou, ''Ultra-low power design strategy for two-stage amplifier topologies,'' Electronics Letters, vol.50, no.8, pp. 583--585, April 2014. [Online]: http://dx.doi.org/10.1049/el.2013.4196
[^129]: H.G. Rey, C.Pedreira, and R.Q. Quiroga, ''Past, present and future of spike sorting techniques,'' Brain Research Bulletin, vol. 119, Part B, pp. 106--117, October 2015, advances in electrophysiological data analysis. [Online]: http://www.sciencedirect.com/science/article/pii/S0361923015000684
[^130]: Y.Chen, A.Basu, L.Liu, X.Zou, R.Rajkumar, G.S. Dawe, and M.Je, ''A digitally assisted, signal folding neural recording amplifier,'' IEEE Transactions on Biomedical Circuits and Systems, vol.8, no.4, pp. 528--542, August 2014. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2288680
[^131]: X.Yue, ''Determining the reliable minimum unit capacitance for the dac capacitor array of sar adcs,'' Microelectronics Journal, vol.44, no.6, pp. 473 -- 478, 2013. [Online]: http://www.sciencedirect.com/science/article/pii/S0026269213000815
[^132]: Y.Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, S.-P. U, R.Martins, and F.Maloberti, ''Split-sar adcs: Improved linearity with power and speed optimization,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.22, no.2, pp. 372--383, February 2014. [Online]: http://dx.doi.org/10.1109/TVLSI.2013.2242501
[^133]: L.Xie, G.Wen, J.Liu, and Y.Wang, ''Energy-efficient hybrid capacitor switching scheme for sar adc,'' Electronics Letters, vol.50, no.1, pp. 22--23, January 2014. [Online]: http://dx.doi.org/10.1049/el.2013.2794
[^134]: P.Nuzzo, F.DeBernardinis, P.Terreni, and G.Vander Plas, ''Noise analysis of regenerative comparators for reconfigurable adc architectures,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.55, no.6, pp. 1441--1454, July 2008. [Online]: http://dx.doi.org/10.1109/TCSI.2008.917991
[^135]: G.Heinzel, A.R\"udiger, and R.Schilling, ''Spectrum and spectral density estimation by the discrete fourier transform (dft), including a comprehensive list of window functions and some new at-top windows,'' pp. 25--27, February 2002. [Online]: http://hdl.handle.net/11858/00-001M-0000-0013-557A-5
[^136]: F.Gerfers, M.Ortmanns, and Y.Manoli, ''A 1.5-v 12-bit power-efficient continuous-time third-order sigma; delta; modulator,'' IEEE Journal of Solid-State Circuits, vol.38, no.8, pp. 1343--1352, Aug 2003. [Online]: http://dx.doi.org/10.1109/JSSC.2003.814432
[^137]: Y.Chae, K.Souri, and K.A.A. Makinwa, ''A 6.3$ \mu$w 20$ $bit incremental zoom-adc with 6 ppm inl and 1 $\mu$v offset,'' IEEE Journal of Solid-State Circuits, vol.48, no.12, pp. 3019--3027, Dec 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2278737
[^138]: Y.S. Shu, L.T. Kuo, and T.Y. Lo, ''An oversampling sar adc with dac mismatch error shaping achieving 105db sfdr and 101db sndr over 1khz bw in 55nm cmos,'' in IEEE Proceedings of the International Solid-State Circuits Conference, January 2016, pp. 458--459. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7418105
[^139]: P.Harpe, E.Cantatore, and A.van Roermund, ''An oversampled 12/14b sar adc with noise reduction and linearity enhancements achieving up to 79.1db sndr,'' in IEEE Proceedings of the International Solid-State Circuits Conference, February 2014, pp. 194--195. [Online]: http://dx.doi.org/10.1109/ISSCC.2014.6757396
[^140]: ibitemchrch-turingM.Braverman, J.Schneider, and C.Rojas, ''Space-bounded church-turing thesis and computational tractability of closed systems,'' Physical Review Letters, vol. 115, August 2015. [Online]: http://link.aps.org/doi/10.1103/PhysRevLett.115.098701
[^141]: M.Verhelst and A.Bahai, ''Where analog meets digital: Analog-to-information conversion and beyond,'' IEEE Solid-State Circuits Magazine, vol.7, no.3, pp. 67--80, September 2015. [Online]: http://dx.doi.org/10.1109/MSSC.2015.2442394
[^142]: H.A. Marblestone, M.B. Zamft, G.Y. Maguire, G.M. Shapiro, R.T. Cybulski, I.J. Glaser, D.Amodei, P.B. Stranges, R.Kalhor, A.D. Dalrymple, D.Seo, E.Alon, M.M. Maharbiz, M.J. Carmena, M.J. Rabaey, S.E. Boyden, M.G. Church, and P.K. Kording, ''Physical principles for scalable neural recording,'' Frontiers in Computational Neuroscience, vol.7, no. 137, 2013. [Online]: http://www.frontiersin.org/computational_neuroscience/10.3389/fncom.2013.00137
[^143]: L.Traver, C.Tarin, P.Marti, and N.Cardona, ''Adaptive-threshold neural spike by noise-envelope tracking,'' Electronics Letters, vol.43, no.24, pp. 1333--1335, November 2007. [Online]: http://dx.doi.org/10.1049/el:20071631
[^144]: I.Obeid and P.Wolf, ''Evaluation of spike-detection algorithms fora brain-machine interface application,'' IEEE Transactions on Biomedical Engineering, vol.51, no.6, pp. 905--911, June 2004. [Online]: http://dx.doi.org/10.1109/TBME.2004.826683
[^145]: P.Watkins, G.Santhanam, K.Shenoy, and R.Harrison, ''Validation of adaptive threshold spike detector for neural recording,'' in IEEE Proceedings of the International Conference on Engineering in Medicine and Biology Society, vol.2, September 2004, pp. 4079--4082. [Online]: http://dx.doi.org/10.1109/IEMBS.2004.1404138
[^146]: T.Takekawa, Y.Isomura, and T.Fukai, ''Accurate spike sorting for multi-unit recordings,'' European Journal of Neuroscience, vol.31, no.2, pp. 263--272, 2010. [Online]: http://dx.doi.org/10.1111/j.1460-9568.2009.07068.x
[^147]: A.Zviagintsev, Y.Perelman, and R.Ginosar, ''Low-power architectures for spike sorting,'' in IEEE Proceedings of the International Conference on Neural Engineering, March 2005, pp. 162--165. [Online]: http://dx.doi.org/10.1109/CNE.2005.1419579
[^148]: A.Rodriguez-Perez, J.Ruiz-Amaya, M.Delgado-Restituto, and A.Rodriguez-Vazquez, ''A low-power programmable neural spike detection channel with embedded calibration and data compression,'' IEEE Transactions on Biomedical Circuits and Systems, vol.6, no.2, pp. 87--100, April 2012. [Online]: http://dx.doi.org/10.1109/TBCAS.2012.2187352
[^149]: U.Rutishauser, E.M. Schuman, and A.N. Mamelak, ''Online detection and sorting of extracellularly recorded action potentials in human medial temporal lobe recordings, in vivo,'' Journal of Neuroscience Methods, vol. 154, no. 1–2, pp. 204 -- 224, 2006. [Online]: http://www.sciencedirect.com/science/article/pii/S0165027006000033
[^150]: F.Franke, M.Natora, C.Boucsein, M.Munk, and K.Obermayer, ''\BIBforeignlanguageEnglishAn online spike detection and spike classification algorithm capable of instantaneous resolution of overlapping spikes,'' \BIBforeignlanguageEnglishJournal of Computational Neuroscience, vol.29, no. 1-2, pp. 127--148, 2010. [Online]: http://dx.doi.org/10.1007/s10827-009-0163-5
[^151]: M.S. Chae, Z.Yang, M.Yuce, L.Hoang, and W.Liu, ''A 128-channel 6 mw wireless neural recording ic with spike feature extraction and uwb transmitter,'' IEEE Transactions on Neural Systems and Rehabilitation Engineering, vol.17, no.4, pp. 312--321, August 2009. [Online]: http://dx.doi.org/10.1109/TNSRE.2009.2021607
[^152]: P.H. Thakur, H.Lu, S.S. Hsiao, and K.O. Johnson, ''Automated optimal detection and classification of neural action potentials in extra-cellular recordings,'' Journal of Neuroscience Methods, vol. 162, no. 1–2, pp. 364 -- 376, 2007. [Online]: ttp://www.sciencedirect.com/science/article/pii/S0165027007000477
[^153]: J.Zhang, Y.Suo, S.Mitra, S.Chin, S.Hsiao, R.Yazicioglu, T.Tran, and R.Etienne-Cummings, ''An efficient and compact compressed sensing microsystem for implantable neural recordings,'' IEEE Transactions on Biomedical Circuits and Systems, vol.8, no.4, pp. 485--496, August 2014. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2284254
[^154]: Y.Suo, J.Zhang, T.Xiong, P.S. Chin, R.Etienne-Cummings, and T.D. Tran, ''Energy-efficient multi-mode compressed sensing system for implantable neural recordings,'' IEEE Transactions on Biomedical Circuits and Systems, vol.8, no.5, pp. 648--659, October 2014. [Online]: http://dx.doi.org/10.1109/TBCAS.2014.2359180
[^155]: B.Yu, T.Mak, X.Li, F.Xia, A.Yakovlev, Y.Sun, and C.S. Poon, ''Real-time fpga-based multichannel spike sorting using hebbian eigenfilters,'' IEEE Transactions on Emerging and Selected Topics in Circuits and Systems, vol.1, no.4, pp. 502--515, December 2011. [Online]: http://dx.doi.org/10.1109/JETCAS.2012.2183430
[^156]: V.Ventura, ''Automatic spike sorting using tuning information,'' Neural computation, vol.21, no.9, pp. 2466--2501, September 2009. [Online]: http://www.ncbi.nlm.nih.gov/pmc/articles/PMC4167425/
[^157]: D.Y. Barsakcioglu, A.Eftekhar, and T.G. Constandinou, ''Design optimisation of front-end neural interfaces for spike sorting systems,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2013, pp. 2501--2504. [Online]: http://dx.doi.org/10.1109/ISCAS.2013.6572387
[^158]: A.M. Sodagar, K.D. Wise, and K.Najafi, ''A fully integrated mixed-signal neural processor for implantable multichannel cortical recording,'' IEEE Transactions on Biomedical Engineering, vol.54, no.6, pp. 1075--1088, June 2007. [Online]: http://dx.doi.org/10.1109/TBME.2007.894986
[^159]: Y.Xin, W.X. Li, R.C. Cheung, R.H. Chan, H.Yan, D.Song, and T.W. Berger, ''An fpga based scalable architecture of a stochastic state point process filter (ssppf) to track the nonlinear dynamics underlying neural spiking,'' Microelectronics Journal, vol.45, no.6, pp. 690 -- 701, June 2014. [Online]: http://www.sciencedirect.com/science/article/pii/S0026269214000913
[^160]: C.Qian, J.Shi, J.Parramon, and E.Sánchez-Sinencio, ''A low-power configurable neural recording system for epileptic seizure detection,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.4, pp. 499--512, August 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2012.2228857
[^161]: K.C. Chun, P.Jain, J.H. Lee, and C.H. Kim, ''A 3t gain cell embedded dram utilizing preferential boosting for high density and low power on-die caches,'' IEEE Journal of Solid-State Circuits, vol.46, no.6, pp. 1495--1505, June 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2128150
[^162]: R.E. Matick and S.E. Schuster, ''Logic-based edram: Origins and rationale for use,'' IBM Journal of Research AND Development, vol.49, no.1, pp. 145--165, January 2005. [Online]: http://dx.doi.org/10.1147/rd.491.0145
[^163]: R.Nair, ''Evolution of memory architecture,'' Proceedings of the IEEE, vol. 103, no.8, pp. 1331--1345, August 2015. [Online]: http://dx.doi.org/10.1109/JPROC.2015.2435018
[^164]: C.E. Molnar and I.W. Jones, ''Simple circuits that work for complicated reasons,'' in IEEE Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2000, pp. 138--149. [Online]: http://dx.doi.org/10.1109/ASYNC.2000.836995
[^165]: ibitemBN-formH.Schorr, ''Computer-aided digital system design and analysis using a register transfer language,'' IEEE Transactions on Electronic Computers, vol. EC-13, no.6, pp. 730--737, December 1964. [Online]: http://dx.doi.org/10.1109/PGEC.1964.263907
[^166]: D.Wang, A.Rajendiran, S.Ananthanarayanan, H.Patel, M.Tripunitara, and S.Garg, ''Reliable computing with ultra-reduced instruction set coprocessors,'' IEEE Micro, vol.34, no.6, pp. 86--94, November 2014. [Online]: http://dx.doi.org/10.1109/MM.2013.130
[^167]: ''Msp430g2x53 mixed signal microcontroller - data sheet,'' Texas Instruments Incorporated, Dallas, Texas, pp. 403--413, May 2013. [Online]: http://www.ti.com/lit/ds/symlink/msp430g2553.pdf
[^168]: F.L. Yuan, C.C. Wang, T.H. Yu, and D.Marković, ''A multi-granularity fpga with hierarchical interconnects for efficient and flexible mobile computing,'' IEEE Journal of Solid-State Circuits, vol.50, no.1, pp. 137--149, January 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2372034
[^169]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational amplifiers and their application to continuous-time filters in nanoscale cmos,'' IEEE Journal of Solid-State Circuits, vol.49, no.12, pp. 2758--2772, December 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2354641
[^170]: Y.Tsividis, ''Event-driven data acquisition and continuous-time digital signal processing,'' in IEEE Proceedings of the Custom Integrated Circuits Conference, September 2010, pp. 1--8. [Online]: http://dx.doi.org/10.1109/CICC.2010.5617618
[^171]: I.Lee, D.Sylvester, and D.Blaauw, ''A constant energy-per-cycle ring oscillator over a wide frequency range for wireless sensor nodes,'' IEEE Journal of Solid-State Circuits, vol.51, no.3, pp. 697--711, March 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2517133
[^172]: B.Drost, M.Talegaonkar, and P.K. Hanumolu, ''Analog filter design using ring oscillator integrators,'' IEEE Journal of Solid-State Circuits, vol.47, no.12, pp. 3120--3129, December 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2225738
[^173]: V.Unnikrishnan and M.Vesterbacka, ''Time-mode analog-to-digital conversion using standard cells,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.61, no.12, pp. 3348--3357, December 2014. [Online]: http://dx.doi.org/10.1109/TCSI.2014.2340551
[^174]: K.Yang, D.Blaauw, and D.Sylvester, ''An all-digital edge racing true random number generator robust against pvt variations,'' IEEE Journal of Solid-State Circuits, vol.51, no.4, pp. 1022--1031, April 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2519383
[^175]: ibitem0.5V-CircuitS.Chatterjee, Y.Tsividis, and P.Kinget, ''0.5-v analog circuit techniques and their application in ota and filter design,'' IEEE Journal of Solid-State Circuits, vol.40, no.12, pp. 2373--2387, December 2005. [Online]: http://dx.doi.org/10.1109/JSSC.2005.856280
[^176]: M.Alioto, ''Understanding dc behavior of subthreshold cmos logic through closed-form analysis,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.57, no.7, pp. 1597--1607, July 2010. [Online]: http://dx.doi.org/10.1109/TCSI.2009.2034233
[^177]: A.Hajimiri and T.Lee, ''A general theory of phase noise in electrical oscillators,'' IEEE Journal of Solid-State Circuits, vol.33, no.2, pp. 179--194, February 1998. [Online]: http://dx.doi.org/10.1109/4.658619
[^178]: A.Demir, A.Mehrotra, and J.Roychowdhury, ''Phase noise in oscillators: a unifying theory and numerical methods for characterization,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.47, no.5, pp. 655--674, May 2000. [Online]: http://dx.doi.org/10.1109/81.847872
[^179]: A.Hajimiri, S.Limotyrakis, and T.Lee, ''Phase noise in multi-gigahertz cmos ring oscillators,'' in IEEE Proceedings of the Custom Integrated Circuits Conference, May 1998, pp. 49--52. [Online]: http://dx.doi.org/10.1109/CICC.1998.694905
[^180]: W.Jiang, V.Hokhikyan, H.Chandrakumar, V.Karkare, and D.Markovic, ''A ±50mv linear-input-range vco-based neural-recording front-end with digital nonlinearity correction,'' in IEEE Proceedings of the International Solid-State Circuits Conference, January 2016, pp. 484--485. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7418118
[^181]: C.Weltin-Wu and Y.Tsividis, ''An event-driven clockless level-crossing adc with signal-dependent adaptive resolution,'' IEEE Journal of Solid-State Circuits, vol.48, no.9, pp. 2180--2190, September 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2262738
[^182]: H.Y. Yang and R.Sarpeshkar, ''A bio-inspired ultra-energy-efficient analog-to-digital converter for biomedical applications,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.53, no.11, pp. 2349--2356, November 2006. [Online]: http://dx.doi.org/10.1109/TCSI.2006.884463
[^183]: F.Corradi and G.Indiveri, ''A neuromorphic event-based neural recording system for smart brain-machine-interfaces,'' IEEE Transactions on Biomedical Circuits and Systems, vol.9, no.5, pp. 699--709, October 2015. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2479256
[^184]: K.A. Ng and Y.P. Xu, ''A compact, low input capacitance neural recording amplifier,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.5, pp. 610--620, October 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2280066
[^185]: J.Agustin and M.Lopez-Vallejo, ''An in-depth analysis of ring oscillators: Exploiting their configurable duty-cycle,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.62, no.10, pp. 2485--2494, October 2015. [Online]: http://dx.doi.org/10.1109/TCSI.2015.2476300
[^186]: K.Ng and Y.P. Xu, ''A compact, low input capacitance neural recording amplifier,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.5, pp. 610--620, October 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2280066
[^187]: M.Elia, L.B. Leene, and T.G. Constandinou, ''Continuous-time micropower interface for neural recording applications,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2016.
[^188]: Y.W. Li, K.L. Shepard, and Y.P. Tsividis, ''A continuous-time programmable digital fir filter,'' IEEE Journal of Solid-State Circuits, vol.41, no.11, pp. 2512--2520, November 2006. [Online]: http://dx.doi.org/10.1109/JSSC.2006.883314
[^189]: B.Schell and Y.Tsividis, ''A continuous-time adc/dsp/dac system with no clock and with activity-dependent power dissipation,'' IEEE Journal of Solid-State Circuits, vol.43, no.11, pp. 2472--2481, November 2008. [Online]: http://dx.doi.org/10.1109/JSSC.2008.2005456
[^190]: S.Aouini, K.Chuai, and G.W. Roberts, ''Anti-imaging time-mode filter design using a pll structure with transfer function dft,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.59, no.1, pp. 66--79, January 2012. [Online]: http://dx.doi.org/10.1109/TCSI.2011.2161411
[^191]: X.Xing and G.G.E. Gielen, ''A 42 fj/step-fom two-step vco-based delta-sigma adc in 40 nm cmos,'' IEEE Journal of Solid-State Circuits, vol.50, no.3, pp. 714--723, March 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2393814
[^192]: K.Reddy, S.Rao, R.Inti, B.Young, A.Elshazly, M.Talegaonkar, and P.K. Hanumolu, ''A 16-mw 78-db sndr 10-mhz bw ct $\delta \sigma$ adc using residue-cancelling vco-based quantizer,'' IEEE Journal of Solid-State Circuits, vol.47, no.12, pp. 2916--2927, December 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2218062
[^193]: J.Daniels, W.Dehaene, M.S.J. Steyaert, and A.Wiesbauer, ''A/d conversion using asynchronous delta-sigma modulation and time-to-digital conversion,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.57, no.9, pp. 2404--2412, September 2010. [Online]: http://dx.doi.org/10.1109/TCSI.2010.2043169
[^194]: F.M. Yaul and A.P. Chandrakasan, ''A sub-$\mu$w 36nv/$√Hz$ chopper amplifier for sensors using a noise-efficient inverter-based 0.2v-supply input stage,'' in IEEE Proceedings of the International Solid-State Circuits Conference, January 2016, pp. 94--95. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7417923
[^195]: S.Patil, A.Ratiu, D.Morche, and Y.Tsividis, ''A 3-10 fj/conv-step error-shaping alias-free continuous-time adc,'' IEEE Journal of Solid-State Circuits, vol.51, no.4, pp. 908--918, April 2016. [Online]: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7433385&isnumber=7446371
[^196]: J.M. Duarte-Carvajalino and G.Sapiro, ''Learning to sense sparse signals: Simultaneous sensing matrix and sparsifying dictionary optimization,'' IEEE Transactions on Image Processing, vol.18, no.7, pp. 1395--1408, July 2009. [Online]: http://dx.doi.org/10.1109/TIP.2009.2022459
[^197]: R.S. Schneider and H.C. Card, ''Analog hardware implementation issues in deterministic boltzmann machines,'' IEEE Transactions on Circuits and Systems---Part II: Analog and Digital Signal Processing, vol.45, no.3, pp. 352--360, Mar 1998. [Online]: http://dx.doi.org/10.1109/82.664241
[^198]: J.Lu, S.Young, I.Arel, and J.Holleman, ''A 1 tops/w analog deep machine-learning engine with floating-gate storage in 0.13$\mu$m cmos,'' IEEE Journal of Solid-State Circuits, vol.50, no.1, pp. 270--281, January 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2356197
[^199]: M.T. Wolf and J.W. Burdick, ''A bayesian clustering method for tracking neural signals over successive intervals,'' IEEE Transactions on Biomedical Engineering, vol.56, no.11, pp. 2649--2659, November 2009. [Online]: http://dx.doi.org/10.1109/TBME.2009.2027604
[^200]: D.Y. Barsakcioglu and T.G. Constandinou, ''A 32-channel mcu-based feature extraction and classification for scalable on-node spike sorting,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2016.
[^201]: R.P. Feynman, ''There's plenty of room at the bottom,'' American Physical Society, vol.23, no.5, pp. 22--36, February 1960. [Online]: http://www.zyvex.com/nanotech/feynman.html
[^202]: G.Leuba and L.J. Garey, ''Comparison of neuronal and glial numerical density in primary and secondary visual cortex of man,'' Experimental Brain Research, vol.77, no.1, pp. 31--38, 1989. [Online]: http://dx.doi.org/10.1007/BF00250564
[^203]: I.Guideline, ''Guidelines for limiting exposure to time-varying electric, magnetic, and electromagnetic fields (up to 300 ghz),'' Health Physics, vol.74, no.4, pp. 494--522, October 1998. [Online]: http://www.icnirp.org/cms/upload/publications/ICNIRPemfgdl.pdf
[^204]: L.B. Leene, S.Luan, and T.G. Constandinou, ''A 890fj/bit uwb transmitter for soc integration in high bit-rate transcutaneous bio-implants,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2013, pp. 2271--2274. [Online]: http://dx.doi.org/10.1109/ISCAS.2013.6572330
[^205]: ''Unconventional processing of signals for intelligent data exploitation (upside),'' Defense Advanced Research Projects Agency, Arlington, Texas, January 2016. [Online]: http://www.darpa.mil/program/unconventional-processing-of-signals-for-intelligent-data-exploitation

651
content/publications/2016/brain-machine-interfaces-neural-recording-neuron-processor-interface.md Normal file
View File

@ -0,0 +1,651 @@
---
title: "Brain machine interfaces: Neuron Processor Interface"
date: 2016-08-08T15:26:46+01:00
draft: false
toc: true
math: true
type: posts
tags:
- chapter
- thesis
- CMOS
- biomedical
---
Lieuwe B. Leene, Yan Liu, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
A core aspect of emerging neuroscience is quintessentially performing real-time data analysis at a massive scale. However when we observe its manifestation in state-of-the-art neural interfaces we find the hardware is very limited to specific methods that can be objectively short-sighted. This chapter aims to direct our attention to a different point of view with respect to how these sensor systems can be structured. In particular we are guided by the concept where an implant is capable of performing software defined instrumentation. This is associated with a focus that lies with enabling real time & in-vivo testing of a more diverse set of signal characterization methods. More importantly we will demonstrate that this can be made feasible for large scale distributed systems.
This particular approach is motivated by a number of factors that aim to increase performance and enable research opportunities. The first is that many aspects with regard to the signal quality of an implant cannot be predicted beforehand. As a result implementing a specific algorithm for specific signal characteristics may lead to failure or an overly conservative design because the environment can potentially be excessively noisy. By introducing the capacity to dynamically execute different processing methods on neural data the implanted system to use either LFP and EAP activity in real-time. This may be a significant element to improving the success for chronic BMI implants. Moreover the prolific development in characterization methods used for decoding neural data inhibits a general consensus for DSP techniques. This prevents a single method and corresponding architecture to be applicable in most scenarios. The second factor is that this approach conceptually enables the development of real-time resource constrained algorithms which are virtues often neglected when working with data sets. Currently most BMI development platforms have limited capabilities to allow algorithms to use external or multi-modal features to inform local operation and simultaneously provide recordings from hundreds of electrodes. This construction may be a key factor to allowing high level algorithms to directly manipulate machine learning parameters local to each implant. This hierarchical fashion should improve the efficiency of distributed BMIs for decoding information. In contrast we question the feasibility for scaling the current supervised methods that require fine measurements of each electrode's recording to approach a optimal decoding strategy. Typically the computational efficiency of this approach remains exhaustive when reconfiguring sensor parameters because it use a centralized unit that recalibrates all recording channels in an elaborate fashion.
This chapter is organized as follows; Section 31 motivates localized processing for increased efficiency and estimates to what extent we can perform on-chip processing. This is followed by Section 32 where typical methods used for neural signal analysis are introduced and the respective hardware complexity is demonstrated in Section 33. This leads into the proposed distributed processing architecture in Section 38 where the design is discussed with respect to the implementation. Section 41 demonstrates the realization of this platform. Finally Section 42 draws conclusions with respect to the digital approach to neural instrumentation.
# 31 Processing at the interface
Ideally a neural interface device is tasked with recording from a large ensemble of electrodes and transmitting information with the lowest bandwidth because the harvested power is a scarce resource for implants inside the body. However over the course of an implant's life time most signal characteristics are dynamically changing which implies that there should be an involved learning process that similarly adapts to these changes. This can also mean that the output bandwidth is constrained by the total amount of mutual information that can be retained within the device. Such a device will predict the expected recording from one time interval to the next and differentiate any new information that needs to be transmitted. Hence we should be convinced that the processing capacity or complexity for a closed or memory limited system should reflect in its fundamental ability to store information [^140].
In order to capture some high level trends with respect to processing requirements let us normalise memory capacity in terms of state variables that is independent of modality. This is particularly useful because the number of state variables in a dynamic process is a good indicator for complexity whether is a digital classifier or an analogue filter. Here we will exclusively focus on processing by assuming the signal being operated on is idealized with respect amplitude and its representation. This extends from our analysis in Section\ref{ch:T1_model} by elaborating specifically on comparing digital and analogue resource allocation associated with processing.
$$ R_{A} = \underbrace{\frac{2\pi BW kT SNR^2 U_T}{V_{DD} L}}_{power} \cdot \underbrace{\left( \frac{A_{min}}{L} +\frac{kT SNR^2}{L Vdd^2 C_{dens}} \right)}_{Area} $$
If we represent the resource required as the power area product for a state variable then in the analogue domain it would be represented by Equation 32. Here \\(BW\\), \\(V_{DD}\\), \\(C_{dense}\\), \\(A_{min}\\) reflect the signal bandwidth, supply voltage, capacitor density, and typical transconductance area overhead for a particular technology respectively. \\(L\\) is a normalized feature size that allows us to evaluate parameters for a particular technology and extrapolate them based on constant field scaling factors.
$$ R_{D} = \underbrace{ 2BW \alpha \log_2(SNR) C_{gate} V_{dd}^2 L^2 }_{power} \cdot\underbrace{ \alpha \log_2(SNR) A_{gate} L^2}_{Area} $$
Similarly Equation 33 represents the power area product for a digital state variable. \\(C_{gate}\\), \\(A_{gate}\\), \\(\alpha\\) parametrise typical gate capacitance, area, and overhead for each register respectively. Generally the dependency of both parameters \\(R_A\\) and \\(R_D\\) are well understood and guide maximizing system efficiency in an abstract sense [^141].
{{< figure src="technical_2/impact.png" title="Figure 49: Impact of technology on \\(R_A\\) analogue (green) and \\(R_D\\) digital (blue) processing resource requirements extrapolated from a \\(180 nm\\) CMOS technology under constant field scaling." width="500" >}}
For neural instrumentation however both power and area requirements must be highly constrained in order to realize a device that can accommodate a large number of recording channels and remain implantable. Figure 49 shows the resource requirements for processing in the analogue and digital domain with respect to signal fidelity and CMOS technology. Either approach can present an advantage over the other under specific conditions. Digital systems appear favourable beyond \\(65 nm\\) CMOS where analogue will do better at lower SNR conditions given a technology with a larger feature size. The discussion in Section \ref{ch:T1_model} suggested the analogue preconditioning requires a resource allocation of $10^{-15} Wm^2$ with a weak dependence on technology. Moreover if quantization is not considered then power can be entirely determined by the noise specification and the area requirements are dependent on the gain configuration. Comparing this figure with the estimate on \\(R_D\\) indicates that we should be able to integrate a considerable amount of processing capabilities before the DSP uses a comparable amount of resources. This is important because improving on-chip processing capacity ideally results in requiring less supervision and a lower wireless communication bandwidth.
While we may expect other sources of over-head and extra power dissipation components, we should instead take a moment to consider the implications of this result. Particularly when considering the claim that electronic sensing of brain activity on larger scales is not viable due to the excessive data rates derived from the principle entropy relations and the associated communication bandwidth [^142]. Clearly any degree of on-chip processing undermines this limitation because it enables us to achieve data rates far lower than that of the electrical signals by finding a more appropriate basis of encoding information. On the other hand it does raise an important point regarding the relationship of the generated output data rate and the recorded signal to noise ratio. In some sense we are simply faced with the challenge of best consolidating the recorded information towards high level indicators for specific objective functions. This allows us to approach data rates extracted from current BMI studies which are negligible in comparison to the Nyquist rates. In this light we argue that electronic methods for recording activity are the closest to realizing a viable neuroprosthetic solution in the near future when comparing optical, magnetic and less invasive BMI architectures.
Now we can make the assertion that there should be two approaches to solving the system level challenge of integrating wireless neural instrumentation systems. The first approach would be a mixed signal topology that extensively uses analogue processing such that technology has a weak impact on improving efficiency. Instead the critical component lies with the effectiveness of analogue dimensionality reduction. In such a case we need to adopt a well established algorithm that can accommodate analogue variability an still deliver exceptional signal characterization. The second approach is to rely on digital methods that deliver robust and reconfigurable compute resources that scale well with technology. This should grantee the capacity for a variety of fully adaptive algorithms capable of extracting multi-modal characteristics from recordings. This could much more valuable for experimental neuroscience at this point in time. Unfortunately not all forms of algorithms can use the low power characteristics of processing in the analogue domain. Moreover they are typically limited by underlying assumptions regarding noisy perturbations. When we introduce different contexts of operation reconfiguring the analogue is not done as arbitrarily as a digital structure would. For this reason we will adopt the digital approach in order to leverage robust reconfigurable capabilities and reconsider the analogue approach in Section 48.
The significance here is that these trends allow us to roughly estimate the complexity of algorithms for different technologies if their resource requirements made to be equivalent to that of the instrumentation circuits. We show in Figure 50 that using a $0.18 \mu m$ CMOS process should give way to approximately 100 state variables or equivalently perform about 100 operations per sample taken. In fact looking at image processors that similarly rely extensively on data intensive post processing we can see an identical dependency on technology scaling as we have predicted for various levels of digital performance at different technology nodes. It is important to note that the normalized efficiency evaluated here is in fact independent of signal bandwidth and only depends on signal to noise ratio and its relation to the supply voltage.
{{< figure src="./technical_2/Operations.pdf}" title="Figure 50: Analytic number of digital operations available with respect to different technologies (red) with references to the normalized performance of image processors (blue)." width="500" >}}
$$ P_{system} = \underbrace{ N_{channel} \cdot \left( P_{Algo} + P_{Transmit} \right) }_{In \: Channel} + \underbrace{ P_{Control} + P_{Comms} }_{System \: Level} $$
System level design of a embedded processing system for BMIs should be guided entirely by the optimization of compute power efficiency. As shown by Equation 34 we expect are two primary components in the system power breakdown. The over all objective should lie with minimizing the channel level power dissipation of the algorithm \\(P_{algo}\\) by increasing that of the system level control \\(P_{Control}\\) such that the component that scales with channel count is reduced. Secondly we should keep in mind that reducing in processed output data alleviates the dissipation of the on-chip communication \\(P_{Transmit}\\) and the external telemetry power consumption \\(P_{Comms}\\).
## 32 Methods for Neural Signals
A key component to developing this platform is a discussion on the diverse set of signal processing methods performed on neural data and their computational requirements in order to determine our system's specifications. More importantly we want to judge what is the expected complexity for some of these operators and how many variables are allocated during each process. There are in principle four different categories for the methods that are applied to process neural signals which are listed below. In practice, a single integrated system will utilize a multitude of different techniques to achieve denoising and feature extraction.
\textbf{Pre-Processing} is the filtering and conditioning of each ADC output sample using FIR, IIR, or non-linear filters. Here the objective is simply to de-noise the features or signal components. The resulting signal allows for better detection or more precise evaluation of the signal characteristics and is often closely related to the characteristics of the instrumentation circuits. This output may be considered as the raw signal recording that is used to bench mark any post processing methods or other instrumentation systems.
**Detection** is associated particularly with capturing the intermittent spike events. There is no quantitative evaluation made with regard to the nature of the detected spike but any detection may trigger the process that records contiguous samples around the detection event that are then subsequently characterized. These events are commonly triggered upon simple threshold crossings of the signal or its integral power over several samples. In some systems the interest lies only with the accurate detection of spike events which is sufficient to perform closed loop therapeutic treatment or control actuators external to the body.
**Data reduction** can be interpreted either as representing a spike waveform in terms of defining features or with a reduced basis to allow approximate reconstruction by using spike amplitude or wavelet decomposition. Representing waveforms in terms of their quintessential components allows for more efficient post processing and reduces data rates in the case of wireless telecommunication. In its primitive sense this is simply dimensionality reduction of the recorded data and is usually followed by supervised or unsupervised signal classification.
**Classification** is the predominant objective for BMIs and is the main difficulty to realize inside a embedded recording system. Such a task in spike based systems primarily performs a generalization of the detected spike shape in terms the previously detected neurons. This reflects the fact that in most cases multiple neurons can be detected by a single electrode and by distinguishing these events the integrity of information can be preserved. The objective here lies with having an equivalent spike event output as simple detection to perform actuation but with better fidelity.
It should also be clear that the above operations primarily focus on reducing the recorded signal to its primitive components in terms of spike events at the rate of \\(100 b/s\\) instead of the \\(256 Kb/s\\) data stream typically generated by the ADC. The processing layer on top of this elementary function will either aim to evaluate neural connectivity or use collections spike rates to perform inference of high-level dynamics. This application specific processing of these systems will not be considered here primarily because the nature of such a problem is very different from the more generic information extraction from recordings. As a result that system architecture should revolve specifically around multichannel trained dimensionality reduction. Even when such a task can adjoin to what is presented here it will be out side the scope of this discussion which targets more generic signal instrumentation.
{{< figure src="technical_2/Survay_I.pdf}" title="Figure 51: Estimated resource requirements for different classes of algorithms use for processing neural recordings found in literature." width="500" >}}
When we survey the various algorithms found in recent literature and estimate the expected memory/computational requirements we might observe a distribution like that shown in Figure 51. For fair comparison we have adopted these methods to operate on a window size of 32 samples with three types of dectected spike waveforms when applicable and only accounted for memory allocation that cannot be shared across channels. This should give a good normalized indication of the limiting components for each method which we could then further optimize in a more specialized manner. Notice that there is a strong correlation in the memory usage and the required number of operations for most embedded systems.
Some of the most efficient spike detection and feature extraction is associated with using temporal characteristics of the spiking waveforms. Common examples include using the time interval between minimum and maximum peaks or the duration of threshold crossing for detected spikes. The defining characteristic here is that alignment buffers are not needed which leads to using very few operations per sample. Inherently the drawback is the increased sensitivity to noise which implies a very limited capacity to distinguish and classify different spike shapes. Unless more filtering is performed. There are other methods that also operate with reduced signal buffers. For instance using compressed sensing where signals a continuously re-projected with a sensing matrix. This requires a few accumulators for each coefficient being extracted but this is strictly data compression. Ultimately This may not help directly with classification or signal characterization that must now be performed off-chip before any benefit can be realized.
Many other classes of algorithms operate on a windowed basis that exploit learned mean spike shapes that are expected in the recording. Here a convolution or distance operator will indicate which class of spike is detected. For terminology let each convolution of the signal result in a feature that is used for detection and/or classification. The adaptive component of these methods leverage a significant amount of noise shaping and separation depending on what the objective function entails when the basis for convolution is being determined. The most prevalent approach is convolving with principle components which simply maximizes the signal variance in the projected space. In contrast to using temporal feature that struggle with sample limited denoising, the windowed operators should be more robust towards noise. Instead there is some difficulty in systematic alignment of the window with the spike. This aspect often motivates increased sampling rates or interpolation in order to perform accurate alignment.
The objective function for determining the convolution kernels can be oriented towards maximising sparsity[^154], signal to noise[^155], cluster separation[^49], or expectation maximization[^156] each reflecting different signal modalities and analysis methods. Although the complexity for training can be varied extensively the local operations for classification after adaptation is almost equivalent. This operation is the \\(F\\) linear projections using \\(W\\) samples onto the feature space where \\(F\\) and \\(W\\) are the number of features used and the number of samples in the window respectively. There may be some deviation from this operation if we also consider the different confidence intervals for each class is taken into account. This can be done by evaluating centroid distances in terms of the variance for each respective centroid. Conversely to such training, generalized templates averaged over a number of recording channels may also be used for feature extraction in order to share the memory requirements at the loss of not achieving maximally separated clusters for each individual channel.
Naturally it is challenging to objectively judge feature extraction and classification methods. We could always reduce the dimensionality of the search space or by simplifying the convergence strategies to reduce memory and computational requirements. For this reason the details in Figure 51 should be considered in relative terms due to the generalizations made with regard to system specifications. As many methods in the literature are not performed at the sensor interface they typically will not take advantage of processing on a sample to sample basis and opt for a batched or sequenced processing methodology.
We claim however that the segregation between methods primarily lies with whether the classification features are based on sample space characteristics or alternatively use windowed convolution operators. The former is the less rigorously justified as the features relating to amplitude and spike width have weak physiological significance but are aggressively more efficient than other methods. The characteristic requirement of the later later approach is typically related to the window size that is indirectly associated with the sampling speed in order to fit the relevant spike shape into the window. One important objective of current decoding research is related to introducing adaptive techniques that iteratively improve classification without supervision. Particularly without excessive memory requirements in order to keep track of long term statistics. To demonstrate why this can be particularly challenging, consider a simplified example of using K-means to directly cluster the sample space adaptively where we are fortunate to know the number of classes is three.
Clearly for each detected spike we would need to evaluate the distance between our data the centroids having a memory and complexity requirement of \\((1+F) W\\) variables and \\(2 F W\\) operations respectively. Then once the class is determined an additional \\(2W\\) operations are needed to adjust the centroid with the new data. This may include keeping track of the additional \\(F W\\) truncation residues that allow using a small enough adjustment weight for convergence when our quantization is limited by an 8 bit system. Now for completion, assume our window is 32 samples and we come to the conclusion that for each recording channel we to actively need to allocate nearly \\(2 K bits\\).
Typically this primitive aspect of a generic classification algorithm is intensive enough warrant not performing it locally in contrast to the complexity of the aforementioned temporal features. It also raises the challenge of trained dimensionality reduction without supervision which exclusively relies on evaluating the covariance matrix in order to minimize the correlation of non-signal components with our new basis. The above algorithm may be representative in terms of complexity with the exception that basis pursuit relies heavily on inner products. There is some relief from the fact these optimal basis change very slowly and actively adapting is only needed once few hours as the electrode recording changes slowly with respect to the neural activity. As will be demonstrated the feasibility of these more involved methods rely very much on the careful construction and memory allocation of the algorithm with respect to the processing architecture. Operations like k-means and PCA decomposition can be performed to a certain extent if the operations are broken down into a incremental procedures.
# 33 Resource Constrained Classification
Primarily to substantiate our expectations for performing processing at the sensor interface and evaluate where the system level requirements should lie. Ultimately such a system needs to encompass a significant variety of different application requirements. We will consider the implementation of two well known methods that process neural recording and generate classified events. This will be applied to the equivalent scenario where the proposed instrumentation front-end is used from Section 17 such that the digitized signal will have considerable dynamic range but lacks analogue filtering. In particular this implies the recorded signal is filtered by a first order butterworth low pass filter in addition to near-DC rejection while being sampled at \\(25 KS/s\\). We will address the rejection of low frequency aggressors in addition to the computational requirement of typical processing algorithms.
Many of the filter and processing considerations are guided by evaluating accuracy empirically and justified though constrained parametric optimization [^157]. The particular algorithms implemented here are structured in such a way they perform specific considerations for the underlying hardware. On numerous occasions we will employ single bit accumulators as approximations to the IIR equivalent feedback structures in order to improve our effective register depth through feedback. This is a primary advantage of in-channel processing where we may exhaustively make use of recorded data without having concern for the communication of these components.
Empirical validation is demonstrated by using of synthetic data sets that are publicly available online. This data is based on characterized extracellular recording where both background activity and spike morphologies are extracted from a human neocortex and basal ganglia. The synthesized recording was originally used to evaluate the performance of super-paramagnetic clustering with wavelet decomposition at different background noise levels in [^1]. Synthetic data specifically allows the inference of the ground truth resulting in unbiased performance indicators. For fair comparison of analogue and digital techniques we additionally include low frequency content from \\(1-300 Hz\\) at \\(10\times\\) of the largest peak to peak amplitude of the extracellular action potentials found in the recordings.
## 34 Spike Detection & Filtering
Arguably the most influential aspect to neural detection and classification algorithms is the signal preconditioning for systematic and accurate detection of spike events. The importance lies with the fact that detection behaviour has the significant influence on how the feature space appears when the spike is characterized with various methods. Although amplitude noise can usually be accounted for in terms of filtering. Any misalignment in the time domain due to noisy aggressors in the detection operator can up modulate low frequency components. The tendency to perform detection in the digital domain is entirely related to the instantaneous characteristic of discreet time processing which is superior to the group delay inherent to analogue implementations. Minimizing this factor will minimize additional memory for capturing any signal before the detection event.
The method proposed here tracks both the mean spike amplitude and back ground noise levels in order to assert the detection level of spike events. Motivated by using physiological characteristics to specify the underlying operation parameter \\(k_3\\) is introduced to represent the relative amplitude of background activity to that the maximum spike waveform that is intended to be detected. Or in other words if we are only interested in the closest neurons to the electrode \\(k_3\\) should be close to 1, otherwise if we also want to detect background activity with an amplitude at \\(25%\\) of the largest spiking events \\(k_3\\) should approach \\(4\\). In actuality this term should also be related to how well our classification can separate noisy detection or actual spike events.
\begin{algorithm}
\DontPrintSemicolon
\KwData{Sample from ADC \\(X[n]\\)}
\KwResult{Detection events & spike window \\(W_1\\)}
\Begin{
\ShowLn
Update \\(V_{LFP}\\) with $k_1 \cdot (X[n]-V_{LFP})$ \tcp*{ Track low frequency content}
Set \\(S[n]\\) with $X[n] - V_{LFP} + k_2 \cdot S[n-1]$ \tcp*{ IIR bandpass filter}
Set \\(G[n]\\) as $\sum S[n]\cdot FIR(2*R) $ \tcp*{ FIR bandpass filter }
Set \\(ES[n]\\) as $S[n] \cdot G[n-R]$ \tcp*{ Energy Estimate from IIR & FIR product }
Update \\(V_{noise}\\) with $k_1 \cdot (|ES[n]|-V_{noise})$ \tcp*{ Estimate variance on energy estimate }
\uIf{$ES[n] > V_{th}$ **and** $ES[n] > max_{local}$ \tcp*{ Find threshold crossing or new local max } }{
Update \\(V_{th}\\) with $k_1 (ES[n-1]+2V_{noise} - k_3 \cdot V_{th})$ \tcp*{ Adapt peaks and varience}
Initiate Spike Alignment \;
Set \\(max_{local}\\) to \\(ES[n]\\) \tcp*{Set local maximum}
Set \\(index\\) to \\(0\\) \tcp*{Initiate data pointer}
}
\uElseIf{Currently alligning spike (\\(index<16\\)) }{
Set \\(W_1[index]\\) to \\(G[n-10]\\) \tcp*{Store spike waveform with delayed samples}
Set \\(index\\) to \\(index+1\\) \tcp*{Increment data pointer}
}
\uElseIf{Idle state (\\(index>31\\))}{
Set \\(max_{local}\\) to \\(0\\) \tcp*{Finish classification & find next local maximum}
}
\uElse{
Accumulate \\(index\\) with \\(1\\) \tcp*{Increment data pointer}
%Perform Classification on \\(W_1[index]\\)\;
}
}
\BlankLine
\caption{Spike Detection and Alignment}
\label{aglo:T2_Detection}
\end{algorithm}
The specifics of this operation is reflected in Alg. \ref{aglo:T2_Detection}. Here the term Update, Set, and Accumulate represent recurrence, instantaneous, and integrated relations respectively. The state variable \\(V_{LFP}\\) primarily removes low frequency drift that is not associated with individual spiking events and \\(S[n]\\) is as a result a bandpass equivalent of our sampled signal \\(X[n]\\). The signal's instantaneous energy is represented by \\(ED[n]\\) which is a product of \\(S[n]\\) and the delayed derivative computed by the FIR of even order \\(2R\\) with the coefficients $a_n= -a_{2R-n} = 1-2/R \cdot(n-1)$ for \\(n\\) from \\(1\\) to \\(R\\). The factor \\(R\\) is in association with the ratio of sampling interval to spike polarization interval, equivalently as $R=f_{nyquist} / 5KHz$. At the maximum of \\(ED[n]\\) operation on line 5 essentially measures the product of the maximum spike intensity with the maximum derivative that proceeds it by \\(R\\) samples. This method primarily depends on the fact that spike detection looks for highly correlated narrow band energy which rejects a substantial amount of white noise. Moreover the operator compresses uncorrelated components in amplitude as it exhibits a square dependency in terms of $ED[n] \propto S[n]^2$ making variation in the threshold less sensitive to detection. The fact that the operator is narrow band limits the detection of slower spike waveforms that do not contain large derivative components but on the other hand this grantees more systematic alignment. In this case alignment is done simply with respect to where the peak value of \\(ES[n]\\) is detected.
{{< figure src="technical_2/freq_pfd.pdf}" width="500" >}}
{{< figure src="technical_2/phase_pfd.pdf}" title="Figure 52: Extracted frequency characteristics of digital filter used in Algorithm \ref{aglo:T2_Detection}." width="500" >}}
The overall filtering characteristic of \\(S[n]\\) and \\(G[n]\\) is shown in Figure 52. The IIR bandpass is a result of \\(k_2\\) being \\(0.5\\) such that both filters suppress components around the Nyquist frequency. The group delay should be equivalent to a single high pass pole at $250 Hz$ but the FIR assists in further suppressing high and low frequency components. We should not expect significant contribution from group delay induced distortion as the features of interest will predominantly have $1 KHz - 5 KHz$ components. Besides \\(R\\) and \\(k_1\\) can always be adjusted to reposition the high-pass poles closer to DC. Note that \\(V_{LFP}\\) will represent the \\(DC-250 Hz\\) signal components that can be used to infer characteristics about the background activity.
{{< figure src="technical_2/C05.pdf}" width="500" >}}
{{< figure src="technical_2/C01.pdf}" width="500" >}}
{{< figure src="technical_2/C02.pdf}" title="Figure 53: False alarm rates normalized by true positives for data sets with different background activity." width="500" >}}
The overall performance shown in Figure 53 reflects how spike detection is systematically accurate until the noise level approached \\(50%\\) of the signal intensity irrespective of the data set with the default case where \\(k_3=3\\). Note that the white noise is additive to the background activity implying \\(-14dB\\) of white noise and \\(-14dB\\) of background activity should evaluate to around \\(-8dB\\) accumulated SNR. When the noise level exceeds the anticipated background activity for \\(K_3\\) we observe a strong increase in the number of detected false positives. The rate of erroneously detected false negatives presents a more gradual increase but at this point classification is much more challenging. As expected background has a considerably bigger impact on false alarm rate because spectral content and signal structure is equivalent to that of the foreground activity.
We can observe that the main component for computational complexity in this detection operator arises from the FIR & IIR high-pass filters where the order is closely related to the sampling frequency. In fact if we ignore the buffer used to capture features before the alignment event then this filter accounts for 70% of the memory utilization and 53% of the elementary operations while the rest is used for evaluating the instantaneous energy and performing overhead control. Note that the classification operator should be introduced in line 19 with a sample basis using the index as referenced pointer. This implies that we will be classifying while repolarization occurs at the electrode and our detection trigger is blanked out during this interval. This implies that we lose the capacity to detect any over lapping spikes. Such events have limited occurrences and missing such events can be acceptable because proper classification will likely fail as well.
## 35 Recursive Variance Decomposition
Another commonly used technique is that of principle component analysis (PCA) which extracts the largest loading vectors \\(\nu_n\\) of the covariance matrix. This predominantly negates the systematic components of the captured signal and reduces the dimensionality of the spike window to a sub-set of maximally varying features by linear transformation. These components are particularly useful as indication for spiking activity in the signal due to structure in \\(\nu_n\\) but typically also suffice for providing a basis for classification in low noise conditions and reducing complexity once these vectors are found. The challenge specifically lies with the fact that determining this is basis requires both the computation of the covariance matrix that evolves over time as well as finding the transformation that diagonalizes that matrix. The implication is that in order to extract the first two principle components we need to track a total of \\(W(W+3)\\) state variables where \\(W\\) is the number of samples in the spike window.
The iterative method employed here referred to as recursive variance decomposition (RVD) and is an approximation to standard PCA by recursively tracking the largest two loading vectors reducing the minimum number of state variables to $3W + 3$. Similarly to PCA estimators like hebbian eigenfilters [^155], every iteration incrementally updates the the learned basis without requiring extensive computation. The methodology is based on recursive extraction of the largest loading vector $|\nu_1|$ that is normalized by \\(g_1\\) by checking the condition $(x - x \cdot \nu)\cdot \nu = 0 $. This condition checks if there is any residue in the direction of \\(\nu_1\\) after removing its component to see if it is appropriately scaled. Moreover due to the strong correlation between the mean and first principle component we approximate that $sign(\mu) \approx sign(\nu_1)$ completing the extraction of \\(\nu_1\\). In fact these two statements allow a significant reduction in complexity as normalization is achieved through feedback. The noise shaping and orthogonality properties associated with PCA is preserved using this extraction which is the most important aspect.
\begin{algorithm}
\DontPrintSemicolon
\KwData{Spike window \\(W_1\\)}
\KwResult{First two aggregate loading vectors \\(\nu_1\\) & \\(\nu_2\\)}
\Begin{
\ForEach{Sample **n** in window \tcp*{ Projection phase } }{
$D_1[n] = W_1[n] - \mu[n]$ \tcp*{ Get distance from mean spike }
Accumulate \\(p_1\\) with $D_1[n] \cdot \nu_1 \cdot sign(\mu[n])$ \tcp*{ Project spike with \\(\nu_1\\) }
Accumulate \\(p_2\\) with $D_1[n] \cdot \nu_2 $ \tcp*{ Project spike with \\(\nu_2\\) }
}
\;
\ForEach{Sample **n** in window \tcp*{ Training phase } }{
Update \\(\mu[n]\\) with $ k_1 \cdot sign(W_1[n] - \mu[n])$ \tcp*{ Track mean spike }
Accumulate \\(\nu_{1}[n]\\) with $k_1 \cdot sign(| D_1[n]\cdot g_1 | - \nu_{1}[n])$ \tcp*{ Move \\(\nu_1\\) towards \\(D_1[n]\\) }
Accumulate \\(\nu_{2}[n]\\) with $k_1 \cdot sign( (D_1[n] - \nu_{1}[n] \cdot p_1)\cdot g_2 - \nu_{2}[n])$ \; \tcp*{ Move \\(\nu_2\\) towards \\(D_1[n]-p_1\cdot\nu_1\\) }
Accumulate \\(p_3\\) with $(|D_1[n]| - \nu_{1}[n]\cdot p_1) \cdot \nu_{1}[n]$ \tcp*{ Get gain error }
Accumulate \\(p_4\\) with $(|D_1[n]| - \nu_{2}[n]\cdot p_2) \cdot \nu_{2}[n]$ \tcp*{ Get gain error }
}
Accumulate \\(g_1\\) with $k_1 \cdot sign(p_3)$ \tcp*{ Adjust gain on \\(\nu_1\\) }
Accumulate \\(g_2\\) with $k_1 \cdot sign(p_4)$ \tcp*{ Adjust gain on \\(\nu_2\\) }
}
\BlankLine
\caption{Recursive variance decomposition}
\label{aglo:T2_PC_l1min}
\end{algorithm}
Algorithm \ref{aglo:T2_PC_l1min} shows the operation for estimating the first two PCA components. Here \\(D[n]\\) is the new data point off set by the mean spike waveform $\mu [n]$ which allows the long term estimation of aggregate variance. Similarly parameter \\(k_1\\) specifies how the state variables are exponentially averaged over the preceding data points. Because the projection of the first loading vector must be evaluated before the second vector these operations must be sequenced in time or with memory buffers. The evaluation of \\(p_4\\) is strictly for illustrating the iterative method at which other components are evaluated while \\(g_2\\) can also be adjusted to normalize the values of \\(p_2\\) to prevent overflow without needing \\(p_4\\).
## 36 Template Matching using K-means
Finally we consider the implementation of template matching in channel. This can be seen as simply a K-means clustering method without dimensionality reduction on the input vector. The implication is that it is characteristically more memory intensive but requires less computationally intensive operators.
\begin{algorithm}
\DontPrintSemicolon
\KwData{Spike window \\(W_1\\)}
\KwResult{Classification with respect to aggregate clusters}
\Begin{
Accumulate $Spike \: Count$ with \\(1\\) \tcp*{track accumulated statistics}
\ForEach{Sample **n** in window \tcp*{Projection Phase} } {
\ForEach{Template **k** in memory} {
Accumulate \\(p_k\\) with $W_1[n] - T_k[n] $ \tcp*{Get \\(l_1\\) distance for each spike class}
}
}
Find $p_{min}=min{[|p_1|, \: |p_2|, \: |p_3|, \: |p_4|]}$ and Set \\(c\\) to index \tcp*{Find most similar}
\ForEach{Sample **n** in window \tcp*{Training phase} }{
Accumulate \\(K_c[n]\\) with $k_1 \cdot sign(W_1[n] - T_c[n])$ \tcp*{ Adjust most similar class}
\If{ Not all templates generated **and** $Spike \: Count > k_2$ } {
Duplicate exiting templates \;
Set $Spike \: Count$ to 0 \;
}
}
}
\BlankLine
\caption{Incremental K-Means classification}
\label{algo:T2_Kmean}
\end{algorithm}
The implementation considered in Algorithm \ref{algo:T2_Kmean} is relatively straightforward where one section evaluates the generation of new templates and the other adjust existing templates with new data. The template approach in general has good noise performance due to the redundancy in correlated features that average out white noise. There is some usually some concern with respect to the convergence of k-means centroids. Typically due the the fact that noisy sample points may be initialized as new clusters and thereby wasting memory. The method used here is iteratively duplicating centroids after convergence. This minimizes the impact of noisy data in the feature space. As illustrated in Figure 54 during each iteration the centroids converge to mean positions. Due to the morphology that these centroids may be in we generally need more centroids than there are clusters but this approach works well when there are few spike classes. The assumption here is that we are clustering features that are characteristically Gaussian mixtures.
{{< figure src="technical_2/Cdup.pdf" title="Figure 54: Illustration of centroid evolution over several iterations." width="500" >}}
## 37 Complexity Evaluation
Generally the application of these methods should reflect a system level objective. For the configuration used here the memory and algorithmic operations are estimated in Table 7. Multiplications are equivalent to eight elementary operations and the memory calls are not considered as a computation but as load/store cycles. The impression made here is that template matching is strictly very efficient if the the memory allows large allocation of active spike waveforms. Similarly RVD could show a considerable reduction in operations if a dedicated multiplier is introduced but that depends on how much we value compactness over execution speed. The disparity in memory requirement will dramatically worsen when the number of centroids is increased which is not the case for the computational complexity in RVD.
Table 7: Estimation on memory and computational resource requirements for each algorithm.
| **Algorithm** | **Memory** | **Operations** | **cycles per sample** |
|----|----|----|----|
| NEO Peak Detection | 20 Elements | 30 | 56 |
| RVD / training | 63 Elements | 29 / 88 | 57 / 116 |
| Template / training | 85 Elements | 9 / 16 | 27 / 34 |
{{< figure src="technical_2/P05.pdf}" width="500" >}}
{{< figure src="technical_2/D05.pdf}" title="Figure 55: RVD and template based classification for data sets with \\(-26 dB\\) background activity." width="500" >}}
{{< figure src="technical_2/P01.pdf}" width="500" >}}
{{< figure src="technical_2/D01.pdf}" title="Figure 56: RVD and template based classification for data sets with \\(-20 dB\\) background activity." width="500" >}}
{{< figure src="technical_2/P02.pdf}" width="500" >}}
{{< figure src="technical_2/D02.pdf}" title="Figure 57: RVD and Template based classification for data sets with \\(-16 dB\\) background activity." width="500" >}}
The empirical results in Figure 56 generally show that in moderate noise conditions our classification accuracy is typically better than $85 %$ which is calculated in terms of the aggregate probability of correct classification multiplied with the probability of missing a spike event. Unsurprisingly RVD is not very effective in noisy conditions where the variance accentuates irrelevant components. The classification accuracy from template matching is also shown in Figure 57. These results should primarily show an improved noise rejection characteristic but more generally this approach is more resilient at dealing with false positives. In principle a new cluster will be assigned to a zero mean template representing the false positives while maintaining the other templates intact. Strictly the detection circuit should be readjusted to favour increased detection of false positives as long as the rate of false negatives remains low. But instead exactly the same parameters are used for every test.
We should be careful to judge the effectiveness of these implementations particularly with respect to efficiency. While we can generally increase performance by allocating more memory or introducing additional computation we need to quantitatively evaluate the objective. We suggest normalizing the resource allocation with respect to increased information extracted from the signal by classifying. That is how much more processing are we allocating for classification by proportionally increasing the signal to noise ratio of our output. In the optimistic case when the three classes neurons being detected are uncorrelated our base-line accuracy would be \\(33%\\) while needing \\(56\\) cycle of operation for spike detection. In fact this leads us to believe both algorithms in this respect decrease resource efficiency by a factor around \\(2\\) accounting for an increased memory, processing requirement compensated with increased accuracy. While this claim is very sceptical with respect to the motivation for classifying spike events it also reasons the aggressive reduction in algorithmic complexity through approximations presented here. There is genuine benefit in classification that assists the convergence of further processing algorithms. In addition we simply argue that excessive dedication of resources that exceed that needed for signal conditioning may not be worth while. They key point demonstrated here is that these methods appear very much attainable in terms of on-chip processing capacity. Here we considered the case without supervision specifically in consideration for scalability. It is likely that further reductions or optimizations can be made in that regard to the structure of these methods to improve accuracy and noise tolerance.
# 38 System Architecture
The conceptual architecture of the system proposed here is foremost based on the opportunity for software defined real-time instrumentation that has not yet be exploited in chronic implantable systems at this scale. Currently it is common place to see synthesized logic that performs all processing and data handling procedures in such a way that they have very limited high-level reconfigurability. This is strictly in order to save power and reduce complexity at the system level. It is important to note that for any recording device there are a multitude of phases during its operation where this flexibility can be highly advantageous once sensor characteristics are learned. Like discussed in Section 32 many classification algorithms benefit from training or characterizing the recording conditions.
The approach to specialized DSP in the literature reflects two problems in this field. The first is signal extraction from recordings that relates to what we have discussed in terms of spike detection to extract compressed spike train data. The other is associated with accelerating adaptive filters that map these spike trains on to estimates for cognitive dynamics or invoked limb movement. Typical examples for spike sorting are fully synthesized cores [^49] [^158] that can be integrated and are capable in achieving respectable processing capacity for specific algorithms. In contrast to spike train decoding that is predominantly performed by FPGAs as integration make less sense for the development high dimensional adaptive filters like [^159] that do not need to be embedded within body. Interestingly the work in [^40] proposes a application specific instruction set processor (ASIP) that similarly argues for high performance computation for these structures with a high degree of flexibility that reflects the different models used for spike encoding. Additionally we see the advantage of using off-chip microcontrollers like MSP430 that interface with a highly reconfigurable instrumentation front-end to leverage both adaptive and involved noise shaping to perform more intricate operations such as seizure detection or artefact removal [^160]. While these works may not be viable for high channel count implantable devices it does highlight the considerations for designing fully integrated prosthetics that is in-line with this work.
Here we will consider a particular type of microcontroller topology that can support reconfigurable functionality and reflects the fact that although multichannel BMIs are highly parallel in nature the associated processing can also be algorithmically intensive. The feasibility of this notion has been estimated to an extent but many components are subject to implementation. In essence we optimistically approach this design problem with a strategy that exploits both the homogeneity in processing and the information locality in order to realize a feasible solution. This lets us focus on the in-channel operation where efficiency is maximized through the topology of the execution unit. Regardless of the end result this proposed system will be one step towards the goal for more effective chronic neural implants.
## 39 Distributed System
The system illustrated in Figure 58 represents the distributed microcontroller architecture. The primary mechanism of operation is the program memory that continuously feeds the stored instructions into the pipelined array of processors that operate locally on the recorded data. The execution of these instructions is handled with what is essentially a instruction decoder, memory module and an arithmetic unit that is interfaced with four analogue recording channels. This approach guarantees that the absolute minimum amount of energy is required for the communication of recorded data as the information is processed and consolidated to its elementary component at the quantization interface.
{{< figure src="technical_2/Sys_sH.pdf" title="Figure 58: Illustration of the proposed distributed \\(\mu\\)C array for homogeneous program execution at the sensor interface." width="500" >}}
Inherently this implementation will sacrifice the availability of more intricate functionality found in DSPs since the data is not funnelled into one processing unit that can be very elaborate in complexity. The distributed structure is rationalized by the fact that the intensive operations such as clustering methods operate at a much lower speed due to the sporadic spiking activity that make statistical convergence slow. Furthermore these adaptations need to be performed on the order of minutes by which such functions may also be implemented through the redundancy of elementary operations. Moreover multiplexing loses effectiveness in memory intensive applications as it does mitigate the power & area scaling associated with memory allocation.
Also consider that the program control that gives this implementation its capability for generic computation does not scale with the number of processing units. This is an important distinction when addressing a hundreds of channels on chip that will allow this implementation to outperform any other architecture and leverage the fully integrated form factor. We also note that whether this architecture is realized by synthesized logic, FPGA fabric, or more custom logic cells is insignificant to the extent that the memory structure plays a more profound role. This claim is based on the algorithms in Section32 that allocate significantly more resources to memory than algorithmic operators. In particular memory density and efficiency is a critical component to the success of this type of large scale sensor system. Here 3-T eDRAM is employed which is more effective than alternative solutions memory solution and can still be realized on a standard CMOS process [^161]. When compared to an SRAM equivalent we find it can readily achieve a factor 8 improvement in density [^162].
{{< figure src="technical_2/NPI_TLT2.pdf" title="Figure 59: System architecture for NPI sensing platform with digital interfaces annotated." width="500" >}}
The high-level interfaces are illustrated in Figure 59. There are multiple layers with respect to how internal resources are accessed for reconfiguration. This is primarily for robustness where each layer increases in complexity and chance of failure. The low-speed interface is the simplest element which acquires commands from an external device with very relaxed requirements on input timing. These commands allow us to reconfigure the high level sub-blocks like tuning the generated reference voltages provided by the power management, control reset/power of individual sub-blocks and selecting which digital test signals should be monitored. In particular the processor array and program memory layers almost operate in isolation to the peripherals. These blocks are timed by the internal PLL structure that drives significantly higher data rates that do not need to propagate to the pad level in order to save power. The back-end of the system similarly communicates data uni-directionally between two different clock domains to send data packets off-chip using a number of handshaking protocols.
The implementation of the analogue circuitry has been discussed in Section 23 where we additionally constrain all algorithms to a maximum of 1024 cycles per sample while maximally allocating \\(128\\) words of memory. With respect to our previous discussion this amount of hardware should allow a large set algorithms that are resource efficient. If not the topology will promote the construction of processing with more aggressive memory efficiency and using feedback dynamics to implement more complex operators such as division. It should be noted that these specifications have flexibility by sampling multiple times per program cycle or reducing the system clock using the configurable phase locked loop in order to reduce power.
{{< figure src="technical_2/Lay_sH.pdf}" width="500" >}}
{{< figure src="technical_2/Lay_sH.png}" title="Figure 60: Physical implementation of NPI system using a 6-metal $0.18 \mu m$ CMOS process. " width="500" >}}
Figure 60 presents the fabricated prototype device. It can be seen that integrating many peripheral blocks such as a phase locked loop, voltage supply regulators, and program memory on chip minimizes the pad count required for the digital and power domains. However even for a 64 channels system the number of analogue pads required for the sensor interface play a significant role on top level organization. In addition careful consideration has to be made with respect to how the digital signals propagate where minimizing track length not only reduces digital noise coupled to the substrate but more significantly the associated power dissipation. The number of processing elements can in fact quite easily be scaled up by extending the instruction pipeline where the system level timing constraint for speed and fanout lies with the program memory which has an internal pipeline that needs to connect the program memory together.
## 40 Processing Core
In order to allow the hardware to provides generic processing capabilities in a distributed fashion a number of considerations have to be made. In particular we need to reflect the typical operations with certain modalities of operation. It is clear that although all recording channels should execute the same algorithm they will typically not share the same state of operation. This state dependency is exemplified with respect to intermittent processing during bursting neural activity and idling during quiet periods. This is an inherent limitation to sharing the program memory as the dynamic execution of the code where each core has its own program counter or a top level scheduler is not feasible for an arbitrary number of channels. The quasi-out-of-order execution makes it challenging for us to adopt scalable tile structures found in image processing [^105] that excel in maximizing area and power efficiency in a scalable sense.
Lead by maximizing the locality of data execution [^163] where this aspect of branch control or conditional execution is mediated by skipping a section of the incoming instructions if a condition is not met. The approach of skipping sections of code up on branching is relatively in-efficient with respect to throughput. This approach is optimal at the system level when individual cores may need to execute any section code and branching will only be limited by the dissipation related to the registers pipe-lining the instructions across the chip.
{{< figure src="technical_2/Sys_uC.pdf" title="Figure 61: Organization of the distributed execution unit detailing components and the interconnect." width="500" >}}
The individual components of the execution unit are shown in Figure 61 and details the main data buses used for exchanging data. The majority operations revolve around manipulating data in the registers R1-R16 as A operand in association with any other data sources that can be used as B operand. The operation performed by the arithmetic logic unit (ALU) will always overwrite the result to the location of the A operand but can in extension also be used to to write to other locations (i.e. memory, periphery, etc.). This implies that in terms of instructions there are always two components where the first is simply the operation executed by the ALU in addition to the two memory sources. The second component optionally extends this simple functionality by writing these intermediate values to multiple other locations or arbitrary branching operations that will take the unit out of sleep.
On that note we mention that the local execution controller consists of three registers that assist in branching operations or conditional execution. When either of these registers have logic one the instruction is gated by a null operation before execution. One of these registers will self reset allowing for if-else functionality by skipping a single instruction. The two other registers need to be cleared actively but in combination this will allow for nested conditioning of up to three levels. While in idle state no internal registers are clocked with the exception of the instruction pipeline and the branch controller saving a significant amount of power as the instruction does not need to be decoded.
The digital data interface provides the means for communicating data either off chip or to adjacent execution units. This functionality allows granular consolidation of features or signal structure and correlate measurements with system level parameters. For example consider each execution unit is listening to the most informative analogue instrumentation channel, it is conceivable that comparing its spike train with that of an adjacent units to evaluate neural interconnect level features. The Asynchronous data bus on the other hand is a key feature that allows this system to appear as a slave at the network level that does not need to be coherent with the system or off-chip clock. This bus is in essence a large buffer distributed across many channels utilising asynchronous hand-shake protocols to funnel the data to a SPI module that is clocked either externally or internally [^164]. This solves a number of coherence problems that mitigates the need of having a FPGA to drive this system as the SPI module is not timing critical. Furthermore this alleviates clock distribution as the timing constraints are always local to each execution unit and not the data bus that is distributed across the chip which may either be very restricting or power intensive.
The dynamic control with respect to the analogue channel is enabled by one designated 8 bit register per analogue channel. In this particular case 4 bits are used to specify gain, 2 bits for configuring the biasing current as 0x,1x,2x,3x, and 1 bit of the reset function. In particular the reset phase will temporarily boost the transconductance on the band-limited filtering stage to allow sub-microsecond auto-zero for active noise shaping. For both the ADC and the amplifiers there is one bit that controls a multiplexer at the input that can switch in the sensor or a global differential test net for calibration or verification. Similarly the ADC has 2 bits to select which analogue channel another bit to clock at the full rate or half the rate of ad joint micro-controller. In addition there are 3 bits to control the how the chopper frequency is divided from the sampling signal which is the final control bit. Understandably the analogue configuration will remain static after the appropriately being set. The ADC configuration register is considerably more dynamic as the multiplexer needs to be reconfigured and sampling needs to toggle persistently.
There are two modes of getting quantized data from the ADC depending on the desired functionality. The first is simply reading the 8 bit quantization register that shadows the 7bits quantized by successive approximation and the LSB from the first integration result. In order to utilize the higher resolution capability the comparator output is used to integrate coefficients from the instruction onto a local register where the comparators will decrement or increment the register accordingly. If no calibration data is locally stored this operation first integrates binary weights on one register during the SAR cycles and then integrates the FIR window onto another register. This is large investment of cycles to perform high resolution quantization but this can be optimized for specific applications when it is necessary. If the calibration data is available for the 7 SAR weights then the ADC must be configured to run at half the system speed and before quantization these weights are loaded from the memory onto registers R2-R7. Followed by the usual process of SAR quantization while these weights as simultaneously also integrated on a second register. Then after the integration phase three registers will contain quantized data. The scaling of coefficients is key and should be such that the $\Sigma \Delta$ result simply copies the sign bit of the SAR operation and can concatenate the lower 7 bits with the SAR result. Then the calibration data is scaled appropriately and added to the 14bit signed double with carry logic. Clearly there a number of conventions suggested here that will best exploit the capabilities of the design.
The memory module local to each execution unit hold 128 words of data which can be shared across the analogue channels with 32 locations each. Particularly when the DSP is mainly performing filtering the recorded data can be buffered for FIR filtering or keep its high precision filter state variables for IIR structures. These filter and program coefficients are stored in the shared program memory such that the execution unit does not experience an overhead in memory requirement. However for other memory intensive algorithms such as template matching, serving the most informative of the four analogue channels will have to suffice because the memory requirement is beyond the capabilities of this configuration. The DRAM architecture has a refresh-up-on-read mechanism which implies that the used memory locations will have to systematically be read to keep the data stored valid. Fortunately this requirement is self fulfilling as the program recycles itself every $100 \mu s$ and the DRAM retention time is on the order of $1 m s$ implying that as long as there is a guaranteed read on the memory location it will stay valid. The physical read mechanism however does require a minimum of two cycles. The first is in the background which simply prepares the internal registers of the module while a different execution is taking place and the second is in the foreground where the location is read and the data bus is driven by the DRAM.
{{< figure src="./technical_2/Lay_uC.pdf}" width="500" >}}
{{< figure src="./technical_2/uCm.png}" title="Figure 62: Physical implementation of execution unit using a 6-metal $0.18 \mu m$ CMOS process " width="500" >}}
As the illustration in Figure 62 shows, keeping the 8 bit structure in terms of parallel operations maintains a very compact floor plan. This is typical of data flow intensive designs where the digital logic should be placed underneath the associated data buses. This is difficult to replicate by automated synthesis tool where signal congestion is the most stringent aspect. The digital signals for the two operands and the data line span horizontally where sub-blocks extensively take advantage of the gated output buffers for each sub-block that is controlled by the decoders. The full custom approach taken here sacrifices design effort for additional performance in terms of reduced parasitics and more aggressive power gating.
$$ \mbox{\textbf{\textless C\textgreater,[\textless CE\textgreater],\textless A\textgreater,\textless B\textgreater,[\textless OE\textgreater*]}} $$
The syntax for constructing instructions needs to be in the Backus Normal Form [^165] as formatted in Equation35 with reference to Table 8 which summarises all possible compositions. A parser is implemented that will translate an ordered set of these instructions directly into hardware specific machine code that needs to fed into the instruction pipeline any violations or exceptions will be caught by this script automatically. Although there is no dedicated multiplication hardware there are specialized registers that allow shift add based multiplication over eight cycles. Any other primitive logical or arithmetic function can be realized with this instruction set as it is turning-complete. This assertion is made by noting that it can evaluate the operation; subtract and branch if less than or equal to zero, which is sufficient for a one instruction set computer [^166].
Table 8: Overview of instruction sub-components.
| **Index** | **Operation Subset** | **Summary of Possible Entries** |
|----|----|----|
| C | Logic Operation: | Logical Shift Left/Right, Arithmetic Shift Left/Right, XOR, XNOR, AND, OR, MOVE-A, MOVE-B |
| C | Arith. Operation: | Compare, Add, Carry Add, Multiply, Complete Multiply |
| CE | Compare Option: | \textgreater, =, \textless, Overflow |
| CE | Add Option: | Subtract, Absolute Value, Increment Overflow Bit |
| CE | Mov Option: | Mem. Address is from Data line. Default is from Instruction |
| A | Operand A: | R1-R8, R9-R13, ID, Count, Memory |
| B | Operand B: | R1-R8, Left uC, Right uC, Instruction, ADC, Memory, Null |
| OE | IO Extension: | Write to Left uC, Write to Right uC, ADC Sample enable, Write Output Buffer |
| OE | Branch Extension: | Write to Branch Register BR1-BR3, Invert Branch Result |
| OE | Memory Extension: | Write Address, Write Data, Read Data |
It should be mentioned that there a number of hardware specific details with respect to how certain instructions behave that need careful consideration towards the implementation details. For example if no comparison is made but a branch register is accessed the output of the comparator will be treated as false no matter what logic the overflow bit is. This allows us to clear or set branch registers while simultaneously performing an operation. Another example is that by default the instruction data is ready at the input of the memory address to prepare a read in the background. In most cases it is intuitive and we simply strive to maximize the cycle efficiency. At all times the execution unit is capable of dealing with the compute aspects while performing branching and memory access simultaneously.
This work also provides an elaborate set of test tools that allows compilation of instruction code and the generation of piece-wise-linear 'csv' files for test sources that can be used in the circuit simulators. This can be used in association with the transistor or verilog implementation of the processing core. The behavioural models in particular are important for the translation of this architecture to other implementations.
{{< figure src="./technical_2/uC_PS.pdf" title="Figure 63: Power dissipation with respect to specific operations for the same operand A=113 & B=114 in randomized order." width="500" >}}
The results in Figure 63 exemplifies the dependency of power dissipation with respect to different operators for the same operand A and B. It should be expected that the is a strong operand dependency with respect to power consumption but these results follow our expectations closely. Generally the simpler the operation the lower the current dissipation is because less complexity is involved with the switching losses. Here again we observe that when the unit is in a sleep or branching state the power dissipation is mainly associated with the instruction pipeline. As this 32bit pipeline transverses the entire execution unite it plays a significant contribution towards the baseline power consumption. The typical power consumption for full activity will lie around $45 \mu A$ it should be noted that sporadic spiking activity will gate the majority of operations and it is likely that running at half the designed rate with 512 cycles is more than sufficient. Note the typical figure of power is \\(2.7 pJ/Cycle\\) or $2.7 \mu W/MIPS$ which is several orders of magnitude better than 16-bit microcontrollers such as the MSP-430[^167].
Table 9: Summary of performance specifications for the NPI system and state-of-the-art specialized integrated processing architectures. \\(^\star\\) Reconfigurable topology.
| Parameter | Unit | This Work | Markovic [^168] | Arimoto [^105]|
|----|----|----|----|----|
| Architecture | | Distributed (\mu)C Array | Multi-Grain FPGA | Dedicated Tile Array|
| Technology | [nm] | 180 | 40 | 65 |
| Supply Voltage | [V] | (1.2) | (1) | (1.2)|
| Parallel Units | | (64) | (16^\star) | (2048)|
| Instruction Size | [bits] | (32) | - | (32) |
| Operational Frequency | [MHz] | (20) | (400) | (300) |
| Sampling Frequency | [S/s] | (32k) | (100M) | - |
| Operations per Sample | [Cycles] | $256 $ | (4) | - |
| (P_{Digital}) per Channel | [(\mu)A] | (44) | - | -|
| (P_{Analogue}) per Channel | [(\mu)A] | (16) | - | - |
| System Power | [mA] | (1.42) | $ 11.6 $ | (300)|
| Program Memory Capacity | [kb] | (32) | - | - |
| Processor Memory Capacity | [kb] | (1) | (36) | (1) |
| Processor Array Area | [mm(^2)] | $1.04 \times 1.32$ | $3.8 \times 5.4$ | $1.60 \times 3.19$ |
| Power Efficiency | [GOPS/mW] | (1.52) | $ 0.86 $ | (0.31) |
| Area Efficiency | [GOPS/mm(^2)] | (0.88) | $ 2.34$ | (36.1)|
The specifications given in Table 9 summarize the main features associated with this system on chip for processing neural data at the sensor interface. As the total power consumption is on the order of \\(1.5 mW\\) there is some concern with respect to the power density associated with the system in full operation that in this particular case is \\(26 mW/cm^2\\). In fact if the number of channels is scaled up beyond 64 channels this power density will tend to \\(29 mW/cm^2\\) but will not exceed it. Either figure will likely be smaller subject to the physical & software implementations but more importantly will not result in a thermal agitation or the heating of cortical tissue that exceeds \\(2^{\circ}C\\) [^68]. More generally we have the advantage of tuning processing capabilities to the heat-capacity of the implanted package. In fact comparing this work to state of the art FPGA topologies[^168] and highly parallel ASIC structures[^105] that follow the same design methodology we find that power and area efficiency that exceeds that of stand-alone microprocessors by orders of magnitude. These figures also reflect the expectation that technology scaling should lead to even more compact configurations. In addition Gate leakage may introduces some diminishing returns with respect to power efficiency. We mention that these figures are extrapolated based on the performance of a single execution unit and we expect more overhead from other components that is not accounted for in this comparison.
$$ R_{D} = \frac{P_{\mu C} \cdot A_{\mu C}}{N^{2}_{chan} \cdot Cycles} = \frac{44 \mu W \cdot 196 \times 158 \mu m^2} {4^2 \cdot 256}\approx 3.3 \cdot 10^{-16} \: \left[W mm^2 \: per \: OP \right] $$
Re-evaluating our power/area figure of merit in Figure 49 with Equation 36 we observe that practically we lose a factor of ten in efficiency when compared to a dedicated ASIC implementation because resource utilization inside the execution unit can not be maximized. This was expected given that instead we attain high-level reconfigurability. However this does achieve a very good understanding with regard to where the system scales from this point both with respect to area and power requirements.
## 41 Testing Platform
As this system is directed at generic use for the neuroscience community where high level programming and interfaces are essential for end user adoption. The testing platform presented here is aligned in such a fashion that its fundamental components can be extended upon greatly to serve a multitude of needs. This ambitious design criteria is primarily provided by the real-time platform illustrated in Figure 64 that supports a standard Linux operating system. The thee components compromise of the custom NPI system on chip, the Raspberry Pi platform, and networked resources.
{{< figure src="technical_2/Sys_iP.pdf" title="Figure 64: Block diagram of the instrumentation platform developed as framework for real-time applications." width="500" >}}
The software stack running on the Raspberry Pi primarily handles the high speed SPI link that fetches data from the NPI system at \\(10 Mb/s\\) and stores it to a local buffer for some of the data visualization. This data stream is then forwarded to a network routine that is connected to a server over the local area network via a UDP protocol to allow large quantities of data to be stored in a scalable fashion. The graphical user interface is built on top of this process in order to give a means to both configure the device actively and provide some form of interactive interrogation with respect to the recorded data and the algorithm being executed.
The application of a generic internet of things platform plays a important role with respect to long term development objectives. It signifies that the ASIC is there to provide a specialized interface with the sensor and a generic digital interface with the external control to allow rapid adoption of new techniques or other components as software extensions. This substantiates the modular approach where design effort is explicitly focused towards specialized hardware for the sensor and software development at the system level. This is important given the complexity of these systems where overspecialisation limits the versatility of existing designs thereby limiting the utility of other commercially available tools/devices.
The advantage here is that a multitude of procedures can be run on the real-time platform without supervision that are detailed in high-level programming code that have fast development and turn-around capabilities. In this case it significantly improved test procedures by enabling automated exhaustive characterization of logical integrity. In fact the standalone module of the microcontroller structure can run 1 MIPS of on the fly randomly generated operations. This can be seen in Figure 65 where the Saleae logic analyser is used to probe the internal data bus of one particular core.
{{< figure src="technical_2/Scope.png" title="Figure 65: Digital waveform of the internal data bus BIT 1-8 as new instructions are being loaded into the device using the clocked Latch and Configure signals." width="500" >}}
Table 10: Section of Instructions and recorded outputs from $\mu C$ structure with the associated machine code.
| **BITLINE**| **INSTRUCTION** | **Machine Code** |
|----|----|----|
| 00011010 | MOVB R5 DINST 26 |0011111100000000011000000011010|
| 11101111 | MOVA R3 DINST -17 |0011011000000000011010011101111|
| 00001010 | AND R5 R3 |1110111100000000000000000000000|
| 00011010 | MOVB R5 DINST 26 |0011111100000000011000000011010|
| 11101111 | MOVA R3 DINST -17 |0011011000000000011010011101111|
| 11111111 | OR R5 R3 |1110111100000000000010000000000|
| 00011010 | MOVB R5 DINST 26 |0011111100000000011000000011010|
| 11101111 | MOVA R3 DINST -17 |0011011000000000011010011101111|
| 11110101 | XOR R5 R3 |1110111100000000000100000000000|
This is partly shown in Table 10 where the internal bit-line of one such execution unit could be directly accessed. Because it is not viable for us to exhaustively simulate the hardware in various conditions we use a physical test bench in order to record the performance tolerance with respect to voltage supply and operating frequency. Moreover what the user sees is reduced to latent frames of data over several milliseconds and the corresponding instruction code executed by the platform. The physical interfacing protocols are very much transparent. By construction each core has a hard wired ID that will allow the active supervision of internal variables for development and debugging of single units. Due to the specialized hardware the instrumentation programs currently still require careful tailoring of the instruction code but this can be extended towards compiling directly from C++ code that is also used to construct the rest of the platform.
{{< figure src="technical_2/TPlat.pdf" title="Figure 66: Graphical user interface used for configuring the NPI system showing test data." width="500" >}}
Figure 66 depicts the GPU accelerated graphical set-up used for testing the device where the functionality is mainly associated with reconfiguration and powering different system sub-blocks for validation. From a engineering point of view it is more of a convenience to have automated reconfiguration of the device as one interacts with the various settings. Particularly in associated with probing the supply voltages or analogue reference signals generated on chip. It would be more typical that during experimentation this functionality can be reduced to simply selecting from a set of predetermined programs.
{{< figure src="technical_2/TPhw.pdf" title="Figure 67: Test bed used for characterization with various components illustrated." width="500" >}}
In order to move towards fully isolated operation which will be the case for a implanted device the system on chip architecture relies on a minimum amount of off-chip components in order to bring the resource requirements of the topology into scope. This is shown in Figure 67. These feasibility considerations are generally with respect to reasonable assumptions associated with a wireless implant that is hermetically sealed. In this particular case we will allow a number of off-chip decoupling capacitors, a reference resistor and a reference voltage which may very well be integrated on chip in one way or another if necessary. The system also uses a \\(1 MHz\\) external clock reference which may be realized at the wireless power carrier frequency and is locked onto with a phase locked loop to generate the internal \\(20 MHz\\) system clock. Three linear LDOs were integrated to provide a \\(1.2 V\\) supply to the digital,analogue, and memory separately. Where the analogue supply voltage used to derive internal ADC voltages references of \\(1.2 V,0.9 V,0.6 V,0.3 V\\) from the unregulated supply using high speed buffers.
# 42 Conclusion
This chapter substantiates a scalable and long-term approach for the development of programmable neural interfaces. In particular we discuss why moving away from the fixed purpose DSP architectures seen in many conventional systems is of significance with respect to performance and reliability. In addition we provide indicators that show the majority of modern CMOS technologies using dedicated on-chip processing hardware is viable to perform local signal analysis. Furthermore we highlight the importance of efficient algorithm construction were operators should revolve around execution per sample and processing structures that improve scalability for systems with many recording channels in association with the near-data-processing paradigm. PCA & template maching methods are proposed for embedded systems that require 57 operations per sample and 680 bits of memory with entirely unsupervised operation that can achieve over 80% accuracy during spike detection & classification.
A distributed micro-controller structure is proposed in effort to realize these characteristics and reveal underlying constraints. The topology reflects the nature of processing neural data in the context of achieving generic computational capacity. This discussion details both low-level and system level considerations that address the software stack. The impact of memory requirement that results from being able to execute arbitrary algorithms in isolation is evident both in-channel and chip level. In the proposed configuration the amount of resources allocated for this function is comparable to that of the signal processing but depends very much on the number of channels that are integrated together. We point out that if the number of channels is increased this component does not change and allows this topology to become more effective. The distributed processing architecture operates with an efficiency of 1.52 GOPS/mW and each core only requires a 0.02mm\\(^2\\) silicon foot print with fully reconfigurable 8 bit processing capabilities.
The foregoing discussion has depicted the intricate complexity associated with these sensing systems and revealed the diversity of aspects that should be taken into consideration. Sustainable development for these systems will need long-term solutions due to the excessive design effort that prevents rapid turn around and progress. Moreover innovation needs to be contextualized at the system level to ascertain whether new techniques and methods have significant impact. This requires the abstraction and modelling of these implementations to gauge impact using empirical indicators.
# References:
[^1]: R.Q. Quiroga, Z.Nadasdy, and Y.Ben-Shaul, ''Unsupervised spike detection and sorting with wavelets and superparamagnetic clustering,'' Neural Computation, vol.16, pp. 1661--1687, April 2004. [Online]: http://dx.doi.org/10.1162/089976604774201631
[^2]: R.A. Normann, ''Technology insight: future neuroprosthetic therapies for disorders of the nervous system,'' Nature Clinical Practice Neurology, vol.3, pp. 444--452, August 2007. [Online]: http://dx.doi.org/10.1038/ncpneuro0556
[^3]: K.Birmingham, V.Gradinaru, P.Anikeeva, W.M. Grill, B.Pikov, VictorMcLaughlin, P.Pasricha, K.Weber, DouglasLudwig, and K.Famm, ''Bioelectronic medicines: a research roadmap,'' Nature Reviews Drug Discovery, vol.13, pp. 399--400, May 2014. [Online]: http://dx.doi.org/10.1038/nrd4351
[^4]: ''Bridging the bio-electronic divide,'' Defense Advanced Research Projects Agency, Arlington, Texas, January 2016. [Online]: http://www.darpa.mil/news-events/2015-01-19
[^5]: G.Fritsch and E.Hitzig, ''ber die elektrische erregbarkeit des grosshirns,'' Archiv für Anatomie, Physiologie und Wissenschaftliche Medicin., vol.37, pp. 300--332, 1870.
[^6]: G.E. Loeb, ''Cochlear prosthetics,'' Annual Review of Neuroscience, vol.13, no.1, pp. 357--371, 1990, pMID: 2183680. [Online]: http://dx.doi.org/10.1146/annurev.ne.13.030190.002041
[^7]: ''Annual update bcig uk cochlear implant provision,'' British Cochlear Implant Group, London WC1X 8EE, UK, pp. 1--2, March 2015. [Online]: http://www.bcig.org.uk/wp-content/uploads/2015/12/CI-activity-2015.pdf
[^8]: M.Alexander, ''Neuro-numbers,'' Association of British Neurologists (ABN), London SW9 6WY, UK, pp. 1--12, April 2003. [Online]: http://www.neural.org.uk/store/assets/files/20/original/NeuroNumbers.pdf
[^9]: A.Jackson and J.B. Zimmermann, ''Neural interfaces for the brain and spinal cord — restoring motor function,'' Nature Reviews Neurology, vol.8, pp. 690--699, December 2012. [Online]: http://dx.doi.org/10.1038/nrneurol.2012.219
[^10]: M.Gilliaux, A.Renders, D.Dispa, D.Holvoet, J.Sapin, B.Dehez, C.Detrembleur, T.M. Lejeune, and G.Stoquart, ''Upper limb robot-assisted therapy in cerebral palsy: A single-blind randomized controlled trial,'' Neurorehabilitation AND Neural Repair, vol.29, no.2, pp. 183--192, February 2015. [Online]: http://nnr.sagepub.com/content/29/2/183.abstract
[^11]: P.Osten and T.W. Margrie, ''Mapping brain circuitry with a light microscope,'' Nature Methods, vol.10, pp. 515--523, June 2013. [Online]: http://dx.doi.org/10.1038/nmeth.2477
[^12]: S.M. Gomez-Amaya, M.F. Barbe, W.C. deGroat, J.M. Brown, J.Tuite, Gerald F.ANDCorcos, S.B. Fecho, A.S. Braverman, and M.R. RuggieriSr, ''Neural reconstruction methods of restoring bladder function,'' Nature Reviews Urology, vol.12, pp. 100--118, February 2015. [Online]: http://dx.doi.org/10.1038/nrurol.2015.4
[^13]: H.Yu, W.Xiong, H.Zhang, W.Wang, and Z.Li, ''A parylene self-locking cuff electrode for peripheral nerve stimulation and recording,'' IEEE/ASME Journal of Microelectromechanical Systems, vol.23, no.5, pp. 1025--1035, Oct 2014. [Online]: http://dx.doi.org/10.1109/JMEMS.2014.2333733
[^14]: J.S. Ho, S.Kim, and A.S.Y. Poon, ''Midfield wireless powering for implantable systems,'' Proceedings of the IEEE, vol. 101, no.6, pp. 1369--1378, June 2013. [Online]: http://dx.doi.org/10.1109/JPROC.2013.2251851
[^15]: R.D. KEYNES, ''Excitable membranes,'' Nature, vol. 239, pp. 29--32, September 1972. [Online]: http://dx.doi.org/10.1038/239029a0
[^16]: A.D. Grosmark and G.Buzs\'aki, ''Diversity in neural firing dynamics supports both rigid and learned hippocampal sequences,'' Science, vol. 351, no. 6280, pp. 1440--1443, March 2016. [Online]: http://science.sciencemag.org/content/351/6280/1440
[^17]: B.Sakmann and E.Neher, ''Patch clamp techniques for studying ionic channels in excitable membranes,'' Annual Review of Physiology, vol.46, no.1, pp. 455--472, October 1984, pMID: 6143532. [Online]: http://dx.doi.org/10.1146/annurev.ph.46.030184.002323
[^18]: M.P. Ward, P.Rajdev, C.Ellison, and P.P. Irazoqui, ''Toward a comparison of microelectrodes for acute and chronic recordings,'' Brain Research, vol. 1282, pp. 183 -- 200, July 2009. [Online]: http://www.sciencedirect.com/science/article/pii/S0006899309010841
[^19]: J.E.B. Randles, ''Kinetics of rapid electrode reactions,'' Discuss. Faraday Soc., vol.1, pp. 11--19, 1947. [Online]: http://dx.doi.org/10.1039/DF9470100011
[^20]: M.E. Spira and A.Hai, ''Multi-electrode array technologies for neuroscience and cardiology,'' Nature Nanotechnology, vol.8, pp. 83 -- 94, February 2013. [Online]: http://dx.doi.org/10.1038/nnano.2012.265
[^21]: G.E. Moore, ''Cramming more components onto integrated circuits,'' Proceedings of the IEEE, vol.86, no.1, pp. 82--85, January 1998. [Online]: http://dx.doi.org/10.1109/JPROC.1998.658762
[^22]: I.Ferain, C.A. Colinge, and J.-P. Colinge, ''Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors,'' Nature, vol. 479, pp. 310--316, November 2011. [Online]: http://dx.doi.org/10.1038/nature10676
[^23]: I.H. Stevenson and K.P. Kording, ''How advances in neural recording affect data analysis,'' Nature neuroscience, vol.14, no.2, pp. 139--142, February 2011. [Online]: http://dx.doi.org/10.1038/nn.2731
[^24]: C.Thomas, P.Springer, G.Loeb, Y.Berwald-Netter, and L.Okun, ''A miniature microelectrode array to monitor the bioelectric activity of cultured cells,'' Experimental cell research, vol.74, no.1, pp. 61--66, September 1972. [Online]: http://dx.doi.org/0.1016/0014-4827(72)90481-8
[^25]: R.A. Andersen, E.J. Hwang, and G.H. Mulliken, ''Cognitive neural prosthetics,'' Annual review of Psychology, vol.61, pp. 169--190, December 2010, pMID: 19575625. [Online]: http://dx.doi.org/10.1146/annurev.psych.093008.100503
[^26]: L.A. Jorgenson, W.T. Newsome, D.J. Anderson, C.I. Bargmann, E.N. Brown, K.Deisseroth, J.P. Donoghue, K.L. Hudson, G.S. Ling, P.R. MacLeish etal., ''The brain initiative: developing technology to catalyse neuroscience discovery,'' Philosophical Transactions of the Royal Society of London B: Biological Sciences, vol. 370, no. 1668, p. 20140164, 2015.
[^27]: E.DAngelo, G.Danese, G.Florimbi, F.Leporati, A.Majani, S.Masoli, S.Solinas, and E.Torti, ''The human brain project: High performance computing for brain cells hw/sw simulation and understanding,'' in Proceedings of the Digital System Design Conference, August 2015, pp. 740--747. [Online]: http://dx.doi.org/10.1109/DSD.2015.80
[^28]: K.Famm, B.Litt, K.J. Tracey, E.S. Boyden, and M.Slaoui, ''Drug discovery: a jump-start for electroceuticals,'' Nature, vol. 496, no. 7444, pp. 159--161, April 2013. [Online]: http://dx.doi.org/0.1038/496159a
[^29]: K.Deisseroth, ''Optogenetics,'' Nature methods, vol.8, no.1, pp. 26--29, January 2011. [Online]: http://dx.doi.org/10.1038/nmeth.f.324
[^30]: M.Velliste, S.Perel, M.C. Spalding, A.S. Whitford, and A.B. Schwartz, ''Cortical control of a prosthetic arm for self-feeding,'' Nature, vol. 453, no. 7198, pp. 1098--1101, June 2008. [Online]: http://dx.doi.org/10.1038/nature06996
[^31]: T.N. Theis and P.M. Solomon, ''In quest of the "next switch" prospects for greatly reduced power dissipation in a successor to the silicon field-effect transistor,'' Proceedings of the IEEE, vol.98, no.12, pp. 2005--2014, December 2010. [Online]: http://dx.doi.org/10.1109/JPROC.2010.2066531
[^32]: G.M. Amdahl, ''Validity of the single processor approach to achieving large scale computing capabilities, reprinted from the afips conference proceedings, vol. 30 (atlantic city, n.j., apr. 18-20), afips press, reston, va., 1967, pp. 483-485, when dr. amdahl was at international business machines corporation, sunnyvale, california,'' in AFIPS Conference Proceedings, Vol. 30 (Atlantic City, N.J., Apr. 18-20), vol.12, no.3.\hskip 1em plus 0.5em minus 0.4em elax IEEE, Summer 2007, pp. 19--20. [Online]: http://dx.doi.org/0.1109/N-SSC.2007.4785615
[^33]: J.G. Koller and W.C. Athas, ''Adiabatic switching, low energy computing, and the physics of storing and erasing information,'' in IEEE Proceedings of the Workshop on Physics and Computation.\hskip 1em plus 0.5em minus 0.4em elax IEEE, October 1992, pp. 267--270. [Online]: http://dx.doi.org/10.1109/PHYCMP.1992.615554
[^34]: E.P. DeBenedictis, J.E. Cook, M.F. Hoemmen, and T.S. Metodi, ''Optimal adiabatic scaling and the processor-in-memory-and-storage architecture (oas :pims),'' in IEEE Proceedings of the International Symposium on Nanoscale Architectures.\hskip 1em plus 0.5em minus 0.4em elax IEEE, July 2015, pp. 69--74. [Online]: http://dx.doi.org/10.1109/NANOARCH.2015.7180589
[^35]: S.Houri, G.Billiot, M.Belleville, A.Valentian, and H.Fanet, ''Limits of cmos technology and interest of nems relays for adiabatic logic applications,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.62, no.6, pp. 1546--1554, June 2015. [Online]: http://dx.doi.org/10.1109/TCSI.2015.2415177
[^36]: S.K. Arfin and R.Sarpeshkar, ''An energy-efficient, adiabatic electrode stimulator with inductive energy recycling and feedback current regulation,'' IEEE Transactions on Biomedical Circuits and Systems, vol.6, no.1, pp. 1--14, February 2012. [Online]: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6036003&isnumber=6138606
[^37]: P.R. Kinget, ''Scaling analog circuits into deep nanoscale cmos: Obstacles and ways to overcome them,'' in IEEE Proceedings of the Custom Integrated Circuits Conference.\hskip 1em plus 0.5em minus 0.4em elax IEEE, September 2015, pp. 1--8. [Online]: http://dx.doi.org/10.1109/CICC.2015.7338394
[^38]: K.Bernstein, D.J. Frank, A.E. Gattiker, W.Haensch, B.L. Ji, S.R. Nassif, E.J. Nowak, D.J. Pearson, and N.J. Rohrer, ''High-performance cmos variability in the 65-nm regime and beyond,'' IBM Journal of Research AND Development, vol.50, no. 4.5, pp. 433--449, July 2006. [Online]: http://dx.doi.org/10.1147/rd.504.0433
[^39]: L.L. Lewyn, T.Ytterdal, C.Wulff, and K.Martin, ''Analog circuit design in nanoscale cmos technologies,'' Proceedings of the IEEE, vol.97, no.10, pp. 1687--1714, October 2009. [Online]: http://dx.doi.org/10.1109/JPROC.2009.2024663
[^40]: Y.Xin, W.X.Y. Li, Z.Zhang, R.C.C. Cheung, D.Song, and T.W. Berger, ''An application specific instruction set processor (asip) for adaptive filters in neural prosthetics,'' IEEE/ACM Transactions on Computational Biology and Bioinformatics, vol.12, no.5, pp. 1034--1047, September 2015. [Online]: http://dx.doi.org/10.1109/TCBB.2015.2440248
[^41]: G.Schalk, P.Brunner, L.A. Gerhardt, H.Bischof, and J.R. Wolpaw, ''Brain-computer interfaces (bcis): detection instead of classification,'' Journal of neuroscience methods, vol. 167, no.1, pp. 51--62, 2008, brain-Computer Interfaces (BCIs). [Online]: http://www.sciencedirect.com/science/article/pii/S0165027007004116
[^42]: Z.Li, J.E. O'Doherty, T.L. Hanson, M.A. Lebedev, C.S. Henriquez, and M.A. Nicolelis, ''Unscented kalman filter for brain-machine interfaces,'' PloS one, vol.4, no.7, pp. 1--18, 2009. [Online]: http://dx.doi.org/10.1371/journal.pone.0006243
[^43]: A.L. Orsborn, H.G. Moorman, S.A. Overduin, M.M. Shanechi, D.F. Dimitrov, and J.M. Carmena, ''Closed-loop decoder adaptation shapes neural plasticity for skillful neuroprosthetic control,'' Neuron, vol.82, pp. 1380 -- 1393, March 2016. [Online]: http://dx.doi.org/10.1016/j.neuron.2014.04.048
[^44]: Y.Yan, X.Qin, Y.Wu, N.Zhang, J.Fan, and L.Wang, ''A restricted boltzmann machine based two-lead electrocardiography classification,'' in IEEE Proceedings of the International Conference on Wearable and Implantable Body Sensor Networks.\hskip 1em plus 0.5em minus 0.4em elax IEEE, June 2015, pp. 1--9. [Online]: http://dx.doi.org/10.1109/BSN.2015.7299399
[^45]: B.M. Yu and J.P. Cunningham, ''Dimensionality reduction for large-scale neural recordings,'' Nature Neuroscience, vol.17, pp. 1500 -- 1509, November 2014. [Online]: http://dx.doi.org/10.1038/nn.3776
[^46]: S.Makeig, C.Kothe, T.Mullen, N.Bigdely-Shamlo, Z.Zhang, and K.Kreutz-Delgado, ''Evolving signal processing for brain: Computer interfaces,'' Proceedings of the IEEE, vol. 100, no. Special Centennial Issue, pp. 1567--1584, May 2012. [Online]: http://dx.doi.org/10.1109/JPROC.2012.2185009
[^47]: G.Indiveri and S.C. Liu, ''Memory and information processing in neuromorphic systems,'' Proceedings of the IEEE, vol. 103, no.8, pp. 1379--1397, August 2015. [Online]: http://dx.doi.org/10.1109/JPROC.2015.2444094
[^48]: Y.Chen, E.Yao, and A.Basu, ''A 128-channel extreme learning machine-based neural decoder for brain machine interfaces,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.3, pp. 679--692, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2483618
[^49]: V.Karkare, S.Gibson, and D.Marković, ''A 75- $\mu$w, 16-channel neural spike-sorting processor with unsupervised clustering,'' IEEE Journal of Solid-State Circuits, vol.48, no.9, pp. 2230--2238, September 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2264616
[^50]: T.C. Chen, W.Liu, and L.G. Chen, ''128-channel spike sorting processor with a parallel-folding structure in 90nm process,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2009, pp. 1253--1256. [Online]: http://dx.doi.org/10.1109/ISCAS.2009.5117990
[^51]: G.Baranauskas, ''What limits the performance of current invasive brain machine interfaces?'' Frontiers in Systems Neuroscience, vol.8, no.68, April 2014. [Online]: http://www.frontiersin.org/systems_neuroscience/10.3389/fnsys.2014.00068
[^52]: E.F. Chang, ''Towards large-scale, human-based, mesoscopic neurotechnologies,'' Neuron, vol.86, pp. 68--78, March 2016. [Online]: http://dx.doi.org/10.1016/j.neuron.2015.03.037
[^53]: M.A.L. Nicolelis and M.A. Lebedev, ''Principles of neural ensemble physiology underlying the operation of brain-machine,'' Nature Reviews Neuroscience, vol.10, pp. 530--540, July 2009. [Online]: http://dx.doi.org/10.1038/nrn2653
[^54]: Z.Fekete, ''Recent advances in silicon-based neural microelectrodes and microsystems: a review,'' Sensors AND Actuators B: Chemical, vol. 215, pp. 300 -- 315, 2015. [Online]: http://www.sciencedirect.com/science/article/pii/S092540051500386X
[^55]: N.Saeidi, M.Schuettler, A.Demosthenous, and N.Donaldson, ''Technology for integrated circuit micropackages for neural interfaces, based on gold–silicon wafer bonding,'' Journal of Micromechanics AND Microengineering, vol.23, no.7, p. 075021, June 2013. [Online]: http://stacks.iop.org/0960-1317/23/i=7/a=075021
[^56]: K.Seidl, S.Herwik, T.Torfs, H.P. Neves, O.Paul, and P.Ruther, ''Cmos-based high-density silicon microprobe arrays for electronic depth control in intracortical neural recording,'' IEEE Journal of Microelectromechanical Systems, vol.20, no.6, pp. 1439--1448, December 2011. [Online]: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6033040&isnumber=6075219
[^57]: T.D.Y. Kozai, N.B. Langhals, P.R. Patel, X.Deng, H.Zhang, K.L. Smith, J.Lahann, N.A. Kotov, and D.R. Kipke, ''Ultrasmall implantable composite microelectrodes with bioactive surfaces for chronic neural interfaces,'' Nature Materials, vol.11, pp. 1065--1073, December 2012. [Online]: http://dx.doi.org/10.1038/nmat3468
[^58]: D.A. Schwarz, M.A. Lebedev, T.L. Hanson, D.F. Dimitrov, G.Lehew, J.Meloy, S.Rajangam, V.Subramanian, P.J. Ifft, Z.Li, A.Ramakrishnan, A.Tate, K.Z. Zhuang, and M.A.L. Nicolelis, ''Chronic, wireless recordings of large-scale brain activity in freely moving rhesus monkeys,'' Nature Methods, vol.11, pp. 670--676, April 2014. [Online]: http://dx.doi.org/10.1038/nmeth.2936
[^59]: P.Ruther, S.Herwik, S.Kisban, K.Seidl, and O.Paul, ''Recent progress in neural probes using silicon mems technology,'' IEEJ Transactions on Electrical and Electronic Engineering, vol.5, no.5, pp. 505--515, 2010. [Online]: http://dx.doi.org/10.1002/tee.20566
[^60]: ibitem3d-printH.-W. Kang, S.J. Lee, I.K. Ko, C.Kengla, J.J. Yoo, and A.Atala, ''A 3d bioprinting system to produce human-scale tissue constructs with structural integrity,'' Nature Biotechnology, vol.34, pp. 312--319, March 2016. [Online]: http://dx.doi.org/10.1038/nbt.3413
[^61]: ibitemdistrib-electC.Xie, J.Liu, T.-M. Fu, X.Dai, W.Zhou, and C.M. Lieber, ''Three-dimensional macroporous nanoelectronic networks as minimally invasive brain probes,'' Nature Materials, vol.14, pp. 1286--1292, May 2015. [Online]: http://dx.doi.org/10.1038/nmat4427
[^62]: R.R. Harrison, P.T. Watkins, R.J. Kier, R.O. Lovejoy, D.J. Black, B.Greger, and F.Solzbacher, ''A low-power integrated circuit for a wireless 100-electrode neural recording system,'' IEEE Journal of Solid-State Circuits, vol.42, no.1, pp. 123--133, Jan 2007. [Online]: http://dx.doi.org/10.1109/JSSC.2006.886567
[^63]: J.Guo, W.Ng, J.Yuan, S.Li, and M.Chan, ''A 200-channel area-power-efficient chemical and electrical dual-mode acquisition ic for the study of neurodegenerative diseases,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.3, pp. 567--578, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2468052
[^64]: W.Biederman, D.J. Yeager, N.Narevsky, J.Leverett, R.Neely, J.M. Carmena, E.Alon, and J.M. Rabaey, ''A 4.78 mm 2 fully-integrated neuromodulation soc combining 64 acquisition channels with digital compression and simultaneous dual stimulation,'' IEEE Journal of Solid-State Circuits, vol.50, no.4, pp. 1038--1047, April 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2384736
[^65]: R.Muller, S.Gambini, and J.M. Rabaey, ''A 0.013mm$^2$, $5 \mu w$, dc-coupled neural signal acquisition ic with 0.5v supply,'' IEEE Journal of Solid-State Circuits, vol.47, no.1, pp. 232--243, Jan 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2163552
[^66]: H.Kassiri, A.Bagheri, N.Soltani, K.Abdelhalim, H.M. Jafari, M.T. Salam, J.L.P. Velazquez, and R.Genov, ''Battery-less tri-band-radio neuro-monitor and responsive neurostimulator for diagnostics and treatment of neurological disorders,'' IEEE Journal of Solid-State Circuits, vol.51, no.5, pp. 1274--1289, May 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2528999
[^67]: M.Ballini, J.Müller, P.Livi, Y.Chen, U.Frey, A.Stettler, A.Shadmani, V.Viswam, I.L. Jones, D.Jäckel, M.Radivojevic, M.K. Lewandowska, W.Gong, M.Fiscella, D.J. Bakkum, F.Heer, and A.Hierlemann, ''A 1024-channel cmos microelectrode array with 26,400 electrodes for recording and stimulation of electrogenic cells in vitro,'' IEEE Journal of Solid-State Circuits, vol.49, no.11, pp. 2705--2719, Nov 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2359219
[^68]: P.D. Wolf, Thermal considerations for the design of an implanted cortical brain--machine interface (BMI).\hskip 1em plus 0.5em minus 0.4em elax CRC Press Boca Raton, FL, 2008, pMID: 21204402. [Online]: http://www.ncbi.nlm.nih.gov/books/NBK3932
[^69]: T.Denison, K.Consoer, W.Santa, A.T. Avestruz, J.Cooley, and A.Kelly, ''A 2 $\mu$w 100 nv/rthz chopper-stabilized instrumentation amplifier for chronic measurement of neural field potentials,'' IEEE Journal of Solid-State Circuits, vol.42, no.12, pp. 2934--2945, December 2007. [Online]: http://dx.doi.org/10.1109/JSSC.2007.908664
[^70]: B.Johnson, S.T. Peace, A.Wang, T.A. Cleland, and A.Molnar, ''A 768-channel cmos microelectrode array with angle sensitive pixels for neuronal recording,'' IEEE Sensors Journal, vol.13, no.9, pp. 3211--3218, Sept 2013. [Online]: http://dx.doi.org/10.1109/JSEN.2013.2266894
[^71]: C.M. Lopez, A.Andrei, S.Mitra, M.Welkenhuysen, W.Eberle, C.Bartic, R.Puers, R.F. Yazicioglu, and G.G.E. Gielen, ''An implantable 455-active-electrode 52-channel cmos neural probe,'' IEEE Journal of Solid-State Circuits, vol.49, no.1, pp. 248--261, January 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2284347
[^72]: J.Scholvin, J.P. Kinney, J.G. Bernstein, C.Moore-Kochlacs, N.Kopell, C.G. Fonstad, and E.S. Boyden, ''Close-packed silicon microelectrodes for scalable spatially oversampled neural recording,'' IEEE Transactions on Biomedical Engineering, vol.63, no.1, pp. 120--130, Jan 2016. [Online]: http://dx.doi.org/10.1109/TBME.2015.2406113
[^73]: M.Han, B.Kim, Y.A. Chen, H.Lee, S.H. Park, E.Cheong, J.Hong, G.Han, and Y.Chae, ''Bulk switching instrumentation amplifier for a high-impedance source in neural signal recording,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.62, no.2, pp. 194--198, Feb 2015. [Online]: http://dx.doi.org/10.1109/TCSII.2014.2368615
[^74]: R.Muller, S.Gambini, and J.M. Rabaey, ''A 0.013$ $mm$^2$, 5$ \mu$w, dc-coupled neural signal acquisition ic with 0.5 v supply,'' IEEE Journal of Solid-State Circuits, vol.47, no.1, pp. 232--243, Jan 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2163552
[^75]: ''Rhd2164 digital electrophysiology interface chip - data sheet,'' Intan Technologies, Los Angeles, California, December 2013. [Online]: http://www.intantech.com/files/Intan_RHD2164_datasheet.pdf
[^76]: K.M. Al-Ashmouny, S.I. Chang, and E.Yoon, ''A 4 $\mu$w/ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-d neural microsystems,'' IEEE Transactions on Biomedical Circuits and Systems, vol.6, no.5, pp. 403--413, October 2012. [Online]: http://dx.doi.org/10.1109/TBCAS.2012.2218105
[^77]: D.Han, Y.Zheng, R.Rajkumar, G.S. Dawe, and M.Je, ''A 0.45 v 100-channel neural-recording ic with sub-$\mu$w/channel consumption in 0.18$\mu$m cmos,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.6, pp. 735--746, December 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2014.2298860
[^78]: S.B. Lee, H.M. Lee, M.Kiani, U.M. Jow, and M.Ghovanloo, ''An inductively powered scalable 32-channel wireless neural recording system-on-a-chip for neuroscience applications,'' IEEE Transactions on Biomedical Circuits and Systems, vol.4, no.6, pp. 360--371, Dec 2010. [Online]: http://dx.doi.org/10.1109/TBCAS.2010.2078814
[^79]: J.Yoo, L.Yan, D.El-Damak, M.A.B. Altaf, A.H. Shoeb, and A.P. Chandrakasan, ''An 8-channel scalable eeg acquisition soc with patient-specific seizure classification and recording processor,'' IEEE Journal of Solid-State Circuits, vol.48, no.1, pp. 214--228, Jan 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2221220
[^80]: M.A.B. Altaf and J.Yoo, ''A 1.83$ \mu$j/classification, 8-channel, patient-specific epileptic seizure classification soc using a non-linear support vector machine,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.1, pp. 49--60, Feb 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2014.2386891
[^81]: K.Abdelhalim, H.M. Jafari, L.Kokarovtseva, J.L.P. Velazquez, and R.Genov, ''64-channel uwb wireless neural vector analyzer soc with a closed-loop phase synchrony-triggered neurostimulator,'' IEEE Journal of Solid-State Circuits, vol.48, no.10, pp. 2494--2510, Oct 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2272952
[^82]: A.Bagheri, S.R.I. Gabran, M.T. Salam, J.L.P. Velazquez, R.R. Mansour, M.M.A. Salama, and R.Genov, ''Massively-parallel neuromonitoring and neurostimulation rodent headset with nanotextured flexible microelectrodes,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.5, pp. 601--609, Oct 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2281772
[^83]: H.G. Rhew, J.Jeong, J.A. Fredenburg, S.Dodani, P.G. Patil, and M.P. Flynn, ''A fully self-contained logarithmic closed-loop deep brain stimulation soc with wireless telemetry and wireless power management,'' IEEE Journal of Solid-State Circuits, vol.49, no.10, pp. 2213--2227, Oct 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2346779
[^84]: W.Biederman, D.J. Yeager, N.Narevsky, J.Leverett, R.Neely, J.M. Carmena, E.Alon, and J.M. Rabaey, ''A 4.78 mm 2 fully-integrated neuromodulation soc combining 64 acquisition channels with digital compression and simultaneous dual stimulation,'' IEEE Journal of Solid-State Circuits, vol.50, no.4, pp. 1038--1047, April 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2384736
[^85]: A.Mendez, A.Belghith, and M.Sawan, ''A dsp for sensing the bladder volume through afferent neural pathways,'' IEEE Transactions on Biomedical Circuits and Systems, vol.8, no.4, pp. 552--564, Aug 2014. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2282087
[^86]: T.T. Liu and J.M. Rabaey, ''A 0.25 v 460 nw asynchronous neural signal processor with inherent leakage suppression,'' IEEE Journal of Solid-State Circuits, vol.48, no.4, pp. 897--906, April 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2239096
[^87]: D.Han, Y.Zheng, R.Rajkumar, G.S. Dawe, and M.Je, ''A 0.45 v 100-channel neural-recording ic with sub-$\mu$w/channel consumption in 0.18$ \mu$m cmos,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.6, pp. 735--746, Dec 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2014.2298860
[^88]: R.Muller, H.P. Le, W.Li, P.Ledochowitsch, S.Gambini, T.Bjorninen, A.Koralek, J.M. Carmena, M.M. Maharbiz, E.Alon, and J.M. Rabaey, ''A minimally invasive 64-channel wireless $\mu$ecog implant,'' IEEE Journal of Solid-State Circuits, vol.50, no.1, pp. 344--359, Jan 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2364824
[^89]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational amplifiers and their application to continuous-time filters in nanoscale cmos,'' IEEE Journal of Solid-State Circuits, vol.49, no.12, pp. 2758--2772, December 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2354641
[^90]: V.Karkare, H.Chandrakumar, D.Rozgić, and D.Marković, ''Robust, reconfigurable, and power-efficient biosignal recording systems,'' in IEEE Proceedings of the Custom Integrated Circuits Conference, Sept 2014, pp. 1--8. [Online]: http://dx.doi.org/10.1109/CICC.2014.6946018
[^91]: L.B. Leene and T.G. Constandinou, ''A 0.45v continuous time-domain filter using asynchronous oscillator structures,'' in IEEE Proceedings of the International Conference on Electronics, Circuits and Systems, December 2016.
[^92]: R.Mohan, L.Yan, G.Gielen, C.V. Hoof, and R.F. Yazicioglu, ''0.35 v time-domain-based instrumentation amplifier,'' Electronics Letters, vol.50, no.21, pp. 1513--1514, October 2014. [Online]: http://dx.doi.org/10.1049/el.2014.2471
[^93]: X.Zhang, Z.Zhang, Y.Li, C.Liu, Y.X. Guo, and Y.Lian, ''A 2.89$ \mu$w dry-electrode enabled clockless wireless ecg soc for wearable applications,'' IEEE Journal of Solid-State Circuits, vol.51, no.10, pp. 2287--2298, Oct 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2582863
[^94]: M.Elia, L.B. Leene, and T.G. Constandinou, ''Continuous-time micropower interface for neural recording applications,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2016, pp. 534--537. [Online]: http://dx.doi.org/10.1109/ISCAS.2016.7527295
[^95]: N.Guo, Y.Huang, T.Mai, S.Patil, C.Cao, M.Seok, S.Sethumadhavan, and Y.Tsividis, ''Energy-efficient hybrid analog/digital approximate computation in continuous time,'' IEEE Journal of Solid-State Circuits, vol.51, no.7, pp. 1514--1524, July 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2543729
[^96]: B.Bozorgzadeh, D.R. Schuweiler, M.J. Bobak, P.A. Garris, and P.Mohseni, ''Neurochemostat: A neural interface soc with integrated chemometrics for closed-loop regulation of brain dopamine,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.3, pp. 654--667, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2453791
[^97]: E.B. Myers and M.L. Roukes, ''Comparative advantages of mechanical biosensors,'' Nature nanotechnology, vol.6, no.4, pp. 1748--3387, April 2011. [Online]: http://dx.doi.org/10.1038/nnano.2011.44
[^98]: R.Machado, N.Soltani, S.Dufour, M.T. Salam, P.L. Carlen, R.Genov, and M.Thompson, ''Biofouling-resistant impedimetric sensor for array high-resolution extracellular potassium monitoring in the brain,'' Biosensors, vol.6, no.4, p.53, October 2016. [Online]: http://dx.doi.org/10.3390/bios6040053
[^99]: J.Guo, W.Ng, J.Yuan, S.Li, and M.Chan, ''A 200-channel area-power-efficient chemical and electrical dual-mode acquisition ic for the study of neurodegenerative diseases,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.3, pp. 567--578, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2468052
[^100]: D.A. Dombeck, A.N. Khabbaz, F.Collman, T.L. Adelman, and D.W. Tank, ''Imaging large-scale neural activity with cellular resolution in awake, mobile mice.'' Neuron, vol.56, no.1, pp. 43--57, October 2007. [Online]: http://dx.doi.org/10.1016/j.neuron.2007.08.003
[^101]: T.York, S.B. Powell, S.Gao, L.Kahan, T.Charanya, D.Saha, N.W. Roberts, T.W. Cronin, J.Marshall, S.Achilefu, S.P. Lake, B.Raman, and V.Gruev, ''Bioinspired polarization imaging sensors: From circuits and optics to signal processing algorithms and biomedical applications,'' Proceedings of the IEEE, vol. 102, no.10, pp. 1450--1469, Oct 2014. [Online]: http://dx.doi.org/10.1109/JPROC.2014.2342537
[^102]: K.Paralikar, P.Cong, O.Yizhar, L.E. Fenno, W.Santa, C.Nielsen, D.Dinsmoor, B.Hocken, G.O. Munns, J.Giftakis, K.Deisseroth, and T.Denison, ''An implantable optical stimulation delivery system for actuating an excitable biosubstrate,'' IEEE Journal of Solid-State Circuits, vol.46, no.1, pp. 321--332, Jan 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2010.2074110
[^103]: N.Ji and S.L. Smith, ''Technologies for imaging neural activity in large volumes,'' Nature Neuroscience, vol.19, pp. 1154--1164, September 2016. [Online]: http://dx.doi.org/10.1038/nn.4358
[^104]: S.Song, K.D. Miller, and L.F. Abbott, ''Competitive hebbian learning through spike-timing-dependent synaptic plasticity,'' Nature Neuroscience, vol.3, pp. 919--926, September 2000. [Online]: http://dx.doi.org/10.1038/78829
[^105]: T.Kurafuji, M.Haraguchi, M.Nakajima, T.Nishijima, T.Tanizaki, H.Yamasaki, T.Sugimura, Y.Imai, M.Ishizaki, T.Kumaki, K.Murata, K.Yoshida, E.Shimomura, H.Noda, Y.Okuno, S.Kamijo, T.Koide, H.J. Mattausch, and K.Arimoto, ''A scalable massively parallel processor for real-time image processing,'' IEEE Journal of Solid-State Circuits, vol.46, no.10, pp. 2363--2373, October 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2159528
[^106]: J.Y. Kim, M.Kim, S.Lee, J.Oh, K.Kim, and H.J. Yoo, ''A 201.4 gops 496 mw real-time multi-object recognition processor with bio-inspired neural perception engine,'' IEEE Journal of Solid-State Circuits, vol.45, no.1, pp. 32--45, Jan 2010. [Online]: http://dx.doi.org/10.1109/JSSC.2009.2031768
[^107]: C.C. Cheng, C.H. Lin, C.T. Li, and L.G. Chen, ''ivisual: An intelligent visual sensor soc with 2790 fps cmos image sensor and 205 gops/w vision processor,'' IEEE Journal of Solid-State Circuits, vol.44, no.1, pp. 127--135, Jan 2009. [Online]: http://dx.doi.org/10.1109/JSSC.2008.2007158
[^108]: H.Noda, M.Nakajima, K.Dosaka, K.Nakata, M.Higashida, O.Yamamoto, K.Mizumoto, T.Tanizaki, T.Gyohten, Y.Okuno, H.Kondo, Y.Shimazu, K.Arimoto, K.Saito, and T.Shimizu, ''The design and implementation of the massively parallel processor based on the matrix architecture,'' IEEE Journal of Solid-State Circuits, vol.42, no.1, pp. 183--192, Jan 2007. [Online]: http://dx.doi.org/10.1109/JSSC.2006.886545
[^109]: M.S. Chae, W.Liu, and M.Sivaprakasam, ''Design optimization for integrated neural recording systems,'' IEEE Journal of Solid-State Circuits, vol.43, no.9, pp. 1931--1939, September 2008. [Online]: http://dx.doi.org/10.1109/JSSC.2008.2001877
[^110]: K.J. Miller, L.B. Sorensen, J.G. Ojemann, and M.den Nijs, ''Power-law scaling in the brain surface electric potential,'' PLoS Comput Biol, vol.5, no.12, pp. 1--10, 12 2009. [Online]: http://dx.doi.org/10.1371%2Fjournal.pcbi.1000609
[^111]: R.Harrison and C.Charles, ''A low-power low-noise cmos amplifier for neural recording applications,'' IEEE Journal of Solid-State Circuits, vol.38, no.6, pp. 958--965, June 2003. [Online]: http://dx.doi.org/10.1109/JSSC.2003.811979
[^112]: W.Sansen, ''1.3 analog cmos from 5 micrometer to 5 nanometer,'' in IEEE Proceedings of the International Solid-State Circuits Conference.\hskip 1em plus 0.5em minus 0.4em elax IEEE, February 2015, pp. 1--6. [Online]: http://dx.doi.org/10.1109/ISSCC.2015.7062848
[^113]: M.S.J. Steyaert and W.M.C. Sansen, ''A micropower low-noise monolithic instrumentation amplifier for medical purposes,'' IEEE Journal of Solid-State Circuits, vol.22, no.6, pp. 1163--1168, December 1987. [Online]: http://dx.doi.org/10.1109/JSSC.1987.1052869
[^114]: W.Wattanapanitch, M.Fee, and R.Sarpeshkar, ''An energy-efficient micropower neural recording amplifier,'' IEEE Transactions on Biomedical Circuits and Systems, vol.1, no.2, pp. 136--147, June 2007. [Online]: http://dx.doi.org/10.1109/TBCAS.2007.907868
[^115]: B.Johnson and A.Molnar, ''An orthogonal current-reuse amplifier for multi-channel sensing,'' IEEE Journal of Solid-State Circuits, vol.48, no.6, pp. 1487--1496, June 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2257478
[^116]: C.Qian, J.Parramon, and E.Sanchez-Sinencio, ''A micropower low-noise neural recording front-end circuit for epileptic seizure detection,'' IEEE Journal of Solid-State Circuits, vol.46, no.6, pp. 1392--1405, June 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2126370
[^117]: X.Zou, L.Liu, J.H. Cheong, L.Yao, P.Li, M.-Y. Cheng, W.L. Goh, R.Rajkumar, G.Dawe, K.-W. Cheng, and M.Je, ''A 100-channel 1-mw implantable neural recording ic,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.60, no.10, pp. 2584--2596, October 2013. [Online]: http://dx.doi.org/10.1109/TCSI.2013.2249175
[^118]: V.Majidzadeh, A.Schmid, and Y.Leblebici, ''Energy efficient low-noise neural recording amplifier with enhanced noise efficiency factor,'' IEEE Transactions on Biomedical Circuits and Systems, vol.5, no.3, pp. 262--271, June 2011. [Online]: http://dx.doi.org/10.1109/TBCAS.2010.2078815
[^119]: ibitemQ-basedC.C. Enz and E.A. Vittoz, Charge-based MOS transistor modeling: the EKV model for low-power AND RF IC design.\hskip 1em plus 0.5em minus 0.4em elax John Wiley & Sons, August 2006. [Online]: http://eu.wiley.com/WileyCDA/WileyTitle/productCd-0470855452.html
[^120]: Y.Yasuda, T.-J.K. Liu, and C.Hu, ''Flicker-noise impact on scaling of mixed-signal cmos with hfsion,'' IEEE Transactions on Electron Devices, vol.55, no.1, pp. 417--422, January 2008. [Online]: http://dx.doi.org/10.1109/TED.2007.910759
[^121]: S.-Y. Wu, C.Lin, M.Chiang, J.Liaw, J.Cheng, S.Yang, M.Liang, T.Miyashita, C.Tsai, B.Hsu, H.Chen, T.Yamamoto, S.Chang, V.Chang, C.Chang, J.Chen, H.Chen, K.Ting, Y.Wu, K.Pan, R.Tsui, C.Yao, P.Chang, H.Lien, T.Lee, H.Lee, W.Chang, T.Chang, R.Chen, M.Yeh, C.Chen, Y.Chiu, Y.Chen, H.Huang, Y.Lu, C.Chang, M.Tsai, C.Liu, K.Chen, C.Kuo, H.Lin, S.Jang, and Y.Ku, ''A 16nm finfet cmos technology for mobile soc and computing applications,'' in IEEE Proceedings of the International Electron Devices Meeting, December 2013, pp. 9.1.1--9.1.4. [Online]: http://dx.doi.org/10.1109/IEDM.2013.6724591
[^122]: L.B. Leene, Y.Liu, and T.G. Constandinou, ''A compact recording array for neural interfaces,'' in IEEE Proceedings of the Biomedical Circuits and Systems Conference, October 2013, pp. 97--100. [Online]: http://dx.doi.org/10.1109/BioCAS.2013.6679648
[^123]: Q.Fan, F.Sebastiano, J.Huijsing, and K.Makinwa, ''A $1.8 \mu w\:60 nv/√Hz$ capacitively-coupled chopper instrumentation amplifier in 65 nm cmos for wireless sensor nodes,'' IEEE Journal of Solid-State Circuits, vol.46, no.7, pp. 1534--1543, July 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2143610
[^124]: H.Chandrakumar and D.Markovic, ''A simple area-efficient ripple-rejection technique for chopped biosignal amplifiers,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.62, no.2, pp. 189--193, February 2015. [Online]: http://dx.doi.org/10.1109/TCSII.2014.2387686
[^125]: H.Chandrakumar and D.Markovic, ''A 2$\mu$w 40mvpp linear-input-range chopper-stabilized bio-signal amplifier with boosted input impedance of 300mohm and electrode-offset filtering,'' in IEEE Proceedings of the International Solid-State Circuits Conference.\hskip 1em plus 0.5em minus 0.4em elax IEEE, January 2016, pp. 96--97. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7417924
[^126]: H.Rezaee-Dehsorkh, N.Ravanshad, R.Lotfi, K.Mafinezhad, and A.M. Sodagar, ''Analysis and design of tunable amplifiers for implantable neural recording applications,'' IEEE Transactions on Emerging and Selected Topics in Circuits and Systems, vol.1, no.4, pp. 546--556, December 2011. [Online]: http://dx.doi.org/10.1109/JETCAS.2011.2174492
[^127]: X.Zou, X.Xu, L.Yao, and Y.Lian, ''A 1-v 450-nw fully integrated programmable biomedical sensor interface chip,'' IEEE Journal of Solid-State Circuits, vol.44, no.4, pp. 1067--1077, April 2009. [Online]: http://dx.doi.org/10.1109/JSSC.2009.2014707
[^128]: L.Leene and T.Constandinou, ''Ultra-low power design strategy for two-stage amplifier topologies,'' Electronics Letters, vol.50, no.8, pp. 583--585, April 2014. [Online]: http://dx.doi.org/10.1049/el.2013.4196
[^129]: H.G. Rey, C.Pedreira, and R.Q. Quiroga, ''Past, present and future of spike sorting techniques,'' Brain Research Bulletin, vol. 119, Part B, pp. 106--117, October 2015, advances in electrophysiological data analysis. [Online]: http://www.sciencedirect.com/science/article/pii/S0361923015000684
[^130]: Y.Chen, A.Basu, L.Liu, X.Zou, R.Rajkumar, G.S. Dawe, and M.Je, ''A digitally assisted, signal folding neural recording amplifier,'' IEEE Transactions on Biomedical Circuits and Systems, vol.8, no.4, pp. 528--542, August 2014. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2288680
[^131]: X.Yue, ''Determining the reliable minimum unit capacitance for the dac capacitor array of sar adcs,'' Microelectronics Journal, vol.44, no.6, pp. 473 -- 478, 2013. [Online]: http://www.sciencedirect.com/science/article/pii/S0026269213000815
[^132]: Y.Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, S.-P. U, R.Martins, and F.Maloberti, ''Split-sar adcs: Improved linearity with power and speed optimization,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.22, no.2, pp. 372--383, February 2014. [Online]: http://dx.doi.org/10.1109/TVLSI.2013.2242501
[^133]: L.Xie, G.Wen, J.Liu, and Y.Wang, ''Energy-efficient hybrid capacitor switching scheme for sar adc,'' Electronics Letters, vol.50, no.1, pp. 22--23, January 2014. [Online]: http://dx.doi.org/10.1049/el.2013.2794
[^134]: P.Nuzzo, F.DeBernardinis, P.Terreni, and G.Vander Plas, ''Noise analysis of regenerative comparators for reconfigurable adc architectures,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.55, no.6, pp. 1441--1454, July 2008. [Online]: http://dx.doi.org/10.1109/TCSI.2008.917991
[^135]: G.Heinzel, A.R\"udiger, and R.Schilling, ''Spectrum and spectral density estimation by the discrete fourier transform (dft), including a comprehensive list of window functions and some new at-top windows,'' pp. 25--27, February 2002. [Online]: http://hdl.handle.net/11858/00-001M-0000-0013-557A-5
[^136]: F.Gerfers, M.Ortmanns, and Y.Manoli, ''A 1.5-v 12-bit power-efficient continuous-time third-order sigma; delta; modulator,'' IEEE Journal of Solid-State Circuits, vol.38, no.8, pp. 1343--1352, Aug 2003. [Online]: http://dx.doi.org/10.1109/JSSC.2003.814432
[^137]: Y.Chae, K.Souri, and K.A.A. Makinwa, ''A 6.3$ \mu$w 20$ $bit incremental zoom-adc with 6 ppm inl and 1 $\mu$v offset,'' IEEE Journal of Solid-State Circuits, vol.48, no.12, pp. 3019--3027, Dec 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2278737
[^138]: Y.S. Shu, L.T. Kuo, and T.Y. Lo, ''An oversampling sar adc with dac mismatch error shaping achieving 105db sfdr and 101db sndr over 1khz bw in 55nm cmos,'' in IEEE Proceedings of the International Solid-State Circuits Conference, January 2016, pp. 458--459. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7418105
[^139]: P.Harpe, E.Cantatore, and A.van Roermund, ''An oversampled 12/14b sar adc with noise reduction and linearity enhancements achieving up to 79.1db sndr,'' in IEEE Proceedings of the International Solid-State Circuits Conference, February 2014, pp. 194--195. [Online]: http://dx.doi.org/10.1109/ISSCC.2014.6757396
[^140]: ibitemchrch-turingM.Braverman, J.Schneider, and C.Rojas, ''Space-bounded church-turing thesis and computational tractability of closed systems,'' Physical Review Letters, vol. 115, August 2015. [Online]: http://link.aps.org/doi/10.1103/PhysRevLett.115.098701
[^141]: M.Verhelst and A.Bahai, ''Where analog meets digital: Analog-to-information conversion and beyond,'' IEEE Solid-State Circuits Magazine, vol.7, no.3, pp. 67--80, September 2015. [Online]: http://dx.doi.org/10.1109/MSSC.2015.2442394
[^142]: H.A. Marblestone, M.B. Zamft, G.Y. Maguire, G.M. Shapiro, R.T. Cybulski, I.J. Glaser, D.Amodei, P.B. Stranges, R.Kalhor, A.D. Dalrymple, D.Seo, E.Alon, M.M. Maharbiz, M.J. Carmena, M.J. Rabaey, S.E. Boyden, M.G. Church, and P.K. Kording, ''Physical principles for scalable neural recording,'' Frontiers in Computational Neuroscience, vol.7, no. 137, 2013. [Online]: http://www.frontiersin.org/computational_neuroscience/10.3389/fncom.2013.00137
[^143]: L.Traver, C.Tarin, P.Marti, and N.Cardona, ''Adaptive-threshold neural spike by noise-envelope tracking,'' Electronics Letters, vol.43, no.24, pp. 1333--1335, November 2007. [Online]: http://dx.doi.org/10.1049/el:20071631
[^144]: I.Obeid and P.Wolf, ''Evaluation of spike-detection algorithms fora brain-machine interface application,'' IEEE Transactions on Biomedical Engineering, vol.51, no.6, pp. 905--911, June 2004. [Online]: http://dx.doi.org/10.1109/TBME.2004.826683
[^145]: P.Watkins, G.Santhanam, K.Shenoy, and R.Harrison, ''Validation of adaptive threshold spike detector for neural recording,'' in IEEE Proceedings of the International Conference on Engineering in Medicine and Biology Society, vol.2, September 2004, pp. 4079--4082. [Online]: http://dx.doi.org/10.1109/IEMBS.2004.1404138
[^146]: T.Takekawa, Y.Isomura, and T.Fukai, ''Accurate spike sorting for multi-unit recordings,'' European Journal of Neuroscience, vol.31, no.2, pp. 263--272, 2010. [Online]: http://dx.doi.org/10.1111/j.1460-9568.2009.07068.x
[^147]: A.Zviagintsev, Y.Perelman, and R.Ginosar, ''Low-power architectures for spike sorting,'' in IEEE Proceedings of the International Conference on Neural Engineering, March 2005, pp. 162--165. [Online]: http://dx.doi.org/10.1109/CNE.2005.1419579
[^148]: A.Rodriguez-Perez, J.Ruiz-Amaya, M.Delgado-Restituto, and A.Rodriguez-Vazquez, ''A low-power programmable neural spike detection channel with embedded calibration and data compression,'' IEEE Transactions on Biomedical Circuits and Systems, vol.6, no.2, pp. 87--100, April 2012. [Online]: http://dx.doi.org/10.1109/TBCAS.2012.2187352
[^149]: U.Rutishauser, E.M. Schuman, and A.N. Mamelak, ''Online detection and sorting of extracellularly recorded action potentials in human medial temporal lobe recordings, in vivo,'' Journal of Neuroscience Methods, vol. 154, no. 1–2, pp. 204 -- 224, 2006. [Online]: http://www.sciencedirect.com/science/article/pii/S0165027006000033
[^150]: F.Franke, M.Natora, C.Boucsein, M.Munk, and K.Obermayer, ''\BIBforeignlanguageEnglishAn online spike detection and spike classification algorithm capable of instantaneous resolution of overlapping spikes,'' \BIBforeignlanguageEnglishJournal of Computational Neuroscience, vol.29, no. 1-2, pp. 127--148, 2010. [Online]: http://dx.doi.org/10.1007/s10827-009-0163-5
[^151]: M.S. Chae, Z.Yang, M.Yuce, L.Hoang, and W.Liu, ''A 128-channel 6 mw wireless neural recording ic with spike feature extraction and uwb transmitter,'' IEEE Transactions on Neural Systems and Rehabilitation Engineering, vol.17, no.4, pp. 312--321, August 2009. [Online]: http://dx.doi.org/10.1109/TNSRE.2009.2021607
[^152]: P.H. Thakur, H.Lu, S.S. Hsiao, and K.O. Johnson, ''Automated optimal detection and classification of neural action potentials in extra-cellular recordings,'' Journal of Neuroscience Methods, vol. 162, no. 1–2, pp. 364 -- 376, 2007. [Online]: ttp://www.sciencedirect.com/science/article/pii/S0165027007000477
[^153]: J.Zhang, Y.Suo, S.Mitra, S.Chin, S.Hsiao, R.Yazicioglu, T.Tran, and R.Etienne-Cummings, ''An efficient and compact compressed sensing microsystem for implantable neural recordings,'' IEEE Transactions on Biomedical Circuits and Systems, vol.8, no.4, pp. 485--496, August 2014. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2284254
[^154]: Y.Suo, J.Zhang, T.Xiong, P.S. Chin, R.Etienne-Cummings, and T.D. Tran, ''Energy-efficient multi-mode compressed sensing system for implantable neural recordings,'' IEEE Transactions on Biomedical Circuits and Systems, vol.8, no.5, pp. 648--659, October 2014. [Online]: http://dx.doi.org/10.1109/TBCAS.2014.2359180
[^155]: B.Yu, T.Mak, X.Li, F.Xia, A.Yakovlev, Y.Sun, and C.S. Poon, ''Real-time fpga-based multichannel spike sorting using hebbian eigenfilters,'' IEEE Transactions on Emerging and Selected Topics in Circuits and Systems, vol.1, no.4, pp. 502--515, December 2011. [Online]: http://dx.doi.org/10.1109/JETCAS.2012.2183430
[^156]: V.Ventura, ''Automatic spike sorting using tuning information,'' Neural computation, vol.21, no.9, pp. 2466--2501, September 2009. [Online]: http://www.ncbi.nlm.nih.gov/pmc/articles/PMC4167425/
[^157]: D.Y. Barsakcioglu, A.Eftekhar, and T.G. Constandinou, ''Design optimisation of front-end neural interfaces for spike sorting systems,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2013, pp. 2501--2504. [Online]: http://dx.doi.org/10.1109/ISCAS.2013.6572387
[^158]: A.M. Sodagar, K.D. Wise, and K.Najafi, ''A fully integrated mixed-signal neural processor for implantable multichannel cortical recording,'' IEEE Transactions on Biomedical Engineering, vol.54, no.6, pp. 1075--1088, June 2007. [Online]: http://dx.doi.org/10.1109/TBME.2007.894986
[^159]: Y.Xin, W.X. Li, R.C. Cheung, R.H. Chan, H.Yan, D.Song, and T.W. Berger, ''An fpga based scalable architecture of a stochastic state point process filter (ssppf) to track the nonlinear dynamics underlying neural spiking,'' Microelectronics Journal, vol.45, no.6, pp. 690 -- 701, June 2014. [Online]: http://www.sciencedirect.com/science/article/pii/S0026269214000913
[^160]: C.Qian, J.Shi, J.Parramon, and E.Sánchez-Sinencio, ''A low-power configurable neural recording system for epileptic seizure detection,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.4, pp. 499--512, August 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2012.2228857
[^161]: K.C. Chun, P.Jain, J.H. Lee, and C.H. Kim, ''A 3t gain cell embedded dram utilizing preferential boosting for high density and low power on-die caches,'' IEEE Journal of Solid-State Circuits, vol.46, no.6, pp. 1495--1505, June 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2128150
[^162]: R.E. Matick and S.E. Schuster, ''Logic-based edram: Origins and rationale for use,'' IBM Journal of Research AND Development, vol.49, no.1, pp. 145--165, January 2005. [Online]: http://dx.doi.org/10.1147/rd.491.0145
[^163]: R.Nair, ''Evolution of memory architecture,'' Proceedings of the IEEE, vol. 103, no.8, pp. 1331--1345, August 2015. [Online]: http://dx.doi.org/10.1109/JPROC.2015.2435018
[^164]: C.E. Molnar and I.W. Jones, ''Simple circuits that work for complicated reasons,'' in IEEE Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2000, pp. 138--149. [Online]: http://dx.doi.org/10.1109/ASYNC.2000.836995
[^165]: ibitemBN-formH.Schorr, ''Computer-aided digital system design and analysis using a register transfer language,'' IEEE Transactions on Electronic Computers, vol. EC-13, no.6, pp. 730--737, December 1964. [Online]: http://dx.doi.org/10.1109/PGEC.1964.263907
[^166]: D.Wang, A.Rajendiran, S.Ananthanarayanan, H.Patel, M.Tripunitara, and S.Garg, ''Reliable computing with ultra-reduced instruction set coprocessors,'' IEEE Micro, vol.34, no.6, pp. 86--94, November 2014. [Online]: http://dx.doi.org/10.1109/MM.2013.130
[^167]: ''Msp430g2x53 mixed signal microcontroller - data sheet,'' Texas Instruments Incorporated, Dallas, Texas, pp. 403--413, May 2013. [Online]: http://www.ti.com/lit/ds/symlink/msp430g2553.pdf
[^168]: F.L. Yuan, C.C. Wang, T.H. Yu, and D.Marković, ''A multi-granularity fpga with hierarchical interconnects for efficient and flexible mobile computing,'' IEEE Journal of Solid-State Circuits, vol.50, no.1, pp. 137--149, January 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2372034
[^169]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational amplifiers and their application to continuous-time filters in nanoscale cmos,'' IEEE Journal of Solid-State Circuits, vol.49, no.12, pp. 2758--2772, December 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2354641
[^170]: Y.Tsividis, ''Event-driven data acquisition and continuous-time digital signal processing,'' in IEEE Proceedings of the Custom Integrated Circuits Conference, September 2010, pp. 1--8. [Online]: http://dx.doi.org/10.1109/CICC.2010.5617618
[^171]: I.Lee, D.Sylvester, and D.Blaauw, ''A constant energy-per-cycle ring oscillator over a wide frequency range for wireless sensor nodes,'' IEEE Journal of Solid-State Circuits, vol.51, no.3, pp. 697--711, March 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2517133
[^172]: B.Drost, M.Talegaonkar, and P.K. Hanumolu, ''Analog filter design using ring oscillator integrators,'' IEEE Journal of Solid-State Circuits, vol.47, no.12, pp. 3120--3129, December 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2225738
[^173]: V.Unnikrishnan and M.Vesterbacka, ''Time-mode analog-to-digital conversion using standard cells,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.61, no.12, pp. 3348--3357, December 2014. [Online]: http://dx.doi.org/10.1109/TCSI.2014.2340551
[^174]: K.Yang, D.Blaauw, and D.Sylvester, ''An all-digital edge racing true random number generator robust against pvt variations,'' IEEE Journal of Solid-State Circuits, vol.51, no.4, pp. 1022--1031, April 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2519383
[^175]: ibitem0.5V-CircuitS.Chatterjee, Y.Tsividis, and P.Kinget, ''0.5-v analog circuit techniques and their application in ota and filter design,'' IEEE Journal of Solid-State Circuits, vol.40, no.12, pp. 2373--2387, December 2005. [Online]: http://dx.doi.org/10.1109/JSSC.2005.856280
[^176]: M.Alioto, ''Understanding dc behavior of subthreshold cmos logic through closed-form analysis,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.57, no.7, pp. 1597--1607, July 2010. [Online]: http://dx.doi.org/10.1109/TCSI.2009.2034233
[^177]: A.Hajimiri and T.Lee, ''A general theory of phase noise in electrical oscillators,'' IEEE Journal of Solid-State Circuits, vol.33, no.2, pp. 179--194, February 1998. [Online]: http://dx.doi.org/10.1109/4.658619
[^178]: A.Demir, A.Mehrotra, and J.Roychowdhury, ''Phase noise in oscillators: a unifying theory and numerical methods for characterization,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.47, no.5, pp. 655--674, May 2000. [Online]: http://dx.doi.org/10.1109/81.847872
[^179]: A.Hajimiri, S.Limotyrakis, and T.Lee, ''Phase noise in multi-gigahertz cmos ring oscillators,'' in IEEE Proceedings of the Custom Integrated Circuits Conference, May 1998, pp. 49--52. [Online]: http://dx.doi.org/10.1109/CICC.1998.694905
[^180]: W.Jiang, V.Hokhikyan, H.Chandrakumar, V.Karkare, and D.Markovic, ''A ±50mv linear-input-range vco-based neural-recording front-end with digital nonlinearity correction,'' in IEEE Proceedings of the International Solid-State Circuits Conference, January 2016, pp. 484--485. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7418118
[^181]: C.Weltin-Wu and Y.Tsividis, ''An event-driven clockless level-crossing adc with signal-dependent adaptive resolution,'' IEEE Journal of Solid-State Circuits, vol.48, no.9, pp. 2180--2190, September 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2262738
[^182]: H.Y. Yang and R.Sarpeshkar, ''A bio-inspired ultra-energy-efficient analog-to-digital converter for biomedical applications,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.53, no.11, pp. 2349--2356, November 2006. [Online]: http://dx.doi.org/10.1109/TCSI.2006.884463
[^183]: F.Corradi and G.Indiveri, ''A neuromorphic event-based neural recording system for smart brain-machine-interfaces,'' IEEE Transactions on Biomedical Circuits and Systems, vol.9, no.5, pp. 699--709, October 2015. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2479256
[^184]: K.A. Ng and Y.P. Xu, ''A compact, low input capacitance neural recording amplifier,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.5, pp. 610--620, October 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2280066
[^185]: J.Agustin and M.Lopez-Vallejo, ''An in-depth analysis of ring oscillators: Exploiting their configurable duty-cycle,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.62, no.10, pp. 2485--2494, October 2015. [Online]: http://dx.doi.org/10.1109/TCSI.2015.2476300
[^186]: K.Ng and Y.P. Xu, ''A compact, low input capacitance neural recording amplifier,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.5, pp. 610--620, October 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2280066
[^187]: M.Elia, L.B. Leene, and T.G. Constandinou, ''Continuous-time micropower interface for neural recording applications,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2016.
[^188]: Y.W. Li, K.L. Shepard, and Y.P. Tsividis, ''A continuous-time programmable digital fir filter,'' IEEE Journal of Solid-State Circuits, vol.41, no.11, pp. 2512--2520, November 2006. [Online]: http://dx.doi.org/10.1109/JSSC.2006.883314
[^189]: B.Schell and Y.Tsividis, ''A continuous-time adc/dsp/dac system with no clock and with activity-dependent power dissipation,'' IEEE Journal of Solid-State Circuits, vol.43, no.11, pp. 2472--2481, November 2008. [Online]: http://dx.doi.org/10.1109/JSSC.2008.2005456
[^190]: S.Aouini, K.Chuai, and G.W. Roberts, ''Anti-imaging time-mode filter design using a pll structure with transfer function dft,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.59, no.1, pp. 66--79, January 2012. [Online]: http://dx.doi.org/10.1109/TCSI.2011.2161411
[^191]: X.Xing and G.G.E. Gielen, ''A 42 fj/step-fom two-step vco-based delta-sigma adc in 40 nm cmos,'' IEEE Journal of Solid-State Circuits, vol.50, no.3, pp. 714--723, March 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2393814
[^192]: K.Reddy, S.Rao, R.Inti, B.Young, A.Elshazly, M.Talegaonkar, and P.K. Hanumolu, ''A 16-mw 78-db sndr 10-mhz bw ct $\delta \sigma$ adc using residue-cancelling vco-based quantizer,'' IEEE Journal of Solid-State Circuits, vol.47, no.12, pp. 2916--2927, December 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2218062
[^193]: J.Daniels, W.Dehaene, M.S.J. Steyaert, and A.Wiesbauer, ''A/d conversion using asynchronous delta-sigma modulation and time-to-digital conversion,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.57, no.9, pp. 2404--2412, September 2010. [Online]: http://dx.doi.org/10.1109/TCSI.2010.2043169
[^194]: F.M. Yaul and A.P. Chandrakasan, ''A sub-$\mu$w 36nv/$√Hz$ chopper amplifier for sensors using a noise-efficient inverter-based 0.2v-supply input stage,'' in IEEE Proceedings of the International Solid-State Circuits Conference, January 2016, pp. 94--95. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7417923
[^195]: S.Patil, A.Ratiu, D.Morche, and Y.Tsividis, ''A 3-10 fj/conv-step error-shaping alias-free continuous-time adc,'' IEEE Journal of Solid-State Circuits, vol.51, no.4, pp. 908--918, April 2016. [Online]: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7433385&isnumber=7446371
[^196]: J.M. Duarte-Carvajalino and G.Sapiro, ''Learning to sense sparse signals: Simultaneous sensing matrix and sparsifying dictionary optimization,'' IEEE Transactions on Image Processing, vol.18, no.7, pp. 1395--1408, July 2009. [Online]: http://dx.doi.org/10.1109/TIP.2009.2022459
[^197]: R.S. Schneider and H.C. Card, ''Analog hardware implementation issues in deterministic boltzmann machines,'' IEEE Transactions on Circuits and Systems---Part II: Analog and Digital Signal Processing, vol.45, no.3, pp. 352--360, Mar 1998. [Online]: http://dx.doi.org/10.1109/82.664241
[^198]: J.Lu, S.Young, I.Arel, and J.Holleman, ''A 1 tops/w analog deep machine-learning engine with floating-gate storage in 0.13$\mu$m cmos,'' IEEE Journal of Solid-State Circuits, vol.50, no.1, pp. 270--281, January 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2356197
[^199]: M.T. Wolf and J.W. Burdick, ''A bayesian clustering method for tracking neural signals over successive intervals,'' IEEE Transactions on Biomedical Engineering, vol.56, no.11, pp. 2649--2659, November 2009. [Online]: http://dx.doi.org/10.1109/TBME.2009.2027604
[^200]: D.Y. Barsakcioglu and T.G. Constandinou, ''A 32-channel mcu-based feature extraction and classification for scalable on-node spike sorting,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2016.
[^201]: R.P. Feynman, ''There's plenty of room at the bottom,'' American Physical Society, vol.23, no.5, pp. 22--36, February 1960. [Online]: http://www.zyvex.com/nanotech/feynman.html
[^202]: G.Leuba and L.J. Garey, ''Comparison of neuronal and glial numerical density in primary and secondary visual cortex of man,'' Experimental Brain Research, vol.77, no.1, pp. 31--38, 1989. [Online]: http://dx.doi.org/10.1007/BF00250564
[^203]: I.Guideline, ''Guidelines for limiting exposure to time-varying electric, magnetic, and electromagnetic fields (up to 300 ghz),'' Health Physics, vol.74, no.4, pp. 494--522, October 1998. [Online]: http://www.icnirp.org/cms/upload/publications/ICNIRPemfgdl.pdf
[^204]: L.B. Leene, S.Luan, and T.G. Constandinou, ''A 890fj/bit uwb transmitter for soc integration in high bit-rate transcutaneous bio-implants,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2013, pp. 2271--2274. [Online]: http://dx.doi.org/10.1109/ISCAS.2013.6572330
[^205]: ''Unconventional processing of signals for intelligent data exploitation (upside),'' Defense Advanced Research Projects Agency, Arlington, Texas, January 2016. [Online]: http://www.darpa.mil/program/unconventional-processing-of-signals-for-intelligent-data-exploitation

561
content/publications/2016/brain-machine-interfaces-neural-recording-time-domain-techniques.md Normal file
View File

@ -0,0 +1,561 @@
---
title: "Brain machine interfaces: Time Domain Techniques"
date: 2016-08-08T15:26:46+01:00
draft: false
toc: true
math: true
type: posts
tags:
- chapter
- thesis
- CMOS
- biomedical
---
Lieuwe B. Leene, Yan Liu, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 43 Time Domain Techniques
Thus far our work has detailed numerous design techniques that extend on contemporary work where the classical analogue approach with digital processing has demonstrated its capabilities. However we have also analytically shown that although we can still strive to improve area and efficiency, there are a number of factors that prevent making significant progress in terms of improving system characteristics. Moreover there is a strict need for more efficient computational processing that appears overwhelming if it is made robust and adaptive. If we keep the current processing methodology this component can only be made viable with smaller technologies and voltage scaling that can substantially diminish the performance of analogue operations. Here we will attempt to address the two factors that have the most significant impact on improving sensing electronics based on the observations made in the foregoing discussions to consolidate this work. The first is introducing all-digital instrumentation that is not diminished by technology related scaling and the characteristics of nano-meter transistors. The second objective is developing a mixed signal topology for analogue to information conversion where feature extraction is performed adaptively in the analogue domain.
This chapter will focus on exploring the emerging time domain processing modality in order leverage increased digital performance associated with modern CMOS processes. In fact this motivation is carefully addressed in the literature[^169] where logic-gate based topologies demonstrate better scalability with respect to linearity and bandwidth. Here we will demonstrate how the fundamental limits of noise efficiency can be approached by proposing several topologies and design techniques. Further we will elaborate on the characteristic relations between analogue performance and resource requirements that enable these structures. The organization of this chapter is as follows. Section 44 will introduce the essential design considerations for continuous time-domain circuits by considering the phase characteristics of oscillators in relation to driving transistors that are used for analogue feedback. This structure will be used to implement both amplifying and filtering structures to compose the instrumentation front end. This is followed by Section 48 where we propose a mixed signal topology for analogue domain classification.
# 44 Principles for time domain processing
There are two driving factors to approaching time domain concepts where signals are represented in terms of delays between pulse edges or phase components in oscillators. The first benifit is the inherent digital operation where continuous valued signals are represented by digital events with respect to a global or local reference [^170]. This implies that the typical analogue processing has the same power scaling and advantages as the digital processing in terms of technology parameters. This allows oscillator structures to approach very efficient operation irrespective of the oscillation frequency or supply voltage [^171]. The second is that many operations are not restrained by non-linearity from individual transistors giving way to ideal integrators and other operators [^172]. The overall result is that even with limited power budgets the topologies have an overwhelming excess in bandwidth where performance can scale with digital gate delay or its switching energy. The abundance of digital operations for such systems allows these topologies have the potential for digital synthesis using standard cells and a digital design flow to directly process analogue signals [^173]. Moreover event based representation of continuous valued signals allows for often a surprisingly efficient implementation with reduced complexity for a variety of elementary operations. For example [^174] presents a clock-less PVT invariant true random number generator based on the collapse of a ring oscillator structure.
{{< figure src="technical_3/BW-VDD.pdf}}" width="500" >}}
{{< figure src="technical_3/mLP.pdf}}" title="Figure 68: Voltage supply relationship with respect to the bandwidth and linearity requirements with respect to different technologies " width="500" >}}
Let us elaborate on the notion of scaling analogue with digital characteristics quantitatively. Figure 68 illustrates the drawback of conventional analogue techniques from first principles by looking more closely at the voltage scaling characteristics. Here transitioning to nanometre technologies gives us the capability of reducing our voltage supply because the desired bandwidth can be achieved with a smaller inversion coefficient or equivalent gate voltage. However the transconductance and consequently linearity and noise efficiency can degrade as the drain voltage is reduced. This dependency is because transistor gain requires a large channel resistance which is a function of \\((1-e^{-V_{DS}/U_T})\\) in addition to any DIBL which introduce a asymptotic limit where the former is in fact not process dependent [^176]. This limits the output swing \\(V_{max}\\) with a overhead that is \\(5 U_T\\) [^119]. Figure 68 b) demonstrates the resulting the class-A power efficiency measured as \\(V_{max}/V_{DD}\\) to reflect how efficiently we can use the provided voltage supply. This is evaluated in terms of \\(P_{out}/P_{vdd}\\) where \\(P_{out}\\) and \\(P_{vdd}\\) are the output signal power and the power dissipated by the voltage supply respectively. We can conclude that conventional low noise amplification structures can no longer benefit from technology scaling unless we adopt topologies that do not rely on amplification in the voltage domain. Because the input referred noise of a circuit relies only on its current dissipation scaling supply voltages remains a viable means to reduce power if time-domain structures can mitigate the need for voltage gain.
## 45 Sub-threshold Ring Oscillators
The understanding and the interpretation of principle elements for a given modality has the most influential impact on how well it can be utilised. Moreover encoding signals in the time domain will influence how flexibly certain objectives are approached either using digital operations or analogue feedback. Here we will review some basic understanding for ring oscillator structures that are biased in weak inversion. This component will provide a fundamental basis for the topologies proposed here because it connects analogue signals at the input to phase and time domain signals at its output. The interest here specifically lies with using current controlled oscillators that have a well defined linear relationship associated with any injected charge and the resulting shift in output phase. This will lead to the small signal transfer function that relates to the biasing current of the oscillator. Moreover we must be able to evaluate the different components of phase noise and refer it back to the input of transconductive element because we will apply this structure to instrumentation.
$$ V_{out} (t) = A(t) \cdot f\left[ \omega_0 t + \phi(t) \right] $$
A generalized time dependent model for an oscillator is represented by Equation 37 where \\(A\\) and \\(\phi\\) represent the amplitude and phase state variables of the system. \\(f\\) describes the limit cycle of the oscillator over time that maps the steady state output voltage \\(V_{out}\\) as function of phase. The challenge for sub-threshold current biased ring oscillators is that the non-linearity in \\(f\\) is difficult to analytically predict without well informed priori. This is of significance as it will determine how noise sources perturb coupled to the output phase state.
{{< figure src="technical_3/impulse.png" title="Figure 69: " width="500" >}}
Many principle aspects of phase dependencies in oscillators have been well described in a generalized form using numerical methods [^178] and by approximation [^177]. The underlying characteristics however are illustrated in Figure 69 where charge perturbations integrate on to the phase of state the oscillator with respect to the impulse sensitivity function (ISF) \\(\Gamma(x)\\). This factor is a cyclo stationary function that describes how the coupling changes as a function of the phase state \\(\phi\\) subject to the source of perturbation. Moreover this allows us to predict the accumulated phase noise due to a time varying process according to Equation 38.
$$ \phi (t) = \int_{-\infty}^{\infty} h_{\phi}(t,\tau) i(\tau) \: d\tau = \int_{-\infty}^{t} \Gamma(\omega_0 \tau) i(\tau) \: d\tau $$
The integral dependency on accumulated phase is what leads to the infinite open loop gain for oscillator based amplifiers. This also implies that any white noise source that is incoherent with the oscillator fundamental frequency will translate to the output phase as \\(\Gamma_{rms}\\). This depends on the assertion that incoherence implies uncorrelated which is subject to the beat frequencies of the two sources. In practical cases this is a fair approximation not only because the oscillator frequency drifts freely but also because we explicitly consider closed loop implementations that aggressively shape in band perturbations. The utility of Equation 38 lies with its ability to predict the single-side band output noise spectrum due to a white noise current source with spectral density $i_n^2 / \Delta f$ with carrier off-set frequency \\(f_{off}\\) according to Equation 39 [^179].
$$ L(f_{off}) = \left( \frac{\Gamma_{rms}}{2\pi f_{off}} \right)^2 \cdot \frac{i_n^2 / \Delta f}{2} $$
The \\(N\\) stage ring oscillator structure of interest is illustrated in Figure 70. Opposed to voltage controlled structures this configuration is current biased and the oscillating ring is isolated from the supplies. Here the oscillating frequency in sub-threshold operation can be approximated as $f_0 = I_B / (N C_{gate} V_{RS})$ where \\(I_B\\) is the biasing current and \\(C_{gate}\\) is the input capacitance of the delay element. \\(V_{RS}\\) is the voltage across the oscillating structure and is evaluated using Equation 40 where \\(V_{th}\\) is the transistor threshold voltage. In this case \\(M_2\\) provides a biasing current from the PMOS side and \\(M_1\\) if designed appropriately will allow isolation from the ground supply. This is particularly useful in differential configurations where capacitance on a common \\(V_R\\) or \\(V_S\\) can minimize high frequency noise from coupling directly to the differential phase component through the common mode feedback.
$$ V_{RS} = V_{th} + \eta U_T \ln \left( \frac{2 I_B}{2\eta U_T^2 \mu C_{ox}} \frac{L}{W} \right) $$%
{{< figure src="technical_3/schematic_RO.pdf" title="Figure 70: Schematic of current regulated ring oscillator with capacitively couple noise source. " width="500" >}}
The defining characteristic of the current biased oscillator is that the conduction of the NMOS and PMOS devices in each delay element is strictly non-overlapping. This is different when compared to oscillators biased in strong inversion and implies maximum current efficiency in a large signal sense. In addition it leads to the respective NMOS and PMOS ISF being non-negative. Thus the focus should lie with optimizing its rms value by balancing pull-up pull-down conductance. In fact we can empirically demonstrate that despite the intricacies of non-linear phenomena a current starved ring oscillator presents a significantly superior noise excess factor when compared to that of a transistor biased with the same weak inversion conditions due to change being retained in the high impedance nodes.
{{< figure src="technical_3/state_variables.pdf}" width="500" >}}
{{< figure src="technical_3/ISF_bias_nmos_pmos.pdf}" title="Figure 71: Simulation results outlining the dependency of parameter dynamics as a function of oscillator phase" width="500" >}}
Figure 71 exemplifies the challenge of being able to predict internal parameter dependency analytically. Specifically in \textbf{a)} where the NMOS and PMOS of a single delay slice is evaluated both the saturation and linear conduction phases contribute towards accumulated phase noise. It is indicative to note that the bias transistor has a near uniform ISF equal to \\(2\pi/q_{max}\\) independent of phase state as expected from the linear phase to charge relation. Here \\(q_{max}\\) simply represents the total charge dissipated by the ring oscilator each cycle which is \\(2N V_{RS} C_{gate}\\). In particular this phase independent sensitivity is surprisingly independent of oscillator configuration in terms of number of stages and delay cell input capacitance. Instead the characteristic relies on the capacitance and channel resistance seen at the drain of M2 such that increasing impedance improves linearity.
When the aggregate contribution of all delay elements is taken into account as well as the increased noise excess factor in the linear region the ISF in \textbf{b)} appears predictable when normalized to that of M2. One may expect that the aggregate ISF of the ring oscillator to exceed the sensitivity to that of M2 as its contribution should have a similar profile and more noisy elements are involved. However the soft-switching of each delay element filters out a significant component of injected noise in addition to the fact that the nodes \\(V_R\\) and \\(V_S\\) retain accumulated current noise that feedback on the following stage.
Insight to optimizing the oscillator consideration is drawn from considering the lossy integration phases on \\(V_X\\). Specifically as the transistors M1 and M2 present high impedance when considering the injection of charge or integration of a noisy current. We can infer that resulting voltage fluctuations are either one of two cases; coupled to \\(V_R\\) or \\(V_S\\) through a transistor in the linear region, or coupled to the switching capacitance during a transition. Rejection of the former will rely on increasing \\(q_{max}\\) and minimizing coupling factors as the ISF is equivalent to that of the bias current.
{{< figure src="technical_3/ISF_M2_compensate.pdf}" width="500" >}}
{{< figure src="technical_3/ISF_M2_injct.pdf}" title="Figure 72: The compensation effect of M1 on the ISF for capacitively couple noise sources with reference to Figure 70" width="500" >}}
It is well known that the dominant factor of noise in ring oscillators comes from supply variations that are capacitively coupled as illustrated in Figure 70. This represents the coupling expected from substrate noise and supply noise that is not generated by the transistors them selves. The impact of introducing M1 opposed to grounding \\(V_T\\) is shown by Figure 72 with a dramatic improvement in ISF characteristics. Moreover large drain resistance of M1 allows the peak to peak ISF to be adjusted by exploiting the dynamics previously discussed. On that note it is important to realize that unlike Gm-C differential implementations the rejection of common mode signals is not present due to the coupling dependency of on phase. The matching/minimization of these factors can still allow a considerable improvement towards performance in practice but the process of optimization is challenging due to the fact that these components can not be well predicted as a priori. More generally incoherent perturbations in differential implementations will scale with \\((\Gamma_{rms}-\Gamma_{dc})^2\\).
It may be obvious that there no high impedance analogue nodes in this configuration that could introduce undesirable poles. But more importantly we do not need to provide extra voltage headroom or a second gain stage to let our output signal vary with maximum amplitude. In this case the oscillator mostly reuses the V<sub>SR<sub> voltage headroom. This raises an interesting question; what limits the required voltage headroom for this circuit? Typically the complementary structure necessitates that the source drain voltage of the current bias transistors and differential pairs is sufficient to provide good channel resistance. However there is another component with regard to the noise generated by the oscillator that should be considered in terms of the oscillator voltage overhead V<sub>RS<sub>. This leads us to evaluate the dependency on sampling noise with respect to the loading capacitor of each delay cell. Considering that the scaling the technology can result in a higher oscillator frequencies and equivalently using a small loading capacitance for the same power budget. It is important to realize that it is a charge induced as sampling noise on each capacitor before each up/down transition as residue from the previous cycle. This sampling noise can be referred to the input of M2 which leads to the expression in Equation 41.
$$ v^2_{smp} = \frac{1}{Gm^2_{M2}} \cdot \underbrace{2N f^2_{osc} kT C_{gate}}_{Noise \: power} $$
As Equation 41 suggests this noisy charge injection occurs for every transition in a delay element which is \\(2N\\) times per period. When we expand this expression in terms of the oscillator power dissipation we can show its underlying dependency in Equation 42.
$$ v^2_{smp} = \frac{4kT}{P_{osc}} \cdot \left( \eta U_T \right)^2 $$
Now it should be clear from Equation 42 that this contribution only depends on the total power dissipation of the oscillator \\(P_{osc}\\). This profound result confirms that without considering band-limiting factors all transistor generated noise densities are in fact independent of the frequency or total capacitance when referred to the gate of the biasing transistor. Following our expectation is that the dominant factor for noise is the total biasing current of the structure which is fundamentally identical to that of an conventional amplifier.
## 46 Time Domain Sensor interface
A principle element to these systems is associated with achieving effective conversion from continuous analogue signals to time encoded binary signals without distortion or excess signal corruption. It is typical to see the removal of VCO non-linearity though LMS post-processing[^180] however this level of in-channel DSP can also be avoided through feedback utilizing the linearity of passive components. Our endeavour here lies with applying the discussion and topology selection in Section 23 to VCO based structures that follow closely to our optimization methodology. We suggest thinking of the oscillator's phase as an analogue memory that represents the state variable of the system which we can freely adjust by injecting charge.
This approach is different from that currently seen in the literature for time-domain based instrumentation of low frequency signals. The time domain encoding concept is predominantly used in asynchronous ADCs that aim to avoid quantization noise from being introduced [^181][^182]. There is some motivation here to approach a neuromorphic amplifier topology that generates tokens with time-domain events that encode the input signal intensity [^183]. Many of these structures leverage signal dependent power dissipation that reduces as the input signal varies more slowly. However they are typically open-loop topologies to avoid a complicated feedback DAC where events are generated upon asynchronous level crossings that reset internal integration nodes or toggle the reference voltages. Linearity and dynamic range can become difficult to achieve while maintaining aggressive power efficiency because resetting integrators or changing references are large signal discontinuities.
{{< figure src="technical_3/LNTI.pdf}" width="500" >}}
{{< figure src="technical_3/TDFB.pdf}" title="Figure 73: Time domain instrumentation topology for low noise voltage to time-domain conversion." width="500" >}}
The proposed implementation shown in Figure 73. This structure opts for a direct conversion of analogue to phase domain signals by relying on the integration to filter out oscillator harmonics present in the feedback signal. Abstractly the topology is seen as a ideal integrator with integration factor \\(\frac{Gm}{q_{max}}\\) proceeded with a non-linear element that introduces spurs around N times the oscillator frequency when feeding back. Here N is the number of taps in the ring oscillator used to simultaneously evaluate the phase difference of the differential structure. This allows us to freely adjust N for improving \\(\Gamma\\) through increasing \\(q_{max}\\) without sacrificing the ability to suppress the harmonics. Since the signals at the output of the phase frequency detector represent the phase difference between the two oscillators is full scale. The capacitive network need to scale down by a relatively large factor to assure \\(V_{x}\\) does not exceed the linear range of the transconductor and is implemented using a capacitance area reduction technique [^184]. When the closed loop gain is large however this concern can be dismissed since the quantization levels scale with $\frac{V_{DD}}{A_{cl} N}$ which will typically be the same order of magnitude as the input signal.
While we are free to adjust the transconductance for noise requirements there is a limitation to the increase the complexity resulting from the capacitive feedback DAC and parallel digital phase processing. Because digital power dissipation scales with $N f_{osc}$ which is bounded by \\(I_B\\) it is independent of \\(N\\) for a fixed capacitive load in the oscillator delay cell. In fact increasing \\(N\\) reduces the total power of the oscillator harmonics as we effectively increase the number of quantization levels. This can be seen at the output of the capacitive DAC but this aspect will not be evident with respect to the processing performed in the time domain.
Note that when using ring oscillators with large number of stages in order to reduce leakage and non-linearities in the limit cycle to some extent we can retain a small factor of \\(N\\) by sub-sampling the output taps of the structure. This does require an integer ratio between the total number of stages and \\(N\\) in order to position the harmonics beyond \\(N f_{osc}\\). Also consider that relation between the phases of the oscillator will imply a specific frequency shaping and harmonic modulation at high frequencies [^185].
The primary design criteria for the phase detector structure and it respective time domain encoding should be related to maximizing power-bandwidth efficiency of digital cells. This is because the time-domain characteristics of the detector could introduce a inverse relation with regard to signal level and required logic gate bandwidth. Using conventional \\(1.5 b\\) encoding with up/down signals for example would give rise to this unwanted discontinuity. This is because the encoding scheme will generate narrower pulses for smaller signals that require exceedingly more bandwidth to process and feed into the time domain memory. It is conceivable that if this bandwidth is insufficient a dead-zone is introduced that is characteristically similar to class-B amplifiers.
Using a single bit representation that results from a XOR phase detector inverts this problem such that for small error the minimum bandwidth is required that successively increases as the loop error increases. In extension any asymmetric switching & delays in driving the capacitive feedback that is expected from process variation exacerbates any capacitive mismatch in the different phases of the feedback additively. These components primarily excite distortion on the output depending on the ratio of gate delay to oscillation period. Here Chopping the input will remove off-set and mismatch related components to a certain extent by up modulating them.
The motivation for using the single stage structure or allocating all the gain to the first stage is also associated with how the supply noise couples to the signal. In this respect we suggest that this structure should be thought of equivalent to that of a ADC. Particularly with respect to the digital feedback where providing asymmetric feedback implies that supply noise coupling can not be cancelled out. In addition capacitive mismatch between the positive and negative branches will also contribute to supply noise coupling. As since supply noise sources couple to the output of the amplifier while providing the maximum closed loop gain minimizes the input referred component. It should be noted that this type of supply sensitivity and capacitive mismatch is equivalent to that found in analogue to digital converters hence this drawback is only with reference to an all analogue solution. Further more once our signal has been encoded in the time domain which we expect to exhibit improved resilience to supply noise because its influence is proportional to the gate delay of the technology used.
{{< figure src="technical_3/schematic_TDI.pdf}" width="500" >}}
{{< figure src="technical_3/schematic_PR.pdf}" title="Figure 74: Transistor level implementation of the phase domain integrator structure with phase detector feedback." width="500" >}}
The schematic implementation of the VCO is show in Figure 74 which is derived from the complementary amplifier structure used in prior work. The fact that both ring oscillators are isolated from the supplies and floating in the middle of the rails presents an improved ISF as well as assuring the buffer that amplifies the clock phases to the full scale is guaranteed to be centred around the switching point of a balanced inverter. The most crucial component for effective operation however lies with the sizing of the input NMOS M2 with respect to loading ring oscillator. The DC operating point M2 and R1 will present an load equivalent to that of a diode connected transistor. If the delay element is balanced the current bias of the oscillator is evaluated with \\(K_{M2}\\) and \\(K_{N}\\) representing the \\(W/L\\) ratio of transistors M2 and the NMOS in the delay cell respectively.
{{< figure src="technical_3/DIG2.pdf" title="Figure 75: Simulated transient behaviour of the differential oscillator and the generated digital output. " width="500" >}}
Figure 75 clarifies the principle operation of this topology. We can see that as two currents are being integrated on the differential oscillator a phase shift will start to emerge when the two waveforms are compared. This phase difference on node $\Delta \phi$ represents our system output where the signal is encoded in the pulse width of the digital signal. This signal is applied to the capacitor array for feedback.
$$ f_{osc} \approx \frac{\alpha I_{M1}}{N C_{gate} V_{th}} \text{where} \alpha = \frac{K_{M2}}{2 K_{N}} $$
The factor \\(\alpha\\) in Equation 43 dominates the noise performance when referred to the input which would ideally approach the \\(NEF\\) of that without the oscillator. Similarly the corner frequency of the oscillator flicker noise which is not rejected by the chopper scales with this factor. It follows that the transistor length of the oscillator has a strong relation with respect to $f_{cor} \propto 1/L^{2}$. Fortunately it is easy to diminish this contribution as only a small bias is needed to result in a oscillation frequency several orders outside the signal bandwidth.
$$ H_{sys}(s) \approx \frac{\eta f_{osc} }{s U_T} \cdot \frac{2-\alpha}{\alpha} N and f \approx \frac{C_I}{C_D} \cdot (N+2) $$
The overall open loop system characteristics \\(H_{sys}\\) evaluated in Equation 44. This reflects the single pole nature of the topology that scales with the oscillator frequency and the number of phases taped out as one may expect. Notably the capacitive feedback structure used can represent a very small feedback factor \\(1/f\\) without excess input capacitance that accommodates a large number of oscillator taps [^186]. Evaluating the low pass 3dB point of the system which reveals a dependency as shown in Equation 45.
$$ f_{3dB} = \frac{\eta f_{osc} }{\alpha U_T} \cdot \frac{N}{N+2} \cdot \frac{C_D}{C_I} $$
This expression is primarily dominated by the oscillator frequency which even for a small bias current can result in a considerable bandwidth. Although this is partially expected due to the fact there is no explicit load capacitance it also illustrates the benefits in FOM that can be achieved with this configuration of current-mode time domain architecture. There is a instinctive concern for the stability of the system as a result of the excessive bandwidth driven by maximizing efficiency. The non dominant poles introduced in the voltage domain is due to the parasitic capacitance on node \\(V_Q\\) typicall will not compromise stability due to coupling to the input of the transconductance at higher frequencies. The non-dominant pole on the time domain is introduced by any delay \\(t_d\\) from the VCO to the output buffers of the PFD as $e^{-j\omega t_d}$. This component can be more restrictive for small loop gain as it does not scale with the power of the input stage but with the supply voltage.
The voltage requirement of this structure is improved by biasing the NWell of the PMOS peudo differential pair to \\(V_{XN}\\) & \\(V_{XP}\\) in a cross coupled fashion to reject the differential lading component. The forward biasing reduces the threshold voltage of the devices allowing a supply voltage down to \\(0.6 V\\) without any considerable impact from leakage currents. This configuration also implies that the common mode at \\(V_X\\) is well regulated by the body transconductance of M4 & M5 rejecting common mode input fluctuation. The main voltage requirement actually comes from the switches of the chopper that feeds the ring oscillator that need good on-resistance to prevent noise injection which implies a minimum voltage of approximately \\(2V_{th}+V_{ov}\\). Back-gate biasing will allow us to reduce the impact of \\(V_{th}\\).
The psuedo-resistive feedback structure in Figure 74 b) extracts the signal component from up modulated aggressors using a current DAC which is resistively coupled to the input to close the loop. This allows us to feed back the full swing digital signals to cancel a DC off-set and sets the input common mode by matching the cross coupled transistor with the input pair. This primarily prevents having to use a cascaded resistor structure in order to deal with the large voltage swing on the output that can significantly degrade performance. While stability is trivialized by the capacitive feed forward signal that grantees stability [^187], it is important to note the design choice associated with the two poles in this feedback loop. One pole lies at the input of the complementary pair associated with \\(C_{fb}\\) and the other is at the gate of the cross-coupled pair \\(C_{x}\\).
$$ \tau_{hp1}(s) \approx C_{fb} \cdot R_{psudo} \text{and} \tau_{hp2}(s) \approx C_{x} \cdot \frac{\eta U_{T}}{I_{M1}} \cdot \frac{W_{M6} + W_{M7}}{W_{M6} - W_{M7}} $$
Equation 46 described the dependency of the two time constants in addition to the capacitive feedback. The reduction in capacitance of the feedback network implies that the high pass filter needs careful design in terms of the resulting pole location as the noise expected from the psuedo resistor will appear increasingly wider band as we try to reduce the total capacitance. Here we allow the second pole of \\(C_{x}\\) to approach DC by having $W_{M6} \approx W_{M7}$ resulting in a integration node. This means that the noise around the chopper frequency is strongly related to amount of capacitance we can allocate to \\(C_{x}\\) and the 1/f agressors are now shaped by the VCO integrator and this capacitance. The bias of \\(I_{M1}\\) in the current DAC should be adjusted to set the pole location close to but smaller than the chopper fundamental similar to the conventional design approach.
When we compare this structure to the conventional topology we realize a number of significant advantages. Primarily the inversion coefficient of the transistors is not bound like in a complementary input stage where the \\(V_{GS}\\) voltage for both the NMOS and PMOS has to be sufficiently large to allow the drain voltage to fluctuate by several \\(100 mV\\). This is particularly significant because the minimum feature size is inverse proportional to the optimal inversion coefficient confirming again that conventional means to not work at nano meter technologies. Here the threshold voltage can be arbitrarily small and we still retain a topology that is independent of supply voltage in the sense that it is strictly current biased. This will lead to improving the tolerance towards wafer level variations of the threshold voltage and carrier mobility which many sub \\(1 V\\) structures do not have. Similarly this implies class-A type power dissipation that minimizes switching current seen at the analogue supplies.
The excess in bandwidth from the VCO despite operating with a very small inversion coefficient has enabled us to achieve both \\(40-50 dB\\) closed loop gain while still retaining excess loop gain that easily exceeds \\(30 dB\\). This excess loop gain in the signal band is facilitated by the near ideal VCO integration of this topology that shapes a number of external noise sources and nonidealities. In particular technology scaling allows us to minimizes the noise gain due to the input capacitance \\(C_g\\) according to the expression $1 + C_{g}/C_{in}+ N/A_{cl}$ [^63]. Hence the VCO topology can allow a reduction for the input capacitance by a very significant factor relating to an impedance enhancement that scales with technology.
{{< figure src="technical_3/Sim_Inband.pdf}" width="500" >}}
{{< figure src="technical_3/Sim_Outband.pdf}" title="Figure 76: Transient noise simulation result of the 180nm CMOS time domain instrumentation topology with a \\(6 mV\\) peak to peak sine input at \\(1 kHz\\)." width="500" >}}
A Transient noise simulation performance is shown in Figure 76. This demonstrates that the dependency on nonlinearity is mainly due DAC mismatch components which are modulated the oscillator frequency spurs. Secondly the noise-floor and corner frequency characteristics follow closely to analytic predictions. In addition for the same current bias as a conventional implementation the structure can achieve an equivalent noise floor but at a reduced voltage overhead. Noticeably in the full spectrum there is a considerable amount of harmonics out side of the band induced by the chopped and oscillator aggressors. These components will need to be filtered out in order to approach a \\(60 dB\\) signal to noise ratio. Interestingly there is an observable gain in noise floor as we approach the point where there is no excess loop gain. Note that the spurious free dynamic range of this structure almost exceeds that of the structure used in Section 23 by a factor of 10 for the same power budget due to the increase input range.
## 47 Time Domain analogue filter
Now that we have addressed the aspects of achieving low noise and linear instrumentation we must proceed to address the mechanisms for filtering to implement a band limiting characteristic necessary for the processing algorithms. There is some diversity in the number of approaches used to filter time domain signals. Most notably the continuous-time FIR based structure that represents a number low power characteristics that scales well with technology without sampling or clocking [^188][^189]. However similarly to conventional FIR structures it is limited to signals where the frequency dynamic range is small in order to keep the filter order small. Other examples are found in PLL structures that lock using coherent phase domain signals which is inherently second order due to the analogue integration node which result in a loss of noise efficiency at low frequencies [^190]. We do mention that VCO-based ADCs have been very successful in achieving efficient high-order noise shaping [^191][^192].
It is important to realize that our proposed instrumentation topology converges on incoherent phase domain signals and neglects the modulation products through construction similar to that of asynchronous \\(\Delta\Sigma\\) modulators[^193]. Here we will take a similar approach to construct a first order phase domain integrator where the time-domain signals are also incoherent. Through simplicity the structure achieves a significantly better dynamic range and voltage scaling capability than its analogue domain counterpart. The premise will lie with our assumption that the intermodulation products of the incoherent frequencies are sufficiently out of band to allow construction of higher order filter structures.
{{< figure src="technical_3/TD_ABST.pdf" title="Figure 77: Closed loop time-domain analogue filtering structure" width="500" >}}
The topology used for analogue filtering of time-domain signals is illustrated in Figure 77. This is based similarly on the phase difference of two ring oscillators that integrate a switched current which is generated by evaluating the difference in duty cycle with respect to the input and feedback. The logic simply advances or recedes the phase difference of the oscillator when there is an excess or lack pulse width when comparing the two inputs respectively. This behaviour is shown in Figure 78. The use of logic gates over avoids any drawback that arise from limited linearity and mismatch in the case of approaching this design with current mixing techniques. More over the efficiency of these operations allows miniaturized reconfiguration in the digital domain with a minimal analogue structure.
{{< figure src="technical_3/DIG1.pdf" title="Figure 78: Simulated transient behaviour of the differential oscillator and the time encoded digital signals internal to the feedback loop." width="500" >}}
Most design considerations here are similar to that of conventional filters. We expect the analogue in-band noise components will scale with the biasing current \\(I_b\\) which will determine its input referred noise relative to the transconductance element $\Delta I$. This however does represent a fundamental drawback since the charge pump transconductance element does not benefit from the sub-threshold slope gain factor. $\Delta I$ will typically be larger for the same bandwidth requirements by a factor of \\(1/U_T\\). Although this factor is essential for achieving smaller cut off frequencies while maintaining large oscillation frequencies. The decreased noise efficiency is the fundamental drawback of using a digital logic instead the capacitive feedback network. However in this scenario the processed signal will already be at full dynamic range with reduced noise requirements.
{{< figure src="technical_3/TD_SUB.pdf}" width="500" >}}
{{< figure src="technical_3/TD_FLT.pdf}" title="Figure 79: Schematic sub-blocks for first-order time domain analogue filter " width="500" >}}
The gate level implementation is elaborated in Figure 79. The charge pump structure here uses a cascaded current source and dummy load for bandwidth improvement. This configuration is important because this operator precedes the integration and consequently has a substantial influence on off-set or distortion near the cut-off. The self referenced bias of the charge pump through M11-M14 should allow to good matching independent of the configuration in biasing transistors M2-M3. Similarly the noise figure is improved by sharing the drain voltage of M12-M13 as its noise is coupled to the common mode.
{{< figure src="technical_3/gmc_eqv.pdf}" width="500" >}}
{{< figure src="technical_3/TD_FLT2.pdf}" title="Figure 80: Bandpass time-domain analogue filter which is cascaded to realize a 4\\(^{th}\\) order TD-BPF." width="500" >}}
The two digital components in Figure 79(a) represent the subtraction for feedback and a gain factor \\(G\\) when the phases of \\(Q\\) are mapped to the output. The subtraction logic is determined by considering the XOR-PWM waveform as a two state input of $\pm 1$ and similarly the DAC input states which in this case is \\(+1/0/-1\\). The configuration of both components should compliment each other. This is exemplified when we consider the summing node for another case when two integrators are cascaded with both outputs fed back to achieve a bandpass response. This configuration is shown in Figure 80. The boolean operation required is shown in Figure \ref{fig:T3_logic} where four levels are needed to include carry signals. Here we compromise with two DAC structures with input states \\(\pm 1\\) and \\(+2/0/-2\\).
\begin{karnaughmap}
\centering
\karnaughmap{3}{\\(\boldmath{F}=D-(Q+X)\\) }{D Q X}{{1}{-1}{3}{1}{-1}{-3}{1}{-1}}{}
\caption{ Karnaugh map associated with the subtracting XOR type PWM signals \\(Q\\) & \\(X\\) from \\(D\\) }
\label{fig:T3_logic}
\end{karnaughmap}
The logic that sums the different phases relies on the coherence of it input. Because we know the different taps of the ring oscillator will not over lap with respect to certain signal range at the output we may isolate the components with the \\(AND\\) operation of two different phases to isolate small variations in pulse width and combine them. Analogous to a variable gain amplifier, if the signal variations exceed the section where the two phases overlap the output will saturate. The significance here is that gain achieved with this operation has arbitrary gain bandwidth product with negligible power dissipation. Once blocking or interfering signals have been removed we may give the signal reconfigurable gain by only using a handful of gates. It simply relies on increasing the number of oscillator taps from the previous stage while maintaining its feedback configuration which is independent of noise & linearity performance. In fact for a gain \\(G\\) on the PWM signal \\(D\\) we require \\(2G\\) taps that are summed according to Equation 47.
$$ Q = \bigcup_{k=0}^{G-1} \{ D_{R k} \cap D_{R k+N/2-R/2} \} Where R= \floor{\frac{N}{G}} $$
While \\(AND\\) & \\(OR\\) will perform equivalent operations that retain the oscillator phase difference \\(\Phi\\) but subtract a signal independent component which the gate delay between the two phases being operated on from the pulse width. Here \\(\Phi\\) is normalized such that it represents \\(1\\) and \\(0\\) when the oscillator phase difference is \\(\pi\\) and \\(0\\) respectively. This implies that for a positive gate delay number of $\Delta T$ we will have an output off set by $Q=\Phi - \frac{\Delta T}{N}$. If an \\(XOR\\) gate is used we extract a signal independent component as $Q=2 \cdot \frac{\Delta T}{N}$. Both statements will hold true as long as $\Phi < 1-2\Delta T$ which implies that the pulse section used for computation is signal independent. Using this rather simple construction of logic one may sum phases that are one radian apart with a \\(XNOR\\) gate to realize the absolute value operator which exemplifies the rich utility of this time domain processing.
$$ H_{sys}(s) = \frac{ G }{1 + s/p_1} \text{where} p_1 = \frac{N }{q_{tot}} \cdot \Delta I = \frac{ N \omega_{osc} }{ K } $$
When the primitive topology in Figure 77 is analysed in the Laplace domain we can derive the Equation 48. This demonstrates a first order characteristic similar to the amplifier and has is a close relationship with the oscillation frequency and the filter bandwidth with the addition of the gain factor \\(G\\).
This filter configuration here specifically designed for a $0.18 \mu m$ process. Considering that digital filters will become more viable as the technology node decreases it should be acknowledged that the proposed time-domain filter structure will only be advantageous when frequency dynamic range is large and memory is limited. This is primarily because the \\(kT/C\\) relations inhibit very aggressive sizing in the oscillator structure particularly if no excess loop gain is available. We still require a large amount of energy storage \\(q_{max}\\) to prevent external noise sources from perturbing the output. We point out the proposed topology discussed here provides the means by which instrumentation can successfully scale with technology characteristics. Particularly as it is robust towards transistor non-linearity and imperfections. A large component for performance enhancement will rely on calibration components that improve the resilience of the capacitive feedback structure and filter parameters to allow miniaturization. While this specific time-domain topology will not allow the absolute minimum supply voltage this configuration does take advantage of transistor sub-threshold slope which implies a fundamentally superior noise performance that can also circumvent supply noise.
{{< figure src="technical_3/TD_sys_sim.pdf" title="Figure 81: Transient noise simulation of proposed instrumentation amplifier with time-domain filter structure with a \\(6 mV\\) peak to peak sine input at \\(1 kHz\\)}\label{fig:T3_sys_sim" width="500" >}}
{{< figure src="technical_3/65nQ.pdf" title="Figure 82: Transient noise simulation result of the proposed instrumentation topology in 65nm CMOS with \\(2 mV\\) peak to peak sine input at \\(2 kHz\\)}\label{fig:T3_65nm" width="500" >}}
As shown in Figure 81 both a low noise floor and band limiting behaviour is achieved. In particular we see a \\(40 dB\\) roll off in the noise floor at the \\(6 KHz\\) cut-off frequency from the \\(4^{th}\\) order bandpass filter. While Table 11 reveals some similar performance characteristics as the conventional implementation in Section 23 which is the result of using the same optimization strategy. However this work is the first to consider NEF maximization for the design of time-domain circuits. As a result we are much more confident about the power efficiency for this implementation. As a reference this topology was also implemented using a 65nm CMOS process without filtering structure to confirm the scalability of this structure with the noise transient simulation shown in Figure82. The compact capacitive feedback may not allow linearity beyond 60dB but given the scalability and efficiency of this design there is a significant advantage over current state-of-the-art.
Table 11:
| Parameter | Units | \multicolumn{2}{c}{This work} | Chandrakasan [^194] | Tsividis [^195] | Markovic [^180]|
|----|----|----|----|----|----|
| Modality | | Time | Time | Voltage | Time | Time |
| Technology | [nm] | 180 | 65 | 180 | 28 | 40|
| Supply Voltage | [V] | (0.6) | (0.5) | $0.2 \| 0.8$ | (0.65) | (1.2)|
| Total Current | [(\mu)A] | (0.8) | (1.5) | (1.8) | (36.92) | (5.8) |
| Bandwidth | [Hz] | (375)-(6k) | (1)-(6k) | (1)-(1k) | (40M) | (3-1.5k) |
| Filter Order | | IIR (4^{th}) | - | IIR (2^{nd}) | FIR (8^{th}) | - |
| Noise Floor | [(nV/√{Hz}) ] | (69.4) | (57.5) | (36) | (514) | (427) |
| Noise Corner | [Hz] | (<10) | (<10) | (0.5) | - | (<1)|
| SFDR | [dB] | (58) | (54) | (50.4) | (30) | (78) |
| Area | [mm(^2)]| $115 \times 100 ^\star$ | $64 \times 69 ^\star$ | $800 \times 775$ | $72 \times 45$ | $280 \times 360$ |
| NEF | | (1.18) | (1.22) | (2.1) | (8.13) | (12.9) |
| Chopped Input Capacitance | [pF] | 0.04 | 0.03 | 21.5 | 0.01(^\dagger) | - |
This brings us finally to finding a satisfactory answer to how the area-power product figure of merit limited or bounded in some sense. Section \ref{ch:T1_model} argued that linearity and quantization was crucial constraint in the conventional structures which is not the case for the proposed structures. Instead we observe from Equation 41 we must dissipate a certain power level in the oscillator which we know is biased by a fractional current related to the input referred noise through \\(\alpha\\). As a result the current of the oscillator is fixed and thus when the voltage \\(V_T\\) is scaled down this sampling contribution will progressively become larger to the point that is it comparable to that of the thermal noise. This equality reveals the oscillator voltage should not approach $\alpha \cdot 2U_T$ or the NEF efficiency factor will degrade. We can assert that although at first it appeared that the sampling noise limited the minimum size of the instrumentation circuit here is limits the minimum power of the circuit in a much more explicit manner. The area requirement is more simply proportional to \\(K_F/\alpha\\) reflecting the location of the flicker noise corner and the target oscillator frequency. There are some details remain with regard to choosing \\(\alpha\\) which represents one degree of freedom for trading off oscillator area for minimum voltage but is also strongly depedent on the system bandwidth.
# 48 Analogue Signal Classification
Now our interests will be redirected towards the methods and hardware implementation of neural spike analogue classification in order to faithfully demonstrate that continuous time instrumentation can provide a substantial improvement over the conventional approach at the system level. In particular we demonstrate an unsupervised method that will allow the classification of spikes without requiring signal quantization at any stage of the adaptive process with empirical results.
{{< figure src="technical_3/Nsample.pdf}" width="500" >}}
{{< figure src="technical_3/Fsample.pdf}" title="Figure 83: Illustration of Nyquist rate feature extraction and using feature enhancement in order to operate at sub-Nyquist rates. " width="500" >}}
The abstract motivation here is illustrated in Figure 83. Utilizing digitized recordings as basis for feature extraction implies the necessity of operating with excessive data rates in order to capture the full bandwidth of features in the signal such that $f_s > 2 f_{BW}$. By using mechanisms that enhance & extract prominent features directly in the analogue domain this sampling constraint is eliminated [^141]. Instead we may sample at the rate of spikes present in the recording. Even by approximation we can assert that $f_n << f_s$. In some sense this motivation inspired by that of adaptive compressed sensing or sparse representation methods [^196]. Here we will introduce a perspective based on realizing a less generalized method that can be integrated effortlessly which has not yet been attempted in the literature. The challenge for this approach is finding efficient analogue operators that allow direct feature extraction and more importantly feedback mechanisms that adaptively improve the feature extraction process without substantial resource requirements or supervision.
The notion that motivated this specific classification structure is that in order to improve alignment and thereby reducing how noise couples to features relatively high sampling rates are needed. This implies high temporal resolution for these spread-spectrum signals is desirable such an approach but has unavoidable implications on larger memory and power requirements. As we shall see analysing \\(K\\) features for \\(M\\) centroids with mixed signal methods will require \\(KM+K\\) registers and \\(max(K,M)\\) integrators where register depth has logarithmic dependency on temporal resolution. In contrast to PCA, template matching, and many all-digital methods where temporal resolution or window size is linearly proportional to register count. While it is still vital to align the analogue operators with the spike waveform, increased clock rate does not influence the analogue power dissipation since signal quantization is not performed.
It is relatively rare to see analogue or mixed signal implementations for machine learning classifiers due to the convoluted impact circuit imperfections has of learning dynamics [^197]. This makes it difficult to successfully realize more complex architectures but the methodology can significantly increase the information storage density at very low power budgets. This is exemplified by the system in [^198] that not only achieve 1.04 GOPS/mW but also an area efficiency of 0.03 GOPS/mm\\(^2\\) using a 130 nm technology. Here the continuous valued charge on floating gates was used to preserve learned features without quantization of errors.
## 49 Feature Selection
It should be expected that when a spike event it sampled at a relatively high rate we typically only need a select few samples once it is aligned in side a window in order to tell different classes apart. Only when noise becomes a considerable component must we consider multiple samples before we can make an accurate distinction. In such a scenario we would like to use the samples that maximally distinguish classes. That is, we would like to maximize the quality of our feature \\(Q_F\\) by maximizing for instance a simple sum of \\(N\\) maximally separating samples \\(c\\) in the window \\(W\\) with the linear distance operator \\(D\\).
$$ Q_F = \frac{\sum_{i=1}^{N} D(W[c_i]) }{N} + \frac{en_{rms}}{√{N}} + \frac{BG(t)}{N} $$
The expression in Equation 49 primarily tells us that in the presence of white noise \\(en_{rms}\\) and background activity \\(BG\\). Increasing the number of samples reduces the contribution of white noise by \\(√{N}\\). However if the new samples have negligible signal quality our aggregate distance will decrease fractionally by \\(1/(N+1)\\). This suggests that we should avoid using on a large ensemble of samples because it avoids complexity and may very well improve classification accuracy. Implementing an effective analogue solution requires the evaluation of optimal section in the spike window. To analyse this problem let us define a distance to noise ratio \\((DNR)\\) with respect to the mean spikes of \\(M\\) classes and their standard deviation for each sample in the spike window as;
$$ DNR[n] = \frac{\sum_{i=2}^{M} |\mu_{0}[n] - \mu_{i}[n]|}{√{\sum_{k=1}^{M}\sigma_k^2[n]}} $$
Where \\(\mu_0\\), \\(\mu_k\\),\\(\sigma_k\\) are the mean of all spike waveforms, mean of spike waveforms in class \\(k\\) and the aggregate standard deviation of class \\(k\\) respectively. In a more general form of choosing samples that maximize Equation 50 can be seen as classification by expectation maximization[^199]. In Figure 84 we exemplify this quality factor for a number of training data sets along side the first principle component of each set respectively.
{{< figure src="technical_3/S2PcorA.pdf}" width="500" >}}
{{< figure src="technical_3/S2PcorB.pdf}" width="500" >}}
{{< figure src="technical_3/S2PcorC.pdf}" title="Figure 84: Illustration of feature dependency for windowed neural spikes for data sets from \cite[roman]{} with \\(-16/,dB\\) background noise and \\(-20 dB\\) added white Gaussian noise." width="500" >}}
A number of observations can be made. In particular for a variety of spike shapes show PCA peaks in the first moment which are convex with respect the depolarizing and repolarization sections. In contrast to the DNR plot shows multiple local minima and thus optimization in this space is not considered trivial. What should be pointed out is that the peaks in the PCA curve will typically correspond to good DNR points as they will relate to sections of high variance due to maximum class separation on top of the noise variance. It should also be clear that our interest does not lie in the refractory period as the slow-wave component is small in magnitude and typically corrupted by high-pass filters that reject environmental interference. Hence we inherently expect poor DNR in the latent refractory period of the recorded action potential. One of the more significant implications of not quantizing the signal is related to the fact that features can generally not be extracted before the detection event. This implies that the operator used for detection should avoid introducing group delay that could result in completely missing the most energetic features in the spiking event.
In actuality this hints at the contradictory advantage of analogue filter detection over an FIR filter equivalent. That is this group delay exclusive to IIR filters is highly dependent on the frequency content of the spike waveform. This can to some extent be observed in Figure 84 where class 2 is deliberately delayed with respect to the alignment point since it has a smaller derivative or equivalently less high frequency content. Here the alignment is a achieved by conditioning the signal with a narrow bandpass filter and looking for a peak above the threshold. While a relatively simple in implementation, if designed to maximize output signal to noise power it can be quite effective.
The approach to self mixing spike classes to with the sampling or alignment strategy is effective at improving features of already very similar spike shapes. In fact this alignment in some sense captures the features existent before the detection event and is mixed with latent features. As a result although analogue techniques are less effective at demonstrating resilience towards background noise they can efficiently mix different features to improve discrimination between spike shapes.
## 50 Mixed Signal Implementation
The adaptive method employed here is to section the spike waveform depending on the redundancy in the number of features required. Noting that features in the same polarizing phase will correlate strongly since they emerge from the same phenomena. Each section after the detection event is bounded as priori to grantee non-overlapping features (i.e. $0-150 \mu s , 170-310 \mu s$) and the maximum variance is found in each section respectively. These are assumed as optimal DNR features referred to as \\(\Omega\\)s. Our classification will integrate around these points and perform k-means clustering in the resulting space.
{{< figure src="technical_3/TD_SYS.pdf" title="Figure 85: System abstraction showing the configuration for pre-filtering detection and reconfigurable integrators. " width="500" >}}
The topology is summarized in Figure 85 where the predominant active component lies with the state machine reconfiguring the integrators to optimize the classification. The noise rejection performed by three bandpass filters primarily removes out of band aggressors that prevent accurate classification. Notice the feedback loop for detection relies on a long term average of a narrow band component in addition to a indication of a localized peak above the threshold. Filters \\(F1\\) & \\(F2\\) are band pass filters with first order roll-off and a \\(0.4-7 kHz\\) bandwidth where as \\(F3\\) is a narrow band of $2.5-4.5 kHz$ to maximize group delay sensitivity. There is an additional advantage of pre-sectioning the waveform which is that these optimal points can be found independently in sequence. During initialization we seed the starting point in the middle of the section.
{{< figure src="technical_3/TD_VM.pdf" title="Figure 86: Illustration of closed loop control for finding point of maximum variance. " width="500" >}}
The control loop for implementing this method is shown in Figure 86. Here \\(\Omega_{1/2}\\) represents the temporal off-set separated by $20 \mu s$ with respect to the detection event around which the signal is integrated in the analogue domain. The digital integrators primarily average the aggregate statistics to assist long term convergence by tracking the mean value of both integration results. This allows us to compare the deviation from the mean for each spike event and evaluate which has a larger variance. Note a key characteristic is that signal being analysed is band limited to such an extent that we do not expect local minima within each separate section. Since the digital integrators are accumulating boolean results to reject the uncorrelated noise the factor \\(a_{1}\\) represents the register depth of the counter. To be more precise the \\(\Omega\\)s are taken as a first order difference between the detection event and an off-set.
$$ X(t) = \underbrace{\int_{t0+\Omega}^{t0+\Omega+\Delta +MA} Q_{out}(t) dt}_{Integrated \: Signal} - \underbrace{ 2 \cdot \int_{t0}^{t0+\Delta} Q_{out}(t) dt}_{Off-set} $$
This first order difference operation is shown in Equation 51 where \\(t_0\\), \\(\Delta\\), and \\(Q_{out}\\) are the time where the spike even is aligned, static integration time of $20 \mu s$, and analogue signal containing the spike. This clarifies that the moving average \\(MA\\) is mixed with the signal when it evaluates the mean of the \\(\Omega_{1}\\) section. This approach primarily helps with a self referenced gain that allows smaller register depth.
{{< figure src="technical_3/TD_CC.pdf" title="Figure 87: Illustration of closed loop control for tracking two-centroids with the \\(\Omega_{1}\\) feature. " width="500" >}}
After several seconds of training data or equivalent spike count we can assume that the sections that maximize variance have been approached. At this point the \\(\Omega\\)s are fixed and the centroids need to be generated to complete the adaptive process for classification. As illustrated in Figure 87 a similar feedback mechanism is used to adjust the mean centroids based on boolean results. This particular configuration is the adjustment of two centroids based on one feature in the \\(\Omega_1\\) section. By adjusting the centroids \\(MA_{\mu}\\) when it is the closest to the new data point we realize a k-means clustering method with a \\(l_0\\) norm distance operator.
Since we bound the \\(\Omega\\) sections to be strictly non-overlapping the same analogue integrator can be used to evaluate the accumulated error of all features to each centroid. Moreover for a small \\(a_1\\) the centroid adjustment can be time multiplexed leaving a reduced requirement on the total number of integrators required. This implies that \\(K\\) integrators are needed to iterative adjust all the centroids and \\(M\\) integrators are needed to evaluate the distance from each centroid. Because this adaptive process is performed in isolation we may perform the training in phases that updates clusters and features separately we will only need \\(M\\) or \\(K\\) integrators concurrently which ever is more demanding. However \\(KM\\) registers are needed to specify the location of each centroid which should be converted to a time-domain signal by using reconfigurable delay lines.
{{< figure src="technical_3/TD_ADR.pdf" title="Figure 88: Delay line configuration for evaluating the absolute difference between the asynchronous time domain signal \\(D\\) and the registered centroid position \\(X\\). " width="500" >}}
Such a configuration is illustrated in Figure 88 where there is course control by selecting different phases of \\(D\\) and fine control with a conventional multiplexed delay structure. Again the reduction in complexity and rejection of quantization noise by performing time domain computation opposed to the equivalent \\(8b\\) full adder is typical of this processing modality. Finally the question should remain is that how are centroids initialized without requiring quantization. This requirement is avoided by using an iterative method with respect to centroid generation. After having a single centroid converge to the mean of the feature space we iteratively split centroids in two while training similar to that discussed in Section36. We presume redundant clusters will be generated that are removed if supervision is allowed to intervene or in the case that high level control is used to analyse which clusters are significant after several iterations. The results presented here however do not consider this supervision.
## 51 Validation
In order to demonstrate the viability of this approach we will simulate a linearised model that is constructed using Matlab. Here we aim show to what extent unsupervised methods are constrained with respect to classification performance. Original data sets used in Section 33 have been up sampled from \\(24 kS/s\\) to \\(240 kS/s\\) after the band limiting filters to emulate the continuous time logic that will operate at a high clock rate.
{{< figure src="technical_3/feature_clean.pdf}" width="500" >}}
{{< figure src="technical_3/feature_noisy.pdf}" title="Figure 89: comparing PCA and \\(\Omega\\) feature distribution for the Difficult2 data set. Ground truth for spike classes annotated as cyan, maroon, yellow and blue for false positives." width="500" >}}
The feature space resulting from this method is exemplified in Figure 89. Here we compare it to that of the two component PCA feature space since the \\(\Omega\\) represents its approximation. It is typical to see multiple additional clusters form either due to the detection of false positives or miss alignment of a spike class in the presence of noise. Initializing extra clusters can typically retain classification accuracy in noisy environment but degrade precision in pristine conditions.
{{< figure src="technical_3/A05.pdf}" width="500" >}}
{{< figure src="technical_3/B05.pdf}" title="Figure 90: \\(\Omega_2\\) and \\(\Omega_3\\) classification for data sets with \\(-26 dB\\) background activity." width="500" >}}
{{< figure src="technical_3/A01.pdf}" width="500" >}}
{{< figure src="technical_3/B01.pdf}" title="Figure 91: \\(\Omega_2\\) and \\(\Omega_3\\) classification for data sets with \\(-20 dB\\) background activity." width="500" >}}
{{< figure src="technical_3/A02.pdf}" width="500" >}}
{{< figure src="technical_3/B02.pdf}" title="Figure 92: \\(\Omega_2\\) and \\(\Omega_3\\) classification for data sets with \\(-16 dB\\) background activity." width="500" >}}
The results in Figure 91 demonstrate classification accuracy in terms of the percentage of all correctly classified events with respect to the ground truth including false positives and false negatives. This indicates that when a signal to noise ratio exceeds \\(20dB\\) the conditions are quite forgiving towards the simplicity of the algorithm. The two features used here require very little effort to adapt and classify activity. It is important to mention that a fixed filtering configuration is maintained for all test points in order to demonstrate adaptive characteristics.
The results in Figure 92 shows improvement in noisy conditions if the number of sections is increased to 3 implying a three dimensional feature space to improve centroid distance. Using the same algorithm for feature selection the configuration can deal with twice the amount of background noise without supervision. In some sense the fact that the signal is not quantized does not have a significant impact on classification accuracy. This highlights the importance of closed loop algorithms whether resources are constrained or not. As such constructing a convex search space or extracting well reasoned features from underlying phenomena is crucial to reducing in complexity.
{{< figure src="technical_3/CA01.pdf" title="Figure 93: False alarm rates normalized by true positives for the analogue detection." width="500" >}}
Figure 93 shows that these noise levels detection is relatively consistent but not as adaptive as the digital approach. The threshold for detection will favour generating false positives over false negatives. The main point of failure for noise levels beyond that point lies with the inability to perform feature selection based on localized variance maximization. This is partially expected as PCA will similarly perform poorly when noise levels become comparable to the signal.
In a practical case it may be difficult to ascertain if signal to noise level is adequate to trust classification unless there is confidence to do so in the sense that there may be redundancy in the recording taken. However it is significantly more viable for realizing sub $1 \mu W$ neural spike classification for large scale recordings considering the resource requirements for adaptive classification. Given that each integrator consumes less that \\(50 nW\\) in $0.18 \mu m$ CMOS and each structure needs minimal supervision.
Table 12: Overview of Detection & Classification performance in green for data sets from [^1] for different methods. \\(\star\\) Requires off-chip Supervision. \\(\dagger\\) White noise is also added at -20dB of the signal power.
| Method | Analogue | Digital Registers | Cycles / Sample | Data Set | \small{Background} @ -16dB (^\dagger) | \small{Background} @ -20dB (^\dagger) |
|----|----|----|----|----|----|----|
| \multirow{3}{2.5cm}{RVD} | \multirow{3}{2.5cm}{1(\times)ADC} | \multirow{3}{2cm}{83} | \multirow{3}{2.5cm}{172} | Easy 2 | \flcl{0.734} | \flcl{0.842} |
| | | | | Diff. 1 | \flcl{0.729} | \flcl{0.871} |
| | | | | Diff. 2 | \flcl{0.748} | \flcl{0.848} |
| \multirow{3}{2.5cm}{Template} | \multirow{3}{2.5cm}{1(\times)ADC} | \multirow{3}{2cm}{105} | \multirow{3}{2.5cm}{90} | Easy 2 | \flcl{0.820} | \flcl{0.876} |
| | | | | Diff.1 | \flcl{0.860} | \flcl{0.835} |
| | | | | Diff. 2 | \flcl{0.803} | \flcl{0.875} |
| \multirow{3}{2.5cm}{WDF [^200] } | \multirow{3}{2.5cm}{2(\times)BP-Filter 1(\times)ADC} | \multirow{3}{2cm}{41} | \multirow{3}{2.5cm}{104(^\star)} | Easy 2 | \flcl{0.951} | \flcl{0.991} |
| | | | | Diff. 1 | \flcl{0.850} | \flcl{0.929} |
| | | | | Diff. 2 | \flcl{0.846} | \flcl{0.916} |
| \multirow{3}{2.5cm}{(\Omega_3) Features} | \multirow{3}{2.5cm}{3(\times)BP-Filter 4(\times)Integrator 4(\times)DAC} | \multirow{3}{2cm}{16} | \multirow{3}{2.5cm}{1} | Easy 2 | \flcl{0.800} | \flcl{0.946} |
| | | | | Diff. 1 | \flcl{0.723} | \flcl{0.931} |
| | | | | Diff. 2 | \flcl{0.798} | \flcl{0.886} |
A number of methods are shown in Table 12 where we see classification accuracy and the corresponding hardware requirements in both the analogue and digital domain. The RVD and template methods presented in Section 33 represent the digital approach where little analogue components are needed beside the quantizer. Allocating more processing power or memory resources would imply choosing one over the other. As expected supervised intervention allows methods like WDF [^200] to leverage a substantial improvement with respect to resource efficient classification. In this perspective we see using \\(\Omega_3\\) features as distributing our resources in the analogue domain while still maintaining comparable classification accuracy but require less reliance on digital scaling factors. We provide more comparison details in Section 62 for the proposed digital and analogue methods proposed by this work as well as the equivalent Matlab implementation used for evaluation.
# 52 Conclusion
This chapter has proposed a number of time-domain constructs that encourage mixed signal design for instrumentation. Where we derived underlying concepts from the phase state of a ring oscillator in order to represent continuous valued time domain memory as the equivalent of a clocked filp-flop or sampled capacitor. In addition we have discussed the means to analytically evaluate and optimize the characteristics of these topologies. Overall we present are clear benefits over conventional implementations such as instrumentation and the functional manipulation of continuous valued signals. Moreover these structures will scale performance with technology due to the extensive use of digital gates. The instrumentation structure in particular gives way to fully synthesized platforms. Performing processing and filtering in the digital domain remains to be critical for robust sensing of LFPs and EAPs in very poor signal to noise conditions. A 0.6 V 58 dB SNDR time domain instrumentation architecture is demonstrated with a NEF of 1.18 that generates multiphase PWM encoded digital signals using sub 0.01 mm\\(^2\\) footprint and employing bandpass filtering with 40 dB/Dec roll off.
In extension we demonstrated the capacity for mixed signal analogue to information conversion with respect to unsupervised classification that uses adaptive techniques to converge towards specific signal characteristics. Using reconfigurable integration of selected temporal sections in the spike shape lets us effectively focus resources on feature and cluster evaluation without open loop quantization. This mitigates the trade off associated with resolution and digital complexity. The main challenge as pointed out is establishing what dynamics will allow convergence to optimal feature extraction with reduced hardware requirements. Here we exploit certain phenomena in the principle components of spike shapes and the sensitivity of group delay of analogue detection to frequency content in spike waveforms to achieve direct classification.
It is typical that techniques behind instrumentation and signal acquisition are more mature in development and direction when compared to different processing modalities. Especially when realizing mixed signal methods for machine learning where a multitude of convoluted factors impact performance. There is much still to addressed when adaptive techniques are evaluated with respect to their resource efficiency and this will likely be a important aspect that will emerge in many intelligent sensor systems.
# References:
[^1]: R.Q. Quiroga, Z.Nadasdy, and Y.Ben-Shaul, ''Unsupervised spike detection and sorting with wavelets and superparamagnetic clustering,'' Neural Computation, vol.16, pp. 1661--1687, April 2004. [Online]: http://dx.doi.org/10.1162/089976604774201631
[^2]: R.A. Normann, ''Technology insight: future neuroprosthetic therapies for disorders of the nervous system,'' Nature Clinical Practice Neurology, vol.3, pp. 444--452, August 2007. [Online]: http://dx.doi.org/10.1038/ncpneuro0556
[^3]: K.Birmingham, V.Gradinaru, P.Anikeeva, W.M. Grill, B.Pikov, VictorMcLaughlin, P.Pasricha, K.Weber, DouglasLudwig, and K.Famm, ''Bioelectronic medicines: a research roadmap,'' Nature Reviews Drug Discovery, vol.13, pp. 399--400, May 2014. [Online]: http://dx.doi.org/10.1038/nrd4351
[^4]: ''Bridging the bio-electronic divide,'' Defense Advanced Research Projects Agency, Arlington, Texas, January 2016. [Online]: http://www.darpa.mil/news-events/2015-01-19
[^5]: G.Fritsch and E.Hitzig, ''ber die elektrische erregbarkeit des grosshirns,'' Archiv für Anatomie, Physiologie und Wissenschaftliche Medicin., vol.37, pp. 300--332, 1870.
[^6]: G.E. Loeb, ''Cochlear prosthetics,'' Annual Review of Neuroscience, vol.13, no.1, pp. 357--371, 1990, pMID: 2183680. [Online]: http://dx.doi.org/10.1146/annurev.ne.13.030190.002041
[^7]: ''Annual update bcig uk cochlear implant provision,'' British Cochlear Implant Group, London WC1X 8EE, UK, pp. 1--2, March 2015. [Online]: http://www.bcig.org.uk/wp-content/uploads/2015/12/CI-activity-2015.pdf
[^8]: M.Alexander, ''Neuro-numbers,'' Association of British Neurologists (ABN), London SW9 6WY, UK, pp. 1--12, April 2003. [Online]: http://www.neural.org.uk/store/assets/files/20/original/NeuroNumbers.pdf
[^9]: A.Jackson and J.B. Zimmermann, ''Neural interfaces for the brain and spinal cord — restoring motor function,'' Nature Reviews Neurology, vol.8, pp. 690--699, December 2012. [Online]: http://dx.doi.org/10.1038/nrneurol.2012.219
[^10]: M.Gilliaux, A.Renders, D.Dispa, D.Holvoet, J.Sapin, B.Dehez, C.Detrembleur, T.M. Lejeune, and G.Stoquart, ''Upper limb robot-assisted therapy in cerebral palsy: A single-blind randomized controlled trial,'' Neurorehabilitation AND Neural Repair, vol.29, no.2, pp. 183--192, February 2015. [Online]: http://nnr.sagepub.com/content/29/2/183.abstract
[^11]: P.Osten and T.W. Margrie, ''Mapping brain circuitry with a light microscope,'' Nature Methods, vol.10, pp. 515--523, June 2013. [Online]: http://dx.doi.org/10.1038/nmeth.2477
[^12]: S.M. Gomez-Amaya, M.F. Barbe, W.C. deGroat, J.M. Brown, J.Tuite, Gerald F.ANDCorcos, S.B. Fecho, A.S. Braverman, and M.R. RuggieriSr, ''Neural reconstruction methods of restoring bladder function,'' Nature Reviews Urology, vol.12, pp. 100--118, February 2015. [Online]: http://dx.doi.org/10.1038/nrurol.2015.4
[^13]: H.Yu, W.Xiong, H.Zhang, W.Wang, and Z.Li, ''A parylene self-locking cuff electrode for peripheral nerve stimulation and recording,'' IEEE/ASME Journal of Microelectromechanical Systems, vol.23, no.5, pp. 1025--1035, Oct 2014. [Online]: http://dx.doi.org/10.1109/JMEMS.2014.2333733
[^14]: J.S. Ho, S.Kim, and A.S.Y. Poon, ''Midfield wireless powering for implantable systems,'' Proceedings of the IEEE, vol. 101, no.6, pp. 1369--1378, June 2013. [Online]: http://dx.doi.org/10.1109/JPROC.2013.2251851
[^15]: R.D. KEYNES, ''Excitable membranes,'' Nature, vol. 239, pp. 29--32, September 1972. [Online]: http://dx.doi.org/10.1038/239029a0
[^16]: A.D. Grosmark and G.Buzs\'aki, ''Diversity in neural firing dynamics supports both rigid and learned hippocampal sequences,'' Science, vol. 351, no. 6280, pp. 1440--1443, March 2016. [Online]: http://science.sciencemag.org/content/351/6280/1440
[^17]: B.Sakmann and E.Neher, ''Patch clamp techniques for studying ionic channels in excitable membranes,'' Annual Review of Physiology, vol.46, no.1, pp. 455--472, October 1984, pMID: 6143532. [Online]: http://dx.doi.org/10.1146/annurev.ph.46.030184.002323
[^18]: M.P. Ward, P.Rajdev, C.Ellison, and P.P. Irazoqui, ''Toward a comparison of microelectrodes for acute and chronic recordings,'' Brain Research, vol. 1282, pp. 183 -- 200, July 2009. [Online]: http://www.sciencedirect.com/science/article/pii/S0006899309010841
[^19]: J.E.B. Randles, ''Kinetics of rapid electrode reactions,'' Discuss. Faraday Soc., vol.1, pp. 11--19, 1947. [Online]: http://dx.doi.org/10.1039/DF9470100011
[^20]: M.E. Spira and A.Hai, ''Multi-electrode array technologies for neuroscience and cardiology,'' Nature Nanotechnology, vol.8, pp. 83 -- 94, February 2013. [Online]: http://dx.doi.org/10.1038/nnano.2012.265
[^21]: G.E. Moore, ''Cramming more components onto integrated circuits,'' Proceedings of the IEEE, vol.86, no.1, pp. 82--85, January 1998. [Online]: http://dx.doi.org/10.1109/JPROC.1998.658762
[^22]: I.Ferain, C.A. Colinge, and J.-P. Colinge, ''Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors,'' Nature, vol. 479, pp. 310--316, November 2011. [Online]: http://dx.doi.org/10.1038/nature10676
[^23]: I.H. Stevenson and K.P. Kording, ''How advances in neural recording affect data analysis,'' Nature neuroscience, vol.14, no.2, pp. 139--142, February 2011. [Online]: http://dx.doi.org/10.1038/nn.2731
[^24]: C.Thomas, P.Springer, G.Loeb, Y.Berwald-Netter, and L.Okun, ''A miniature microelectrode array to monitor the bioelectric activity of cultured cells,'' Experimental cell research, vol.74, no.1, pp. 61--66, September 1972. [Online]: http://dx.doi.org/0.1016/0014-4827(72)90481-8
[^25]: R.A. Andersen, E.J. Hwang, and G.H. Mulliken, ''Cognitive neural prosthetics,'' Annual review of Psychology, vol.61, pp. 169--190, December 2010, pMID: 19575625. [Online]: http://dx.doi.org/10.1146/annurev.psych.093008.100503
[^26]: L.A. Jorgenson, W.T. Newsome, D.J. Anderson, C.I. Bargmann, E.N. Brown, K.Deisseroth, J.P. Donoghue, K.L. Hudson, G.S. Ling, P.R. MacLeish etal., ''The brain initiative: developing technology to catalyse neuroscience discovery,'' Philosophical Transactions of the Royal Society of London B: Biological Sciences, vol. 370, no. 1668, p. 20140164, 2015.
[^27]: E.DAngelo, G.Danese, G.Florimbi, F.Leporati, A.Majani, S.Masoli, S.Solinas, and E.Torti, ''The human brain project: High performance computing for brain cells hw/sw simulation and understanding,'' in Proceedings of the Digital System Design Conference, August 2015, pp. 740--747. [Online]: http://dx.doi.org/10.1109/DSD.2015.80
[^28]: K.Famm, B.Litt, K.J. Tracey, E.S. Boyden, and M.Slaoui, ''Drug discovery: a jump-start for electroceuticals,'' Nature, vol. 496, no. 7444, pp. 159--161, April 2013. [Online]: http://dx.doi.org/0.1038/496159a
[^29]: K.Deisseroth, ''Optogenetics,'' Nature methods, vol.8, no.1, pp. 26--29, January 2011. [Online]: http://dx.doi.org/10.1038/nmeth.f.324
[^30]: M.Velliste, S.Perel, M.C. Spalding, A.S. Whitford, and A.B. Schwartz, ''Cortical control of a prosthetic arm for self-feeding,'' Nature, vol. 453, no. 7198, pp. 1098--1101, June 2008. [Online]: http://dx.doi.org/10.1038/nature06996
[^31]: T.N. Theis and P.M. Solomon, ''In quest of the "next switch" prospects for greatly reduced power dissipation in a successor to the silicon field-effect transistor,'' Proceedings of the IEEE, vol.98, no.12, pp. 2005--2014, December 2010. [Online]: http://dx.doi.org/10.1109/JPROC.2010.2066531
[^32]: G.M. Amdahl, ''Validity of the single processor approach to achieving large scale computing capabilities, reprinted from the afips conference proceedings, vol. 30 (atlantic city, n.j., apr. 18-20), afips press, reston, va., 1967, pp. 483-485, when dr. amdahl was at international business machines corporation, sunnyvale, california,'' in AFIPS Conference Proceedings, Vol. 30 (Atlantic City, N.J., Apr. 18-20), vol.12, no.3.\hskip 1em plus 0.5em minus 0.4em elax IEEE, Summer 2007, pp. 19--20. [Online]: http://dx.doi.org/0.1109/N-SSC.2007.4785615
[^33]: J.G. Koller and W.C. Athas, ''Adiabatic switching, low energy computing, and the physics of storing and erasing information,'' in IEEE Proceedings of the Workshop on Physics and Computation.\hskip 1em plus 0.5em minus 0.4em elax IEEE, October 1992, pp. 267--270. [Online]: http://dx.doi.org/10.1109/PHYCMP.1992.615554
[^34]: E.P. DeBenedictis, J.E. Cook, M.F. Hoemmen, and T.S. Metodi, ''Optimal adiabatic scaling and the processor-in-memory-and-storage architecture (oas :pims),'' in IEEE Proceedings of the International Symposium on Nanoscale Architectures.\hskip 1em plus 0.5em minus 0.4em elax IEEE, July 2015, pp. 69--74. [Online]: http://dx.doi.org/10.1109/NANOARCH.2015.7180589
[^35]: S.Houri, G.Billiot, M.Belleville, A.Valentian, and H.Fanet, ''Limits of cmos technology and interest of nems relays for adiabatic logic applications,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.62, no.6, pp. 1546--1554, June 2015. [Online]: http://dx.doi.org/10.1109/TCSI.2015.2415177
[^36]: S.K. Arfin and R.Sarpeshkar, ''An energy-efficient, adiabatic electrode stimulator with inductive energy recycling and feedback current regulation,'' IEEE Transactions on Biomedical Circuits and Systems, vol.6, no.1, pp. 1--14, February 2012. [Online]: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6036003&isnumber=6138606
[^37]: P.R. Kinget, ''Scaling analog circuits into deep nanoscale cmos: Obstacles and ways to overcome them,'' in IEEE Proceedings of the Custom Integrated Circuits Conference.\hskip 1em plus 0.5em minus 0.4em elax IEEE, September 2015, pp. 1--8. [Online]: http://dx.doi.org/10.1109/CICC.2015.7338394
[^38]: K.Bernstein, D.J. Frank, A.E. Gattiker, W.Haensch, B.L. Ji, S.R. Nassif, E.J. Nowak, D.J. Pearson, and N.J. Rohrer, ''High-performance cmos variability in the 65-nm regime and beyond,'' IBM Journal of Research AND Development, vol.50, no. 4.5, pp. 433--449, July 2006. [Online]: http://dx.doi.org/10.1147/rd.504.0433
[^39]: L.L. Lewyn, T.Ytterdal, C.Wulff, and K.Martin, ''Analog circuit design in nanoscale cmos technologies,'' Proceedings of the IEEE, vol.97, no.10, pp. 1687--1714, October 2009. [Online]: http://dx.doi.org/10.1109/JPROC.2009.2024663
[^40]: Y.Xin, W.X.Y. Li, Z.Zhang, R.C.C. Cheung, D.Song, and T.W. Berger, ''An application specific instruction set processor (asip) for adaptive filters in neural prosthetics,'' IEEE/ACM Transactions on Computational Biology and Bioinformatics, vol.12, no.5, pp. 1034--1047, September 2015. [Online]: http://dx.doi.org/10.1109/TCBB.2015.2440248
[^41]: G.Schalk, P.Brunner, L.A. Gerhardt, H.Bischof, and J.R. Wolpaw, ''Brain-computer interfaces (bcis): detection instead of classification,'' Journal of neuroscience methods, vol. 167, no.1, pp. 51--62, 2008, brain-Computer Interfaces (BCIs). [Online]: http://www.sciencedirect.com/science/article/pii/S0165027007004116
[^42]: Z.Li, J.E. O'Doherty, T.L. Hanson, M.A. Lebedev, C.S. Henriquez, and M.A. Nicolelis, ''Unscented kalman filter for brain-machine interfaces,'' PloS one, vol.4, no.7, pp. 1--18, 2009. [Online]: http://dx.doi.org/10.1371/journal.pone.0006243
[^43]: A.L. Orsborn, H.G. Moorman, S.A. Overduin, M.M. Shanechi, D.F. Dimitrov, and J.M. Carmena, ''Closed-loop decoder adaptation shapes neural plasticity for skillful neuroprosthetic control,'' Neuron, vol.82, pp. 1380 -- 1393, March 2016. [Online]: http://dx.doi.org/10.1016/j.neuron.2014.04.048
[^44]: Y.Yan, X.Qin, Y.Wu, N.Zhang, J.Fan, and L.Wang, ''A restricted boltzmann machine based two-lead electrocardiography classification,'' in IEEE Proceedings of the International Conference on Wearable and Implantable Body Sensor Networks.\hskip 1em plus 0.5em minus 0.4em elax IEEE, June 2015, pp. 1--9. [Online]: http://dx.doi.org/10.1109/BSN.2015.7299399
[^45]: B.M. Yu and J.P. Cunningham, ''Dimensionality reduction for large-scale neural recordings,'' Nature Neuroscience, vol.17, pp. 1500 -- 1509, November 2014. [Online]: http://dx.doi.org/10.1038/nn.3776
[^46]: S.Makeig, C.Kothe, T.Mullen, N.Bigdely-Shamlo, Z.Zhang, and K.Kreutz-Delgado, ''Evolving signal processing for brain: Computer interfaces,'' Proceedings of the IEEE, vol. 100, no. Special Centennial Issue, pp. 1567--1584, May 2012. [Online]: http://dx.doi.org/10.1109/JPROC.2012.2185009
[^47]: G.Indiveri and S.C. Liu, ''Memory and information processing in neuromorphic systems,'' Proceedings of the IEEE, vol. 103, no.8, pp. 1379--1397, August 2015. [Online]: http://dx.doi.org/10.1109/JPROC.2015.2444094
[^48]: Y.Chen, E.Yao, and A.Basu, ''A 128-channel extreme learning machine-based neural decoder for brain machine interfaces,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.3, pp. 679--692, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2483618
[^49]: V.Karkare, S.Gibson, and D.Marković, ''A 75- $\mu$w, 16-channel neural spike-sorting processor with unsupervised clustering,'' IEEE Journal of Solid-State Circuits, vol.48, no.9, pp. 2230--2238, September 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2264616
[^50]: T.C. Chen, W.Liu, and L.G. Chen, ''128-channel spike sorting processor with a parallel-folding structure in 90nm process,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2009, pp. 1253--1256. [Online]: http://dx.doi.org/10.1109/ISCAS.2009.5117990
[^51]: G.Baranauskas, ''What limits the performance of current invasive brain machine interfaces?'' Frontiers in Systems Neuroscience, vol.8, no.68, April 2014. [Online]: http://www.frontiersin.org/systems_neuroscience/10.3389/fnsys.2014.00068
[^52]: E.F. Chang, ''Towards large-scale, human-based, mesoscopic neurotechnologies,'' Neuron, vol.86, pp. 68--78, March 2016. [Online]: http://dx.doi.org/10.1016/j.neuron.2015.03.037
[^53]: M.A.L. Nicolelis and M.A. Lebedev, ''Principles of neural ensemble physiology underlying the operation of brain-machine,'' Nature Reviews Neuroscience, vol.10, pp. 530--540, July 2009. [Online]: http://dx.doi.org/10.1038/nrn2653
[^54]: Z.Fekete, ''Recent advances in silicon-based neural microelectrodes and microsystems: a review,'' Sensors AND Actuators B: Chemical, vol. 215, pp. 300 -- 315, 2015. [Online]: http://www.sciencedirect.com/science/article/pii/S092540051500386X
[^55]: N.Saeidi, M.Schuettler, A.Demosthenous, and N.Donaldson, ''Technology for integrated circuit micropackages for neural interfaces, based on gold–silicon wafer bonding,'' Journal of Micromechanics AND Microengineering, vol.23, no.7, p. 075021, June 2013. [Online]: http://stacks.iop.org/0960-1317/23/i=7/a=075021
[^56]: K.Seidl, S.Herwik, T.Torfs, H.P. Neves, O.Paul, and P.Ruther, ''Cmos-based high-density silicon microprobe arrays for electronic depth control in intracortical neural recording,'' IEEE Journal of Microelectromechanical Systems, vol.20, no.6, pp. 1439--1448, December 2011. [Online]: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6033040&isnumber=6075219
[^57]: T.D.Y. Kozai, N.B. Langhals, P.R. Patel, X.Deng, H.Zhang, K.L. Smith, J.Lahann, N.A. Kotov, and D.R. Kipke, ''Ultrasmall implantable composite microelectrodes with bioactive surfaces for chronic neural interfaces,'' Nature Materials, vol.11, pp. 1065--1073, December 2012. [Online]: http://dx.doi.org/10.1038/nmat3468
[^58]: D.A. Schwarz, M.A. Lebedev, T.L. Hanson, D.F. Dimitrov, G.Lehew, J.Meloy, S.Rajangam, V.Subramanian, P.J. Ifft, Z.Li, A.Ramakrishnan, A.Tate, K.Z. Zhuang, and M.A.L. Nicolelis, ''Chronic, wireless recordings of large-scale brain activity in freely moving rhesus monkeys,'' Nature Methods, vol.11, pp. 670--676, April 2014. [Online]: http://dx.doi.org/10.1038/nmeth.2936
[^59]: P.Ruther, S.Herwik, S.Kisban, K.Seidl, and O.Paul, ''Recent progress in neural probes using silicon mems technology,'' IEEJ Transactions on Electrical and Electronic Engineering, vol.5, no.5, pp. 505--515, 2010. [Online]: http://dx.doi.org/10.1002/tee.20566
[^60]: ibitem3d-printH.-W. Kang, S.J. Lee, I.K. Ko, C.Kengla, J.J. Yoo, and A.Atala, ''A 3d bioprinting system to produce human-scale tissue constructs with structural integrity,'' Nature Biotechnology, vol.34, pp. 312--319, March 2016. [Online]: http://dx.doi.org/10.1038/nbt.3413
[^61]: ibitemdistrib-electC.Xie, J.Liu, T.-M. Fu, X.Dai, W.Zhou, and C.M. Lieber, ''Three-dimensional macroporous nanoelectronic networks as minimally invasive brain probes,'' Nature Materials, vol.14, pp. 1286--1292, May 2015. [Online]: http://dx.doi.org/10.1038/nmat4427
[^62]: R.R. Harrison, P.T. Watkins, R.J. Kier, R.O. Lovejoy, D.J. Black, B.Greger, and F.Solzbacher, ''A low-power integrated circuit for a wireless 100-electrode neural recording system,'' IEEE Journal of Solid-State Circuits, vol.42, no.1, pp. 123--133, Jan 2007. [Online]: http://dx.doi.org/10.1109/JSSC.2006.886567
[^63]: J.Guo, W.Ng, J.Yuan, S.Li, and M.Chan, ''A 200-channel area-power-efficient chemical and electrical dual-mode acquisition ic for the study of neurodegenerative diseases,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.3, pp. 567--578, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2468052
[^64]: W.Biederman, D.J. Yeager, N.Narevsky, J.Leverett, R.Neely, J.M. Carmena, E.Alon, and J.M. Rabaey, ''A 4.78 mm 2 fully-integrated neuromodulation soc combining 64 acquisition channels with digital compression and simultaneous dual stimulation,'' IEEE Journal of Solid-State Circuits, vol.50, no.4, pp. 1038--1047, April 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2384736
[^65]: R.Muller, S.Gambini, and J.M. Rabaey, ''A 0.013mm$^2$, $5 \mu w$, dc-coupled neural signal acquisition ic with 0.5v supply,'' IEEE Journal of Solid-State Circuits, vol.47, no.1, pp. 232--243, Jan 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2163552
[^66]: H.Kassiri, A.Bagheri, N.Soltani, K.Abdelhalim, H.M. Jafari, M.T. Salam, J.L.P. Velazquez, and R.Genov, ''Battery-less tri-band-radio neuro-monitor and responsive neurostimulator for diagnostics and treatment of neurological disorders,'' IEEE Journal of Solid-State Circuits, vol.51, no.5, pp. 1274--1289, May 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2528999
[^67]: M.Ballini, J.Müller, P.Livi, Y.Chen, U.Frey, A.Stettler, A.Shadmani, V.Viswam, I.L. Jones, D.Jäckel, M.Radivojevic, M.K. Lewandowska, W.Gong, M.Fiscella, D.J. Bakkum, F.Heer, and A.Hierlemann, ''A 1024-channel cmos microelectrode array with 26,400 electrodes for recording and stimulation of electrogenic cells in vitro,'' IEEE Journal of Solid-State Circuits, vol.49, no.11, pp. 2705--2719, Nov 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2359219
[^68]: P.D. Wolf, Thermal considerations for the design of an implanted cortical brain--machine interface (BMI).\hskip 1em plus 0.5em minus 0.4em elax CRC Press Boca Raton, FL, 2008, pMID: 21204402. [Online]: http://www.ncbi.nlm.nih.gov/books/NBK3932
[^69]: T.Denison, K.Consoer, W.Santa, A.T. Avestruz, J.Cooley, and A.Kelly, ''A 2 $\mu$w 100 nv/rthz chopper-stabilized instrumentation amplifier for chronic measurement of neural field potentials,'' IEEE Journal of Solid-State Circuits, vol.42, no.12, pp. 2934--2945, December 2007. [Online]: http://dx.doi.org/10.1109/JSSC.2007.908664
[^70]: B.Johnson, S.T. Peace, A.Wang, T.A. Cleland, and A.Molnar, ''A 768-channel cmos microelectrode array with angle sensitive pixels for neuronal recording,'' IEEE Sensors Journal, vol.13, no.9, pp. 3211--3218, Sept 2013. [Online]: http://dx.doi.org/10.1109/JSEN.2013.2266894
[^71]: C.M. Lopez, A.Andrei, S.Mitra, M.Welkenhuysen, W.Eberle, C.Bartic, R.Puers, R.F. Yazicioglu, and G.G.E. Gielen, ''An implantable 455-active-electrode 52-channel cmos neural probe,'' IEEE Journal of Solid-State Circuits, vol.49, no.1, pp. 248--261, January 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2284347
[^72]: J.Scholvin, J.P. Kinney, J.G. Bernstein, C.Moore-Kochlacs, N.Kopell, C.G. Fonstad, and E.S. Boyden, ''Close-packed silicon microelectrodes for scalable spatially oversampled neural recording,'' IEEE Transactions on Biomedical Engineering, vol.63, no.1, pp. 120--130, Jan 2016. [Online]: http://dx.doi.org/10.1109/TBME.2015.2406113
[^73]: M.Han, B.Kim, Y.A. Chen, H.Lee, S.H. Park, E.Cheong, J.Hong, G.Han, and Y.Chae, ''Bulk switching instrumentation amplifier for a high-impedance source in neural signal recording,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.62, no.2, pp. 194--198, Feb 2015. [Online]: http://dx.doi.org/10.1109/TCSII.2014.2368615
[^74]: R.Muller, S.Gambini, and J.M. Rabaey, ''A 0.013$ $mm$^2$, 5$ \mu$w, dc-coupled neural signal acquisition ic with 0.5 v supply,'' IEEE Journal of Solid-State Circuits, vol.47, no.1, pp. 232--243, Jan 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2163552
[^75]: ''Rhd2164 digital electrophysiology interface chip - data sheet,'' Intan Technologies, Los Angeles, California, December 2013. [Online]: http://www.intantech.com/files/Intan_RHD2164_datasheet.pdf
[^76]: K.M. Al-Ashmouny, S.I. Chang, and E.Yoon, ''A 4 $\mu$w/ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-d neural microsystems,'' IEEE Transactions on Biomedical Circuits and Systems, vol.6, no.5, pp. 403--413, October 2012. [Online]: http://dx.doi.org/10.1109/TBCAS.2012.2218105
[^77]: D.Han, Y.Zheng, R.Rajkumar, G.S. Dawe, and M.Je, ''A 0.45 v 100-channel neural-recording ic with sub-$\mu$w/channel consumption in 0.18$\mu$m cmos,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.6, pp. 735--746, December 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2014.2298860
[^78]: S.B. Lee, H.M. Lee, M.Kiani, U.M. Jow, and M.Ghovanloo, ''An inductively powered scalable 32-channel wireless neural recording system-on-a-chip for neuroscience applications,'' IEEE Transactions on Biomedical Circuits and Systems, vol.4, no.6, pp. 360--371, Dec 2010. [Online]: http://dx.doi.org/10.1109/TBCAS.2010.2078814
[^79]: J.Yoo, L.Yan, D.El-Damak, M.A.B. Altaf, A.H. Shoeb, and A.P. Chandrakasan, ''An 8-channel scalable eeg acquisition soc with patient-specific seizure classification and recording processor,'' IEEE Journal of Solid-State Circuits, vol.48, no.1, pp. 214--228, Jan 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2221220
[^80]: M.A.B. Altaf and J.Yoo, ''A 1.83$ \mu$j/classification, 8-channel, patient-specific epileptic seizure classification soc using a non-linear support vector machine,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.1, pp. 49--60, Feb 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2014.2386891
[^81]: K.Abdelhalim, H.M. Jafari, L.Kokarovtseva, J.L.P. Velazquez, and R.Genov, ''64-channel uwb wireless neural vector analyzer soc with a closed-loop phase synchrony-triggered neurostimulator,'' IEEE Journal of Solid-State Circuits, vol.48, no.10, pp. 2494--2510, Oct 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2272952
[^82]: A.Bagheri, S.R.I. Gabran, M.T. Salam, J.L.P. Velazquez, R.R. Mansour, M.M.A. Salama, and R.Genov, ''Massively-parallel neuromonitoring and neurostimulation rodent headset with nanotextured flexible microelectrodes,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.5, pp. 601--609, Oct 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2281772
[^83]: H.G. Rhew, J.Jeong, J.A. Fredenburg, S.Dodani, P.G. Patil, and M.P. Flynn, ''A fully self-contained logarithmic closed-loop deep brain stimulation soc with wireless telemetry and wireless power management,'' IEEE Journal of Solid-State Circuits, vol.49, no.10, pp. 2213--2227, Oct 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2346779
[^84]: W.Biederman, D.J. Yeager, N.Narevsky, J.Leverett, R.Neely, J.M. Carmena, E.Alon, and J.M. Rabaey, ''A 4.78 mm 2 fully-integrated neuromodulation soc combining 64 acquisition channels with digital compression and simultaneous dual stimulation,'' IEEE Journal of Solid-State Circuits, vol.50, no.4, pp. 1038--1047, April 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2384736
[^85]: A.Mendez, A.Belghith, and M.Sawan, ''A dsp for sensing the bladder volume through afferent neural pathways,'' IEEE Transactions on Biomedical Circuits and Systems, vol.8, no.4, pp. 552--564, Aug 2014. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2282087
[^86]: T.T. Liu and J.M. Rabaey, ''A 0.25 v 460 nw asynchronous neural signal processor with inherent leakage suppression,'' IEEE Journal of Solid-State Circuits, vol.48, no.4, pp. 897--906, April 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2239096
[^87]: D.Han, Y.Zheng, R.Rajkumar, G.S. Dawe, and M.Je, ''A 0.45 v 100-channel neural-recording ic with sub-$\mu$w/channel consumption in 0.18$ \mu$m cmos,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.6, pp. 735--746, Dec 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2014.2298860
[^88]: R.Muller, H.P. Le, W.Li, P.Ledochowitsch, S.Gambini, T.Bjorninen, A.Koralek, J.M. Carmena, M.M. Maharbiz, E.Alon, and J.M. Rabaey, ''A minimally invasive 64-channel wireless $\mu$ecog implant,'' IEEE Journal of Solid-State Circuits, vol.50, no.1, pp. 344--359, Jan 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2364824
[^89]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational amplifiers and their application to continuous-time filters in nanoscale cmos,'' IEEE Journal of Solid-State Circuits, vol.49, no.12, pp. 2758--2772, December 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2354641
[^90]: V.Karkare, H.Chandrakumar, D.Rozgić, and D.Marković, ''Robust, reconfigurable, and power-efficient biosignal recording systems,'' in IEEE Proceedings of the Custom Integrated Circuits Conference, Sept 2014, pp. 1--8. [Online]: http://dx.doi.org/10.1109/CICC.2014.6946018
[^91]: L.B. Leene and T.G. Constandinou, ''A 0.45v continuous time-domain filter using asynchronous oscillator structures,'' in IEEE Proceedings of the International Conference on Electronics, Circuits and Systems, December 2016.
[^92]: R.Mohan, L.Yan, G.Gielen, C.V. Hoof, and R.F. Yazicioglu, ''0.35 v time-domain-based instrumentation amplifier,'' Electronics Letters, vol.50, no.21, pp. 1513--1514, October 2014. [Online]: http://dx.doi.org/10.1049/el.2014.2471
[^93]: X.Zhang, Z.Zhang, Y.Li, C.Liu, Y.X. Guo, and Y.Lian, ''A 2.89$ \mu$w dry-electrode enabled clockless wireless ecg soc for wearable applications,'' IEEE Journal of Solid-State Circuits, vol.51, no.10, pp. 2287--2298, Oct 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2582863
[^94]: M.Elia, L.B. Leene, and T.G. Constandinou, ''Continuous-time micropower interface for neural recording applications,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2016, pp. 534--537. [Online]: http://dx.doi.org/10.1109/ISCAS.2016.7527295
[^95]: N.Guo, Y.Huang, T.Mai, S.Patil, C.Cao, M.Seok, S.Sethumadhavan, and Y.Tsividis, ''Energy-efficient hybrid analog/digital approximate computation in continuous time,'' IEEE Journal of Solid-State Circuits, vol.51, no.7, pp. 1514--1524, July 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2543729
[^96]: B.Bozorgzadeh, D.R. Schuweiler, M.J. Bobak, P.A. Garris, and P.Mohseni, ''Neurochemostat: A neural interface soc with integrated chemometrics for closed-loop regulation of brain dopamine,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.3, pp. 654--667, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2453791
[^97]: E.B. Myers and M.L. Roukes, ''Comparative advantages of mechanical biosensors,'' Nature nanotechnology, vol.6, no.4, pp. 1748--3387, April 2011. [Online]: http://dx.doi.org/10.1038/nnano.2011.44
[^98]: R.Machado, N.Soltani, S.Dufour, M.T. Salam, P.L. Carlen, R.Genov, and M.Thompson, ''Biofouling-resistant impedimetric sensor for array high-resolution extracellular potassium monitoring in the brain,'' Biosensors, vol.6, no.4, p.53, October 2016. [Online]: http://dx.doi.org/10.3390/bios6040053
[^99]: J.Guo, W.Ng, J.Yuan, S.Li, and M.Chan, ''A 200-channel area-power-efficient chemical and electrical dual-mode acquisition ic for the study of neurodegenerative diseases,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.3, pp. 567--578, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2468052
[^100]: D.A. Dombeck, A.N. Khabbaz, F.Collman, T.L. Adelman, and D.W. Tank, ''Imaging large-scale neural activity with cellular resolution in awake, mobile mice.'' Neuron, vol.56, no.1, pp. 43--57, October 2007. [Online]: http://dx.doi.org/10.1016/j.neuron.2007.08.003
[^101]: T.York, S.B. Powell, S.Gao, L.Kahan, T.Charanya, D.Saha, N.W. Roberts, T.W. Cronin, J.Marshall, S.Achilefu, S.P. Lake, B.Raman, and V.Gruev, ''Bioinspired polarization imaging sensors: From circuits and optics to signal processing algorithms and biomedical applications,'' Proceedings of the IEEE, vol. 102, no.10, pp. 1450--1469, Oct 2014. [Online]: http://dx.doi.org/10.1109/JPROC.2014.2342537
[^102]: K.Paralikar, P.Cong, O.Yizhar, L.E. Fenno, W.Santa, C.Nielsen, D.Dinsmoor, B.Hocken, G.O. Munns, J.Giftakis, K.Deisseroth, and T.Denison, ''An implantable optical stimulation delivery system for actuating an excitable biosubstrate,'' IEEE Journal of Solid-State Circuits, vol.46, no.1, pp. 321--332, Jan 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2010.2074110
[^103]: N.Ji and S.L. Smith, ''Technologies for imaging neural activity in large volumes,'' Nature Neuroscience, vol.19, pp. 1154--1164, September 2016. [Online]: http://dx.doi.org/10.1038/nn.4358
[^104]: S.Song, K.D. Miller, and L.F. Abbott, ''Competitive hebbian learning through spike-timing-dependent synaptic plasticity,'' Nature Neuroscience, vol.3, pp. 919--926, September 2000. [Online]: http://dx.doi.org/10.1038/78829
[^105]: T.Kurafuji, M.Haraguchi, M.Nakajima, T.Nishijima, T.Tanizaki, H.Yamasaki, T.Sugimura, Y.Imai, M.Ishizaki, T.Kumaki, K.Murata, K.Yoshida, E.Shimomura, H.Noda, Y.Okuno, S.Kamijo, T.Koide, H.J. Mattausch, and K.Arimoto, ''A scalable massively parallel processor for real-time image processing,'' IEEE Journal of Solid-State Circuits, vol.46, no.10, pp. 2363--2373, October 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2159528
[^106]: J.Y. Kim, M.Kim, S.Lee, J.Oh, K.Kim, and H.J. Yoo, ''A 201.4 gops 496 mw real-time multi-object recognition processor with bio-inspired neural perception engine,'' IEEE Journal of Solid-State Circuits, vol.45, no.1, pp. 32--45, Jan 2010. [Online]: http://dx.doi.org/10.1109/JSSC.2009.2031768
[^107]: C.C. Cheng, C.H. Lin, C.T. Li, and L.G. Chen, ''ivisual: An intelligent visual sensor soc with 2790 fps cmos image sensor and 205 gops/w vision processor,'' IEEE Journal of Solid-State Circuits, vol.44, no.1, pp. 127--135, Jan 2009. [Online]: http://dx.doi.org/10.1109/JSSC.2008.2007158
[^108]: H.Noda, M.Nakajima, K.Dosaka, K.Nakata, M.Higashida, O.Yamamoto, K.Mizumoto, T.Tanizaki, T.Gyohten, Y.Okuno, H.Kondo, Y.Shimazu, K.Arimoto, K.Saito, and T.Shimizu, ''The design and implementation of the massively parallel processor based on the matrix architecture,'' IEEE Journal of Solid-State Circuits, vol.42, no.1, pp. 183--192, Jan 2007. [Online]: http://dx.doi.org/10.1109/JSSC.2006.886545
[^109]: M.S. Chae, W.Liu, and M.Sivaprakasam, ''Design optimization for integrated neural recording systems,'' IEEE Journal of Solid-State Circuits, vol.43, no.9, pp. 1931--1939, September 2008. [Online]: http://dx.doi.org/10.1109/JSSC.2008.2001877
[^110]: K.J. Miller, L.B. Sorensen, J.G. Ojemann, and M.den Nijs, ''Power-law scaling in the brain surface electric potential,'' PLoS Comput Biol, vol.5, no.12, pp. 1--10, 12 2009. [Online]: http://dx.doi.org/10.1371%2Fjournal.pcbi.1000609
[^111]: R.Harrison and C.Charles, ''A low-power low-noise cmos amplifier for neural recording applications,'' IEEE Journal of Solid-State Circuits, vol.38, no.6, pp. 958--965, June 2003. [Online]: http://dx.doi.org/10.1109/JSSC.2003.811979
[^112]: W.Sansen, ''1.3 analog cmos from 5 micrometer to 5 nanometer,'' in IEEE Proceedings of the International Solid-State Circuits Conference.\hskip 1em plus 0.5em minus 0.4em elax IEEE, February 2015, pp. 1--6. [Online]: http://dx.doi.org/10.1109/ISSCC.2015.7062848
[^113]: M.S.J. Steyaert and W.M.C. Sansen, ''A micropower low-noise monolithic instrumentation amplifier for medical purposes,'' IEEE Journal of Solid-State Circuits, vol.22, no.6, pp. 1163--1168, December 1987. [Online]: http://dx.doi.org/10.1109/JSSC.1987.1052869
[^114]: W.Wattanapanitch, M.Fee, and R.Sarpeshkar, ''An energy-efficient micropower neural recording amplifier,'' IEEE Transactions on Biomedical Circuits and Systems, vol.1, no.2, pp. 136--147, June 2007. [Online]: http://dx.doi.org/10.1109/TBCAS.2007.907868
[^115]: B.Johnson and A.Molnar, ''An orthogonal current-reuse amplifier for multi-channel sensing,'' IEEE Journal of Solid-State Circuits, vol.48, no.6, pp. 1487--1496, June 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2257478
[^116]: C.Qian, J.Parramon, and E.Sanchez-Sinencio, ''A micropower low-noise neural recording front-end circuit for epileptic seizure detection,'' IEEE Journal of Solid-State Circuits, vol.46, no.6, pp. 1392--1405, June 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2126370
[^117]: X.Zou, L.Liu, J.H. Cheong, L.Yao, P.Li, M.-Y. Cheng, W.L. Goh, R.Rajkumar, G.Dawe, K.-W. Cheng, and M.Je, ''A 100-channel 1-mw implantable neural recording ic,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.60, no.10, pp. 2584--2596, October 2013. [Online]: http://dx.doi.org/10.1109/TCSI.2013.2249175
[^118]: V.Majidzadeh, A.Schmid, and Y.Leblebici, ''Energy efficient low-noise neural recording amplifier with enhanced noise efficiency factor,'' IEEE Transactions on Biomedical Circuits and Systems, vol.5, no.3, pp. 262--271, June 2011. [Online]: http://dx.doi.org/10.1109/TBCAS.2010.2078815
[^119]: ibitemQ-basedC.C. Enz and E.A. Vittoz, Charge-based MOS transistor modeling: the EKV model for low-power AND RF IC design.\hskip 1em plus 0.5em minus 0.4em elax John Wiley & Sons, August 2006. [Online]: http://eu.wiley.com/WileyCDA/WileyTitle/productCd-0470855452.html
[^120]: Y.Yasuda, T.-J.K. Liu, and C.Hu, ''Flicker-noise impact on scaling of mixed-signal cmos with hfsion,'' IEEE Transactions on Electron Devices, vol.55, no.1, pp. 417--422, January 2008. [Online]: http://dx.doi.org/10.1109/TED.2007.910759
[^121]: S.-Y. Wu, C.Lin, M.Chiang, J.Liaw, J.Cheng, S.Yang, M.Liang, T.Miyashita, C.Tsai, B.Hsu, H.Chen, T.Yamamoto, S.Chang, V.Chang, C.Chang, J.Chen, H.Chen, K.Ting, Y.Wu, K.Pan, R.Tsui, C.Yao, P.Chang, H.Lien, T.Lee, H.Lee, W.Chang, T.Chang, R.Chen, M.Yeh, C.Chen, Y.Chiu, Y.Chen, H.Huang, Y.Lu, C.Chang, M.Tsai, C.Liu, K.Chen, C.Kuo, H.Lin, S.Jang, and Y.Ku, ''A 16nm finfet cmos technology for mobile soc and computing applications,'' in IEEE Proceedings of the International Electron Devices Meeting, December 2013, pp. 9.1.1--9.1.4. [Online]: http://dx.doi.org/10.1109/IEDM.2013.6724591
[^122]: L.B. Leene, Y.Liu, and T.G. Constandinou, ''A compact recording array for neural interfaces,'' in IEEE Proceedings of the Biomedical Circuits and Systems Conference, October 2013, pp. 97--100. [Online]: http://dx.doi.org/10.1109/BioCAS.2013.6679648
[^123]: Q.Fan, F.Sebastiano, J.Huijsing, and K.Makinwa, ''A $1.8 \mu w\:60 nv/√Hz$ capacitively-coupled chopper instrumentation amplifier in 65 nm cmos for wireless sensor nodes,'' IEEE Journal of Solid-State Circuits, vol.46, no.7, pp. 1534--1543, July 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2143610
[^124]: H.Chandrakumar and D.Markovic, ''A simple area-efficient ripple-rejection technique for chopped biosignal amplifiers,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.62, no.2, pp. 189--193, February 2015. [Online]: http://dx.doi.org/10.1109/TCSII.2014.2387686
[^125]: H.Chandrakumar and D.Markovic, ''A 2$\mu$w 40mvpp linear-input-range chopper-stabilized bio-signal amplifier with boosted input impedance of 300mohm and electrode-offset filtering,'' in IEEE Proceedings of the International Solid-State Circuits Conference.\hskip 1em plus 0.5em minus 0.4em elax IEEE, January 2016, pp. 96--97. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7417924
[^126]: H.Rezaee-Dehsorkh, N.Ravanshad, R.Lotfi, K.Mafinezhad, and A.M. Sodagar, ''Analysis and design of tunable amplifiers for implantable neural recording applications,'' IEEE Transactions on Emerging and Selected Topics in Circuits and Systems, vol.1, no.4, pp. 546--556, December 2011. [Online]: http://dx.doi.org/10.1109/JETCAS.2011.2174492
[^127]: X.Zou, X.Xu, L.Yao, and Y.Lian, ''A 1-v 450-nw fully integrated programmable biomedical sensor interface chip,'' IEEE Journal of Solid-State Circuits, vol.44, no.4, pp. 1067--1077, April 2009. [Online]: http://dx.doi.org/10.1109/JSSC.2009.2014707
[^128]: L.Leene and T.Constandinou, ''Ultra-low power design strategy for two-stage amplifier topologies,'' Electronics Letters, vol.50, no.8, pp. 583--585, April 2014. [Online]: http://dx.doi.org/10.1049/el.2013.4196
[^129]: H.G. Rey, C.Pedreira, and R.Q. Quiroga, ''Past, present and future of spike sorting techniques,'' Brain Research Bulletin, vol. 119, Part B, pp. 106--117, October 2015, advances in electrophysiological data analysis. [Online]: http://www.sciencedirect.com/science/article/pii/S0361923015000684
[^130]: Y.Chen, A.Basu, L.Liu, X.Zou, R.Rajkumar, G.S. Dawe, and M.Je, ''A digitally assisted, signal folding neural recording amplifier,'' IEEE Transactions on Biomedical Circuits and Systems, vol.8, no.4, pp. 528--542, August 2014. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2288680
[^131]: X.Yue, ''Determining the reliable minimum unit capacitance for the dac capacitor array of sar adcs,'' Microelectronics Journal, vol.44, no.6, pp. 473 -- 478, 2013. [Online]: http://www.sciencedirect.com/science/article/pii/S0026269213000815
[^132]: Y.Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, S.-P. U, R.Martins, and F.Maloberti, ''Split-sar adcs: Improved linearity with power and speed optimization,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.22, no.2, pp. 372--383, February 2014. [Online]: http://dx.doi.org/10.1109/TVLSI.2013.2242501
[^133]: L.Xie, G.Wen, J.Liu, and Y.Wang, ''Energy-efficient hybrid capacitor switching scheme for sar adc,'' Electronics Letters, vol.50, no.1, pp. 22--23, January 2014. [Online]: http://dx.doi.org/10.1049/el.2013.2794
[^134]: P.Nuzzo, F.DeBernardinis, P.Terreni, and G.Vander Plas, ''Noise analysis of regenerative comparators for reconfigurable adc architectures,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.55, no.6, pp. 1441--1454, July 2008. [Online]: http://dx.doi.org/10.1109/TCSI.2008.917991
[^135]: G.Heinzel, A.R\"udiger, and R.Schilling, ''Spectrum and spectral density estimation by the discrete fourier transform (dft), including a comprehensive list of window functions and some new at-top windows,'' pp. 25--27, February 2002. [Online]: http://hdl.handle.net/11858/00-001M-0000-0013-557A-5
[^136]: F.Gerfers, M.Ortmanns, and Y.Manoli, ''A 1.5-v 12-bit power-efficient continuous-time third-order sigma; delta; modulator,'' IEEE Journal of Solid-State Circuits, vol.38, no.8, pp. 1343--1352, Aug 2003. [Online]: http://dx.doi.org/10.1109/JSSC.2003.814432
[^137]: Y.Chae, K.Souri, and K.A.A. Makinwa, ''A 6.3$ \mu$w 20$ $bit incremental zoom-adc with 6 ppm inl and 1 $\mu$v offset,'' IEEE Journal of Solid-State Circuits, vol.48, no.12, pp. 3019--3027, Dec 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2278737
[^138]: Y.S. Shu, L.T. Kuo, and T.Y. Lo, ''An oversampling sar adc with dac mismatch error shaping achieving 105db sfdr and 101db sndr over 1khz bw in 55nm cmos,'' in IEEE Proceedings of the International Solid-State Circuits Conference, January 2016, pp. 458--459. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7418105
[^139]: P.Harpe, E.Cantatore, and A.van Roermund, ''An oversampled 12/14b sar adc with noise reduction and linearity enhancements achieving up to 79.1db sndr,'' in IEEE Proceedings of the International Solid-State Circuits Conference, February 2014, pp. 194--195. [Online]: http://dx.doi.org/10.1109/ISSCC.2014.6757396
[^140]: ibitemchrch-turingM.Braverman, J.Schneider, and C.Rojas, ''Space-bounded church-turing thesis and computational tractability of closed systems,'' Physical Review Letters, vol. 115, August 2015. [Online]: http://link.aps.org/doi/10.1103/PhysRevLett.115.098701
[^141]: M.Verhelst and A.Bahai, ''Where analog meets digital: Analog-to-information conversion and beyond,'' IEEE Solid-State Circuits Magazine, vol.7, no.3, pp. 67--80, September 2015. [Online]: http://dx.doi.org/10.1109/MSSC.2015.2442394
[^142]: H.A. Marblestone, M.B. Zamft, G.Y. Maguire, G.M. Shapiro, R.T. Cybulski, I.J. Glaser, D.Amodei, P.B. Stranges, R.Kalhor, A.D. Dalrymple, D.Seo, E.Alon, M.M. Maharbiz, M.J. Carmena, M.J. Rabaey, S.E. Boyden, M.G. Church, and P.K. Kording, ''Physical principles for scalable neural recording,'' Frontiers in Computational Neuroscience, vol.7, no. 137, 2013. [Online]: http://www.frontiersin.org/computational_neuroscience/10.3389/fncom.2013.00137
[^143]: L.Traver, C.Tarin, P.Marti, and N.Cardona, ''Adaptive-threshold neural spike by noise-envelope tracking,'' Electronics Letters, vol.43, no.24, pp. 1333--1335, November 2007. [Online]: http://dx.doi.org/10.1049/el:20071631
[^144]: I.Obeid and P.Wolf, ''Evaluation of spike-detection algorithms fora brain-machine interface application,'' IEEE Transactions on Biomedical Engineering, vol.51, no.6, pp. 905--911, June 2004. [Online]: http://dx.doi.org/10.1109/TBME.2004.826683
[^145]: P.Watkins, G.Santhanam, K.Shenoy, and R.Harrison, ''Validation of adaptive threshold spike detector for neural recording,'' in IEEE Proceedings of the International Conference on Engineering in Medicine and Biology Society, vol.2, September 2004, pp. 4079--4082. [Online]: http://dx.doi.org/10.1109/IEMBS.2004.1404138
[^146]: T.Takekawa, Y.Isomura, and T.Fukai, ''Accurate spike sorting for multi-unit recordings,'' European Journal of Neuroscience, vol.31, no.2, pp. 263--272, 2010. [Online]: http://dx.doi.org/10.1111/j.1460-9568.2009.07068.x
[^147]: A.Zviagintsev, Y.Perelman, and R.Ginosar, ''Low-power architectures for spike sorting,'' in IEEE Proceedings of the International Conference on Neural Engineering, March 2005, pp. 162--165. [Online]: http://dx.doi.org/10.1109/CNE.2005.1419579
[^148]: A.Rodriguez-Perez, J.Ruiz-Amaya, M.Delgado-Restituto, and A.Rodriguez-Vazquez, ''A low-power programmable neural spike detection channel with embedded calibration and data compression,'' IEEE Transactions on Biomedical Circuits and Systems, vol.6, no.2, pp. 87--100, April 2012. [Online]: http://dx.doi.org/10.1109/TBCAS.2012.2187352
[^149]: U.Rutishauser, E.M. Schuman, and A.N. Mamelak, ''Online detection and sorting of extracellularly recorded action potentials in human medial temporal lobe recordings, in vivo,'' Journal of Neuroscience Methods, vol. 154, no. 1–2, pp. 204 -- 224, 2006. [Online]: http://www.sciencedirect.com/science/article/pii/S0165027006000033
[^150]: F.Franke, M.Natora, C.Boucsein, M.Munk, and K.Obermayer, ''\BIBforeignlanguageEnglishAn online spike detection and spike classification algorithm capable of instantaneous resolution of overlapping spikes,'' \BIBforeignlanguageEnglishJournal of Computational Neuroscience, vol.29, no. 1-2, pp. 127--148, 2010. [Online]: http://dx.doi.org/10.1007/s10827-009-0163-5
[^151]: M.S. Chae, Z.Yang, M.Yuce, L.Hoang, and W.Liu, ''A 128-channel 6 mw wireless neural recording ic with spike feature extraction and uwb transmitter,'' IEEE Transactions on Neural Systems and Rehabilitation Engineering, vol.17, no.4, pp. 312--321, August 2009. [Online]: http://dx.doi.org/10.1109/TNSRE.2009.2021607
[^152]: P.H. Thakur, H.Lu, S.S. Hsiao, and K.O. Johnson, ''Automated optimal detection and classification of neural action potentials in extra-cellular recordings,'' Journal of Neuroscience Methods, vol. 162, no. 1–2, pp. 364 -- 376, 2007. [Online]: ttp://www.sciencedirect.com/science/article/pii/S0165027007000477
[^153]: J.Zhang, Y.Suo, S.Mitra, S.Chin, S.Hsiao, R.Yazicioglu, T.Tran, and R.Etienne-Cummings, ''An efficient and compact compressed sensing microsystem for implantable neural recordings,'' IEEE Transactions on Biomedical Circuits and Systems, vol.8, no.4, pp. 485--496, August 2014. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2284254
[^154]: Y.Suo, J.Zhang, T.Xiong, P.S. Chin, R.Etienne-Cummings, and T.D. Tran, ''Energy-efficient multi-mode compressed sensing system for implantable neural recordings,'' IEEE Transactions on Biomedical Circuits and Systems, vol.8, no.5, pp. 648--659, October 2014. [Online]: http://dx.doi.org/10.1109/TBCAS.2014.2359180
[^155]: B.Yu, T.Mak, X.Li, F.Xia, A.Yakovlev, Y.Sun, and C.S. Poon, ''Real-time fpga-based multichannel spike sorting using hebbian eigenfilters,'' IEEE Transactions on Emerging and Selected Topics in Circuits and Systems, vol.1, no.4, pp. 502--515, December 2011. [Online]: http://dx.doi.org/10.1109/JETCAS.2012.2183430
[^156]: V.Ventura, ''Automatic spike sorting using tuning information,'' Neural computation, vol.21, no.9, pp. 2466--2501, September 2009. [Online]: http://www.ncbi.nlm.nih.gov/pmc/articles/PMC4167425/
[^157]: D.Y. Barsakcioglu, A.Eftekhar, and T.G. Constandinou, ''Design optimisation of front-end neural interfaces for spike sorting systems,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2013, pp. 2501--2504. [Online]: http://dx.doi.org/10.1109/ISCAS.2013.6572387
[^158]: A.M. Sodagar, K.D. Wise, and K.Najafi, ''A fully integrated mixed-signal neural processor for implantable multichannel cortical recording,'' IEEE Transactions on Biomedical Engineering, vol.54, no.6, pp. 1075--1088, June 2007. [Online]: http://dx.doi.org/10.1109/TBME.2007.894986
[^159]: Y.Xin, W.X. Li, R.C. Cheung, R.H. Chan, H.Yan, D.Song, and T.W. Berger, ''An fpga based scalable architecture of a stochastic state point process filter (ssppf) to track the nonlinear dynamics underlying neural spiking,'' Microelectronics Journal, vol.45, no.6, pp. 690 -- 701, June 2014. [Online]: http://www.sciencedirect.com/science/article/pii/S0026269214000913
[^160]: C.Qian, J.Shi, J.Parramon, and E.Sánchez-Sinencio, ''A low-power configurable neural recording system for epileptic seizure detection,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.4, pp. 499--512, August 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2012.2228857
[^161]: K.C. Chun, P.Jain, J.H. Lee, and C.H. Kim, ''A 3t gain cell embedded dram utilizing preferential boosting for high density and low power on-die caches,'' IEEE Journal of Solid-State Circuits, vol.46, no.6, pp. 1495--1505, June 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2128150
[^162]: R.E. Matick and S.E. Schuster, ''Logic-based edram: Origins and rationale for use,'' IBM Journal of Research AND Development, vol.49, no.1, pp. 145--165, January 2005. [Online]: http://dx.doi.org/10.1147/rd.491.0145
[^163]: R.Nair, ''Evolution of memory architecture,'' Proceedings of the IEEE, vol. 103, no.8, pp. 1331--1345, August 2015. [Online]: http://dx.doi.org/10.1109/JPROC.2015.2435018
[^164]: C.E. Molnar and I.W. Jones, ''Simple circuits that work for complicated reasons,'' in IEEE Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2000, pp. 138--149. [Online]: http://dx.doi.org/10.1109/ASYNC.2000.836995
[^165]: ibitemBN-formH.Schorr, ''Computer-aided digital system design and analysis using a register transfer language,'' IEEE Transactions on Electronic Computers, vol. EC-13, no.6, pp. 730--737, December 1964. [Online]: http://dx.doi.org/10.1109/PGEC.1964.263907
[^166]: D.Wang, A.Rajendiran, S.Ananthanarayanan, H.Patel, M.Tripunitara, and S.Garg, ''Reliable computing with ultra-reduced instruction set coprocessors,'' IEEE Micro, vol.34, no.6, pp. 86--94, November 2014. [Online]: http://dx.doi.org/10.1109/MM.2013.130
[^167]: ''Msp430g2x53 mixed signal microcontroller - data sheet,'' Texas Instruments Incorporated, Dallas, Texas, pp. 403--413, May 2013. [Online]: http://www.ti.com/lit/ds/symlink/msp430g2553.pdf
[^168]: F.L. Yuan, C.C. Wang, T.H. Yu, and D.Marković, ''A multi-granularity fpga with hierarchical interconnects for efficient and flexible mobile computing,'' IEEE Journal of Solid-State Circuits, vol.50, no.1, pp. 137--149, January 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2372034
[^169]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational amplifiers and their application to continuous-time filters in nanoscale cmos,'' IEEE Journal of Solid-State Circuits, vol.49, no.12, pp. 2758--2772, December 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2354641
[^170]: Y.Tsividis, ''Event-driven data acquisition and continuous-time digital signal processing,'' in IEEE Proceedings of the Custom Integrated Circuits Conference, September 2010, pp. 1--8. [Online]: http://dx.doi.org/10.1109/CICC.2010.5617618
[^171]: I.Lee, D.Sylvester, and D.Blaauw, ''A constant energy-per-cycle ring oscillator over a wide frequency range for wireless sensor nodes,'' IEEE Journal of Solid-State Circuits, vol.51, no.3, pp. 697--711, March 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2517133
[^172]: B.Drost, M.Talegaonkar, and P.K. Hanumolu, ''Analog filter design using ring oscillator integrators,'' IEEE Journal of Solid-State Circuits, vol.47, no.12, pp. 3120--3129, December 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2225738
[^173]: V.Unnikrishnan and M.Vesterbacka, ''Time-mode analog-to-digital conversion using standard cells,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.61, no.12, pp. 3348--3357, December 2014. [Online]: http://dx.doi.org/10.1109/TCSI.2014.2340551
[^174]: K.Yang, D.Blaauw, and D.Sylvester, ''An all-digital edge racing true random number generator robust against pvt variations,'' IEEE Journal of Solid-State Circuits, vol.51, no.4, pp. 1022--1031, April 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2519383
[^175]: ibitem0.5V-CircuitS.Chatterjee, Y.Tsividis, and P.Kinget, ''0.5-v analog circuit techniques and their application in ota and filter design,'' IEEE Journal of Solid-State Circuits, vol.40, no.12, pp. 2373--2387, December 2005. [Online]: http://dx.doi.org/10.1109/JSSC.2005.856280
[^176]: M.Alioto, ''Understanding dc behavior of subthreshold cmos logic through closed-form analysis,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.57, no.7, pp. 1597--1607, July 2010. [Online]: http://dx.doi.org/10.1109/TCSI.2009.2034233
[^177]: A.Hajimiri and T.Lee, ''A general theory of phase noise in electrical oscillators,'' IEEE Journal of Solid-State Circuits, vol.33, no.2, pp. 179--194, February 1998. [Online]: http://dx.doi.org/10.1109/4.658619
[^178]: A.Demir, A.Mehrotra, and J.Roychowdhury, ''Phase noise in oscillators: a unifying theory and numerical methods for characterization,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.47, no.5, pp. 655--674, May 2000. [Online]: http://dx.doi.org/10.1109/81.847872
[^179]: A.Hajimiri, S.Limotyrakis, and T.Lee, ''Phase noise in multi-gigahertz cmos ring oscillators,'' in IEEE Proceedings of the Custom Integrated Circuits Conference, May 1998, pp. 49--52. [Online]: http://dx.doi.org/10.1109/CICC.1998.694905
[^180]: W.Jiang, V.Hokhikyan, H.Chandrakumar, V.Karkare, and D.Markovic, ''A ±50mv linear-input-range vco-based neural-recording front-end with digital nonlinearity correction,'' in IEEE Proceedings of the International Solid-State Circuits Conference, January 2016, pp. 484--485. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7418118
[^181]: C.Weltin-Wu and Y.Tsividis, ''An event-driven clockless level-crossing adc with signal-dependent adaptive resolution,'' IEEE Journal of Solid-State Circuits, vol.48, no.9, pp. 2180--2190, September 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2262738
[^182]: H.Y. Yang and R.Sarpeshkar, ''A bio-inspired ultra-energy-efficient analog-to-digital converter for biomedical applications,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.53, no.11, pp. 2349--2356, November 2006. [Online]: http://dx.doi.org/10.1109/TCSI.2006.884463
[^183]: F.Corradi and G.Indiveri, ''A neuromorphic event-based neural recording system for smart brain-machine-interfaces,'' IEEE Transactions on Biomedical Circuits and Systems, vol.9, no.5, pp. 699--709, October 2015. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2479256
[^184]: K.A. Ng and Y.P. Xu, ''A compact, low input capacitance neural recording amplifier,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.5, pp. 610--620, October 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2280066
[^185]: J.Agustin and M.Lopez-Vallejo, ''An in-depth analysis of ring oscillators: Exploiting their configurable duty-cycle,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.62, no.10, pp. 2485--2494, October 2015. [Online]: http://dx.doi.org/10.1109/TCSI.2015.2476300
[^186]: K.Ng and Y.P. Xu, ''A compact, low input capacitance neural recording amplifier,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.5, pp. 610--620, October 2013. [Online]: http://dx.doi.org/10.1109/TBCAS.2013.2280066
[^187]: M.Elia, L.B. Leene, and T.G. Constandinou, ''Continuous-time micropower interface for neural recording applications,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2016.
[^188]: Y.W. Li, K.L. Shepard, and Y.P. Tsividis, ''A continuous-time programmable digital fir filter,'' IEEE Journal of Solid-State Circuits, vol.41, no.11, pp. 2512--2520, November 2006. [Online]: http://dx.doi.org/10.1109/JSSC.2006.883314
[^189]: B.Schell and Y.Tsividis, ''A continuous-time adc/dsp/dac system with no clock and with activity-dependent power dissipation,'' IEEE Journal of Solid-State Circuits, vol.43, no.11, pp. 2472--2481, November 2008. [Online]: http://dx.doi.org/10.1109/JSSC.2008.2005456
[^190]: S.Aouini, K.Chuai, and G.W. Roberts, ''Anti-imaging time-mode filter design using a pll structure with transfer function dft,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.59, no.1, pp. 66--79, January 2012. [Online]: http://dx.doi.org/10.1109/TCSI.2011.2161411
[^191]: X.Xing and G.G.E. Gielen, ''A 42 fj/step-fom two-step vco-based delta-sigma adc in 40 nm cmos,'' IEEE Journal of Solid-State Circuits, vol.50, no.3, pp. 714--723, March 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2393814
[^192]: K.Reddy, S.Rao, R.Inti, B.Young, A.Elshazly, M.Talegaonkar, and P.K. Hanumolu, ''A 16-mw 78-db sndr 10-mhz bw ct $\delta \sigma$ adc using residue-cancelling vco-based quantizer,'' IEEE Journal of Solid-State Circuits, vol.47, no.12, pp. 2916--2927, December 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2218062
[^193]: J.Daniels, W.Dehaene, M.S.J. Steyaert, and A.Wiesbauer, ''A/d conversion using asynchronous delta-sigma modulation and time-to-digital conversion,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.57, no.9, pp. 2404--2412, September 2010. [Online]: http://dx.doi.org/10.1109/TCSI.2010.2043169
[^194]: F.M. Yaul and A.P. Chandrakasan, ''A sub-$\mu$w 36nv/$√Hz$ chopper amplifier for sensors using a noise-efficient inverter-based 0.2v-supply input stage,'' in IEEE Proceedings of the International Solid-State Circuits Conference, January 2016, pp. 94--95. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7417923
[^195]: S.Patil, A.Ratiu, D.Morche, and Y.Tsividis, ''A 3-10 fj/conv-step error-shaping alias-free continuous-time adc,'' IEEE Journal of Solid-State Circuits, vol.51, no.4, pp. 908--918, April 2016. [Online]: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7433385&isnumber=7446371
[^196]: J.M. Duarte-Carvajalino and G.Sapiro, ''Learning to sense sparse signals: Simultaneous sensing matrix and sparsifying dictionary optimization,'' IEEE Transactions on Image Processing, vol.18, no.7, pp. 1395--1408, July 2009. [Online]: http://dx.doi.org/10.1109/TIP.2009.2022459
[^197]: R.S. Schneider and H.C. Card, ''Analog hardware implementation issues in deterministic boltzmann machines,'' IEEE Transactions on Circuits and Systems---Part II: Analog and Digital Signal Processing, vol.45, no.3, pp. 352--360, Mar 1998. [Online]: http://dx.doi.org/10.1109/82.664241
[^198]: J.Lu, S.Young, I.Arel, and J.Holleman, ''A 1 tops/w analog deep machine-learning engine with floating-gate storage in 0.13$\mu$m cmos,'' IEEE Journal of Solid-State Circuits, vol.50, no.1, pp. 270--281, January 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2356197
[^199]: M.T. Wolf and J.W. Burdick, ''A bayesian clustering method for tracking neural signals over successive intervals,'' IEEE Transactions on Biomedical Engineering, vol.56, no.11, pp. 2649--2659, November 2009. [Online]: http://dx.doi.org/10.1109/TBME.2009.2027604
[^200]: D.Y. Barsakcioglu and T.G. Constandinou, ''A 32-channel mcu-based feature extraction and classification for scalable on-node spike sorting,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2016.
[^201]: R.P. Feynman, ''There's plenty of room at the bottom,'' American Physical Society, vol.23, no.5, pp. 22--36, February 1960. [Online]: http://www.zyvex.com/nanotech/feynman.html
[^202]: G.Leuba and L.J. Garey, ''Comparison of neuronal and glial numerical density in primary and secondary visual cortex of man,'' Experimental Brain Research, vol.77, no.1, pp. 31--38, 1989. [Online]: http://dx.doi.org/10.1007/BF00250564
[^203]: I.Guideline, ''Guidelines for limiting exposure to time-varying electric, magnetic, and electromagnetic fields (up to 300 ghz),'' Health Physics, vol.74, no.4, pp. 494--522, October 1998. [Online]: http://www.icnirp.org/cms/upload/publications/ICNIRPemfgdl.pdf
[^204]: L.B. Leene, S.Luan, and T.G. Constandinou, ''A 890fj/bit uwb transmitter for soc integration in high bit-rate transcutaneous bio-implants,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2013, pp. 2271--2274. [Online]: http://dx.doi.org/10.1109/ISCAS.2013.6572330
[^205]: ''Unconventional processing of signals for intelligent data exploitation (upside),'' Defense Advanced Research Projects Agency, Arlington, Texas, January 2016. [Online]: http://www.darpa.mil/program/unconventional-processing-of-signals-for-intelligent-data-exploitation

259
content/publications/2017/a-0-016-tsqrd-12-b-rds-sar-with-14-fj-conv-for-ultra-low-power-biosensor-arrays.md Normal file
View File

@ -0,0 +1,259 @@
---
title: "A 0.016 mm² 12 b ΔΣSAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays"
date: 2017-06-15T15:26:46+01:00
draft: false
toc: true
math: true
type: posts
tags:
- publication
- instrumentation
- CMOS
- biomedical
- data-converter
---
Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
The instrumentation systems for implantable brain machine interfaces represent one of the most demanding applications for ultra low power analogue-to-digital-converters (ADC) to date. To address this challenge this paper proposes a \\(\Delta\Sigma\\)SAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0-2 MASH topology. This configuration uses a specialized FIR window to decimate the \\(\Delta\Sigma\\) modulator output and reject mismatch errors from the SAR quantizer which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision.} A fully differential prototype was fabricated using \cmostech to demonstrate 10.8 ENOB precision with a 0.016 mm² silicon footprint. Moreover a 14 fJ/conv figure-of-merit (FOM) can be achieved while resolving signals with the maximum input amplitude of \\(\pm\\)1.2 Vpp sampled at 200 kS/s.} The ADC topology exhibits a number of promising characteristics for both high speed and ultra low power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio which are critical parameters for many sensor applications.
# 2 Introduction
The emergent market for wearable electronics and implantable devices for personalized health care has resulted in a growing demand for miniaturized battery powered systems that wirelessly connect a network of sensors[^1]. These systems rely extensively on high precision analogue to digital conversion to leverage digital processing techniques and accommodate stringent diagnostic requirements[^2]. As a result the ADC power, area, and precision can have a profound impact on a system's overall capabilities. For this reason oversampling techniques using \\(\Delta\Sigma\\) ADCs have already been used extensively to accommodate the niche characteristics of biomedical devices and acquire low frequency bio-signals [^3].}
More recent developments allow these techniques to be more applicable to large sensor arrays using an incremental analogue to digital converter (IADC) topology [^4]. This is in contrast to the conventional use where a single oversampling ADC continuously converts the signal from a single sensing unit with exceptional efficiency. IADC designs are unique in the sense that they periodically reset the loop filter which enables a single ADC to process multiple analogue inputs with reduced latency. This periodic reset associates a particular conversion time for each result and enables pipelined [^4], two-step [^5], or multi-step operation [^6]}. The resulting modulator can exhibit reduced mismatch sensitivity and require a smaller oversampling ratio while achieving equivalent performance to that of higher order modulators[^7]. This is crucial for larger sensor arrays because reduced circuit complexity leads to more compact designs and faster signal conversion. These earlier publications realize an IADC structure that explicitly transfers the quantization residue from one quantizer to the next using a sample and hold mechanism which is not necessarily required. For instance the zoom technique used in [^8] reuses the capacitive DAC during conversion thereby reducing complexity and power consumption. The resulting system achieves exceptional precision by combining a SAR with a second order switched capacitor (SC) \\(\Delta\Sigma\\) modulator. A common problem however is that the SAR INL/DNL errors are not shaped by the loop filter and end up limiting the overall precision unless dynamic element matching techniques (DEM) are used. This can lead to exhaustive digital overhead for DEM control and necessitate additional redundancy in the capacitive digital to analogue converter (DAC) to remove the SAR nonlinearity[^9].}
{{< figure src="/images/tcas2017/block_sys.svg" title="Figure 1: Block level implementation of the proposed ADC array structure for sensor arrays using SAR and \\(\Delta\Sigma\\) quantizers where a digital filter is applied to the comparator bit stream to perform decimation and mismatch correction." width="500" >}}
The system proposed by this paper is illustrated in Fig. 1 which uses a SAR and CT-\\(\Delta\Sigma\\) together to convert the signal from four analogue inputs. This configuration is then tiled 16 times in parallel to record from 64 channels simultaneously for neural recording applications. The topology is introduced as a $\Delta \Sigma$SAR because it emerged from introducing higher order CT-\\(\Delta\Sigma\\) type noise shaping to the SAR by processing the residue charge left after the SAR conversion. Using SC techniques with a similar motivation also lead to the noise shaping SAR (NSSAR) topology from [^10] which has been used extensively to achieve very high resolution SARs [^11] and higher order modulators with reduced active filter structures [^12]. In fact the fully-passive NSSAR technique can increase the SAR precision by several bits while immune to PVT variation [^13]. The distinction here is that the NSSAR will shape the quantization noise over multiple samples by introducing 1 to 3 extra cycles per sample where as the $\Delta \Sigma$SAR will allow one-shot conversions but introduce considerably more cycles corresponding to the oversampling ratio of the modulator. The later is characteristic of IADC operation. Additionally the CT approach leads to an inherent reduction in size because the loop filter is not subject to extra sources of sampling noise typical in CS circuits.} The IADC 0-2 multi-stage noise shaping (MASH) quantization scheme used by the \\(\Delta\Sigma\\)SAR can be interpreted as first resolving the sampled input using a conventional SAR and then applying a \\(\Delta\Sigma\\) feedback loop to resolve the remaining quantization residue left on the capacitor array equivalent to the zoom technique. The resulting bit stream from the comparator output consists of both SAR and oversampled quantization results. The advantage this topology presents is that it can be configured without the need for DEM or analogue dithering techniques because SAR INL/DNL errors can instead be cancelled by calibrating the FIR filter that processes this bit stream in the digital domain. This minimises capacitive switching during signal conversion and reduces overall complexity. Moreover by virtue of resolving a small SAR residue, the CT loop filter can maximize its noise efficiency without much concern for distortion or modulator nonlinearity.}
This paper presents an analytic design method for evaluating which condition allows the zoom type IADCs to exhibit high performance and which two-step configuration will lead to the best efficiency or size. Preliminary efforts to realize the system in Fig. 1 are presented in [^14] and the circuits proposed here are improved to achieve better power efficiency as part of a larger reconfigurable neural recording system [^15]. This system uses an array of miniaturised ADCs that distributes the digital processing over many parallel segments leading to lower clock frequencies and better efficiency opposed to demanding a single high frequency ADC and digital core.} To present the design characteristics of the \\(\Delta\Sigma\\)SAR, this paper is organized as follows. Section \ref{sec:design} introduces the principle design relations of this ADC structure with regard to system efficiency and size. This is followed by the proposed mismatch compensation method in Section \ref{sec:cali}. The circuit level implementation is proposed in Section \ref{sec:circ} with design considerations for the loop filter, capacitive DAC and FIR filter. Finally measured results are presented in Section \ref{sec:mes} which are used to draw conclusions in Section \ref{sec:con}.
# 3 \\(\Delta\Sigma\\)SAR Architecture
The \\(\Delta\Sigma\\)SAR topology closely resembles the SAR with an additional loop filter that can switch between amplifying \\(A(s)\\) and integrating \\(H(s)\\) behaviour following the last SAR conversion. This similarity is shown in Fig. 2 which represents a single ended equivalent of the fully differential implementation described here. The input signal is sampled on the bottom plate of the capacitive array such that conventional SAR feedback can be applied while the loop filter is initially providing wideband amplification of 10x. Once the first \\(N\\) bits are resolved the comparator output is connected directly to a unit element in the capacitive array for the \\(\Delta\Sigma\\) quantization phase. Simultaneously the loop filter is switched to introduce second order noise shaping and resolves another \\(M\\) bits using DC extra oversampling cycles. In theory this will result in \\(M+N\\) bits of precision but in practice the SAR conversion will need to evaluate \\(N+1\\) bits with 1 bit of redundancy. This redundancy implies that the residue will always be half of the modulator input range to prevent overloading the \\(\Delta\Sigma\\) ADC[^16]. If 1 cycle is used for sampling the ADC will need to be clocked at \\((N+DC+2)f_{smp}\\) for a sampling frequency \\(f_{smp}\\) with a modulator bandwidth \\(f_{bw}\\) at half this clock frequency. A typical conversion is illustrated by the timing diagram in Fig. 3 which shows the FSM using 1 cycle for sampling, \\(N+1\\) cycles for SAR, and DC cycles for \\(\Delta\Sigma\\) modulation. Meanwhile the comparator results will infer if the corresponding FIR coefficient provided by a shared controller is added or subtracted from a local accumulator thereby resolving the input signal. To provide insight to the design considerations we will first discuss the noise requirements needed for achieving a \\(N+M\\) ADC precision. This will reveal the dominant power requirements due to the filter and capacitive DAC and also give some indication about the size of each capacitor in Fig. 2 which can then be used to estimate area. Note however that the defining characteristic of this quantization process is that the SAR residue is bound to a well defined voltage range of $\pm V_{R}/2^{N+1}$ where \\(V_{R}\\) is the ADC reference voltage. The reduced input range implies that feedback may not be needed to linearise the Gm-C loop filter used during \\(\Delta\Sigma\\) conversion but it also indicates the filter coefficients have to be carefully adjusted to achieve second order noise shaping. }
{{< figure src="/images/tcas2017/sch_adc.svg" title="Figure 2: Proposed topology that interoperates SAR and oversampling quantizers in the same signal loop using a capacitive DAC, switched loop filter, and single bit quantizer." width="500" >}}
{{< figure src="/images/tcas2017/fsm.svg" title="Figure 3: Timing diagram of the sampling (SMP), SAR (S0-SN), and oversampling (\\(\Delta\Sigma\\)) modes of operation where \\(C_{0}\\) to \\(C_{N+DC}\\) correspond to the calibrated coefficients of the FIR filter. EOC is the end-of-conversion signal that is put low when the quantization process is finished. " width="500" >}}
## 4 Topology Optimization
The efficient operation of low speed ADCs primarily relies on the careful consideration of various noise sources to avoid dissipating excess power. However the two modes of operation have characteristically different requirements. Concisely stated the \\(\Delta\Sigma\\) modulator will focus on achieving a specific noise floor because out of band noise is removed after decimation while the SAR operation is sensitive to integrated noise over the entire circuit bandwidth. To illustrate the design relations quantitatively the following discussion will reiterate on several expressions from well established \\(\Delta\Sigma\\) theory [^17]. This will allow us to determine system constraints particularly with respect to the analogue filter that provides second order noise shaping and in this case consumes most of the power.}
## 5 Filter Noise Constraints
First recall that the oversampling ratio for a second order modulator is dictated by Eq. 1 in terms of resolving \\(M\\) bits. This will later be used in association with the expression in Eq. 2 to evaluate acceptable quantization noise power \\(S^2_{n}\\) for a \\(N+M\\) precision ADC.}
$$ DC \geq \sqrt[5]{ \frac{2 \pi^4}{15 \cdot 2^{-2(M+1)}}} $$
$$ S^2_{n} =\frac{1}{12} \left( \frac{V_R}{2^{N+M+1}} \right)^2 $$
Now in order to capture the subjective performance of the circuit level implementation and its impact, this analysis uses the Noise Efficiency Factor (NEF). The expression for NEF in Eq. 3 normalizes the input referred noise \\(e^2_{in}\\) of a particular implementation to that of a bipolar transistor with a biasing current equivalent to that used by the filter \\(I_{filt}\\). As a result we can abstractly consider noise-power relations without considering a specific filter topology that will exhibit some particular NEF.}
$$ NEF^2 \deff \frac{2 I_{filt} e^2_{in}}{\pi U_T 4kT f_{bw}} $$
In fact by combining this with the ADC noise requirement in Eq. 2, \\(I_{filt}\\) can be predicted as a function of circuit topology and its equivalent NEF. This is detailed in Eq. 4 under the condition that \\(e^2_{in} = S^2_{n}\\) where the relevant circuit noise bandwidth is reduced \\(f_{bw}/DC\\) due to oversampling.}
$$ I_{filt} = \pi U_T 24kT \frac{ f_{bw} }{ DC } \left( \frac{ 2^{N+M+1} NEF }{V_R} \right)^2 $$
Similarly \\(I_{filt}\\) can be evaluated for just the SAR operation as a special case: $I_{SAR} \deff I_{filt}(DC=1,M=0)$. In the case that \\(I_{SAR}\\) is larger than the estimate in Eq. 4 we should adopt that value instead. This result is mainly relevant for SAR converters where an analogue amplifier is used to precede the comparator and thereby dominating the noise requirements[^18]. Here it will also be used to indicate the preliminary performance with respect to \\(N\\) & \\(M\\) with a fixed clock speed and the associated conversion time of \\(N+DC+2\\) cycles. The resulting conversion efficiency is proportional to \\(2^{N+M}/P_A(N+DC+2)\\) as conversion per Watt where total analogue power is estimated as $P_{A} \approx V_{R}I_{filt}$. In this case the filter supply voltage is simply equal to the reference voltage. Normalization allows the relative efficiency to be visualized in Fig. 4 which provides some evidence that the filter alone tends to be more efficient as \\(M\\) becomes larger than \\(N\\). However \\(N\\) can not be arbitrarily small if the residue need to be kept in the linear range of the modulator. This implies a direct relationship between the ADC reference voltage and the minimum SAR resolution.} The details of this requirement is strongly dependent on the full ADC precision and its sensitivity towards transistor nonlinearity. However as a priori the minimum SAR resolution \\(N\\) can be approximated by considering that the linear input range for a sub-threshold differential input pair is related to the thermal voltage $\pm U_{T}$[^19] which suggests that \\(N \geq\log_2(V_{R}/U_{T})\\) to keep the residue inside the linear range.}
{{< figure src="/images/tcas2017/Cost.svg" title="Figure 4: Power efficiency as \\(2^{N+M}/P_A(N+DC+2)\\) in terms of conversions per Watt where \\(N+M\\) is the target precision of the analogue filter for different values of \\(N\\) & \\(M\\) normalised by the best case where \\(M=8\\) & \\(N=1\\).}" width="500" >}}
## 6 Estimating System Power
The previous result is relatively optimistic in the sense that it does not consider the decimation filter or DAC power dissipation. To warrant an accurate estimation of the ADC's efficiency and resource requirements the Digital \\(P_{D}\\), and capacitive switching \\(P_{C}\\) losses should also be estimated.}
$$ P_C = C_{U} f_{smp} V^2_R \left(DC/2 + \sum_{i=1}^{N} (2^i-1) 2^{N-2i-2} \right) $$
Eq. 5 includes the SAR energy dissipation in terms of the capacitive switching using the analysis from [^20].} The \\(V_{cm}\\) based switching method employed here retains a stable common mode on \\(V_{DAC}\\) with good conversion efficiency. This will help to preserve the linearity of the modulator. Variation in common mode voltage changes the offset of the loop filter as well as the impact of top plate parasitics[^20]. Both will introduce nonlinearity that is convoluted by the SAR quantization process and can be challenging to compensate accurately. \\(P_{C}\\) is evaluated for \\(N+1\\) SAR cycles where the unit capacitor \\(C_{U}\\) size introduces some degree of freedom. Strictly the total capacitance is bounded such that the \\(kT/C\\) noise is smaller than noise requirement of Eq. 2. For instance we could let the sampling noise contribute half the allowable noise power which leads to a minimum capacitance according to Eq. 6 given a \\(2^{N+1}\\) unit binary DAC.
$$ C_U = \frac{12 kT}{V_R^2} 2^{N+2M+1} $$
This unit element should be noticeably larger than what may be expected from SAR configurations due to the small number of elements in the capacitor array resulting in reduced matching and interconnect complexity. Generally such a configuration will favour high density vertical metal-insulator-metal (MIM) capacitors that have large minimum size requirements and can be placed over active circuitry to reduce silicon footprint. In fact by using a split capacitor configuration the size of \\(C_{U}\\) can be even larger with less elements in the array for the same sampling capacitance leading to very efficient utilization of MIM capacitor area[^21]. It may still be the case that \\(C_{U}\\) is smaller than the minimum capacitance \\(C_{min}\\) for intermediate precision of 6-10 bits. In such a case this model will simply adopt \\(C_{min}\\). This will also apply to the load capacitance \\(C_{L1}\\) when it is calculated with respect to the modulator bandwidth as \\(f_{bw}=gm_{1}/C_{L1}\\). However this should carefully consider the reduced input swing of \\(V_{R}/2^{N+1}\\) which means the transconductance for a conventional fully-differential input in sub-threshold operation would be $gm_{1}=V_{R} I_{filt}/(\eta U_{T} 2^{N})$ where \\(\eta\\) is the transistor slope factor.
In order to estimate the digital losses this model extrapolates the energy dissipation per clock cycle extracted from a 1 bit accumulator taken as \\(E_{reg}\\). The associated register depth \\(R_{D}=N+M+log_{2}(DC)\\) bits is derived by considering the accumulated rounding errors from DC additions during FIR decimation}. This leads to Eq. 7 which is expected to be insignificant at higher resolutions because decimation filter has reduced requirements when compared to the full precision of the integrator.
$$ P_D = R_D E_{reg} f_{smp} \underbrace{(DC+N+2)}_{Cycles/Sample} $$
## 7 FOM Dependence
The above relations should provide a good indication for the power requirements even though some system components such as the comparator and auxiliary circuits have been ignored. The Walden \\(FOM_{W}\\) and Schreier \\(FOM_{S}\\) are presented in Eq. 8 & 9. These performance metrics are plotted in Fig. 5 by assuming typical values from the \cmostech process. \\(V_{R}\\) is adjusted to \\(0.6/1.2/2.4 V\\) which keeps the linear input range of the \\(\Delta\Sigma\\) modulator consistent while resolving different SAR resolutions for fair comparison. Other constants are assumed as follows; \\(\eta=1.2\\), \\(NEF=1.4\\), \\(E_{reg}=1\\) fJ, \\(C_{min}=10\\) fF, \\(f_{smp}=10^5\\) Hz, \\(f_{bw}=10^5 (N+DC+2)/2\\) Hz. The general trend presented here is that the topology operates at maximal performance when the most of the power is dissipated by the oversampling loop and the lowest energy per conversion is dissipated when the capacitive switching and modulator power become comparable. It is not surprising that reducing the supply voltage makes it more difficult to achieve a good FOM because the absolute noise performance becomes more difficult to achieve. For reference a conventional $\Delta \Sigma$ modulator [^22] is designed with the same target specifications and using the same analysis method to configure the OPAMP integrators and resistive input network. Such a configuration achieves 167 dB \\(FOM_{S}\\) irrespective of target resolution when we consider just the filter power dissipation. In fact this figure is commonly achieved by state of the art [^8]. This highlights how the \\(\Delta\Sigma\\)SAR configuration can theoretically achieve more than 2X better performance for resolutions above 12 bits even when operating at lower supply voltages.
$$ FOM_W = \frac{P_C + P_D + P_A}{f_{smp} 2^{N+M}} $$
$$ FOM_S = 6.02 (N+M) + 10 \log_{10}\left( \frac{f_{smp}/2}{P_C + P_D + P_A}\right) $$
{{< figure src="/images/tcas2017/AMD.svg" title="Figure 5: Estimation on the expected \\(FOM_{S}\\) and \\(FOM_{W}\\) for a resolution and varying SAR precision. The red star and blue circle indicate the target and measured performance respectively. The blue stars correspond to \\(FOM_{W}\\) achieved by other works." width="500" >}}
{{< figure src="/images/tcas2017/APM.svg" title="Figure 6: Estimated area requirements with respect to ADC resolution for various SAR resolutions. The red star and blue circle indicate the target and measured performance respectively. The blue stars correspond to area achieved by other works." width="500" >}}
{{< figure src="/images/tcas2017/FOMS_EA.svg" title="Figure 7: The estimated DOP with respect to the target ENOB and the \\(\Delta\Sigma\\) modulator resolution. This normalised by the best configuration where \\(M=5.8\\) & \\(ENOB=10.9\\) (i.e. \\(N=5.1\\)). \\(V_{R}\\) is assumed to be 1.2 V and the red star indicates the target performance for this implementation.}" width="500" >}}
$$ EA = \left( 2 C_{L1} + C_{U} 2^{N+2} \right) / C_{dens} $$
The required area for this configuration is estimated by Eq. 10 which uses the MIM capacitor density \\(C_{dens}\\) of 2fF/\mmu m². As shown in Fig. 6 high resolution configurations will tend towards noise limited requirements that are closely related to the integration and sampling capacitors. Lower resolutions are largely dependent on technology and how the SAR DAC is configured to address mismatch. Fig. 7 shows the impact of \\(M\\) on overall ADC efficiency in combination with the area requirement. This is characterised using the density of performance $DOP = FOM_{S}-10 log_{10}(EA)$ which peaks for an ENOB of 11.4 bits with \\(M\\) being 5.8 bits.} The overall quantitative results show exceptional figures of merit with highly compact configurations for 10-16 bit designs from first principles. The design described above only focuses on achieving an optimal noise performance because it dominates the low frequency FOM metrics.} Naturally a number of extra considerations need to be made for achieving the desired ENOB. Finding the requirements for open loop gain, parasitics, nonlinearity, and digital filtering is done by using numerical optimization on simplified models guided by analytic results from prior work [^22][^24]. However we can observe some agreement with this simplified model and the performance achieved in other works.}
# 8 Foreground Calibration for the $\Delta \Sigma$SAR
{{< figure src="/images/tcas2017/cal_tran.svg" title="Figure 8: Simplified model of the ADC structure quantization process illustrating how capacitor weight estimation \\(W_{SAR}\\) and actual capacitor weights \\(W_{DAC}\\) propagate to the output.}" width="500" >}}
The foregoing analysis suggests that the resources dedicated to SAR operation should be kept small in order to achieve the peak performance of the oversampling modulator. As a result the DAC linearity may be much worse than the target precision. Ideally before instrumentation the system should perform a calibration procedure that determines the actual capacitor weights \\(\mathbf{W}_{DAC}\\) and recovers any lost accuracy due to mismatch in the digital domain[^26][^25]. Digital calibration techniques are extensively used for SAR converters because they enable more aggressive capacitor sizing without introducing extra analogue complexity that does not benefit from technology scaling[^27]. A simplified model of the quantization process is shown in Fig. 8 where the SAR result is fed back according to the 7 capacitor weights \\(\mathbf{W}_{DAC}\\) to produce a residue that is oversampled by the modulator and decimated by the FIR filter. The mismatch errors arise when the coefficients \\(\mathbf{W}_{SAR}\\) do not correctly calculate the exact charge offset by the capacitors (i.e. $\mathbf{W}_{DAC} \neq \mathbf{W}_{SAR}$). The structural advantage here is that all mismatch induced errors are accurately evaluated by the oversampling loop which can operate with extra noise shaping during calibration without needing a more precise reference ADC. First note that the DNL errors due to DAC mismatch are only observed upon changes in the SAR codes. Secondly the single bit \\(\Delta\Sigma\\) modulator can present significantly better linearity without calibration if SAR codes remain unchanged. Moreover if the weights are correctly estimated we should expect no discontinuities in the DNL characteristic for slowly varying inputs. The proposed calibration method takes advantage of these observations by correlating the first order difference of the ADC output and the SAR codes to find the correct coefficients for \\(\mathbf{W}_{SAR}\\). In addition by using a triangular test signal to perform calibration this procedure does not need full precision multipliers. This is because the triangular waveform distributes the occurrences of each SAR code evenly when at least one sample is taken per SAR code. Therefore the number of toggles on each SAR bit is exactly distributed as powers of two. Now if each SAR coefficient is adjusted when the respective SAR bit toggles then the rate of adjustment for each capacitor weight will be uniform if the adjustments are proportionally scaled by powers of two.}
$$ \mathbf{W}_{SAR}[n+1] = \mathbf{W}_{SAR}[n] + \boldsymbol{\alpha} \underbrace{ sign(\dot{Q_{out}}[n] \dot{\mathbf{Q}_{SAR}}[n])}_{\text{ternary result (+1/0/-1) } } $$
Eq. 11 introduces the proposed method for iteratively updating \\(\mathbf{W}_{SAR}\\) for the n\textsuperscript{th} sample using \\(\alpha\\) as fixed adjustment factor. \\(\dot{Q_{out}}\\) is the first order difference of the quantized output which is a function of the SAR \\(Q_{SAR}\\) and modulator \\(Q_{\Sigma\Delta}\\) outputs. The exact relation is expressed in Eq. 12. No multiplication is required here because whether a SAR bit has toggled is strictly Boolean and represented by \\(\dot{\mathbf{Q}_{SAR}}[n]\\). This leads to a ternary result with respect to the adjustment rule for incrementing or decrementing the estimated weights that can be implemented using 7 up/down counters of varying depth. In this case the MSB counter has a logical depth of 16 bits while the LSB uses 22 bits.}
$$ Q_{out}[n] = \mathbf{Q}_{SAR}[n] \cdot \mathbf{W}_{SAR}[n] + 2^{-N} \mathbf{Q}_{\Sigma\Delta} \cdot\mathbf{W}_{FIR} $$
If we presume our \\(\Delta\Sigma\\) converter has ideal performance then $2^{-N} \mathbf{Q}_{\Sigma\Delta} \cdot\mathbf{W}_{FIR} = V_{IN}[n] - \mathbf{W}_{DAC}[n]$ which leads to \\(\dot{Q_{out}}\\) as:}
$$ \dot{Q_{out}}[n] = \dot{V_{IN}[n]} + \dot{\mathbf{W}_{SAR}[n]} - \dot{\mathbf{W}_{DAC}[n]} $$
Eq. 13 reveals that during calibration the output will consist of two components. The first is due to the input as the ramp's rate of change \\(\dot{V_{IN}}\\) that is either increasing or decreasing. The second term results from an incorrect weight estimate on whichever SAR bit changed.} In fact depending on the sign of this error we know if the estimated weight needs to be larger or smaller. In essence Eq. 11 uniformly averages over all DNL errors to approach the correct weights.
# 9 Circuit Implementation
Using the foregoing results, the presented implementation targets a 12 bit resolution using \\(N=6\\) & \\(M=6\\) which should lie just on the inflection point of estimated area requirement curve. In particular we will present the configuration for a fully differential sensor array using analogue and digital supplies at 1.2 V and a commercially available 6-Metal \cmostech technology (AMS/IBM C18A6/7SF).}
## 10 Loop Filter
The loop filter topology used here is a second order feed forward architecture that is used extensively in CT modulators due to its reduced complexity and low distortion[^29][^28]. This particular structure reduces the number of summation nodes and digital feedback elements to minimise power consumption. The signal and noise transfer functions due the loop filter \\(H(s)=2^N (s^2+2 \omega_{bw} s)/\omega^2_{bw}\\) and the feedback factor $f\approx 2^{-N}$ are summarised in Eq. 14 & 15 where \\(\omega_{bw}\\) is the filter bandwidth in radians. The feedback \\(f\\) is determined by evaluating the capacitive coupling from \\(C_{\Delta\Sigma}\\) onto \\(V_{DAC}\\). Since \\(f\\) is quite small there is an apparent gain in the STF but not in the NTF. This gain is provided by increasing the bandwidth of the first stage by \\(2^{N}\\) which substantially diminishes the input referred noise from the second integrator and comparator.} Then using the requirements from Sec. 5 will allow the capacitors to be specified for this implementation as $f_{smp} (N+DC+2)/2=4V_{R} I_{B1}/(\eta U_{T} 2^{N} C_{L1})=2V_{R} I_{B2}/(\eta U_{T} C_{L2})$.}
$$ NTF(s) = \frac{s^2}{s^2 + 2 \omega_{bw} s + \omega^2_{bw}} $$
$$ STF(s) = 2^{N}\frac{2 \omega_{bw} s + \omega^2_{bw}}{s^2 + 2 \omega_{bw} s + \omega^2_{bw}} $$
{{< figure src="/images/tcas2017/sch_lf.svg" title="Figure 9: Schematic level implementation of the switched loop filter using noise efficient complementary transconductors and a current mode summation circuit." width="500" >}}
The transistor level implementation is shown in Fig. 9 where the switches \\(S_{\Delta\Sigma}\\) allow the filter to change its operation. The first stage uses a fully differential complementary or inverter-based transconductor that can tolerate small variations in input common mode fluctuation by \\(\pm\\)100 mV and this specific configuration exhibits an \\(NEF\approx1.6\\). The sizing of this complementary pair requires some attention regarding the capacitive loading on \\(V_{DAC}\\) due to the gate to drain capacitance of the transistors. In fact \\(C_{u}\\) needs to be considerably larger than this parasitic such that the open loop gain of the first integrator is not reduced and thereby diminishing filter performance.} The circuit is segmented into three sections; two analogue integrators and one summation stage. The first integrator will switch between resistive and capacitive loads. This stage will have the most demanding bandwidth requirement when providing pre-amplification during SAR quantization. Both integration capacitors are reset outside of the $\Delta \Sigma$ phase and the last two stages should achieve -40 dB HD<sub>3<sub> for a \\(\pm\\)100 mV input signal which is derived from simulations [^24]. The common mode feedback on the two integrators uses linear mode devices that reference \\(V_{DD}/2\\). These transistors can be quite large and introduce considerable parasitics because of the large current dissipated in the first stage. To avoid a reduction in bandwidth, a sub-set of these gates are connected to the loading capacitor \\(C_{L1}\\) that is switched out during SAR conversion which retains the steady state common mode voltage.} The 1-bit quantization is realized using a dynamic latch where offset associated concerns should follow conventional wisdom for accurate SAR conversion. The diode connected load in the summing stage places the input common mode of the comparator close to \\(V_{DD}\\). This improves both the bandwidth and noise performance of the latch[^30].}
## 11 Capacitive DAC
A 7-bit fully differential binary weighted capacitive DAC is used to perform the SAR quantization. The single ended structure is shown in Fig. 10. The voltage scaling on the last conversion cycle reduces the number of capacitors needed and takes advantage of the reduced reference sensitivity for the last SAR conversion. Because calibration is performed with respect to \\(C_{\Delta\Sigma}\\) that references \\(V_{R}\\) the mismatch in the last SAR coefficient will also accommodate the mismatch in voltage reference.} The array is realized by precision top metal-on-metal capacitor devices which utilize M5-M6. A M4 \\(V_{CM}\\) shield is introduced to isolate this array from active analogue and digital circuitry placed below. While bottom plate sampling diminishes the effect of parasitics on \\(V_{DAC}\\), the split capacitor needs tuning according to the extracted parasitics on the LSB section particularly with respect to the shielding layer. The unit capacitor is 71 fF with 6\\(\times\\)6 \mmu m\\(^2\\) dimensions yielding 0.2% deviation of capacitor mismatch for a \\(3\sigma\\) confidence interval. This should allow a precision of 9 ENOB without calibration [^31] and will utilise all the top metal area needed for the sub-blocks placed below.
{{< figure src="/images/tcas2017/sch_dac.svg" title="Figure 10: Single ended equivalent of the 7-bit split-capacitive SAR DAC using voltage scaling on the smallest weight. " width="500" >}}
During sampling each input will be loaded by a total of 768 fF for an equivalent 52 \mmu V<sub>rms<sub> sampling noise. This should indicate that the upper bound of maximum signal to noise and distortion ratio (SNDR) for this DAC is 78 dB. Also note that the INL characteristic of the SAR and comparator noise will inevitably lead to additional sources of quantization error which implies the \\(\Delta\Sigma\\) input range will correspondingly increase from its expected value. Moreover resolving a sampled input with a \\(\Delta\Sigma\\) modulator can lead to increased distortion due to idle tones. This is why the modulator should be designed such that signals that are -3 dB of the maximum \\(\Delta\Sigma\\) input range can still be adequately resolved. Fortunately comparing single bit modulators reveals second order feed-forward structures are substantially more capable of processing signals close to the full range input due to improved stability dynamics [^16]. This means the DAC mismatch requirements are less stringent and will not need a sub-binary weighting or additional calibration capacitors to minimize the sources of excess residue.} The simpler binary weighted structure will allow good baseline matching for the unit capacitors with the minimum number of elements in the DAC. Moreover introducing the split capacitor in addition to the \\(V_{cm}\\) switching method dramatically reduces the total switching energy to the extent that it is dominated by the oversampling phase. Particularly when multiple data converters are operated in parallel the excessive capacitive switching raises a concern for high frequency supply noise of the reference voltage that is outside the LDO bandwidth. The anti-aliasing provided by the loop filter will partly reject this component as a result of opting for a CT implementation. The \\(\Delta\Sigma\\) feedback will dissipate at most 77 fC every cycle which needs to be partly absorbed by decoupling capacitors local to the ADC. High density MOS capacitors are therefore introduced to load the reference voltage by 20 pF per ADC. The reduced switching noise should represent a clear advantage over switched capacitor modulators. An improvement over the conventional SAR may only be expected when calibration overhead is unavoidable because the sampling noise constraint makes energy dissipation in SAR switching mostly indifferent to its resolution.
## 12 FIR Filtering
Decimation of the \\(\Delta\Sigma\\) bit stream of incremental topologies finds the application of FIR filters particularly suitable. This is in part because resetting the integrators for each sample and discards residual components from the previous conversion and the corresponding group delay requirement can limit the IIR filter design.} Moreover sharing FIR filter coefficients with multiple ADCs reduces the hardware requirements to a shared lookup table with individual accumulators for each modulator. Using an \\(OSR\\) of 24 implies \\(N+DC+1=31\\) additions are needed per sample where a second order CIC filter would need at least \\(N+2DC+3=57\\) additions per sample for a full evaluation and four times the number of registers[^32]. From Sec. \ref{sec:model} we know that the register depth \\(R_{D}\\) should be 16 bits while the FIR coefficient precision needs to be 8 bits.} The application of a symmetric FIR window also assists with a number of circuit considerations for rejecting noisy aggressors near \\(f_{bw}\\)[^8]. Supply noise is a typical culprit but it may be less obvious that the FIR also reduces the sensitivity due to the second integrator's offset when the quantization mode switched.} Hanning or raised cosine FIR windows are known to provide exceptional aliasing particularly when applied to sample limited \\(\Delta\Sigma\\) decimation [^33]. Using a general family of raised cosine windows[^34] a configuration is proposed here that matches the noise shaping of the loop filter order (\\(L\\)) with that of the FIR side-lobe roll-off by defining its coefficients as:}
$$ FIR[n] = cos^{K}\left(\frac{\pi n}{OSR+1}-\frac{\pi}{2}\right) $$
The factor \\(K\\) in Eq. 16 determines the spectral characteristics of the filter similar to that of the kaiser windows. The rapid side-lobe roll-off is related to \\(K\\) as \\(30K \\)dB/Dec with the first zero location at \\(\pi(1+K/2) f_{smp}\\). Because the quantization noise is shaped in relation to \\(L\\) at \\(20L \\)dB/Dec[^5], \\(K\\) can be defined as \\(K=2/3 L\\). This leads to a near uniform quantization noise profile with a reduced transition band from better pole placement. The \\(K\\)-factor dependent frequency characteristics are shown in Fig. 11 for an \\(OSR=16\\) applied to the output of a second order modulator. Note that when \\(K=2\\) the FIR is equivalent to that of a Hanning window. The overall system transfer function \\(Sys(z)\\) can be analysed in the z-domain using a bilinear transform of the loop filter \\(H(s)\\) and convolving it with that of the FIR response. To see how well decimation is achieved we compare the decimation performance to that of an ideal filter .}
{{< figure src="/images/tcas2017/QFIR.svg" title="Figure 11: Overall noise shaping profile of the modulator and FIR in cascade for \\(K=2\\) and \\(K=1.33\\)." width="500" >}}
$$ S_Q^2 = \frac{ 2\pi^{2L} }{3(2L+1)(OSR)^{2L+1} } $$
Eq. 17 introduces the expected in-band quantization noise power \\(S_Q^2\\) from analytic relations[^35] which assume an ideal brick-wall filter with a cut off frequency at \\(f_{smp}/2\\) that is not limited in any way.} Similarly integrating over the resulting power densities in \\(Sys(z)\\) will indicate the expected quantization noise from the proposed configuration. Comparing these two results will indicate how effectively the quantization noise is rejected by the FIR filter.} The noise excess is shown in Fig. 12 as a function of OSR and filter order. This shows that using the proposed window results in loss smaller than 0.5 bits.} Also notice that we do not pay special attention to how the \\(\Delta\Sigma\\) quantization noise folds onto the signal band. After the signal is convolved by the SAR quantization process the residue no longer shares the same structure as the input signal and therefore better in band decimation performance will not lead to better in band SNR.}
{{< figure src="/images/tcas2017/OBT.svg" title="Figure 12: Quantization noise suppression based on numerical simulations and Eq. 17 and the respective precision loss for varying \\(OSR\\)." width="500" >}}
# 13 Measured Results
{{< figure src="/images/tcas2017/chip_micro.svg" title="Figure 13: Microphotograph of the 64 channel neural recording system showing two 32 channel macros used in parallel with integrated power management and digital processing.}" width="500" >}}
{{< figure src="/images/tcas2017/fab_exhibit.svg" title="Figure 14: Fabricated \\(\Delta\Sigma\\)SAR prototype showing a) an isolated test ADC structure used for characterization b) a close up micrograph showing the capacitive DAC and top metal c) the ADC layout with annotated sub-blocks. The SAR capacitors are highlighted in blue and numbered in term of which SAR bit they represent. The analogue MOS and MIM capacitors are highlighted in red showing the filter capacitors L1 & L2 and the decoupling capacitors.}" width="500" >}}
A chip micrograph is shown in Fig. 13 depicting the 64 channel instrumentation system with die size of 6.2 mm<sup>2<sup>. This configuration uses two macros each of which integrates eight ADCs together with the DSP in a tiled fashion to post-process the recordings from 32 instrumentation amplifiers. In fact the architecture may be scaled to accommodate more channels by virtue of the pipelined architecture that distributes the processing capacity. The measured results presented here are taken from an isolated test structure that allows detailed characterization without overhead from the whole system.} The physical implementation of the \\(\Delta\Sigma\\)SAR sub-block is shown in Fig. 14 which is 96\mmu m\\(\times\\) 164\mmu m in size. Because the DSP is assisted by a specialized execution unit that also performs neural signal decomposition only the digital accumulator is included in this figure. The active components inside the modulator contribute to a small portion to the overall system. Instead the most demanding layout consideration is with regard to the switches driving the capacitive DAC. Even though the capacitance is not too large, the switch resistance in \\(\Delta\Sigma\\) mode can introduce a pole leading to excess loop delay that could result in performance degradation [^36].
{{< figure src="/images/tcas2017/INL2.svg" title="Figure 15: Measured INL of the ADC before and after calibration with 2.4 V differential amplitude. " width="500" >}}
{{< figure src="/images/tcas2017/CALC.svg" title="Figure 16: Convergence of DNL rms and peak to peak values during calibration subject to a 90 Hz triangular waveform." width="500" >}}
Initial ADC characterization used a low-frequency 180 Hz tone at half to the full input range where the comparator bit stream was directly acquired off-chip for post-processing. This allowed the proposed calibration mechanism to be compared with more robust methods. In fact when using more elaborate numerical optimization methods to adjust \\(\mathbf{W}_{SAR}\\) the THD only showed 2 dB improvement although convergence is typically much faster. Both testing and calibration waveforms were generated off-chip using an Agilent 33120a with additional bandpass filtering. The measured INL characteristics are shown in Fig. 15. The calibration method decreases the SAR nonlinearity by a factor of 10. As shown in Fig. 16 the main drawback of this method is that in order to reject noisy perturbations the \\(\alpha\\) rate must be small amounting to slow convergence on the order of 10<sup>6<sup> quantization cycles or around 10 seconds. The DAC used for generating the ramp signal will need to be more accurate than the ADC precision to allow correct calibration. On the other hand instead of using a more powerful centralized DSP unit to perform tuning, this system allows all channels to calibrate simultaneously resulting in a speed up for multichannel systems that can share a single high resolution DAC.} The discontinuities visible in this trend result from the fitting method used to calculate DNL as a function of time which is not very consistent.
{{< figure src="/images/tcas2017/Spectrum2.svg" title="Figure 17: Measured ADC performance showing the spectral characteristics of a) SAR residue at the output of the \\(\Delta\Sigma\\) and b) the full precision output which has a SNDR of 66.8 dB. This recording was taken using a 2.35 Vpp 95 kHz input tone sampled at 200 kHz .}" width="500" >}}
{{< figure src="/images/tcas2017/QRES.svg" title="Figure 18: FIR output over time due to a 1.2 Vpp 180 Hz input tone showing the quantized residue after SAR conversion. " width="500" >}}
{{< figure src="/images/tcas2017/MMO.svg" title="Figure 19: Measured quantization noise spectrum of the second order \\(\Delta\Sigma\\) modulator that is clocked at 7 MHz averaged over 10<sup>3<sup> conversions with an OSR of 24.}" width="500" >}}
Fig. 17 shows the spectral characteristics of the ADC after the capacitor weights have been estimated with 16 bit precision together with the SAR residue that can be obtained by only taking the decimated modulator output. This illustrates that SAR residue has its spectral power distributed over the entire bandwidth at multiple tones. This wideband quantization 'noise' will in effect present dithering on modulator's nonlinearity before appearing at the output.} Fig. 18 shows the signal resolved by the modulator as a function of time. Interestingly the polarity in residue will directly correspond to the polarity of the sampled input signal because swapping the reference voltage on the capacitive DAC will imply a successive approximation while maintaining correspondingly positive or negative residues. Then by performing a Fourier transform on the measured modulator output for each conversion separately we can evaluate the noise shaping characteristic of the loop filter. This result is shown in Fig. 19 which follows closely to the expected second order noise shaping.}
{{< figure src="/images/tcas2017/SDOS.svg" title="Figure 20: Measured \\(FOM_{S}\\) dependency for varying OSRs but keeping a 7 MHz system clock frequency for a 10\\( kHz\\) 2.4 Vpp input tone." width="500" >}}
{{< figure src="/images/tcas2017/FDP.svg" title="Figure 21: Measured SNDR dependency for varying input frequency for a 2.35 Vpp input tone." width="500" >}}
Table 1: Comparison of State-of-The-Art ADC specifications
| **Parameter** | Unit | [^18] | [^23] | [^7] | [^13] | [^38] | [^39] | [^40] | [^41] | [^6] | **This Work** |
|----|----|----|----|----|----|----|----|----|----|----|----|
| **Year** | | 2007 | 2014 | 2015 | 2015 | 2016 | 2016 | 2016 | 2016 | 2017 | **2017** |
| **Tech.** | [nm]| 180 | 65 | 180 | 65 | 110 | 65 | 180 | 55 | 180 | **180** |
| **Topology** | | SAR | NSSAR | IADC | NSSAR | SAR | SAR | IADC | NSSAR | IADC | \textbf{(\Delta\Sigma)SAR} |
| **Supply-V** | [V] | 1 | 0.8 | 1.8 | 0.8 | 0.9 | 0.4 | 1.8 | 1.2 | 1.5 | **1.2** |
| **Supply-I** | [\mmu A] | 25 | 1.7 | 19 | 151 | 27 | 1.8 | 16.4 | 13.1 | 23 | **4.3** |
| **Speed** | [S/s] | 100 k | 32 k | 8 k | 6.25 M | 1 M | 1 k | 313 k | 4 k | 2 k | **200 k ** |
| **ENOB** | [bits] | 10.55 | 12.4 | 12.3 | 9.35 | 11.0} | 7.81 | 9.3 | 15.7 | 16.1 | **10.8**} |
| **SNDR** | [dB] | 65 | 76 | 75 | 58 | 67 | 49 | 57 | 96 | 97 | **67**} |
| **Area** | [mm²] | 0.63 | 0.18 | 0.33 | 0.012 | 0.097 | 0.013 | 0.002 | 0.072 | 0.5 | **0.016 ** |
| **FOMW** | [fJ/conv] | 165 | 8 | 862 | 14.8 | 11.7 | 3.19 | 151 | 73.8 | 320 | **14**} |
| **FOMS** | [dB] | 156 | 177 | 159 | 163 | 170 | 137 | 154 | 180 | 175 | **170**} |
In Table 1 the performance is summarized and state-of-the-art noise shaping ADC structures are compared. This work achieves exceptional compactness for the 12 bit target resolution particularly in relation to the conversion efficiency [^37]}. The measured power dissipation is about 5 \mmu W of which simulations indicate 40% is dissipated in the loop filter and 23% in capacitive switching. Note that power dissipation from the look up table is not included in this figure. Fig. 20 presents the measured SNDR and \\(FOM_{W}\\) for varying oversampling ratios. During calibration the OSR was doubled to gain 3 dB in precision while the typical operation uses an \\(OSR\\) of 24.} The total conversion uses an additional 11 cycles for SAR and sampling phases to give the resulting 200 kS/s speed for a 7 MHz system clock. We also show the measured SNDR for varying input frequencies in Fig. 21. This shows that maximum precision is maintained for signals below 20 kHz but also shows some degradation at frequencies near the maximum input bandwidth. The main experimental difficulty resulting from the proposed configuration is that the filter characteristics are closely tied to the reference voltage in a practical setting. On occasion it is useful to give additional voltage overhead for aggressive digital and analogue systems to accommodate process voltage and temperature variance. However in this case the biasing circuit will need extra tuning parameters to keep the modulator's linearity consistent while adjusting the reference voltage. Multi channel systems can generally accommodate complex tuning for all ADCs to eliminate wafer/process level variations without substantial overhead since this functionality is already needed by instrumentation circuits to perform precise filtering. The power management block in Fig. 13 provides 12 bit digital trimming on the ADC reference voltages and bias currents such that most of the off-set can be accommodated although this is performed externally on the test structure.}
# 14 Conclusion
A novel 12-bit analogue-to-digital data converter has been proposed that uses SAR & \\(\Sigma\Delta\\) quantization schemes to realize a compact and ultra low power data converter for a 64 channel neural sensor system. Using an efficient Gm-C filter, compact 7 bit binary DAC, and optimized FIR decimation this work aims to eliminate the circuit complexity from DEM and increase power efficiency which is highly desirable for biomedical sensors.} A prototype fabricated in \cmostech demonstrates 10.8 ENOB precision at the nyquist frequency with a state-of-the-art 0.016 mm² silicon footprint and is capable of resolving full scale signals at 200 kS/s.} The proposed techniques are appropriate for a variety of sampling frequencies making this configuration applicable to numerous other applications that require aggressive ADC miniaturization. In addition a calibration technique suitable for large sensor arrays is presented that takes advantage of the two step quantization scheme to calibrate multiple ADCs simultaneously.}
# 15 Acknowledgement
The authors would like to thank Nicolas Moser and the reviewers for helpful comments and assistance with improving this manuscript.
# Refernces:
[^35]: B.E. Boser and B.A. Wooley, ''The design of sigma delta modulation analog to digital converters,'' IEEE Journal of Solid-State Circuits, vol.23, no.6, pp. 1298--1308, Dec 1988.
[^4]: A.Agah etal., ''A high-resolution low-power incremental $\Sigma \Delta$ ADC with extended range for biosensor arrays,'' IEEE Journal of Solid-State Circuits, vol.45, no.6, pp. 1099--1110, June 2010.
[^30]: P.Nuzzo etal., ''Noise analysis of regenerative comparators for reconfigurable ADC architectures,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.55, no.6, pp. 1441--1454, July 2008.
[^8]: Y.Chae, K.Souri, and K.A.A. Makinwa, ''A 6.3$ \mu$W 20$ $bit incremental zoom-adc with 6 ppm INL and 1 $\mu$V offset,'' IEEE Journal of Solid-State Circuits, vol.48, no.12, pp. 3019--3027, Dec 2013.
[^24]: J.Huang, S.Yang, and J.Yuan, ''A 75 dB SNDR 10-MHz signal bandwidth gm-c-based sigma-delta modulator with a nonlinear feedback compensation technique,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.62, no.9, pp. 2216--2226, Sept 2015.
[^34]: R.Webster, ''A generalized hamming window,'' IEEE Transactions on Acoustics, Speech, and Signal Processing, vol.26, no.3, pp. 269--270, Jun 1978.
[^1]: K.Famm etal., ''Drug discovery: a jump-start for electroceuticals,'' Nature, vol. 496, no. 7444, pp. 159--161, April 2013.
[^15]: L.B. Leene and T.G. Constandinou, ''A 2.7$ \mu$W/MIPS, 0.88$ $GOPS/mm$^2$ distributed processor for implantable brain machine interfaces,'' in IEEE Proceedings of the Biomedical Circuits and Systems Conference, October 2016, pp. 360--363.
[^14]: L.B. Leene, Y.Liu, and T.G. Constandinou, ''A compact recording array for neural interfaces,'' in IEEE Proceedings of the Biomedical Circuits and Systems Conference, October 2013, pp. 97--100.
[^31]: X.Yue, ''Determining the reliable minimum unit capacitance for the DAC capacitor array of SAR ADCs,'' Microelectronics Journal, vol.44, no.6, pp. 473 -- 478, 2013.
[^23]: P.Harpe, E.Cantatore, and A.van Roermund, ''An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1 dB SNDR,'' in IEEE Proceedings of the International Solid-State Circuits Conference, February 2014, pp. 194--195.
[^41]: Y.S. Shu, L.T. Kuo, and T.Y. Lo, ''An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS,'' IEEE Journal of Solid-State Circuits, vol.51, no.12, pp. 2928--2940, Dec 2016.
[^36]: B.D. Vuyst etal., ''The nyquist criterion: A useful tool for the robust design of continuous-time $\Sigma \Delta$ modulators,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.57, no.6, pp. 416--420, June 2010.
[^19]: V.Balasubramanian etal., ''A 0.18$\mu$m biosensor front-end based on 1/f noise, distortion cancelation and chopper stabilization techniques,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.5, pp. 660--673, Oct 2013.
[^21]: Y.Tao and Y.Lian, ''A 0.8-V, 1-mS/s, 10-bit SAR ADC for multi-channel neural recording,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.62, no.2, pp. 366--375, Feb 2015.
[^20]: Z.Zhu and Y.Liang, ''A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-$\mu$m CMOS for medical implant devices,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.62, no.9, pp. 2167--2176, Sept 2015.
[^2]: K.Abdelhalim etal., ''64-channel UWB wireless neural vector analyzer SoC with a closed-loop phase synchrony-triggered neurostimulator,'' IEEE Journal of Solid-State Circuits, vol.48, no.10, pp. 2494--2510, Oct 2013.
[^17]: J.C. Candy and G.C. Temes, The Design of Sigma Delta Modulation Analog to Digital Converters.\hskip 1em plus 0.5em minus 0.4em elax Wiley-IEEE Press, 1992, pp. 293--303.
[^26]: W.Liu, P.Huang, and Y.Chiu, ''A 12-bit, 45-mS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration,'' IEEE Journal of Solid-State Circuits, vol.46, no.11, pp. 2661--2672, Nov 2011.
[^27]: H.S. Lee, D.A. Hodges, and P.R. Gray, ''A self-calibrating 15 bit CMOS A/D converter,'' IEEE Journal of Solid-State Circuits, vol.19, no.6, pp. 813--819, Dec 1984.
[^7]: S.Tao and A.Rusu, ''A power-efficient continuous-time incremental sigma-delta ADC for neural recording systems,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.62, no.6, pp. 1489--1498, June 2015.
[^16]: R.Schreier, ''An empirical study of high-order single-bit delta-sigma modulators,'' IEEE Transactions on Circuits and Systems---Part II: Analog and Digital Signal Processing, vol.40, no.8, pp. 461--466, Aug 1993.
[^13]: Z.Chen, M.Miyahara, and A.Matsuzawa, ''A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC,'' in IEEE Proceedings of the Symposium on VLSI Circuits, June 2015, pp. C64--C65.
[^12]: Z.Chen, M.Miyahara, and A.Matsuzawa, ''A stability-improved single-opamp third-order $\Delta\Sigma$ modulator by using a fully-passive noise-shaping SAR ADC and passive adder,'' in IEEE Proceedings of the European Solid-State Circuits Conference, Sept 2016, pp. 249--252.
[^11]: Y.S. Shu, L.T. Kuo, and T.Y. Lo, ''An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55nm cmos,'' in IEEE Proceedings of the International Solid-State Circuits Conference, January 2016, pp. 458--459.
[^3]: J.M. dela Rosa etal., ''Next-generation delta-sigma converters: Trends and perspectives,'' IEEE Transactions on Emerging and Selected Topics in Circuits and Systems, vol.5, no.4, pp. 484--499, Dec 2015.
[^40]: I.Lee, B.Kim, and B.G. Lee, ''A low-power incremental delta-sigma ADC for CMOS image sensors,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.63, no.4, pp. 371--375, April 2016.
[^6]: Y.Zhang etal., ''A 16 b multi-step incremental analog-to-digital converter with single-opamp multi-slope extended counting,'' IEEE Journal of Solid-State Circuits, vol.52, no.4, pp. 1066--1076, April 2017.
[^33]: E.Nunzi, P.Carbone, and D.Petri, ''Estimation of the in-band delta--sigmanoise power based on windowed data,'' IEEE Transactions on Instrumentation and Measurement, vol.55, no.6, pp. 2221--2226, Dec 2006.
[^39]: P.Harikumar, J.J. Wikner, and A.Alvandpour, ''A 0.4-V subnanowatt 8-bit 1-kS/s SAR ADC in 65-nm cmos for wireless sensor applications,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.63, no.8, pp. 743--747, Aug 2016.
[^5]: C.H. Chen etal., ''A micro-power two-step incremental analog-to-digital converter,'' IEEE Journal of Solid-State Circuits, vol.50, no.8, pp. 1796--1808, Aug 2015.
[^10]: J.A. Fredenburg and M.P. Flynn, ''A 90-mS/s 11-MHz-bandwidth 62-dB SNDR noise-shaping SAR ADC,'' IEEE Journal of Solid-State Circuits, vol.47, no.12, pp. 2898--2904, Dec 2012.
[^25]: D.J. Chang etal., ''Normalized-full-scale-referencing digital-domain linearity calibration for SAR ADC,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.64, no.2, pp. 322--332, Feb 2017.
[^29]: K.Lee, M.R. Miller, and G.C. Temes, ''An 8.1 mW, 82 dB delta-sigma ADC with 1.9 MHz BW and -98 dB THD,'' IEEE Journal of Solid-State Circuits, vol.44, no.8, pp. 2202--2211, Aug 2009.
[^28]: J.Silva etal., ''Wideband low-distortion delta-sigma ADC topology,'' Electronics Letters, vol.37, no.12, pp. 737--738, Jun 2001.
[^22]: F.Gerfers, M.Ortmanns, and Y.Manoli, ''A 1.5-V 12-bit power-efficient continuous-time third-order sigma; delta; modulator,'' IEEE Journal of Solid-State Circuits, vol.38, no.8, pp. 1343--1352, Aug 2003.
[^9]: A.Sanyal, L.Chen, and N.Sun, ''Dynamic element matching with signal-independent element transition rates for multibit $\Delta\Sigma$ modulators,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.62, no.5, pp. 1325--1334, May 2015.
[^32]: E.Hogenauer, ''An economical class of digital filters for decimation and interpolation,'' IEEE Transactions on Acoustics, Speech, and Signal Processing, vol.29, no.2, pp. 155--162, Apr 1981.
[^38]: Y.H. Chung, C.W. Yen, and M.H. Wu, ''A 24-$\mu$W 12-bit 1-mS/s SAR ADC with two-step decision DAC switching in 110-nm cmos,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, no.11, pp. 3334--3344, Nov 2016.
[^18]: N.Verma and A.P. Chandrakasan, ''An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes,'' IEEE Journal of Solid-State Circuits, vol.42, no.6, pp. 1196--1205, June 2007.
[^37]: K.Lee, Y.Yoon, and N.Sun, ''A scaling-friendly low-power small-area $\Delta\Sigma$ ADC with VCO-based integrator and intrinsic mismatch shaping capability,'' IEEE Transactions on Emerging and Selected Topics in Circuits and Systems, vol.5, no.4, pp. 561--573, Dec 2015.

111
content/publications/2017/a-0-5-v-time-domain-instrumentation-circuit-with-clocked-and-unclocked-rds-operation.md Normal file
View File

@ -0,0 +1,111 @@
---
title: "A 0.5 V time-domain instrumentation circuit with clocked and unclocked ΔΣ operation"
date: 2017-05-28T15:26:46+01:00
draft: false
toc: true
math: true
type: posts
tags:
- publication
- instrumentation
- CMOS
- time-domain
- circuit
---
Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
This paper presents a time-domain instrumentation circuit with exceptional noise efficiency directed at using nano metre CMOS for next generation neural interfaces. Current efforts to realize closed loop neuromodulation and high fidelity BMI prosthetics rely extensively on digital processing which is not well integrated with conventional analogue instrumentation. The proposed time-domain topology employs a differential ring oscillator that is put into feedback using a chopper stabilized low noise transconductor and capacitive feedback. This realization promises better digital integration by extensively using time encoded digital signals and seamlessly allows both clocked & unclocked \\(\Delta\Sigma\\) behavior which is useful on-chip characterization and interfacing with synchronous systems. A 0.5 V instrumentation system is implemented using a 65 nm TSMC technology to realize a highly compact footprint that is 0.006 mm² in size. Simulation results demonstrate an excess of 55 dB dynamic range with 3.5 \mmu V<sub>rms<sub> input referred noise for the given 810 nW total system power budget corresponding to an NEF of 1.64.
# 2 Introduction
Recent efforts to realize brain machine interfaces (BMI) target fully integrated neural recording systems that use advanced CMOS technologies to enable real time diagnostics for hundreds of channels simultaneously. This emerging trend is predominately motivated by the extensive use of digital techniques applied to robust therapeutic feedback for closed-loop neuromodulation and signal compression/feature extraction in high channel count BMIs for prosthetic motor control[^1]. However there are a growing number of challenges associated with integrating analogue instrumentation for these digital systems due to the loss in analogue transistor characteristics which has motivated the use of time domain (TD) analogue [^2]. TD systems encode information with respect to the timing intervals of asynchronous digital signals to perform mixed signal processing while extensively using standard logic and oscillators that do not suffer from analogue complications. Many recent publications will indicate the potential for exceptional dynamic range like in the recording system of [^3] or highly compact instrumentation like the potentiostat in \cite{VCO_SENSE2}. We argue that a key advantage for these systems is that supply voltage is utilized more effectively from a fundamental aspect without being impeded by linearity. This allows an aggressive reduction in power dissipation. Furthermore realizing band limiting filters outside the instrumentation loop prevents KT/C relations from limiting the compactness of the system.
{{< figure src="/images/iscas2017/TDI.svg" title="Figure 1: TD system architecture for BMI systems where both the instrumentation and processing sub-blocks manipulate time-encoded signals to perform feature extraction from bio-signal recordings. This paper will present the instrumentation sub-system." width="500" >}}
This work presents a TD instrumentation topology for neural recording applications that targets ultra-low power operation and a highly compact implementation for miniaturized multichannel systems. Based on previous work in [^4], which uses a third order feedback loop to digitize the signal asynchronously, this realization exhibits only one dominant pole and thus reduces the resources spent on achieving stability. While [^4] can achieve a smaller footprint than the topology presented here the feed-forward structure cannot achieve high dynamic range as the high frequency quantization noise and out of band distortion from the counter cannot be suppressed without additional filtering. Our current efforts aim to realize the system architecture illustrated in Fig. 1. This approach aims to use the efficiency of TD processing techniques to extract features from neural recordings which promise an order of magnitude improvement over conventional implementations [^5]. In fact such a TD approach has already been applied to acquire wireless radio signals with a versatile activity dependent power dissipation [^6]. However there will be numerous scenarios where these asynchronous structures must interface with clocked systems to effectively perform calibration or other discrete time analysis. For this reason we specifically consider how the class of circuits presented here and in [^5] can seamlessly realize a more traditional clocked \\(\Delta\Sigma\\) oversampling loops. This is relevant because time encoded signals have a very broad bandwidth of several GHz making it unreasonable to characterize or communicate a large number of them off chip. Finding effective means to convert such time-encoded signals to a clocked and quantized equivalent is crucial for fully integrated systems. This paper is organized as follows; First the basic structure of the proposed circuit is introduced in Sec. \ref{Sec:architecture} which motivates the general topology chosen here. Then in Sec. \ref{Sec:circuit} we shall detail the circuit level implementation and identify important design considerations. Finally Sec. \ref{Sec:simulation} presents the preliminary simulation results which leads to the conclusions in Sec. \ref{Sec:conclusion}.
# 3 Time-Domain Instrumentation Architecture
The proposed configuration is shown in Fig. 2 as a single ended equivalent of the fully differential system implemented here. The neural signals picked up on V<sub>IN<sub> include local field potentials of several millivolt and extracellular action potential from nearby neural tissue with 100 microvolt amplitudes where the total bandwidth of interest here is from near DC to 6 kHz[^1]. Using a reference electrode these components are first chopped to a higher frequency f<sub>chp<sub> at 100 kHz. This is then passed into a capacitive network that allows the digital output signal Q to be directly feedback onto the input after using a XOR gate realize chopper modulation. The intermediate node V<sub>G<sub> is tapped off to a transconductive cell which advances/recedes the phase of a multi stage ring oscillator structure after the signal is chopped back to the base band. By referencing the phase of this oscillator to another oscillator we can realize the time-encoded digital signal that encodes the phase difference \pphi<sub>\dDelta<sub> as pulse width modulated information. Then we may either quantize this signal with a register in the time domain or simply buffer it onto Q to provide asynchronous feedback without time quantization. Now the near-DC aggressors such as off-set and flicker noise from the transconductor are neutralized using the feedback loop through R<sub>p<sub> which presents a high pass response for signals below the chopper frequency on node V<sub>G<sub>. If we simply take the transconductor, oscillator, and digital logic to represent some kind of integrator then the high level instrumentation topology reduces to a relatively simple chopper stabilized circuit. Finally in the synchronous case where time is quantized, the output Q is passed into a second order cascaded integrator–comb (CIC) filter that decimates oversampled signals into discrete samples. Otherwise \pphi<sub>\dDelta<sub> is simply passed onto other TD processing structures which is outside the scope of this paper.
{{< figure src="/images/iscas2017/TDA.svg" title="Figure 2: The proposed chopper stabilized instrumentation system that uses a ring oscillator to realize TD based first order integration with respect to the output phase difference which is then quantized in time and decimated using a CIC filter. " width="500" >}}
We highlight the fact that the high pass feedback uses the output referred signal. This has a profound effect on how the noise profile of R<sub>p<sub> appears at the chopper frequency when referred to the input. In fact if R<sub>p<sub> was tied to a biasing voltage to set V<sub>G<sub> then resistor's noise will have a rms power of \\(√{kT/C_{IN}}\\) at the input that is up modulated and will corrupt the linearity of the integrator. This can be very substantial because C<sub>IN<sub> is reduced to 100 fF in order to boost the input impedance that depends on the chopping frequency as R<sub>IN<sub>=1/(f<sub>chp<sub>C<sub>IN<sub>). This feedback configuration reduces this noise component as a function of closed loop gain A<sub>cl<sub> which is maximized as we realize all the necessary signal gain in a single analogue processing stage. Moreover the chopper stabilization allows an aggressive reduction on input transistor size which is important for reducing parasitics on the node V<sub>G<sub>. Any parasitic loading here can prevent further reduction in C<sub>IN<sub> because it would degrade the noise performance.
The PWM signals \pphi<sub>\dDelta<sub>, Q, and X in Fig. 2 are illustrated in bold because they represent multiphase time-encoded signals by simultaneously taping off multiple phases inside the oscillator and using them in parallel. The capacitive feedback network sums these signals to acquire an analogue equivalent where the number of amplitude quantization levels is 1+N for N phases used in parallel. This is an important point because the error signal on V<sub>G<sub> is a function of the supply voltage as V<sub>DD<sub>/(N A<sub>cl<sub>) which must lie well within the linear range of the transconductor. Adding to the fact that supply noise is also inversely proportional to A<sub>cl<sub> reveals that although we can reduce power by reducing V<sub>DD<sub>, this parameter is tightly coupled to other performance requirements. In fact using the definition of noise efficiency factor NEF from [^7] one can derive the following expression to predict the system power P<sub>sys<sub> for noise limited systems:
$$ P_{sys} = V_{DD} \omega_{3dB} \frac{kT U_T}{e^2_{in}} NEF^2 $$
Eq. 1 uses \\(\omega\\)<sub>3dB<sub>, kT, U<sub>T<sub>, and e²<sub>in<sub> as the signal bandwidth in radians, Boltzmann energy, thermal voltage, and input referred noise power. This expression ignores any constraints due to sampling noise or capacitor sizing that could suffer as the supply voltage decreases. However it clearly illustrates our motivation for reducing power through V<sub>DD<sub> which is allowed in this fashion only if no band limiting behavior is required from the instrumentation loop. In fact an important contribution here is that a near ideal NEF is achieved for the TD structure using the proposed implementation.
# 4 Circuit Implementation
{{< figure src="/images/iscas2017/TDS.svg" title="Figure 3: Transistor level implementation of a) the low noise amplifier and b) high pass filter circuit that removes flicker noise and off-set. A legend is presented in gray showing how a) & b) relate to Fig. 2 and the chopper in a) is omitted for clarity." width="500" >}}
The fully differential analogue part of this system is shown in Fig. 3. Here two analogue structures are shown, one for signal amplification that integrates on the differential phase \pphi<sub>\dDelta<sub> which we shall consider the amplifier. The second structure presents the pseudo resistor that rejects the low frequency aggressors that are being up modulated onto the output Q which we will refer to as the high pass filter. The amplifier is composed of a complementary transcondutor to boost the noise efficiency and is loaded by two ring oscillators that are biased with a current I<sub>X<sub> that is 16x smaller than I<sub>B<sub> such that the input referred noise from the oscillator to V<sub>G<sub> is greatly reduced. A XOR gate is used to compute the phase difference of the two oscillators because it does not have a discontinuity in its phase to PWM characteristic. The floating ground of both oscillators is tied together to reject common mode noise and minimize any coupling to the analogue power supplies.
Actually, the high pass filter not only performs feedback but also determines the common mode input voltage on V<sub>G<sub>. This mechanism is used to set the common mode on V<sub>X<sub> to V<sub>CM<sub> using the transistors M5-M8. This is important because the oscillator needs to run in the middle of the rail to allow more efficient conversion from the small internal voltage oscillation of 300 mV to a digital signal with full swing. The reason a current DAC is used to drive the pseudo resistors is because the linearity of these devices is important and R<sub>p<sub> can only handle \\(\pm\\)100 mV if simple diode connected devices are used. This is why C<sub>L<sub> is introduced to provide some filtering and minimize distortion from the high frequency PWM feedback. Note that because all transistors will use subthreshold operation the threshold voltage V<sub>TH<sub> difference between the input PMOS pair M3-M4 and the high V<sub>TH<sub> devices M9-M10 will represent voltage headroom of the PMOS current bias which should at least be 100 mV.
Now there is quite a significant impact from using an oscillator as load for the amplifier structure in this particular fashion. It may be obvious that there are no high impedance analogue nodes in this configuration that could introduce undesirable poles. But more importantly we do not need to provide extra voltage headroom or a second gain stage to let our output signal vary with maximum amplitude. This proposed implementation allows both simplicity and high power efficiency. In this case the oscillator mostly reuses the V<sub>TH<sub> voltage headroom needed by the NMOS input transistors. This raises an interesting question; what limits the required voltage headroom for this circuit? Typically the complementary structure necessitates that the source drain voltage of the current bias transistors and differential pairs is sufficient to provide good channel resistance. However there is another component with regard to the noise generated by the oscillator that should be considered in terms of the oscillator voltage overhead V<sub>RO<sub>. Consider the noisy charge induced as sampling noise from one of the oscillators on each inverter gate capacitance C<sub>gate<sub> before the up/down transition as residue from the previous cycle. This can be represented by an equivalent noisy current source **i**²<sub>smp<sub> using the oscillator frequency f<sub>osc<sub> as formulated in Eq 2.
$$ i^2_{smp} = 2N f^2_{osc} kT C_{gate} $$
Referring this component to V<sub>G<sub> as input referred voltage noise equivalent **v**²<sub>smp<sub> requires f<sub>osc<sub> to be represented in terms of total charge dissipated each cycle f<sub>osc<sub>=I<sub>X<sub>/(2N V<sub>RO<sub> C<sub>gate<sub>). Taking the transconductance of the amplifier approximately as Gm\\(\approx\\)2I<sub>B<sub>/(\\(\eta\\) U<sub>T<sub>) will resolve the expression as in Eq 3 using \\(\eta\\) and U<sub>T<sub> as slope factor and thermal voltage.
$$ v^2_{smp} = \frac{i^2_{smp}}{Gm^2} = \frac{2 kT}{P_{osc}} \left( \eta U_T \frac{I_X}{2 I_B} \right)^2 $$
This result may be surprising in some sense because indicates the oscillator should dissipate a strict amount of energy to avoid this noise component from being significant. The only way to do this is by increasing the V<sub>RO<sub> because increasing its bias current I<sub>X<sub> will in fact degrade the input referred noise. Also notice that the actual capacitive load of the oscillator does not impact the thermal noise floor although it is directly related to the bandwidth of operation. In this particular case we configured the oscillation frequency to be around 300 kHz after optimization which implies that the effective frequency is around 1.5 MHz given the 5 phases. For this reason when the CIC filter is enabled we use a 3 MHz system clock for time quantization and an over sampling ratio of 128. This implies that the instrumentation bandwidth will be limited to 11 kHz sampled at exactly 22 kS/s.
# 5 Simulation Results
The presented implementation was fabricated using the commercially available TSMC 65 nm CMOS LP MS RF technology (1P9M 6X1Z1U RDL). This system can operate at 0.5 V by extensively using the different V<sub>TH<sub> process options for the standard transistor. Fig. 4 shows the floor plan and final fabricated device and the MIM capacitors covering the active area. A compact configuration was achieved with a 0.006mm² footprint where future work could potentially share the biasing and digital filter resources. Our preliminary results consist of post layout noise simulations that should have a good degree of precision for predicting the expected bench top measurements. Fig 5 shows the ring oscillator output with 200 mV amplitude in the middle of the rail that is fed to the XOR gate to produce the full swing digital signal \pphi<sub>\dDelta<sub>. Fig 6 shows the output of the circuit in the frequency domain before & after decimation by the CIC filter. We can observe that linearity is quite easily achieved due to the exceptional loop gain from the TD integrator and because all analogue nodes exhibit a small signal swing. The performance summary in Table 1 compares this work to recently published instrumentation systems using the 65nm or 90nm technology node. Notice that a comparable noise performance is achieved for a similar if not better input dynamic range while the NEF & area characteristics are respectable given the extra capability that signal quantization is also performed. The input resistance due to chopping for this configuration is estimated to be 57 M\\(\Omega\\) which will be sufficient for most integrated neural recording electrodes.
{{< figure src="/images/iscas2017/LAY.svg" title="Figure 4: The floor plan and micro photograph of the fabricated TD instrumentation prototype. " width="500" >}}
{{< figure src="/images/iscas2017/DIG2.svg" title="Figure 5: Simulation results showing a) the two ring oscillator outputs & b) the respective phase difference signal due to a 5 mVpp sinusoidal signal at 2 kHz at the input of the instrumentation system." width="500" >}}
{{< figure src="/images/iscas2017/SPC2.svg" width="500" >}}
{{< figure src="/images/iscas2017/SPC.svg" title="Figure 6: Spectral characteristics of a) the \\(\Delta\Sigma\\) modulator and b) the CIC filter output due to a 2 kHz 5 mVpp sinusoidal input showing a precision of 54.8 dB SINAD and no visible harmonics due to distortion." width="500" >}}
Table 1: Performance summary and comparison with state of the art.
| Specification | This Work | [^8] | [^9] | [^10] |
|----|----|----|----|----|
| Modality | Time | Volt. | Volt. | Volt. |
| Technology | 65nm | 90nm | 65nm | 65nm |
| Supply [V] | 0.5 | 1 | 1 | 1 |
| Supply [A] | 2.65\mmu (\dagger) | 2.85\mmu | 1**n** | 3.28\mmu |
| Gain [dB] | 46 | 59 | 32 | 52 |
| Bandwidth [Hz] | 11 **k** | 10.5 **k** | 370 | 8.2 **k** |
| SINAD [dB] | 53 | (>)40 | 57 | (>)40 |
| IRN [V<sub>rms<sub>] | 3.8\mmu | 3.04\mmu | 26\mmu | 4.13\mmu |
| NEF | 2.2 | 1.93 | 2.1 | 3.19 |
| Area [mm²] | 0.006(\star) | 0.137 | 0.168(\star) | 0.042 |
\\(^\star\\) Includes ADC area. \\(^\dagger\\) Includes axillary and biasing circuits.
# 6 Conclusion
This work realizes a chopper stabilized \\(\Sigma\Delta\\) modulator right at the sensor interface using a time-domain topology for ultra low voltage operation. The proposed oscillator based instrumentation circuit addresses a number of the challenges associated with instrumentation using nano metre CMOS technologies. This system has a power budget of 810 nW and a compact silicon foot print of 0.006 mm². Moreover this system can achieve a NEF of 1.64 while including the power dissipation due to quantizing the signal with 8.8 effective number of bits at 22 kS/s.
# 7 Acknowledgment
This work was supported by EPSRC grants EP/K015060/1 and EP/M020975/1.
# Refernces:
[^1]: H.Kassiri etal., ''Battery-less tri-band-radio neuro-monitor and responsive neurostimulator for diagnostics and treatment of neurological disorders,'' IEEE J. Solid-State Circuits, vol.51, no.5, pp. 1274--1289, May 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2528999
[^3]: W.Jiang etal., ''A ±50mv linear-input-range vco-based neural-recording front-end with digital nonlinearity correction,'' in IEEE Proc. ISSCC, January 2016, pp. 484--485. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7418118
[^2]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational amplifiers and their application to continuous-time filters in nanoscale cmos,'' IEEE J. Solid-State Circuits, vol.49, no.12, pp. 2758--2772, December 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2354641
[^6]: M.Kurchuk etal., ''Event-driven ghz-range continuous-time digital signal processor with activity-dependent power dissipation,'' IEEE J. Solid-State Circuits, vol.47, no.9, pp. 2164--2173, September 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2203459
[^10]: K.A. Ng and Y.P. Xu, ''A low-power, high cmrr neural amplifier system employing cmos inverter-based otas with cmfb through supply rails,'' IEEE J. Solid-State Circuits, vol.51, no.3, pp. 724--737, March 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2512935
[^9]: P.Harpe etal., ''A 0.20$ $mm$^2$ 3$ $nw signal acquisition ic for miniature sensor nodes in 65 nm cmos,'' IEEE J. Solid-State Circuits, vol.51, no.1, pp. 240--248, Jan 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2487270
[^8]: T.Yang and J.Holleman, ''An ultralow-power low-noise cmos biopotential amplifier for neural recording,'' IEEE Trans. Circuits Syst. II, vol.62, no.10, pp. 927--931, Oct 2015. [Online]: http://dx.doi.org/10.1109/TCSII.2015.2457811
[^7]: M.S.J. Steyaert and W.M.C. Sansen, ''A micropower low-noise monolithic instrumentation amplifier for medical purposes,'' IEEE J. Solid-State Circuits, vol.22, no.6, pp. 1163--1168, December 1987. [Online]: http://dx.doi.org/10.1109/JSSC.1987.1052869
[^4]: M.Elia, L.B. Leene, and T.G. Constandinou, ''Continuous-time micropower interface for neural recording applications,'' in IEEE Proc. ISCAS, May 2016.
[^5]: L.B. Leene and T.G. Constandinou, ''A 0.45v continuous time-domain filter using asynchronous oscillator structures,'' in IEEE Proc. ICECS, December 2016, pp. 49--52. [Online]: http://dx.doi.org/10.1109/ICECS.2016.7841129

14
content/publications/2017/circuit-design-considerations-for-implantable-devices.md Normal file
View File

@ -0,0 +1,14 @@
---
title: "Circuit Design Considerations for Implantable Devices"
date: 2017-11-15T15:26:46+01:00
draft: true
toc: true
math: true
type: posts
tags:
- chapter
- instrumentation
- CMOS
- biomedical
- circuits
---

13
content/publications/2017/microwire-cmos-integration-of-mm-scale-neural-probes-for-chronic-local-field-potential-recording.md Normal file
View File

@ -0,0 +1,13 @@
---
title: "Microwire-CMOS integration of mm-scale neural probes for chronic local field potential recording"
date: 2017-10-19T15:26:46+01:00
draft: true
toc: true
math: true
type: posts
tags:
- publication
- instrumentation
- packaging
- biomedical
---

252
content/publications/2017/time-domain-processing-techniques-using-ring-oscillator-based-filter-structures.md Normal file
View File

@ -0,0 +1,252 @@
---
title: "Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures"
date: 2017-06-07T15:26:46+01:00
draft: false
toc: true
math: true
type: posts
tags:
- publication
- CMOS
- circuits
- time-domain
---
Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
The ability to process time-encoded signals with high fidelity is becoming increasingly important for time domain (TD) circuit techniques that are used at advanced nanometre technology nodes. This work proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation (PWM) encoded signals and makes extensive use of digital logic, enabling low voltage operation. First and second order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modelled precisely to realise more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65 nm CMOS technology to realise a 4\\(^{th}\\) order lowpass Butterworth filter. The system utilises a 0.5 V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73 nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio (SNDR) of 53 dB with a narrow 5 kHz bandwidth resulting in an figure-of-merit (FOM) of 8.2 fJ/pole. With this circuit occupying a compact 0.004 mm² silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters whilst additionally offering direct integration with digital systems.
# 2 Introduction
Modern digital architectures and energy constrained devices are being increasingly challenged by device variability and probabilistic computation that are incompatible with today's digital paradigm [^1]. In contrast, many biological processes such as the human visual system are robust to such challenges. This has inspired research to explore alternative means for signal representation and computation based on phenomena observed in the natural world [^2]. This has led to the re-emergence of processing in the analogue domain as an 'accelerator' inside a digital framework[^3]. This is because the efficiency of analogue processing can be far superior to its digital equivalent for specific applications[^4][^5]. However there remain many challenges that in practice prevent such architectures from achieving a clear advantage. Current systems demand an integrated System on Chip (SoC) solution using digital CMOS technologies to realise cost effective performance. This substantially degrades analogue performance and ultimately leads to the use of time domain (TD) circuits to mitigate a number of these issues[^6]. Out of the different signal modalities that have been established: continuous-time continuous value (i.e. traditional analogue), discrete-time continuous value (i.e. switched cap analogue), discrete-time discrete value (i.e. traditional digital), these TD circuits represent the continuous-time discrete value (i.e. asynchronous digital) approach of representing information.
TD systems rely on encoding signals in terms of the delay between instantaneous events such as clock edges or digital pulses that can be manipulated using asynchronous or synchronous digital logic with very high efficiency[^7]. The nature of digital provides immunity to supply noise and flexibility in signal representation that is less sensitive to operating conditions when compared to conventional voltage or current mode processing. In fact these techniques are becoming increasingly more widespread in recent years extending from the typical use in phase locked loops (PLL) towards sensing[^8] and processing applications[^9]. Moreover the ongoing trends in supply voltage reduction and technology scaling will lead to the time-based alternatives becoming increasingly more favourable for digital system integration[^10].
{{< figure src="/images/tcas2016/td_system.svg" title="Figure 1: Concept of processing multi-phase time-encoded signals using digital logic, in combination with oscillator-based memory elements for retaining system states." width="500" >}}
It is becoming increasingly important to establish which techniques can process time-encoded signals in a way that is robust towards noisy digital environments and the nonlinear characteristics of nanometre-scale CMOS. Several methods have already been developed for PLL subsystems such as using noise to linearise time quantisation[^11] or using two-dimensional vernier lines to perform noise shaping[^12]. One example of a TD processing system is the event-driven digital filter [^13] that uses a reconfigurable delay line to process TD signals asynchronously. This work applies different weights to the delay line outputs to realise finite impulse response (FIR) filtering without introducing clocked time quantization.
Delay based techniques for amplification[^14], addition[^15], and subtraction[^15] have been particularly successful for MHz/GHz signals but tend to be incompatible with low frequency control or when dealing with signals of dissimilar bandwidths. This drawback is also characteristic of FIR techniques due to the fact that millisecond delay lines are easily prone to noisy aggressors and may require an exhaustive number of delay elements. Other systems use open loop voltage-controlled oscillator (VCO) structures for transducing low frequency signals with reduced complexity[^16][^17]. These tend to rely on the linearity of capacitive discharge or voltage-controlled frequency generation for precise processing. However this dependency is particularly vulnerable to process, voltage and temperature variations or device dependent nonlinearities if correction/compensation is not performed. Digital techniques have been proposed to reduce the overhead from correction logic[^8] but it would be desirable to reduce such sensitivities.
This work proposes a ring oscillator based filter (ROF) structure that reduces the complexity of existing TD systems to realise a compact TD filter with closed loop operation for ultra-low-power computationally intensive applications[^18][^19]. The dynamics of this architecture are, in some way, similar to asynchronous delta sigma modulators[^20] or asynchronous delta modulators[^21][^22]. The difference is that the input and output are time-encoded signals such that the functionality is strictly focused on processing. This is illustrated in Fig. 1. This topology aims to exclusively use digital logic and asynchronous control loops to adjust the phase of an oscillator which is in turn used to generate digital feedback signals to realise a continuous-time dynamical system or infinite impulse response (IIR) in the digital domain.
Similarly to the three prior works, the presented implementation also targets near-threshold voltage operation by reducing or in this case eliminating the analogue nodes that necessitate a large voltage swing. Instead the large signal components are encoded using an asynchronous digital representation. The presented technique rely on encoding phase using PWM signals and utilising current-controlled oscillators to achieve low distortion that do not require any overhead for calibration. This approach considers the oscillator as a TD memory element analogous to a capacitor in a Gm-C circuit. The resulting circuit is operated asynchronously but the concept of TD memory can also be found in clocked time to digital converters (TDC)[^23]. Furthermore, the auxiliary digital subsystem will feature additional functionality and flexibility in terms of event-driven/nonlinear outputs and gain control.
The remainder of this paper is organised as follows: Section 3 describes the basic first/second order ROF structures and 'analogue' processing characteristics; Section 6 elaborates on digital processing techniques for manipulating TD signals; Section 9 details the transistor level implementation; Section 14 presents measured results and device characteristics; and Section 20 concludes this work with respect to the achieved performance.
# 3 Analogue Processing using ROFs
The concept for the proposed topology that filters TD signals and allows local feedback without external clocking or control is shown in Fig. 1.
This uses digital control to switch a transconductive element adjusting the oscillator phase according to the intended filter response. The feedback utilises the anti-aliasing properties provided by the current controlled phase modulation to reject high frequency errors in the digital computation thereby allowing the approximate computation presented in Sec. 6.
{{< figure src="/images/tcas2016/TD_modes.svg" title="Figure 2: Analogy between conventional analogue circuits and TD circuits in relation to the four signal modalities." width="500" >}}
The different signal representations and associated processing domains are illustrated in Fig. 2. This shows how the oscillator-based processing concept presented herein relates to conventional analogue circuits, using phase information instead of magnitude to represent signals. Traditional analogue (continuous value and time) employs integration in voltage (or time) using a transconductive element that is loaded by a memory circuit. If the time however is discretized (i.e. sampled-time analogue), there is a requirement for a fast switch and large sampling capacitor. Alternatively, sampling the phase information of an oscillator can be achieved by simply using a clocked register (as the time encoded signal is inherently quantized). This implies that TD systems are able to utilize digital memories to significantly increase information capacity with minimal demand on resource. The analysis that follows develops expressions for this configuration by considering structures that are analogous to single and two-stage amplifiers[^24].
The oscillator's phase (φ) is extracted using an XOR-based phase detector (PD). By using a differential structure, the phase output will not need an external reference since the XOR output will represent the phase difference (\\(\Delta\\)φ) of two synchronized oscillators. In fact this phase measurement is a key feature that mitigates the need for external clocking or digital differentiation, as found in other realizations[^6][^10]. Moreover the XOR PD does not experience distortion from band-limiting digital gates such as the pulse swallowing seen in [^15]. Instead reducing the phase difference and equivalent PWM modulation depth leads to a smaller digital bandwidth requirement, which is not the case for the register based PD.
## 4 Single-Stage ROF
{{< figure src="/images/tcas2016/TD_L1.svg" title="Figure 3: Implementation of the single-stage ROF topology showing: (a) the switched current source driving an oscillator with closed loop feedback control of the TD signals D, Q, E; (b) the simplified s-domain equivalent model based on an ideal integrator in feedback." width="500" >}}
A block diagram of the single-stage ROF is shown in Fig. 3. The signals D & Q are PWM encoded TD signals that are compared and subsequently generate a third output that injects current into the differential oscillator such that the two pulse widths are matched. This control will either increase or decrease the relative phase and proportionally adjust the pulse width of Q in a closed loop fashion. The operation depends on the integral relationship that the output phase φ has with respect to injecting a small signal current i\tss{\\(\Delta\\)}. This is characterised using an impulse sensitivity function (ISF) originally developed for analysing CMOS oscillators [^25].
$$ \phi (t) = \int_{-\infty}^{t} \Gamma_{i\Delta}(\omega_0 , \tau) i_{\Delta}(\tau) \: d\tau $$
Eq. 1 models the ISF due to i\tss{\\(\Delta\\)} as \\(\Gamma_{i\Delta}\\). This implies the simplified s-domain model yields an integration factor k1\\(\approx\\)I\tss{\\(\Delta\\)}\\(\Gamma_{i\Delta}\\). Strictly the ISF is a cyclostationary function implying that \\(\Gamma\\) may have phase dependent sensitivity with respect to i\tss{\\(\Delta\\)}. However because the current is injected into the virtual supply node V<sub>R<sub>, this sensitivity is small as seen from \\(\Gamma_{ig}\\) in Fig. 10 and instead will be assumed phase independent (for clarity). This allows for a relatively simple argument to be made to estimate \\(\Gamma_{i\Delta}\\) for low-power ring oscillators because the low-voltage operation implies that essentially all biasing current will be used to charge and discharge capacitors on each oscillator node. More specifically the contribution of short circuit current is negligible due to strictly non-overlapping conduction of the NMOS & PMOS transistors in the oscillator and similarly the transistor area will be sufficiently small to assume that the gate leakage component is much smaller than I<sub>B<sub>.
Suppose q<sub>max<sub> is the amount of charge dissipated by the oscillator each period. Then it should follow that q<sub>max<sub> = I<sub>B<sub>/f<sub>osc<sub> by definition but this factor should also relate the total amount of capacitance switched every cycle as q<sub>max<sub> = N V<sub>RG<sub> C<sub>gate<sub>, where N, C<sub>gate<sub>, V<sub>RG<sub> are the number of oscillator stages, total capacitive load at the output of every oscillator stage, and voltage across the oscillator respectively. More interestingly if we now consider injecting some excess charge every cycle then its impact is simply normalised by q<sub>max<sub> leading to \\(\Gamma_{i\Delta}\\) = 2π/q<sub>max<sub>. The final result is that if this integrator is configured for unity-gain feedback its bandwidth can be summarised in Eq. 2.
$$ f_{3dB} = \frac{I_{\Delta}}{q_{max}} = f_{osc} \frac{I_{\Delta}}{I_{B}} = \frac{I_{\Delta}}{N V_{RG} C_{gate} } $$
These relations above are needed to point out a defining characteristic of the single-stage ROF which is that the oscillator frequency is directly related to the circuit bandwidth. Moreover in practice it would make sense that the ratio I\tss{\\(\Delta\\)}/I<sub>B<sub> is close to unity to maximise both bandwidth efficiency and minimise the input referred offset due to any difference in f<sub>osc<sub> between the two oscillators. A ratio larger than 1 inherently leads to nonlinearity as V<sub>RG<sub> will become strongly dependent on the dynamic current being switched and therefore vary f<sub>3dB<sub> as a function of input. Instead V<sub>RG<sub> should be well-defined in terms of the biasing current such that it can be estimated using sub-threshold device operation V<sub>RG<sub> = V<sub>th<sub>+η U<sub>T<sub> ln(2I<sub>B<sub>/I<sub>spec<sub>) where V<sub>th<sub>, η, U<sub>T<sub>, and I<sub>spec<sub> are the transistor model parameters for threshold voltage, slope factor, thermal voltage, device specific current respectively[^26]. This formulation allows the nonlinear signal compression to be estimated as \\(\epsilon\\) which is expanded in Eq. 3 to determine an appropriate ratio \\(\Delta\\)=I\tss{\\(\Delta\\)}/I<sub>B<sub> where IC=I<sub>B<sub>/I<sub>spec<sub>. Finally note the desirable property that the open-loop gain is inherently infinite and independent of any operating conditions. Moreover the digital output can virtually drive any type of load without affecting the circuit bandwidth.
$$ \epsilon = \frac{ V_{th} + \eta U_{T} \: ln[ 2 IC (1 + \Delta) ] }{ V_{th} + \eta U_{T} \: ln( 2 IC ) } - 1 $$
## 5 Two-Stage ROF
{{< figure src="/images/tcas2016/TD_L2.svg" title="Figure 4: The compensated two-stage ROF topology which uses the first order structure and introduces a more explicit pole due to the switched current and load capacitor C<sub>L<sub>. Shown are: (a) implementation; and (b) the s-domain equivalent as two ideal integrators in feedback." width="500" >}}
{{< figure src="/images/tcas2016/Bode-Plot.svg" title="Figure 5: Characteristic phase and magnitude response of the two-stage ROF structure with capacitive compensation." width="500" >}}
The two-stage ROF structure is shown in Fig. 4. This provides more degrees of freedom in the design with a small increase in complexity over the single-stage ROF. The main difference here is that a more conventional charge pump now precedes the oscillator and is responsible for the filtering characteristics. By having the digital output drive the capacitor C<sub>L<sub> the TD integrator is both compensated and able to operate at maximum efficiency irrespective of oscillator frequency. The s-domain coefficients are therefore k1 = I\tss{\\(\Delta\\)}/C<sub>L<sub> and k2 = gm<sub>MB<sub>/q<sub>max<sub>. The factor C in Fig. 4 accounts for the total capacitance C<sub>T<sub> on V\tss{P/N} that may attenuate the feedback by defining it as C = C<sub>L<sub>/C<sub>T<sub> and gm<sub>MB<sub> is the transconductance of the biasing transistor M<sub>B<sub>. This means that bandwidth efficiency of the VCO integrator is now boosted by the transistor's sub-threshold slope 1/η U<sub>T<sub>. The requirement of f<sub>osc<sub> in fact becomes relaxed and may actually be smaller than the circuit's bandwidth if multiple phases are used to represent Q in parallel denoted as K.
The impact of processing multiple taps from the ring oscillator is two-fold. First the stability requirement for the VCO pole location to lie outside the circuit bandwidth f<sub>3dB<sub> = k1 /2π generally becomes negligible as it is easy to guarantee k1\textless C K k2. This condition implies that the loop has a phase-margin \textgreater 45\tps{\\(\circ\\)} when the two pole structure is put in unity-gain configuration. Secondly the combined value of Q will in effect have K+1 quantisation levels that due to the capacitive feedback onto V\tss{P/N} presents high frequency quantisation noise with an amplitude of V<sub>DD<sub>/K. Similarly to the previous linearity requirement regarding I\tss{\\(\Delta\\)}/I<sub>B<sub>, K should intentionally be large to obtain linear behaviour of M<sub>B<sub> and the oscillators. Fortunately K does not affect the efficiency or power dissipation of this circuit as the product of K f<sub>osc<sub> is a constant for a fixed current in I<sub>MB<sub>. Instead K influences circuit complexity to some extent. Another benefit of the two-stage configuration is that although the band-limiting capacitor needs to be broken up into K units to accommodate all phases it is an explicit capacitor and unlike the single-stage configuration it does not rely on the precise control/matching of parasitic capacitance to determine the pole location. Moreover charge pump circuits and the associated dynamics have been studied extensively in PLL circuits[^27] and can easily be applied here. That said, it can be concluded that the two-stage ROF should be used in scenarios when the output and bandwidth characteristics need to be precise and the single-stage ROF should be applied when focus lies with performing asynchronous computation with diminished requirements.
$$ H(s) = \frac{k1 k2}{s^2+C k2 s} \cdot e^{-s t_d} $$
The open loop system response with capacitive compensation is characterised by Eq. 4. This is derived using the linearised model and introducing the impact of digital gate delay (t<sub>d<sub>) for further processing Q to the frequency response[^10]. The corresponding Bode plot is shown in Fig. 5. The second order roll-off will assist in rejecting high frequency artefacts due to any approximations made in the digital processing system. It should also be evident from the linearised model that high pass behaviour can be realised with the same feedback but instead taking the output from the digital processing block which is driving the charge-pump circuit.
# 6 Digital Processing using ROFs
From the introduction it is clear that there is large variety of techniques being used to process time domain signals with asynchronous logic. This section will present specific techniques for manipulating the multi-phase PWM signals that can be obtained from the ROF without introducing delay lines. Applying Boolean functions to PWM signals can be divided into two scenarios: coherent and incoherent operation. This relates to the cases when the signals being operated on are the exact same frequency (e.g. different phases of the oscillator) or when they are different frequencies (e.g. when processing the signals D & Q). It will be shown that these two cases lead to significantly different behaviour.
## 7 Coherent Operations
{{< figure src="/images/tcas2016/TDC_1.svg" title="Figure 6: Average PWM output for simple Boolean functions with a coherent input. The output is evaluated with respect to the pulse width of A and the delay \\(\Delta\\)T." width="500" >}}
{{< figure src="/images/tcas2016/TDC_2.svg" title="Figure 7: Average PWM output and the analytical result for a gain of 2x (blue), gain of 4x (green), and the complement of the absolute value for x-0.5 with the exact Boolean operator **B** annotated." width="500" >}}
The coherent operations useful for manipulating the multiple phases output by a single ring oscillator because these delays are relatively well matched with respect to the oscillator period, thereby allowing predictable outputs irrespective of oscillator frequency. These simple operations are summarised in Fig. 6. This visualises the average PWM output Q subject to a PWM input A, the delay \\(\Delta\\)T and a Boolean function **B**. Here A is a periodic function with a normalised periodicity of one. As expected Q is linear with respect to the pulse width x of A. Let A be formally defined in terms of Eq. 5 such that Q can be evaluated as Eq. 6. This calculates the mean value of Q over the period of A denoted as T.
$$ A(\tau,x) =\begin{cases} 1 & \tau (mod\: 1) \: < \:x 0 & \text{otherwise} \end{cases} $$
$$ E[Q(x,\Delta T)] = \int_{0}^{1} \mathbf{B}(A(\tau,x),A(\tau-\Delta T,x)) \: d\tau $$
However most of these operations can be visualised in terms of adding and removing pulses using delayed components of A. For instance using an OR gate with a delay of 0.5T will add an identical pulse at half the period and realise the equivalent 'gain' of 2x and effectively doubling the frequency of A. This example also illustrates that clipping will occur if x exceeds 0.5T as a natural consequence of overflow/saturation. Note that the output of **B** for the AND and OR gates have 3 regions that exhibit saturation, linear dependency, or gain. The interesting aspect here is that the point of clipping can be chosen freely by closely inspecting the region in Fig. 6 for which **B** is always 1. An underflow will occur for a pulse width smaller than c when using an AND gate with a delay of cT and an overflow will occur for a pulse width larger than (1-c) if an OR gate is used with a delay of cT. The clipping regions will not exceed 0.5 unless we combine more phases to realise larger 'gain' factors as illustrated in Fig. 7.
## 8 Incoherent Operations
{{< figure src="/images/tcas2016/TDG_1.svg" title="Figure 8: Average PWM output for simple Boolean functions with incoherent inputs A & B. The output is evaluated with respect to the pulse width of each input." width="500" >}}
{{< figure src="/images/tcas2016/TDG_2.svg" title="Figure 9: The result from applying an AND gate(blue), OR gate (green), and XOR gate (red) to two PWM signals with equal pulse width but are modulated by different frequencies with the analytical polynomial annotated as a function of pulse width x." width="500" >}}
Typically it will be the case that the signals of interest will not have the same frequency which requires us to consider how the two PWM signals A & B interact with one another. The primary interest will still lie with the average or near-DC behaviour of the Boolean function because the ROF is inherently lowpass in response. The main concern is associated with the beat frequency of the two PWM carrier frequencies f<sub>A<sub>-f<sub>B<sub>. This is because this spur needs to lie sufficiently outside of the f<sub>3dB<sub> bandwidth for us to make the approximation that B is uncorrelated with respect to A. This implies that the pulse B can be assumed uniformly distributed with respect to A. The circuit bandwidth will represent the averaging time constant and should ideally not be subject to carrier dependent tones such that a precise output is maintained. The oscillator frequencies are easily perturbed and subject to drift making this assertion quite reasonable in practice. As a result the average output Q due to two PWM signals with pulse width x & y can be calculated using the expression in Eq. 7.
$$ E[Q(x,y)] \approx \int_{0}^{1} \int_{0}^{1} \mathbf{B}(A(\tau,x),B(t-\tau,y)) \: d\tau dt $$
This type of processing uses concepts from stochastic computation \cite{SDSP, sto_cmp} since the two digital signals interact with respect to a probability distribution that is shaped using the Boolean operator. The difference however is that these bitstreams themselves are not stochastic in the large signal sense and they are not clocked by some specific frequency. Instead the bitstreams are intentionally decorrelated by choosing different carrier frequencies. The primitive operations are summarised in Fig. 8 with respect to the PWM signals A and B. In some cases these operations will lead to nonlinear or polynomial behaviour which can be observed in Fig. 9. In addition the inverse of these functions can also be realised by manipulating the feedback and using **B**(Q,R) instead of Q directly where R is the output of a single-stage ROF in unit gain feedback with the input Q but the carrier frequency is doubled to decorrelate R from Q.
# 9 Circuit Implementation
\begin{figure*}
\centering
\includegraphics[width=18cm]{/images/tcas2016/System.svg}
\caption{Detailed transistor level implementation of the second-order ROF structure. Here the digital gates in: (a) implement a difference operator; (b) is the switched current DAC; (c) is the floating differential ring oscillator structure; (d) is the differential delay cell, and (e) is the corresponding buffer that amplifies the oscillator voltage to full swing. All device sizes are shown in (f). }
\label{Fig:TDSys}
\end{figure*}
This particular implementation focuses on achieving robust low-voltage operation and minimising analogue complexity to enable larger multi-channel systems. A commercially available TSMC 65 nm CMOS LP MS RF technology (1P9M 6X1Z1U RDL) was used to develop a lowpass filter that processes the signals from the TD instrumentation circuit in [^30] and illustrates the basic performance characteristics of the ROF structure. The proposed circuit is detailed in Fig. \ref{Fig:TDSys} which can be divided into four sub-blocks: digital control (a), analogue integrator (b), TD integrator (c), and the oscillator stages (d & e).
## 10 Charge Pump
The switches S\tss{A/B/C} control how a reference current I<sub>B<sub> is pumped differentially into nodes V\tss{P/N}. Transistors M\tss{1-2} provide common mode regulation on V\tss{P/N} and mirrors the biasing current into the ring oscillators using M\tss{3-4}. This is extended for multi-phase inputs by operating several charge pumps in parallel. Any resulting voltage difference across V\tss{P/N} injects a differential current into the TD integrator as M\tss{3-4} represent a pseudo-differential pair. Although it is not shown M\tss{3-4} is split up into 5 devices of which two have their drain connected to the opposite polarity which allows us to manipulate the I\tss{\\(\Delta\\)}/I<sub>B<sub> ratio. This leads to a smaller VCO bandwidth and induces more filtering with better linearity. Using high V<sub>th<sub> devices for M\tss{1-4} allows the common mode of V\tss{P/N} to be placed close to 250 mV which leaves enough voltage headroom for the switches and biasing transistors.
{{< figure src="/images/tcas2016/ISF.svg" title="Figure 10: Post-layout simulation results showing to one of the oscillator outputs in a) for reference and the ISF \\(\Gamma_{ig}\\),\\(\Gamma_{io}\\),\\(\Gamma_{ir}\\) for injecting a small signal charge at the virtual ground, oscillator output, and virtual rail nodes." width="500" >}}
## 11 Differential Oscillator
Each oscillator consists of 7 differential delay stages each of which use a cross coupled load resulting in a total of 14 outputs. This structure is based on [^31] to achieve additional supply noise rejection when compared to the conventional ring oscillator. The 5 nA biasing current for each charge pump will lead to sub-threshold operation of all analogue devices which means the oscillator output that swings around V<sub>R<sub> & V<sub>G<sub> is only 100 mVpp with a transition time of 1/(14 f<sub>osc<sub>). Amplifying this output to improve signal transition time with high efficiency is achieved by a buffer that recovers the digital signal integrity and also uses positive feedback provided by M\tss{16-17}. This particular configuration requires some consideration with respect to the the optimal operating conditions of the buffer.
The charge sensitivity for this oscillator is shown in Fig. 10. The ISF has been extracted using using post-layout simulation results. The sensitivities \\(\Gamma_{ig}\\), \\(\Gamma_{ix}\\), and \\(\Gamma_{ir}\\) are evaluated by injecting 1 fC of charge \\(\Delta\\)Q into the nodes V<sub>GP<sub>, V<sub>OP<sub>, V<sub>R<sub> and evaluating the change in phase with respect to having no charge injected. Then \\(\Gamma\\) is characterised by systematically injecting charge at some point in time (t<sub>q<sub>) with respect to the oscillator period and performing normalisation as \\(\Gamma\\)(tq)=2π \\(\Delta\\)φ(t<sub>q<sub>) f<sub>osc<sub>/\\(\Delta\\)Q to obtain the small signal equivalent. This illustrates the phase independent characteristic of \\(\Gamma_{ir}\\) as well as the 100 mV swing of the oscillator. Note that noisy aggressors coupled through \\(\Gamma_{ir}\\) are common to both phase outputs and rejected by the low impedance from M<sub>5<sub>. The behaviour of \\(\Gamma_{ix}\\) is also interesting because when the output is not transitioning the coupling is shorted to either virtual supply and therefore has equivalent sensitivity. However during a transition there is a brief doubling sensitivity as it is being injected into one node instead of being loaded by the differential structure. It should be noted that \\(\Gamma_{ix}\\) is not very representative for modelling how noise couples at the output since many sources will be psuedo-common to all stages (e.g. substrate noise) and the transistor noise is further affected by the operating point of the device itself.
## 12 TDFA unit
The PWM difference operator or time-domain full-adder (TDFA) unit is detailed more clearly in Fig. 11. This shows that a crucial aspect of computing with incoherent TD signals lies with carefully using different signal representations. In this case the nonlinearity that would have been expected from Sec. 8 is negated by using a 1.5 bit ternary encoding. Instead the output Q is linearly dependent on the difference in pulse width of D & Q without distortion. This is important because in-band distortion is not shaped by the filter and any nonlinearity from **B** will propagate to the output including down modulated PWM carrier spurs.
{{< figure src="/images/tcas2016/TDFA.svg" width="500" >}}
{{< figure src="/images/tcas2016/SUM.svg" title="Figure 11: Implementation of the linearised TDFA unit which calculates the difference with respect to the two PWM encoded signals D & Q." width="500" >}}
## 13 Fabricated Prototype
The fabricated device is shown in Fig. 12. This prototype integrates a number of TD sensing systems together where the TD ROF structure is located in the lower left section. This subsystem operates together with an asynchronous analogue to time converter (ATC) such that the measured characterisation reflects system-level performance. Moreover this mitigates any difficulty associated with precisely generating PWM encoded signals off-chip and transmitting them to the filter under low noise conditions. The entire system is 7200 μ m² in size and one ROF is around 30\\(\times\\)40 μ m². Excluding the ATC this filter structure has a 3600 μ m² silicon footprint. There is also a reconfigurable asynchronous DSP block that realises several different coherent Boolean operations intermediate to the ATC and ROFs blocks. In particular there are variable-gain blocks that use the gain function from Sec. 7.
{{< figure src="/images/tcas2016/chip_fab.svg" title="Figure 12: Microphotograph of the fabricated device showing the chip with annotated floor plan in (a) while the P1,M1,M2 layers of the ROF layout are highlighted in (b) (n.b. metal fill omitted for clarity)." width="500" >}}
# 14 Measured Results
{{< figure src="/images/tcas2016/setup.svg" title="Figure 13: Experimental setup used for characterising the ROF filters. Various off-chip instruments are used to supply power and analogue test signals to the device while a Saleae Logic digital acquisition tool samples the PWM output from the chip." width="500" >}}
{{< figure src="/images/tcas2016/pcb.svg" title="Figure 14: Photograph of the custom printed circuit board used for testing the ASIC." width="500" >}}
## 15 Experimental Setup
A custom test platform was developed to characterise the fabricated ASIC using Raspberry Pi 3 development board to provide a graphical interface that automates the low level device control and test routines. This setup is illustrated in Fig. 13 with a photograph of the custom PCB in Fig. 14. The SPI interface allows the hardware to be reconfigured using a configuration register where 3 bits are used to fine tune the biasing current I<sub>B<sub> and another 10 bits are used for variable gain (VG) settings and output control. As shown the ROF signal chain consists of 6 blocks in the following order: ATC, VG, ROF, VG, MUX. The ATC will sense and amplify 5 mVpp differential signals and generate a PWM encoded signal with a 450 kHz carrier frequency. The VG blocks can select additional X1-X4 gain settings using only digital logic. The cascaded ROF provides a 4th order lowpass filter and the MUX gives control over which signals are sent off chip. Not all the TD phases will be sent off chip because of noise and overhead concerns. Instead the MUX will output one phase from the ATC or ROF for preliminary characterisation during asynchronous operation. The digital bit stream appearing at the output is then acquired at 100 MS/s over 1 second using a digital scope.
{{< figure src="/images/tcas2016/spec.svg" title="Figure 15: Spectral power densities of the ROF PWM output with a 4 mVpp 1 kHz differential input signal where the distortion has been annotated in red and the oscillator harmonics are annotated in blue." width="500" >}}
## 16 Filter Characteristics
Taking the Fourier transform of the PWM output gives the spectrum shown in Fig. 15. Here the ROF oscillator frequency is observed at around 35 kHz with the corresponding higher harmonics. The bandwidth of this filter was designed to be 5 kHz which means these aggressors are sufficiently rejected for most applications. In fact the measured filter response in Fig. 16 shows the cascaded ROF will reject these harmonics by more than 50 dB. More practically, when the output of the ROF output needs to be sampled without the interference of such harmonics, this structure can easily be transformed into an oversampling TDC that decimates the PWM signal and filters out of band components [^17][^30]. This particular setup uses a 5.2 nA biasing current which leads to the charge-pump pole being precisely situated at the 5 kHz. Because the VCO pole location suffers from increased variability it is intentionally placed at twice the charge-pump cut-off frequency. It is evident from Fig. 16 that verifying the post-fabrication pole position and the corresponding variance remains challenging. If necessary this pole location can be calibrated using established techniques such as trimming M\tss{3-4} or introducing a digitally-switched capacitive load [^32] at the cost of increasing circuit complexity.
## 17 Linearity
Using a 1 kHz tone, the linearity characteristics are shown in Fig. 17. It is important to note that the use of an on-chip ATC implies that the distortion also includes nonlinearity from the amplifying ATC. The signal processing chain can accept a maximum input 4 mVpp under before the ATC feedback loop starts to overload the asynchronous \\(\Delta\Sigma\\) modulator. These measurements show that a maximum total harmonic distortion (THD) and spurious-free dynamic range SFDR of 53 dB is achievable for a 0.6 mVpp input amplitude. The noise floor is slightly higher than -80 dB and calculating the integrated noise over 10 kHz indicated that the maximum SNR is 55 dB for a 4 mVpp input signal that has a THD of 44 dB. In order to minimise the impact of ATC nonlinearity a 2x VG setting is used during this test such that the ATC output is at -4 dB of the full range but the ROF processes signals near the full input dynamic range.
## 18 Supply Noise Sensitivity
The PSRR has been tested using a 10 mVpp tone at different frequencies while the ATC input was shorted together. The result is presented in Fig. 18. This perturbation induces output tones at -55 dB of the full range which when referred to the 4 mV input range implies a PSRR of 63 dB. This level of supply coupling is difficult to improve because of this measurement setup and the ADC nature of the ATC. The implementation of the ATC uses V<sub>DD<sub> as reference voltage such that it is coupled asymmetrically to analogue nodes degrading supply rejection even in differential configurations. Although the impact of using the differential oscillator structure is not well represented, any further degradation in PSRR is prevented and the input referred noise-floor is not corrupted by supply noise coupled from the digital switching. Moreover this figure should be very representative for larger scale or multi channel systems as this implementation only uses a 2.5 pF decoupling capacitor for the shared 0.5 V supply. It can thus be expected that using more decoupling capacitance or separating the supplies will further improve this figure at the cost of allocating more resources.
{{< figure src="/images/tcas2016/measure.svg" title="Figure 16: Measured filter response due to a 4 mVpp differential sinusoidal input at frequencies from 1 kHz to 100 kHz." width="500" >}}
{{< figure src="/images/tcas2016/THD1.svg" title="Figure 17: Measured harmonics due to a 1 kHz differential input tone with increasing input amplitudes. The spectral power of the output tones are calculated with respect to the maximum output dynamic range." width="500" >}}
{{< figure src="/images/tcas2016/PSRR.svg" title="Figure 18: Measured PSRR of the entire system due to a 10 mVpp sinusoidal signal on top of a 0.5 V bias driving the system's V<sub>DD<sub> at frequencies from 50 Hz to 60 kHz." width="500" >}}
## 19 Performance Summary
Table 1: System Characteristics and Comparison with State-of-the-Art
| Parameter [unit] |\textbf{\small{This Work}} | [^13](^\ddagger) | [^6] | [^10] | [^17]\cite{1} | [^20] | [^34] |
|----|----|----|----|----|----|----|----|
| Tech.[nm] | **65** | 130 | 90 | 65 | 40 | 130 | 180 |
| Modality | **Time** | Time | Time | Time | Time | Volt. | Volt. |
| Type | \textbf{TD-IIR} | TD-FIR | TD-IIR | TD-IIR | TD-(\Delta\Sigma) | GmC-(\Delta\Sigma) | GmC-IIR |
| Order | **4** | 16 | 4 | 4 | 2 | 1 | 5 |
| Supply-V[V] | **0.5** | 1 | 0.55 | 0.6 | 0.9 | 0.25 | 0.5 |
| Supply-I[A] | **146 n** | 0.46 m | 5.27 m | 43.7 m | 2.8 m | 72 n | 1.2 m |
| Bandwidth[Hz] | **5 k** | 70 k | 7 M | 70 M | 40 M | 1.9 k | 135 k |
| DR[dB] | \textbf{55(\dagger)} | 50 | 61 | 58 | 61 | 58 | 61 |
| Area[mm²] | **0.004** | 5 | 0.29 | 0.38 | 0.017 | 0.08(^\star) | 0.29 |
| FOM[fJ/pole] | **8.17** | 1299 | 92 | 118 | 28 | 12 | 520 |
{\thanks{\\(\dagger\\) using a 10 kHz integrated noise figure, \\(^\ddagger\\) performance quote from full system asynchronous PWM operation, \\(^\star\\) uses external passive components.}}
The filter performance is summarized in Table 1. The circuit power consumption has been measured to be 73 nW of which simulation results indicate 16 nW is dissipated in the charge pump plus oscillator circuits and 21 nW is dissipated by the biasing circuits. The remaining 36 nW is due to digital control and PWM switching. One of these contributions comes from applying digital feedback onto the capacitor C<sub>L<sub> which is 560 fF. This is expected to dissipate power according to f<sub>osc<sub>C<sub>L<sub>V²<sub>DD<sub> or in this particular case 3 nW. This later component can be become substantial if the supply voltage is not small enough or if very low-noise performance is required since in-band noise performance is directly dependent on C<sub>L<sub>. However when compared to other works the achieved performance is comparable and can operate with good energy efficiency. This is evaluated using the FOM from [^34] which is defined in Eq. 8 using the system power (P<sub>sys<sub>) and the number of poles (N<sub>poles<sub>) to normalise performance. The most substantial gain from the ROF filter is that the reduced complexity leads to a very compact implementation that is not only considerably smaller than state-of-the-art but also more capable of reconfigurable functionality. Based on KT/C relations we may expect all-analogue processing to be more power efficient in a noise limited scenario because such systems can take advantage of the transistor sub-threshold slope. This drawback is similar to the noise performance from all-digital PLLs in comparison to sub-sampling PLLs. However the time-domain circuits will allow far superior linearity & dynamic range during ultra low voltage operation which the all-analogue systems cannot achieve. The 65 nm technology primarily influences the impact of excess digital switching from the asynchronous logic/overhead. Using an advanced CMOS technology allows most of the power to be dissipated in the oscillator and enables more efficient performance.
$$ FOM = \frac{P_{sys}}{N_{poles} f_{3dB} DR} $$
# 20 Conclusion
This work presents the first system to explicitly deliver IIR or analogue filtering for PWM encoded signals asynchronously using standard CMOS technology. The implementation and model of a low-complexity oscillator based filter is detailed to complement existing FIR and delay line based techniques for clockless processing of time-encoded signals. The proposed topology can deliver 53 dB SFDR with a maximum SNR of 55 dB while operating at 0.5 V. The extensive use of digital logic allows highly flexible and reconfigurable oscillator based computing for future ultra-low-power systems in nanometre CMOS. Measured results demonstrate 8.17 fJ/pole efficiency for the 5 kHz bandwidth and reports an area requirement of 0.004 mm² . In fact unlike prior art this topology is substantially more efficient and compact at processing asynchronous TD signals that have reduced bandwidths or require low frequency filtering than state-of-the-art. Moreover the ROF primitives and digital processing techniques presented here can be directly applied to ultra-low-power \\(\Delta\Sigma\\) modulators and mixed signal systems due to its simplicity and affinity for low voltage mixed signal operation.
# 21 Acknowledgement
The authors would like to thank Dr. Pantelis Georgiou, and the Europractice Advanced Technology Stimulation programme for providing access to the TSMC 65nm technology. The authors additionally thank Michal Maslik for the helpful comments and assistance with improving this manuscript.
# Refernces:
[^1]: I.L. Markov, ''Limits on fundamental limits to computation,'' Nature, vol. 512, pp. 147--154, August 2014. [Online]: http://dx.doi.org/10.1038/nature13570
[^2]: R.Sarpeshkar, ''Analog versus digital: Extrapolating from electronics to neurobiology,'' Neural Computation, vol.10, no.7, pp. 1601--1638, Oct 1998. [Online]: http://dx.doi.org/10.1162/089976698300017052
[^3]: N.Guo etal., ''Energy-efficient hybrid analog/digital approximate computation in continuous time,'' IEEE Journal of Solid-State Circuits, vol.51, no.7, pp. 1514--1524, July 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2543729
[^4]: M.Verhelst and A.Bahai, ''Where analog meets digital: Analog-to-information conversion and beyond,'' IEEE Solid-State Circuits Magazine, vol.7, no.3, pp. 67--80, September 2015. [Online]: http://dx.doi.org/10.1109/MSSC.2015.2442394
[^5]: Y.Chen, E.Yao, and A.Basu, ''A 128-channel extreme learning machine-based neural decoder for brain machine interfaces,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.3, pp. 679--692, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2483618
[^6]: B.Drost, M.Talegaonkar, and P.K. Hanumolu, ''Analog filter design using ring oscillator integrators,'' IEEE Journal of Solid-State Circuits, vol.47, no.12, pp. 3120--3129, Dec 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2225738
[^7]: G.W. Roberts and M.Ali-Bakhshian, ''A brief introduction to time-to-digital and digital-to-time converters,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.57, no.3, pp. 153--157, March 2010. [Online]: http://dx.doi.org/10.1109/TCSII.2010.2043382
[^8]: T.Anand, K.A.A. Makinwa, and P.K. Hanumolu, ''A vco based highly digital temperature sensor with 0.034 $^\circ$C/mV supply sensitivity,'' IEEE Journal of Solid-State Circuits, vol.51, no.11, pp. 2651--2663, Nov 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2598765
[^9]: V.Pourahmad etal., ''Nonboolean pattern recognition using chains of coupled cmos oscillators as discriminant circuits,'' IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol.3, pp. 1--9, Dec 2017. [Online]: http://dx.doi.org/10.1109/JXCDC.2017.2654300
[^10]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational amplifiers and their application to continuous-time filters in nanoscale cmos,'' IEEE Journal of Solid-State Circuits, vol.49, no.12, pp. 2758--2772, Dec 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2354641
[^11]: S.Zheng and H.C. Luong, ''A wcdma/wlan digital polar transmitter with low-noise adpll, wideband pm/am modulator, and linearized pa,'' IEEE Journal of Solid-State Circuits, vol.50, no.7, pp. 1645--1656, July 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2413846
[^12]: P.Lu, Y.Wu, and P.Andreani, ''A 2.2-ps two-dimensional gated-vernier time-to-digital converter with digital calibration,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.63, no.11, pp. 1019--1023, Nov 2016. [Online]: http://dx.doi.org/10.1109/TCSII.2016.2548218
[^13]: C.Vezyrtzis etal., ''A flexible, event-driven digital filter with frequency response independent of input sample rate,'' IEEE Journal of Solid-State Circuits, vol.49, no.10, pp. 2292--2304, Oct 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2336532
[^14]: H.J. Kwon etal., ''Analysis of an open-loop time amplifier with a time gain determined by the ratio of bias current,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.61, no.7, pp. 481--485, July 2014. [Online]: http://dx.doi.org/10.1109/TCSII.2014.2328800
[^15]: W.Yu, K.Kim, and S.Cho, ''A 0.22 ps rms integrated noise 15 mhz bandwidth fourth-order $\Delta \Sigma$ time-to-digital converter using time-domain error-feedback filter,'' IEEE Journal of Solid-State Circuits, vol.50, no.5, pp. 1251--1262, May 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2399673
[^16]: W.Jiang etal., ''A ±50 mV linear-input-range vco-based neural-recording front-end with digital nonlinearity correction,'' IEEE Journal of Solid-State Circuits, vol.52, no.1, pp. 173--184, Jan 2017. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2624989
[^17]: M.Hovin etal., ''Delta-sigma modulators using frequency-modulated intermediate values,'' IEEE Journal of Solid-State Circuits, vol.32, no.1, pp. 13--22, Jan 1997. [Online]: http://dx.doi.org/10.1109/4.553171
[^18]: Y.Liu, J.L. Pereira, and T.G. Constandinou, ''Clockless continuous-time neural spike sorting: Method, implementation and evaluation,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2016, pp. 538--541. [Online]: http://dx.doi.org/10.1109/ISCAS.2016.7527296
[^19]: M.Yang etal., ''A 0.5 v 55 $\mu$w 64$ imes$2 channel binaural silicon cochlea for event-driven stereo-audio sensing,'' IEEE Journal of Solid-State Circuits, vol.51, no.11, pp. 2554--2569, Nov 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2604285
[^20]: L.H.C. Ferreira and S.R. Sonkusale, ''A 0.25-V 28-nW 58-dB dynamic range asynchronous delta sigma modulator in 130-nm digital cmos process,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.23, no.5, pp. 926--934, May 2015. [Online]: http://dx.doi.org/10.1109/TVLSI.2014.2330698
[^21]: R.Mohan etal., ''A 0.6 V, 0.015-mm$^2$, time-based ecg readout for ambulatory applications in 40 nm cmos,'' IEEE Journal of Solid-State Circuits, vol.52, no.1, pp. 298--308, Jan 2017. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2615320
[^22]: S.Patil etal., ''A 3-10 fJ/conv-step error-shaping alias-free continuous-time adc,'' IEEE Journal of Solid-State Circuits, vol.51, no.4, pp. 908--918, April 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2519396
[^23]: J.P. Caram, J.Galloway, and J.S. Kenney, ''Harmonic ring oscillator time-to-digital converter,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2015, pp. 161--164. [Online]: http://dx.doi.org/10.1109/ISCAS.2015.7168595
[^24]: W.-H. Ki, ''Signal flow graph analysis of feedback amplifiers,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.47, no.6, pp. 926--933, Jun 2000. [Online]: http://dx.doi.org/10.1109/81.852948
[^25]: A.Hajimiri, S.Limotyrakis, and T.Lee, ''Phase noise in multi-gigahertz cmos ring oscillators,'' in IEEE Proceedings of the Custom Integrated Circuits Conference, May 1998, pp. 49--52. [Online]: http://dx.doi.org/10.1109/CICC.1998.694905
[^26]: ibitemQ-basedC.C. Enz and E.A. Vittoz, Charge-based MOS transistor modeling: the EKV model for low-power AND RF IC design.\hskip 1em plus 0.5em minus 0.4em elax John Wiley & Sons, August 2006. [Online]: http://eu.wiley.com/WileyCDA/WileyTitle/productCd-0470855452.html
[^27]: A.Homayoun and B.Razavi, ''On the stability of charge-pump phase-locked loops,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.63, no.6, pp. 741--750, June 2016. [Online]: http://dx.doi.org/10.1109/TCSI.2016.2537823
[^28]: D.Jenson and M.Riedel, ''A deterministic approach to stochastic computation,'' in IEEE Proceedings of the International Conference on Computer-Aided Design, Nov 2016, pp. 102:1--102:8. [Online]: http://dx.doi.org/10.1145/2966986.2966988
[^29]: M.Alawad and m.lin, ''Survey of stochastic-based computation paradigms,'' IEEE Transactions on Emerging Topics in Computing, vol.PP, no.99, pp. 1--1, 2016. [Online]: http://dx.doi.org/10.1109/TETC.2016.2598726
[^30]: L.B. Leene and T.G. Constandinou, ''A 0.5V time-domain instrumentation circuit with clocked and unclocked $\Delta\Sigma$ operation,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2017, pp. 2619--2622.
[^31]: W.S.T. Yan and H.C. Luong, ''A 900-MHz cmos low-phase-noise voltage-controlled ring oscillator,'' IEEE Transactions on Circuits and Systems---Part II: Analog and Digital Signal Processing, vol.48, no.2, pp. 216--221, Feb 2001. [Online]: http://dx.doi.org/10.1109/82.917794
[^32]: Y.Zhang etal., ''A 0.35-0.5 V 18-152 MHz digitally controlled relaxation oscillator with adaptive threshold calibration in 65 nm cmos,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.62, no.8, pp. 736--740, Aug 2015. [Online]: http://dx.doi.org/10.1109/TCSII.2015.2433531
[^33]: X.Xing and G.G.E. Gielen, ''A 42 fj/step-fom two-step vco-based delta-sigma adc in 40 nm cmos,'' IEEE Journal of Solid-State Circuits, vol.50, no.3, pp. 714--723, March 2015.
[^34]: P.Khumsat and A.Worapishet, ''A 0.5-V R-MOSFET-C filter design using subthreshold r-mosfet resistors and otas with cross-forward common-mode cancellation technique,'' IEEE Journal of Solid-State Circuits, vol.47, no.11, pp. 2751--2762, Nov 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2216708

257
content/publications/2018/a-0-006-mm-tsqrd-1-2-rmu-w-analogue-to-time-converter-for-asynchronous-bio-sensors.md Normal file
View File

@ -0,0 +1,257 @@
---
title: "A 0.006 mm2 1.2 uW Analog-to-Time Converter for Asynchronous Bio-Sensors"
date: 2018-07-23T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
- publication
- CMOS
- circuits
- data-converter
- biomedical
---
Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
This work presents a low-power analogue-to-time converter (ATC) for integrated bio-sensors. The proposed circuit facilitates the direct conversion of electrode biopotential recordings into time-encoded digital pulses with high efficiency without prior signal amplification. This approach reduces the circuit complexity for multi-channel instrumentation systems and allows asynchronous digital control to maximise the potential power savings during sensor inactivity. A prototype fabricated using a 65 nm CMOS technology is demonstrated with measured characteristics. Experimental results show an input-referred noise figure of 3.8 μ V<sub>rms<sub> for a 11 kHz signal bandwidth while dissipating 1.2 μ W from a 0.5 V supply and occupying 60\\(\times\\)80 μ m² silicon area. This compact configuration is enabled by the proposed asynchronous readout that shapes the mismatch components arising from the multi-bit quantiser and the use of capacitive feedback.
# 2 Introduction
The current trend in sensor systems is to integrate many analogue sensors together with larger digital systems to provide smart data collection for miniaturised wearables or low cost system-in-package (SiP) electronics [^2][^1]. The digital oriented design flow of these systems compels designers to look for sensor interfaces that accommodate the trends in CMOS technology scaling and smaller supply voltages for digital power reduction. For this reason many data converters and sensing circuits have utilised voltage controlled oscillators (VCO) to convert analogue signals into a periodic digital waveform where information is encoded by its frequency. This type of conversion is highly applicable at every technology node and the time encoded output is considerably more robust than the voltage output of conventional amplifiers when considering supply noise and the process, voltage and temperature (PVT) variations. The time-domain concept has seen extensive use in recent publications because the voltage to frequency conversion provides high gain and exceptional dynamic range [^5][^4][^3] that can also accommodate conventional chopper techniques [^6][^7].
The conversion from analogue to frequency is not the only means by which analogue circuits can encode signals in the time-domain. It is well known that both synchronous [^8] and asynchronous [^9] oversampling modulators will generate a pulse-width-modulated (PWM) output bitstream. However these realisations conventionally do not perform integration in the time-domain and instead use charge pumps that suffer from typical drawbacks in advanced CMOS technologies such as gain degradation and limited voltage swing [^10]. In contrast the modulating characteristic of oscillators can negate component mismatch in any proceeding digital-to-analogue conversion since the digital output inherently provides data-weighted averaging [^5].
{{< figure src="/images/jssc2018/obi.svg" title="Figure 1: The proposed Analogue-to-Time Converter (ATC) that provides closed loop conversion of an analogue input voltage into an asynchronous multi-bit digital data stream." width="500" >}}
In order to retain high performance and minimise the requirement of ideal analogue components, time-based systems should be designed in a fashion where only small error signals are processed in the analogue domain with constrained linearity. Signals with large dynamics should be time-encoded and manipulated with robust digital logic. The proposed ATC realisation that follows this concept is shown in Fig. 1. This topology presents an asynchronous delta-sigma modulator (ADSM) that accumulates a phase difference between two oscillators to realise time-based integration and utilises capacitive feedback to linearise the conversion.
Here the sensor's voltage fluctuations on V<sub>IN<sub> modulate the pulse width of the PWM signal generated by the phase detector by combining multiple phases from each stage in the oscillator. In this fashion the output bit-stream D<sub>OUT<sub> can in effect resolve finer quantisation levels. In contrast to prior oscillator-based systems that are clocked, the asynchronous operation proposed here enables high-speed signal processing with oscillator-based filters [^11] or a continuous-time digital core [^12]. Both avoid the need for a high speed clock when processing a large number of recording channels and can therefore enable substantial power saving.
This work is a first step towards realising a sensor system that fundamentally only processes using time-encoded signals and can potentially operate using a supply voltage of only several hundred millivolts since the circuit can accurately convert millivolt level signals without prior analogue signal amplification [^14][^13]. This is because oscillator based integrators can operate with a voltage headroom close to transistor threshold voltage without diminishing loop gain or dynamic range. This advantage is not diminished by practical issues and large common-mode interference or electrode offset can be rejected because the sensor input is capacitively coupled to the main feedback loop. There are a number of established techniques such as using a DC servo loop or performing ripple rejection that prevent these issues from degrading circuit performance [^15]. This means that the voltage appearing at V<sub>X<sub> well controlled through feedback and that the amplifier can maximise power-efficiency-factor (PEF) [^16] without requiring additional voltage overhead to accommodate voltage fluctuation at its input.
This paper presents the implementation and modelling aspects of the oscillator based ATC using the following organisation: Section 3 details the instrumentation topology and Section 4 describes the corresponding transistor level implementation, Section 9 discusses the impact of technology and mismatch parameters of this circuit, Section 12 presents the measured results of a fabricated prototype, and Section 13 concludes this work.
# 3 Concept and ATC Architecture
This section introduces the operating principle and circuit dynamics of the proposed instrumentation system that is used to sense intra-cortical neural activity using a conventional electrode instrumentation setup. Such a scenario would record activity in-vivo or ex-vivo from the 1 Hz to 10 kHz frequency band where the signals are no larger than a few millivolts in amplitude[^17]. The circuit sensitivity must match the noise characteristics of the electrode or biological tissue and target a noise floor of around 50 nV/\rtxt{Hz}[^18]. These sensitivity conditions require the circuit dissipate several microamps and easily leads to a circuit bandwidth much larger than 10 kHz. For this reason this ATC will provide gain for a bandwidth exceeding 10 kHz since it is more resource effective to rely on proceeding processing stages to perform filtering when necessary.
{{< figure src="/images/jssc2018/obi_sys.svg" width="500" >}}
{{< figure src="/images/jssc2018/obi_blk.svg" title="Figure 2: Detailed system topology in a) and equivalent analytical model in b) of the proposed chopper stabilised ATC." width="500" >}}
A block diagram of the proposed architecture is detailed in Fig. 2a. For clarity, this shows the single ended equivalent of the fully differential circuit that was implemented. The difference in potential between two electrode inputs V<sub>R<sub> & V<sub>IN<sub> is chopped at the chopper frequency f<sub>chp<sub> to generate a up-modulated voltage waveform that couples the input onto V<sub>X<sub> through C<sub>I<sub>. The essential mechanism here is that signals appearing on V<sub>X<sub> induce a current that feeds into two oscillators with different polarities after being demodulated. This current forces the oscillators accumulate a relative phase difference because the phase is dependent on the integral of injected current [^19]. This phase difference is then evaluated for each oscillator tap using XOR logic to yield multiple time-encoded PWM signals that can also be chopped using digital logic. The resulting digital signal is capacitively coupled onto V<sub>X<sub> in parallel to close the loop. This is the main signal amplifying path that realises a first-order asynchronous ΔΣ modulator and this sense using N phase detectors in parallel represents asynchronous quantization of the phase difference with a resolution of log<sub>2<sub>(1+N) bits. Using this interpretation we can construct the corresponding analytical model that is shown in Fig. 2b and will assist in deducing the design's parameter dependencies.
$$ H(s) = \frac{ 1 }{ s / k_1 + N f } \approx \frac{1}{s\cdot \frac{N C_{gate} V_{RG}}{Gm}+\frac{C_F}{C_I}\frac{C_U}{C_U+\:\:\text{\makebox[-3pt][l]{\\(\nearrow\\)}}C_G/N}} $$
$$ f = {\frac{C_F}{C_{I}+C_{F}}} \cdot \frac{N C_{U}}{C_{F}+N C_{U}+ \text{\makebox[-3pt][l]{\\(\nearrow\\)}}C_{G}} $$
First the expression in Eq. 1 can be derived to characterise the signal amplifying loop. The feedback factor \\(f\\) evaluated in Eq. 2 corresponds to the capacitive coupling of a particular PWM phase Q on to V<sub>X<sub> with respect to the capacitors C<sub>I<sub>, C<sub>F<sub>, C<sub>G<sub>, C<sub>U<sub>. In this case C<sub>G<sub> can be digitally tuned to provide varying gain settings (41-53 dB). The oscillator's integration factor k<sub>1<sub> is derived by evaluating the impulse sensitivity function (ISF). The ISF captures how the oscillator phase is affected as a function of charge being injected into the virtual supply of the oscillator V<sub>R<sub> [^19]. Following the derivation for Eq. 2 in [^11] this factor can be assumed constant and is simply dependent on the transconductance Gm, loading capacitance of each delay stage C<sub>gate<sub>, and the voltage across the oscillator V<sub>RG<sub> such that k<sub>1<sub>=Gm/(N C<sub>gate<sub> V<sub>RG<sub>).
The second control loop is used to reject near-DC aggressors that will appear at the input of the main transconductor. Chopping will prevent the input-referred noise profile from being corrupted by flicker noise but in turn several large tones will appear at harmonics of f<sub>chp<sub> because off-set is being up-modulated. Moreover because this structure is not providing narrowband amplification the feedback must actively suppress these tones to avoid the output from being saturated and distorted. These components are integrated with a gain of approximately A<sub>ripple<sub>=k<sub>1<sub>/f<sub>chp<sub> which induces a 90\\(^\circ\\) phase shift. The phase-shift can be corrected for by using the chopper clock that is delayed by 1/4<sup>th<sup> of the period when demodulating Q to recover the off-set. The flicker rejection further depends on the transfer function F(s) which represents how the recovered signal is smoothed and fed back onto V<sub>X<sub>. Using a charge pump in addition to the pseudo-resistor R<sub>P<sub> will yield an expression for F(s) according to Eq. 3 where C<sub>L<sub> and I\tss{Δ} represent the main integration capacitor and charge pump bias current respectively. This is also shown in Fig. 2.
$$ F(s) = \frac{N I_{\Delta}}{s (C_{L} C_{I} R_{P} s + C_{L} + C_{I})} $$
Combining F(s) and A<sub>ripple<sub> will then predict how the noise aggressors at V<sub>x<sub> are removed. The frequency dependent response in Fig. 3 evaluates this control mechanism at different points in the loop using the following implemented circuit parameters: N=5, f<sub>chp<sub>=75 kHz, C<sub>I<sub>=288 fF, C<sub>G<sub>=69 fF, C<sub>F<sub>=C<sub>U<sub>=14 fF, R<sub>P<sub>=100 MΩ, C<sub>L<sub>=1.6 pF, I\tss{Δ}=5 nA. This shows the influence of noise at the input (e²<sub>flk<sub>) with respect to the ripple at the ATC output and the fluctuations on V<sub>X<sub> as a function of frequency. First notice the increased chopper frequency enables this circuit to increase its bandwidth and reject more of the low-frequency band including common-mode signals that asymmetrically couple onto V<sub>X<sub>. In addition the second order low-pass characteristic provides increased rejection of the chopper and oscillator tones such that the two control loops operate in isolation. A known drawback of increasing f<sub>chp<sub> is the reduction in input impedance but as shown in Sec. 10 this reduction can be mitigated with technology scaling and using a smaller value for C<sub>I<sub>.
{{< figure src="/images/jssc2018/noise_tf.svg" title="Figure 3: The closed loop response of the flicker rejection loop due to input-referred noise e²<sub>flk<sub> evaluated with respect to the ripple magnitude seen at Q (solid), the feedback seen at V<sub>X<sub> (dotted), and the open loop response F(s)\\(\cdot\\)A<sub>ripple<sub> (dashed)." width="500" >}}
Given these dynamics there is still important distinction to be made with regards to the rate of information seen at the output and the 3 dB bandwidth for signal amplification that in this case is the product of \\(f\\) k<sub>1<sub>\\(\approx\\)250 kHz. The digital output will encode an effective number of bits (ENOB) that relates to the ATC's precision (i.e. SNDR) and presents pulse width information of every cycle that in this case is oversampled by N parallel phases. However for one phase the entropy rate can be estimated in terms of f<sub>osc<sub> (SNDR-1.76)/6.02. This highlights an important motivation for time-domain processing since this information rate may easily be 10\\(\times\\) larger than a clocked digital bit-stream that maximally yields 1 bit per clock cycle. Optimistically this implies that time-domain techniques achieve a proportional boost in power efficiency since the digital power dissipation is a function of f<sub>osc<sub> even though a higher rate of information is being processed. For the latter to hold we must require the analogue and oscillator sub-blocks to operate with negligible power budget.
# 4 Circuit Implementation
{{< figure src="/images/jssc2018/obi_sch.svg" title="Figure 4: The transistor level implementation of the ATC circuit in Fig. 2a. Here the complementary structure in a) represents the main transconductor; b) represents the pseudo-differential oscillator where each delay cell is shown in c); The flicker rejection stage is shown in d) where only the grey section is replicated for each phase. Note that all devices have their body connected to the corresponding supplies with the exception of M\tss{5-8} which have the body connected to the drain of M<sub>9<sub>. Furthermore M\tss{13-16} and M\tss{21-22} their body connected to V<sub>R<sub> and either terminal of C<sub>L<sub> respectively." width="500" >}}
The transistor schematic for the proposed ATC is presented in Fig. 4 and the sizing of each device is listed in Table 1. This circuit can be segmented into four parts corresponding to the transconductor, oscillator, delay stage, and flicker rejection circuit. Each sub-block, including the capacitor array, will be described below. This configuration uses two bias voltages V<sub>BN<sub> & V<sub>BP<sub> to source the annotated drain currents. Both of these voltages are derived on-chip using a simple current mirror structure and a 1 μ A off-chip reference. Furthermore an external reference voltage V<sub>C<sub> is used to control the common mode voltage of V<sub>R<sub> that is placed at V<sub>DD<sub>/2. Note that the 65 nm technology used here provides transistors that can be configured with 150 mV (lvt), 250 mV (vt), and 350 mV (hvt) threshold voltages (V<sub>TH<sub>). The lvt option is used exclusively to reduce the supply voltage to 0.5 V with the exception of M\tss{23-24} which use a 250 mV threshold.
Table 1: Device Sizing in micrometers with the labels from Fig. 4
| Device | Size (W/L) | Device | Size (W/L) |
|----|----|----|----|
| M<sub>0<sub> | 26/5 | M\tss{15-16} | 0.2/2.5 |
| M\tss{1-2} | 16/0.25 | M\tss{17-18} | 2/5 |
| M\tss{3-4} | 2/1 | M\tss{19-20} | 10/0.2 |
| M\tss{5-6} | 4/0.5 | M\tss{21-22} | 1.6/0.4 |
| M\tss{7-8} | 0.8/1.4 | M\tss{23-24} | 0.96/4 |
| M<sub>9<sub> | 32/0.1 | Logic | 0.3/0.1 |
| M<sub>10<sub> | 6/5 | Switch<sub>CHP<sub> | 1/0.1 (P<sub>type<sub>) |
| M\tss{11-12} | 1.5/2.4 | Switch<sub>X<sub> | 1/0.2 (N<sub>type<sub>) |
| M\tss{13-14} | 2.3/2.5 | C<sub>L<sub> | 21/21 |
## 5 Low-Noise Transconductor
The complementary style transconductor (Fig. 4a) is adopted from [^20] to exploit two aspects of oscillator based integration. The first is that the operating conditions and transistor characteristics do not influence the loop gain of the time-based integrator but rather effect the noise characteristics which are already improved due to current recycling. Secondly the voltage fluctuation across V<sub>X<sub> & V<sub>S<sub> is negligible particularly if all transistors in the Gm cell and oscillator are in sub-threshold operation. This implies that the circuit can operate reliably with a narrow V<sub>DS<sub> margin for each transistor since the gate voltage V<sub>X<sub> is carefully controlled in closed loop and there is little concern for instability. The self-biasing cascodes M<sub>3,6<sub> biases each input pair with a V<sub>DS<sub> that is highly correlated with the threshold voltage and provides abundant dummy devices to improve matching. The cascodes also reduce the parasitic gate capacitance of the transconductor by reducing the Miller effect that may otherwise lead to increased noise.
Achieving good noise performance for this configuration relies on minimising the drain current noise from each transistor in the oscillator when referred to the input[^7]. As the ratio I<sub>M10<sub>/I<sub>M0<sub> is reduced the NEF of this circuit will asymptotically decrease to the optimal value for this topology (i.e. η\rtxt{2})[^21]. On the other hand I<sub>M10<sub> controls the oscillation frequency which must be sufficiently large such that the oscillator harmonics lie out of band similar to the chopper harmonics.
The lack of filtering requirements allows the asynchronous implementation to chose a large f<sub>osc<sub> by reducing C<sub>gate<sub> such that any intermodulation products with f<sub>chp<sub> do not fall in-band [^22] and the circuit size is minimised. When using this configuration as a clocked ΔΣ modulator[^23] this freedom is lost because k<sub>1<sub> must be directly related to the oversampling ratio. If the system can afford a fast oversampling clock f<sub>osc<sub> can still be large but it would be more effective to chose f<sub>osc<sub> close to the Nyquist frequency such that the harmonics of f<sub>osc<sub> can be removed reliably during decimation as they have already be shaped by the loop-filter. This circuit also constrains the minimum value for N due to the limited linearity of the transconductor for a given input range. This is because the ratio 2V<sub>DD<sub> \\(f\\)/(N+1) determines the maximum peak-to-peak amplitude of the error signal seen at V<sub>X<sub>. Fortunately for high-gain applications \\(f\\) is small resulting in sub-millivolt signal at V<sub>X<sub> and therefore high linearity can be achieved while using just a few phases in parallel.
## 6 Pseudo-Differential Oscillator
The main feature of the oscillators (Fig. 4b) used by this ATC is that it uses differential logic and the delay stage (Fig. 4c) is biased around the middle of the supply making the digital buffers for phase detection more power efficient. The corresponding advantages are best contrasted with a simple inverter delay cell that uses a capacitive load to ground. First the inverter based implementation would experience voltage spikes on V<sub>R<sub> due to discontinuous conduction of current but would also contaminate the ground with the AC current pulses. The configuration adopted from [^24] exhibits continuous charging & discharging currents that can be confined within the virtual supply nodes V<sub>G<sub>/V<sub>R<sub>. Moreover using switching transistors that are several μ m² in size to load for the preceding gate reduces the sensitivity to process variation with smaller area requirements since the transistor gate capacitance achieves a higher density than poly-poly or metal-oxide-metal (MOM) capacitors.
## 7 Flicker Rejection Stage
The flicker removal circuit (Fig. 4d) biases the input of the transconductor by feeding back common mode and differential mode signals using a cross coupled load to enable low voltage operation without an additional common-mode-feedback circuit[^20]. The differential feedback provides flicker cancellation by demodulating the digital output using a switched current DAC that integrates on C<sub>L<sub> which is a large vertical metal-insulator-metal (MIM) capacitor placed over the analogue circuitry. The diode connected devices M\tss{21-22} represent pseudo-resistors of 100 MΩ that provide a resistive path to V<sub>X<sub> and further smooths high frequency tones from f<sub>chp<sub> and f<sub>osc<sub>. A significant variation in resistive value is inherently expected but it is important to note that it does not influence the signal amplifying path and the non-dominant poles are far away from the 8 kHz bandwidth of F(s) in Eq. 3 by virtue of not using a second analogue integrator that may compromise stability. The common mode feedback regulates V<sub>R<sub> with respect to V<sub>C<sub> by biasing the common mode of V<sub>X<sub>. For this loop the gain arises from transconductance ratio gm\tss{M19-M20}/gm\tss{M23-M24} together with the drain resistance ratio rds<sub>M10<sub>/(rds<sub>M0<sub>+rds<sub>M9<sub>). This readily provides over 30 dB of gain with the dominant pole provided by the pseudo-resistors that will also attenuate the input common mode signals.
## 8 Capacitive Feedback Network
Both electrode inputs feed into separate capacitor arrays that off-set the scaled PWM signal generated at the output to calculate the differential error signal on V<sub>X<sub>. Each array is 20\\(\times\\)23 μ m² in size and uses 28 elements in a 4 by 7 configuration with 2.7\\(\times\\)2.7 μ m² horizontal MOM capacitors with 6 fingers on metal layers 2-7. The following allocation is used: C<sub>I<sub>=17\\(\times\\), C<sub>F<sub>=1\\(\times\\), C<sub>U<sub>=5\\(\times\\), C<sub>G<sub>=[0-5]\\(\times\\). The particular configuration in Fig. 2 can readily accommodate changes in dynamic range or adjustments in N. This is because \\(f\\) is dominated by the ratio C<sub>F<sub>/C<sub>I<sub> such that the design can freely change the number of phases being fed back without significantly changing the amplification dynamics. Additionally increasing C<sub>F<sub> will extend the dynamic range of the circuit since the noise floor will remain unchanged while providing less signal gain and having excessive circuit bandwidth.
# 9 The Impact of Technology Parameters
This section further highlights two features of the proposed topology that can be taken advantage of in advanced CMOS technologies where mismatch and process variation are the leading concern for designers. First we will summarise the scaling properties that arise when chopping in the input signal and secondly we will show that also for the asynchronous case the time-domain integration fundamentally helps with mitigating mismatch in digital to analogue conversion using a behavioural model as example.
## 10 CMOS Scaling of Chopper Impedance
First consider the input impedance R<sub>IN<sub> of the simple chopper structure used here[^25]. For sensor applications it is essential to maintain a large input impedance that avoids signal attenuation because many integrated sensors exhibit a source resistance of several M\\(\Omega\\).
$$ C_{I} = 10 C_{GM} = \frac{20}{3} W L C_{ox} $$
$$ f_{chp} = 2 f_{cor} = \frac{2 K_F}{W L C^2_{ox} e^2_{gd}} $$
The expression in Eq. 4 is first used select C<sub>I<sub> as 10\\(\times\\) the parasitic capacitance C<sub>GM<sub> seen on V<sub>X<sub> due the transconductor. This configuration avoids degrading the noise performance during amplification[^17]. C<sub>I<sub> is further equated in terms of the width W and length L of the input transistors. The chopper frequency is placed at exactly twice the corner frequency f<sub>cor<sub> which is the frequency at which the flicker noise is equal to the thermal noise floor e²<sub>gd<sub> of the target input-referred noise profile. Rearrangement of the terms will yield Eq. 5 which uses the trap density K<sub>F<sub> to estimate for flicker noise for a specific fabrication process[^26].
$$ R_{IN} = \frac{1}{2 C_{I} f_{chp} } = \frac{ 3 C_{ox} e^2_{gd} }{80 K_F } $$
{{< figure src="/images/jssc2018/sizing.svg" title="Figure 5: Chopper based input impedance as a function of CMOS technology using typical process parameters K<sub>F<sub>=3.2e-38 and C<sub>ox<sub>=1.6e-12 [F/μ m²]/L where L is the technology feature size in nanometre with the oxide thickness being estimated as 1/50 times the feature size." width="500" >}}
Eq. 6 calculates the expected input resistance and provides a first order estimation of amplifier impedance with respect to process parameters. The fact that R<sub>IN<sub> depends linearly on C<sub>ox<sub> implies that input resistance can be improved by using more advanced technologies. The expected values for R<sub>IN<sub> are plotted in Fig. 5 as a function of CMOS technology with varying noise requirements. Eventually the gate leakage will inhibit this trend as the associated shot-noise limits the sensitivity for technologies beyond 65 nm. This result primarily constrains the selection of transistor size[^25] that in turn determines f<sub>chp<sub> and f<sub>osc<sub>.
## 11 Modulated Mismatch in Oscillators
Mismatch due to process variation is the primary cause of distortion during multi-bit signal conversion. Minimising this source of nonlinearity is essential for both synchronous and asynchronous ΔΣ modulators because mismatch in the feedback DAC is not shaped by the loop filter [^27]. Fortunately the modulating property of the oscillator can remove this distortion if the phase readout is performed in a parallel fashion [^5]. Here we will concisely demonstrate that property arises because the mismatch induced components are simply being averaged and induce a DC-offset together with tones at the harmonic components of f<sub>osc<sub>. This uses a mapping that relates the phase difference \\(x\\) to the generated PWM waveform as a function of time \\(\tau\\) defined in Eq. 7. The following expression in Eq. 8 then evaluates the analogue feedback voltage that appears on V<sub>X<sub> in the ideal case for a given a phase difference of Δφ between the two oscillators.
$$ A(\tau,x) \triangleq\begin{cases} 1 & \tau (mod\: 1) \: < \:x 0 & \text{otherwise} \end{cases} $$
$$ V_{X}(t) = f \cdot \sum_{k=0}^{N-1} \underbrace{A( t \cdot f_{osc}+\frac{k}{N}\:,\: \Delta \phi )}_{Q_{k}(t)} $$
$$ Q_{k}(t) = (1+\frac{\sigma_{C,k}}{C_U}) A( t \cdot f_{osc} + \frac{k}{N} \: , \: \sigma_{\tau-\mu,k} + \Delta \phi) $$
There are two independent sources of mismatch for each phase: the deviation in capacitor weights of C<sub>U<sub> σ<sub>C,k<sub> and the differential delay variation in oscillator stages as a fraction of the oscillation period σ\tss{τ,k} that includes the digital gates generating Q (i.e. inverters and XOR-gate). These are used to formulate Eq. 9 which considers a particular phase of Q(t) and the random mismatch variables that have process dependent normal distributions. The variation in delay will locally increase/decrease the pulse-width of Q for a specific phase \\(k\\). This is a time-invariant component of the gate delay while Δφ and T<sub>osc<sub> are signal dependent. Precisely formulating the cumulative variation of σ\tss{τ} will relate the transistor sizing, gate capacitance, and threshold voltage of each delay during operation.
Notice that A is a linear function of Δφ with a gain of 1 for the DC component of the PWM output which can be further expanded to extract the high frequency behaviour. However by design these components are intentionally avoided which should reveal that that the capacitor weights are always uniformly averaged irrespective Δφ. Closed-loop operation feeds back each σ\tss{τ,k} such that the sum all components has zero mean, that is σ\tss{τ-μ,k}\ = σ\tss{τ,k}-(\\(\sum_{k=0}^{N-1}\\) σ\tss{τ,k}/N). The residual variation in delay for each phase inevitably induces spurs at at harmonics of f<sub>osc<sub>.
{{< figure src="/images/jssc2018/vco_model.svg" title="Figure 6: A continuous-time multi-phase VCO model for evaluating parameter sensitivity with transient simulations using the logical operator **B** in Eq. 10." width="500" >}}
Verifying this behaviour is best done by modifying the behavioural model commonly used for oscillators[^28] to accommodate multi-phase readout using the above expressions. Such a model is shown in Fig. 6. This configuration uses an internal time variable at V<sub>T<sub> that accumulates according to f<sub>osc<sub>. Given a set of quantisation levels L<sub>k<sub> or equivalently the number of phases, a logical function **B** will compute the corresponding PWM waveform of Q which are weighted by the associated capacitor C<sub>k<sub>. In this case the digital gate delay arising from computing the phase difference and applying feedback to the capacitive DAC can also be modelled by adjusting τ<sub>dly<sub>.
$$ \begin{split}\mathbf{B}(\phi_{S},\phi_{R},L) \triangleq & \left(\phi_{S} > L > \phi_{R} \right) \lor \left(\phi_{S} < \phi_{R} < L \right) & \lor \left( L < \phi_{S} < \phi_{R} \right)\end{split} $$
The logical expression in Eq. 10 simply compares the two phases with respect to L and evaluates the digital condition for which the output should be high. This representation implies that the delays correspond to the interval between each level which can be distributed uniformly as L<sub>k<sub>=(0.5+k)/L for integers k from 0 to N-1. By distributing the quantisation levels from 0 to 1 the corresponding delays are inherently normalised to the periodicity of φ\tss{S/R} without explicitly having to compute values with respect to f<sub>osc<sub> even when it is dynamically changing. In addition a difference in oscillator frequency between X\tss{1-2} can also be accommodated by adding a second integrated frequency component to the summation node.
{{< figure src="/images/jssc2018/dac_mm.svg" title="Figure 7: Simulated output spectrum with a 2.5 kHz input at -6 dB of the full input-range for a equivalent asynchronous flash quantiser with 2.6 bits of resolution and 5 % mismatch in σ\tss{τ,k} and σ<sub>C,k<sub>." width="500" >}}
{{< figure src="/images/jssc2018/dac_mm2.svg" title="Figure 8: Simulated output spectrum with a 2.5 kHz input at -6 dB of the full input-range for a asynchronous VCO quantiser with 2.6 bits of resolution, 300 kHz f<sub>osc<sub> and 5 % mismatch in σ\tss{τ,k} and σ<sub>C,k<sub>." width="500" >}}
Now the impact of mismatch can be simulated by adding parameter variation in the quantiser levels and the feedback weights (f). The analogous case where the mismatch is not modulated (i.e. f<sub>osc<sub> is 0) loosely corresponds to a flash-based ADC since the phase is simply being compared with N thresholds. The corresponding spectra of the flash quantiser is shown in Fig. 7 and oscillating quantiser is shown in Fig. 8 where we observe the distortion components in different bands of the spectrum.
# 12 Measured Results
{{< figure src="/images/jssc2018/micrograph.svg" title="Figure 9: Micro-photograph of the fabricated prototype showing an annotated floor plan in (a) and the poly layer together with the first three metal layers of the circuit layout in (b)." width="500" >}}
{{< figure src="/images/jssc2018/setup.svg" title="Figure 10: Experimental setup used for characterising the ATC for low-noise signal conversion showing the respective instruments that were used." width="500" >}}
The commercially available TSMC 65 nm CMOS LP MS RF technology (1P9M 6X1Z1U RDL) was used to prototype the proposed circuit and demonstrate measured noise and linearity characteristics. The chip micro-photograph of this prototype is shown in Fig. 9. The setup used to take these measurements is shown in Fig. 10 and uses a custom PCB to regulate V<sub>DD<sub> on-board with additional decoupling.
The external biasing allows this setup to first tune the circuit sensitivity by adjusting the 1 μ A reference current which scales all bias currents proportionally and then using V<sub>C<sub> the oscillation frequency can be fine tuned as V<sub>R<sub> is controlled which modulates I<sub>M10<sub>. The supply voltage can be tuned but reducing the supply below 0.5 V limits the biasing current and reduces the circuit sensitivity. Similarly increasing the supply is mainly constrained by the buffers that digitise the oscillator waveform and can induce a large leakage current beyond a voltage of 0.65 V.
The tone generated by the Agilent signal generator is attenuated resistively by a factor of 10 to achieve a low-noise differential test signal at the input of the instrumentation circuit. Two phases from the asynchronous output Q are captured at 500 MS/s using high-speed digital scope which can then be post-processed off-line to investigate the features of separate PWM signals during different operating conditions. Both the chopper tones and PWM carrier can be observed outside the signal bandwidth at harmonics of 78 kHz and 350 kHz respectively.
The characterisation procedure evaluates the signal to noise and distortion ratio (SNDR) for varying input amplitudes and frequencies. For a particular device, this characteristic is shown in Fig. 11. In extension, Fig. 12-13 show the distortion components as a function of amplitude along SA and the frequency along SF respectively. Fig. 14 shows what the input-referred power-spectral-density of Q looks like for a particular operating point at P. Here the lowest gain setting of 41 dB was used to demonstrate operation with maximum dynamic range. Although the circuit bandwidth theoretically exceeds the range of frequencies resolved here, the interfering tones seen in Fig. 14 prevent inaccurate measurements to confirm this result. Using a similar procedure the CMRR is characterised and shown in Fig. 15. Again, Fig. 17-16 show the distortion components due to a common mode input as a function of amplitude along SA and frequency along SF respectively. Due to the limited voltage overhead from the current sources in the transcondutor the high-frequency common-mode interference can result in degenerated operation as they are not attenuated by the pseudo-resistor. This mode of failure where the oscillators are saturated is out-lined by the dashed region.
Note that flicker noise from each oscillator is not removed by the chopper configuration in Fig. 4. However there is no apparent 1/f noise profile in the 10-100 Hz band even though the oscillators are small in size. This is because the rms-gate-voltage fluctuation due to flicker noise at each device is scaled by the open-loop gain of the ATC when referred to the input.
The maximum achieved THD was 60 dB for a 1 kHz sinusoidal input. The main source of performance degeneration in this circuit for larger input signals is due to the use of poorly regulated bias currents in the differential pair and relying on pseudo-differential phase read-out that allows some common-mode fluctuation at V<sub>S<sub> to couple to the output Q. Either introducing cascodes or using a folded cascode topology may improve linearity at the cost of increasing the required voltage headroom or reducing the noise efficiency. However the dynamic range exceeding 50 dB should be sufficient for the physiological range of amplitudes for neural activity given that there are no external aggressors present during recording. We can further confirm the effectiveness of the mismatch rejection technique as the Monte Carlo simulation results indicate that each phase should exhibit 1.1 % standard deviation in coupling factor for a 3-σ\: confidence interval. This should lead to a similar distortion characteristic shown in Fig. 7 with a large number of dominant harmonics being generated due to mismatch errors. Instead distortion is dominated by the second and third harmonic typical of more conventional analogue nonlinearity.
{{< figure src="/images/jssc2018/sndr_dm_sweep.svg" title="Figure 11: Characterisation sweep evaluating the SNDR performance using differential sinusoid at the input with varying amplitudes and frequencies. " width="500" >}}
{{< figure src="/images/jssc2018/thd_dm_vid.svg" title="Figure 12: Measured output harmonics due to a differential-mode 1 kHz input signal at different amplitudes corresponding to the SNDR measurement along SA in Fig. 11." width="500" >}}
{{< figure src="/images/jssc2018/thd_dm_frq.svg" title="Figure 13: Measured output harmonics due to a differential-mode 1.5 mVpp input signal at different frequencies corresponding to the SNDR measurement along SF in Fig. 11." width="500" >}}
{{< figure src="/images/jssc2018/spec_1k.svg" title="Figure 14: Measured output spectrum due to a differential 2 mVpp input signal at 1 kHz corresponding to the SNDR measurement at point P in Fig. 11." width="500" >}}
{{< figure src="/images/jssc2018/cmrr_cm_sweep.svg" title="Figure 15: Characterisation sweep evaluating the CMRR performance using large common-mode sinusoid at the input with varying amplitudes and frequencies." width="500" >}}
{{< figure src="/images/jssc2018/thd_cm_frq.svg" title="Figure 16: Measured output harmonics due to a common-mode 10 mVpp input signal at different frequencies corresponding to the CMRR measurement along SF in Fig. 15." width="500" >}}
{{< figure src="/images/jssc2018/thd_cm_vid.svg" title="Figure 17: Measured output harmonics due to a common-mode 1 kHz input signal at different amplitudes corresponding to the CMRR measurement along SA in Fig. 15." width="500" >}}
{{< figure src="/images/jssc2018/ccouple.svg" title="Figure 18: Measured frequency response due to differential 2 mVpp input signal that is capacitively coupled to the ATC input using 0.47 nF capacitors." width="500" >}}
The input impedance of this circuit was estimated by removing the resistive attenuation network and instead capacitively coupling the signal generator to the input. This assumes that the input will exhibit a RC time constant that is dominated by the coupling capacitor and the resistive/leakage component from the chopper in combination with the ESD protection that can be measured directly. The frequency dependent response is shown in Fig. 18. The 3dB cut-off frequency was estimated at 21.8 Hz. In this case two 0.47 nF capacitors were used to couple both inputs which implies the input resistance is around 31 MΩ. Parasitics at the input or capacitor variation can inflate this value and it is likely the impedance is closer to the analytical estimate of 22 MΩ \:according to Eq.6.
Table 2: System Characteristics and Comparison with State-of-the-Art
| Parameter [unit] | This Work | [^8] | [^29] | [^7] | [^6] | [^30] | [^31] | [^32] | [^33] | [^34] |
|----|----|----|----|----|----|----|----|----|----|----|
| Year | **2017** | 2017 | 2017 | 2017 | 2017 | 2016 | 2016 | 2015 | 2013 | 2012 |
| Application | **EAP** | ECG | LFP | - | LFP | ECG | EAP | EAP | EAP | EAP |
| Technology[nm] | **65** | 40 | 130 | 40 | 40 | 65 | 65 | 90 | 180 | 65|
| Modality | **Time** | Time | Volt. | Time | Volt. | Volt. | Volt. | Volt. | Volt. | Mix |
| Supply-V[V] | **0.5** | 0.6 | 1.2 | 1.2 | 1.2 | 0.6 | 1 | 1 | 0.45 | 0.5 |
| Supply-I[A] | \textbf{2.55 μ} | 5.5 μ | 5.3 μ | 14 μ | 2.5 μ | 3 n | 3.3 μ | 2.8 μ | 2.1 μ | 10 μ |
| Bandwidth[Hz] | **11 k** | 150 | 500 | 5 k | 200 | 370 | 8.2 k | 10.5 k | 10 k | 10 k |
| Input Range[mVpp] | **4** | 40 | - | 8 | 100 | 25 | 220 | 1 | 1 | 1 |
| CMRR[dB] | \textbf{(>)60(^\star)} | 60 | 90 | 97 | - | 60 | (>)80 | (>)45 | 73 | 75 |
| SFDR[dB] | **60** | 56 | 72 | 70 | 79 | 75 | (>)40 | (>)37 | (>)46 | (>)34 |
| Noise Floor[V/\rtxt{Hz}] | **36 n** | 0.6 μ | 46n | 32 n | - | 1.4 μ | 27.5n | 35n | 29n | 100n |
| RMS Noise[μ V<sub>rms<sub>] | **3.8** | 7.8 | 1.1 | 2.3 | 5.2 | 26 | 4.1 | 3.04 | 3.2 μ | 4.9 μ |
| Area[mm²] | **0.006** | 0.015 | 0.013 | 0.015 | 0.135 | 0.15 | 0.042 | 0.137 | 0.25 | 0.013 |
| NEF / PEF | \textbf{2.2 / 2.4} | 8.1 / 39| 2.9 / 10| 4.7 / 27| 22 / 581| 2.1 / 2.6| 3.2 / 10| 1.9 / 3.6 | 1.57 / 1.1 | 5.99 / 18 |
{{< figure src="/images/jssc2018/breakdown.svg" title="Figure 19: Power and area contributions from each sub-circuit." width="500" >}}
The detailed system characteristics are summarised in Table 2. The system power dissipation was specified at 1.3 μ W from these measurements. The relative power and area utilisation of each subcircuit is compared in Fig 19. As expected, a large fraction of both power and area is used by the main analogue circuits that consists of the low-noise transconductor and the flicker rejection stage. This distribution maximises the NEF and shows that the asynchronous digital logic can provide additional functionality without a significant resource overhead. In relation to the work in [^7], this ATC topology exhibits as significant reduction in power budget although input-referred noise figure is slightly increased. This improvement is not as pronounced in comparison with [^8] but instead the figure of merit is superior. Other works show that both time-based and voltage-based instrumentation can achieve near ideal noise efficiency but only select topologies enable more advanced CMOS process to yield a smaller silicon footprint. The pioneering work in [^34] already demonstrated that resource efficient signal acquisition is best realised by combing signal quantisation and amplification into a single loop. The main drawback was that this mixed signal topology was still relatively complex for hundreds of channels and linearising the feedback for closed loop quantisation came with a considerable reduction in noise efficiency. However the ΣΔ operation of the clocked VCO and the ΣΔ modulated DAC in the feedback enable a powerful technique that trades off excessive bandwidth for reduced circuit size or DAC complexity. The same technique is applied here to enable a compact multichannel configuration. Our future work will extend on the current prototype by additionally providing electrode off-set cancellation for \textit{in-vivo} experiments with multi-channel recording capabilities.
# 13 Conclusion
This work proposes a chopper-stabilised ATC to enable high-impedance electrode instrumentation for integrated sensing systems that require ultra low-voltage operation for power saving. The time-domain techniques enabled by this ATC topology alleviate the difficulty of performing precise instrumentation in advanced CMOS technologies while also providing improved power efficiency together with a substantial reduction in size. The presented configuration achieves a power budget of 1.2 μ W for a 36 nV/\rtxt{Hz} noise floor requirement and a compact silicon footprint of 0.006 mm². In extension to presenting the implementation details, this work also provides essential modelling and analytical tools for further optimisation. This will enable other mixed-signal systems that require high noise-efficiency, high-speed, or asynchronous signal conversion to effectively adopt time-based techniques and utilise the presented circuit implementation.
# 14 Acknowledgement
The authors would like to thank Dr. Pantelis Georgiou, and the Europractice Advanced Technology Stimulation programme for providing access to the TSMC 65 nm technology. The authors additionally thank Yan Liu and the anonymous reviewers for their valuable assistance with this manuscript.
# Refernces:
[^18]: J.Guo, J.Yuan, and M.Chan, ''Modeling of the cell-electrode interface noise for microelectrode arrays,'' IEEE Trans. Biomed. Circuits Syst., vol.6, no.6, pp. 605--613, Dec 2012.
[^2]: C.Huang and S.Chakrabartty, ''An asynchronous analog self-powered cmos sensor-data-logger with a 13.56 MHz RF programming interface,'' IEEE J. Solid-State Circuits, vol.47, no.2, pp. 476--489, Feb 2012.
[^1]: J.Yoo etal., ''An 8-channel scalable EEG acquisition SoC with patient-specific seizure classification and recording processor,'' IEEE J. Solid-State Circuits, vol.48, no.1, pp. 214--228, Jan 2013.
[^5]: K.Lee, Y.Yoon, and N.Sun, ''A scaling-friendly low-power small-area $\Delta \Sigma$ ADC with VCO-based integrator and intrinsic mismatch shaping capability,'' IEEE Trans. Emerg. Sel. Topics Circuits Syst., vol.5, no.4, pp. 561--573, Dec 2015.
[^8]: R.Mohan etal., ''A 0.6 V, 0.015-mm$^2$, time-based ECG readout for ambulatory applications in 40 nm CMOS,'' IEEE J. Solid-State Circuits, vol.52, no.1, pp. 298--308, Jan 2017.
[^6]: W.Jiang etal., ''A ±50 mV linear-input-range VCO-based neural-recording front-end with digital nonlinearity correction,'' IEEE J. Solid-State Circuits, vol.52, no.1, pp. 173--184, Jan 2017.
[^4]: P.Prabha etal., ''A highly digital VCO-based ADC architecture for current sensing applications,'' IEEE J. Solid-State Circuits, vol.50, no.8, pp. 1785--1795, Aug 2015.
[^3]: T.Anand, K.A.A. Makinwa, and P.K. Hanumolu, ''A VCO based highly digital temperature sensor with 0.034 $^\circ$C/mV supply sensitivity,'' IEEE J. Solid-State Circuits, vol.51, no.11, pp. 2651--2663, Nov 2016.
[^10]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational amplifiers and their application to continuous-time filters in nanoscale CMOS,'' IEEE J. Solid-State Circuits, vol.49, no.12, pp. 2758--2772, Dec 2014.
[^23]: L.B. Leene and T.G. Constandinou, ''A 0.5V time-domain instrumentation circuit with clocked and unclocked Delta Sigma operation,'' in 2017 IEEE International Symposium on Circuits and Systems (ISCAS), May 2017, pp. 1--4.
[^12]: Y.Chen etal., ''A continuous-time digital IIR filter with signal-derived timing and fully agile power consumption,'' IEEE J. Solid-State Circuits, vol.53, no.2, pp. 418--430, Feb 2018.
[^22]: S.Pavan, ''Analysis of chopped integrators, and its application to continuous-time delta-sigma modulator design,'' IEEE Trans. Circuits Syst. I, vol.64, no.8, pp. 1953--1965, Aug 2017.
[^24]: W.S.T. Yan and H.C. Luong, ''A 900-MHz cmos low-phase-noise voltage-controlled ring oscillator,'' IEEE Trans. Circuits Syst. II, vol.48, no.2, pp. 216--221, Feb 2001.
[^17]: R.R. Harrison and C.Charles, ''A low-power low-noise CMOS amplifier for neural recording applications,'' IEEE J. Solid-State Circuits, vol.38, no.6, pp. 958--965, June 2003.
[^19]: A.Hajimiri and T.H. Lee, ''A general theory of phase noise in electrical oscillators,'' IEEE J. Solid-State Circuits, vol.33, no.2, pp. 179--194, Feb 1998.
[^25]: T.Denison etal., ''A 2 muW 100 nV/rtHz chopper-stabilized instrumentation amplifier for chronic measurement of neural field potentials,'' IEEE J. Solid-State Circuits, vol.42, no.12, pp. 2934--2945, Dec 2007.
[^14]: Y.Li, D.Zhao, and W.A. Serdijn, ''A sub-microwatt asynchronous level-crossing ADC for biomedical applications,'' IEEE Trans. Biomed. Circuits Syst., vol.7, no.2, pp. 149--157, April 2013.
[^13]: W.Tang etal., ''Continuous time level crossing sampling ADC for bio-potential recording systems,'' IEEE Trans. Circuits Syst. I, vol.60, no.6, pp. 1407--1418, June 2013.
[^9]: G.D. Colletta etal., ''A 20 nW 0.25 V inverter-based asynchronous delta-sigma modulator in 130 nm digital CMOS process,'' IEEE Trans. VLSI Syst., vol.25, no.12, pp. 3455--3463, Dec 2017.
[^16]: F.M. Yaul and A.P. Chandrakasan, ''A noise-efficient 36 nV/ txtHz chopper amplifier using an inverter-based 0.2 V supply input stage,'' IEEE J. Solid-State Circuits, vol.52, no.11, pp. 3032--3042, Nov 2017.
[^29]: H.Kassiri etal., ''Rail-to-rail-input dual-radio 64-channel closed-loop neurostimulator,'' IEEE J. Solid-State Circuits, vol.52, no.11, pp. 2793--2810, Nov 2017.
[^28]: C.C. Kuo etal., ''Fast statistical analysis of process variation effects using accurate PLL behavioral models,'' IEEE Trans. Circuits Syst. I, vol.56, no.6, pp. 1160--1172, June 2009.
[^7]: C.C. Tu, Y.K. Wang, and T.H. Lin, ''A low-noise area-efficient chopped VCO-based CTDSM for sensor applications in 40 nm CMOS,'' IEEE J. Solid-State Circuits, vol.52, no.10, pp. 2523--2532, Oct 2017.
[^31]: K.A. Ng and Y.P. Xu, ''A low-power, high CMRR neural amplifier system employing CMOS inverter-based OTAs with CMFB through supply rails,'' IEEE J. Solid-State Circuits, vol.51, no.3, pp. 724--737, March 2016.
[^30]: P.Harpe etal., ''A 0.20$ $mm$^2$ 3$ $nW signal acquisition IC for miniature sensor nodes in 65 nm CMOS,'' IEEE J. Solid-State Circuits, vol.51, no.1, pp. 240--248, Jan 2016.
[^32]: T.Yang and J.Holleman, ''An ultralow-power low-noise CMOS biopotential amplifier for neural recording,'' IEEE Trans. Circuits Syst. II, vol.62, no.10, pp. 927--931, Oct 2015.
[^21]: S.Mondal and D.A. Hall, ''An ECG chopper amplifier achieving 0.92 NEF and 0.85 PEF with AC-coupled inverter-stacking for noise efficiency enhancement,'' May 2017, pp. 1--4.
[^11]: L.B. Leene and T.G. Constandinou, ''Time domain processing techniques using ring oscillator-based filter structures,'' IEEE Trans. Circuits Syst. I, vol.64, no.12, pp. 3003--3012, Dec 2017.
[^33]: D.Han etal., ''A 0.45 V 100-channel neural-recording IC with sub- mu w/channel consumption in 0.18 mu m CMOS,'' IEEE Trans. Biomed. Circuits Syst., vol.7, no.6, pp. 735--746, Dec 2013.
[^34]: R.Muller, S.Gambini, and J.M. Rabaey, ''A 0.013 mm sqrd, 5 W, DC-coupled neural signal acquisition IC with 0.5 V supply,'' IEEE J. Solid-State Circuits, vol.47, no.1, pp. 232--243, Jan 2012.
[^15]: A.Bagheri etal., ''Low-frequency noise and offset rejection in DC-coupled neural amplifiers: A review and digitally-assisted design tutorial,'' IEEE Trans. Biomed. Circuits Syst., vol.11, no.1, pp. 161--176, Feb 2017.
[^20]: S.Chatterjee, Y.Tsividis, and P.Kinget, ''0.5-V analog circuit techniques and their application in OTA and filter design,'' IEEE J. Solid-State Circuits, vol.40, no.12, pp. 2373--2387, Dec 2005.
[^26]: C.C. Enz and E.A. Vittoz, Charge-based MOS transistor modeling: the EKV model for low-power and RF IC design.\hskip 1em plus 0.5em minus 0.4em elax John Wiley & Sons, Aug 2006.
[^27]: K.-D. Chen and T.-H. Kuo, ''An improved technique for reducing baseband tones in sigma-delta modulators employing data weighted averaging algorithm without adding dither,'' IEEE Trans. Circuits Syst. II, vol.46, no.1, pp. 63--68, Jan 1999.

144
content/publications/2018/autonomous-soc-for-neural-local-field-potential-recording-in-mm-scale-wireless-implants.md Normal file
View File

@ -0,0 +1,144 @@
---
title: "Autonomous SoC for neural local field potential recording in mm-scale wireless implants"
date: 2018-07-23T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
- publication
- CMOS
- wireless
- system-on-chip
- biomedical
---
Lieuwe B. Leene, Peilong Feng, Michal Maslik, Katarzyna M. Szostak, Federico Mazza, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
Next generation brain machine interfaces fundamentally need to improve the information transfer rate and chronic consistency. This needs them to be highly scalable but also to observe signals that are stable over time. Towards this aim, this paper presents a novel System-on-Chip (SoC) for a mm-scale wireless neural recording node that can be implanted in a distributed fashion. The proposed self-regulating architecture allows each implant to operate autonomously and adaptively load the electromagnetic field to extract a precise amount of power for full-system operation. This can allow for a large number of recording sites across multiple implants extending through cortical regions without increased control overhead in the external head-stage. By observing only local field potentials (LFPs), chronic stability is improved and good coverage is achieved whilst reducing the spatial density of recording sites. The system features a \\(\Delta\Sigma\\) based instrumentation circuit that digitises high fidelity signal features at the sensor interface thereby minimising analogue resource requirements while maintaining exceptional noise efficiency. This has been implemented in a 0.35 μ m CMOS technology allowing for wafer-scale post-processing for integration of electrodes, RF coil, electronics and packaging within a 3D structure. The presented configuration will record LFPs from 8 electrodes with a 825 Hz bandwidth and an input referred noise figure of 1.23μ V<sub>rms<sub>. The resulting electronics has a core area of 2.1 mm² and a power budget of 80 μW.
# 2 Introduction
There has been significant effort in developing integrated circuits for Brain Machine Interfaces (BMIs)[^1]. These systems enable a wide range of applications from recording neural signals for scientific study to treating neurological conditions. They integrate a multitude of functions for sensing, processing, telemetry and power management. There is a drive to develop wireless modules that are hermetically packaged for chronic implant applications[^2]. Moreover, any reduction in size can substantially improve device efficacy by reducing the impact on surrounding tissue. Any reduction in weight is also highly desirable for behaving animal studies. While a number of proposed systems have relied on PCB[^3] or flexible [^4] technologies that allow low cost, rapid development. This approach leads to substantially larger implants when compared to silicon-based integration[^1]. This is because the silicon substrate enables a large number of electrodes to be integrated directly onto the active die in the shape of an implantable shank[^5]. In contrast, making a large number of intra-device connections has a significant impact on device footprint as well as fabrication complexity with added bio-compatibility constraints [^6]. For this reason a number of groups are investigating millimetre-scale solutions for recording[^7] and stimulation[^8] with all aspects of the implant integrated within the silicon die or micro-machined package.
{{< figure src="Figures/ENGINI.pdf" title="Figure 1: The ENGINI concept showing: (a) multiple freely floating probes being wirelessly interrogated by a headstage unit; (b) schematic representation." width="500" >}}
The 'Empowering Next Generation Implantable Neural Interfaces' (ENGINI) project achieves its scalability by utilising multiple mm-scale probes that are each implanted and 'freely floating' in the cortex. These observe field potentials along the cortical column but also laterally through different probes. These are wirelessly coupled to an external headstage with trancutanious and transdural inductive links to deliver power and exchange data. This is illustrated in Fig. 1.
This particular system relies on the autonomous behaviour of each probe such that a downlink is not required and each probe simply backscatters recorded activity using load shift keying (LSK) modulated at different preconfigured frequencies derived from the carrier. This allows each probe to be uniquely identified without increased control overhead for larger ensembles of probes. The probe circuit additionally includes all front-end instrumentation. An aggressive strategy is thus needed to reduce system complexity to enable package miniaturisation. Such a system may therefore not be able to incorporate more advanced functionality found in the state-of-the-art[^9]. Instead the electronics will perform direct quantization of the 1-825 Hz local field potential (LFP) signal bandwidth that is transmitted directly without compression to allow long term recordings with sub-millimetre spacial resolution for chronic BMI applications. The rest of this paper is organised as follows: Section 3 details the overall system operation and high level implementation; Section 4 describes the circuit implementation; Section 8 presents simulation results and system characteristics; and Section 9 concludes this work with respect to the achieved performance.
# 3 System Architecture
The integrated system architecture is shown in Fig. 2. This shows a single recording unit which is inductively coupled to a primary coil L<sub>1<sub> that provides power using a 433 MHz carrier to leave sufficient bandwidth for frequency division multiplexing multiple recording units. In fact the receiving coil L<sub>2<sub> will be located on a passive undoped silicon interposer that is flip-chip bonded to the active instrumentation IC. The resonant tank L<sub>2<sub> C<sub>2<sub> receives the transmitted power and establishes a DC voltage on V<sub>DD<sub> once the rectifier down-converts the carrier. First a biasing circuit is powered that generates digital flags that indicate the supply voltage level. These flags assist the self-tuning control algorithm to adjust the loading capacitance C<sub>T<sub> to tune or detune the resonant tank L<sub>2<sub>C<sub>2<sub> and receive a specific amount of power to establish 1.5 V on the V<sub>DD<sub> supply. This feedback regulates the supply voltage in a course manner without needing active control from the primary side (external controller). This implies the analogue circuits need to accommodate for any fluctuations without diminishing sensor precision. The continuous-time fully-differential modulator topology will further prevent these supply noise aggressors from being aliased in-band during sampling. The system clock can be directly extracted from the resonant tank using adiabatic logic elements to implement a series of frequency dividers before passing the clock to the digital core[^10].
{{< figure src="Figures/SYS.pdf" title="Figure 2: ENGINI system architecture for recording LFP at high resolution. This tunes the receiving resonant tank L<sub>2<sub>C<sub>2<sub> to regulate V<sub>DD<sub>." width="500" >}}
# 4 Circuit Implementation
This ENGINI prototype has been developed for a 0.35 μ m CMOS technology such that assembly of the 3D probe can be performed in-house using low-cost micro-fabrication and micro-packaging techniques. The implementation of each subsystem will be detailed below.
## 5 Self-Regulated Power Harvesting
This provides a stable power supply for the electronics and back-scatters digitised recordings. The circuit architecture is shown in Fig. 3. This contains a binary weighted capacitor bank C<sub>T<sub>, a passive full wave rectifier, and a sensing circuit which are all digitally-controlled. The principle of operation can be described as follows. First, the cross-coupled rectifier converts the induced AC voltage to a DC power on V<sub>x<sub>. Then, the low voltage amplifier A<sub>2<sub> performs auto-zeroing by shorting C<sub>F<sub> and simultaneously sampling the rectified voltage onto C<sub>I<sub>. After sampling, the parallel binary-weighted capacitor bank C<sub>T<sub> is adjusted to tune or de-tune LC tank on the secondary side. There is therefore a voltage fluctuation at node V<sub>x<sub>. The change in V<sub>x<sub> is amplified 30\\(\times\\) by A<sub>2<sub> which corresponds to the ratio C<sub>I<sub>/C<sub>F<sub>. The polarity of the resulting change is digitised using the comparator, instructing the digital control to add or remove parallel capacitors in the next cycle of regulation. Two supply voltage level indicators from the biasing circuit further assist this feedback to increase or reduce the supply voltage and whether to perform LSK respectively. The resistor R<sub>z<sub> is added after the output of rectifier such that the speed at which V<sub>X<sub> can be controlled is not dependent on the load capacitance C<sub>L<sub> which may be quite large. This allows fast regulation with a clock speed of 846 kHz at the cost of some reduction in power efficiency due to the voltage drop from V<sub>X<sub> to V<sub>DD<sub>.
{{< figure src="Figures/REG.pdf" title="Figure 3: Adaptive power conversion and regulation circuit using full-wave rectifier, tunable LC tank, auto-zeroing amplifier and strong arm comparator" width="500" >}}
%
## 6 \\(\Delta\Sigma\\) Instrumentation Circuit
The instrumentation circuit used to acquire the electrode recordings is based on the time-domain \\(\Delta\Sigma\\) modulator in [^11]. This uses differential oscillators as the integration element with an asynchronous signal quantizer. However the implementation presented here introduces an additional Gm-C integrator and a feed-forward path to realise second-order noise shaping. This reduces the oversampling ratio (OSR) requirement and substantially increases the dynamic range of the system. A single-ended equivalent of the fully-differential structure used here is shown in Fig. 4.
{{< figure src="Figures/SDM.pdf" title="Figure 4: Simplified equivalent of the second-order \\(\Delta\Sigma\\) modulator using time-domain signal quantization exhibiting a bandpass response due to the switched current DAC which removes any electrode offset." width="500" >}}
%
Note that this is a DC-coupled configuration where the analogue node V<sub>O<sub> tracks the electrode potential. An electrode offset larger than \\(\pm\\)100 mV can be accommodated without saturating the modulator by adding the digitally switched and duty cycled current in the feedback path. The quantized signal Q is AC coupled onto V<sub>O<sub> with a relatively large attenuation factor due to capacitive division α=1/(C<sub>0<sub>/C<sub>C<sub>+1) which will allow the in-band signal gain. This can be confirmed using the small signal model for this circuit described in Eq. 1-4 where H(s) represents the second-order loop filter and C(s) the charge pump with capacitive feed-forward. The factor k1=OSR f<sub>smp<sub>/2 reflects the modulator bandwidth in terms of the target sampling frequency f<sub>smp<sub>. The factor k2=2\\(\pi\\) f<sub>hp<sub> represents the integration constant of the charge pump in terms of the high-pass cut-off frequency f<sub>hp<sub>. This approach is inspired by the first order modulator in [^12]. The implemented circuit uses an OSR of 64, a 1 Hz high-pass corner frequency, and third order CIC filter to decimate the output. This leads to the noise and signal transfer functions shown in Fig. 5.
$$ STF(s) = \frac{H}{1+\alpha C H} $$
$$ H(s) = \left( 2 + \frac{k1}{s} \right) \frac{k1}{\alpha s} $$
$$ NTF(s) = \frac{1}{1+\alpha C H} $$
$$ C(s) = 1 + \frac{k2}{s} $$
{{< figure src="Figures/BODE.pdf" title="Figure 5: Analytical quantisation noise and signal transfer functions of the proposed modulator configuration." width="500" >}}
## 7 Reference and Biasing Circuit
The reference circuit loosely based on [^13] is used to establish the required noise shaping and precision in the \\(\Delta\Sigma\\) modulators. This provides a stable bias current using the structure shown in Fig. 6. Its core entails a β-multiplier generating a reference current of 800 nA flowing through resistor R<sub>1<sub>. This is scaled and mirrored to generate 8 current sinks for the front-end. Generation of a nominal 1.2 V reference is achieved by passing the reference current through a diode-connected PNP BJT B<sub>1<sub> and multiplying the BE (base-emitter) voltage using amplifier A<sub>2<sub> with resistive feedback. As the output voltage V<sub>REF<sub> primarily depends on the BJT BE voltage and ratio of R<sub>2<sub> and R<sub>3<sub> it is possible to achieve a very accurate voltage output independent of process variation.
Since the circuit is going to be operated in a neural implant it is expected that its operating temperature is going to remain stable and it is therefore not necessary to optimise the circuit for temperature independence. The main design target therefore lies in maximisation of the achieved PSRR (Power Supply Ripple Rejection) and minimisation of power consumption. The PSRR of the β-multiplier is maximised by cascoding both PMOS and NMOS current mirrors (M<sub>1<sub>\&M<sub>2<sub>, M<sub>3<sub>\&M<sub>4<sub>) [^14]. The same is achieved for V<sub>REF<sub> by employing a regulated cascode for BJT current generation.
In addition, the reference circuit generates logic levels indicating that the supply voltage has reached \\(\approx\\) 1 V, 1.3 V and 1.5 V used by the control loop of the SoC. The first indicator (1 V) is designed using a current source inverter as described in [^15]. The remaining two indicators are derived from V<sub>REF<sub> to ensure good tolerance to process variations.
{{< figure src="Figures/refc.pdf" title="Figure 6: Schematic of the reference and biasing circuit (start-up circuit not shown)." width="500" >}}
# 8 Simulation Results
The circuit was designed and validated using PSP models from the commercially available AMS 0.35 μ m CMOS technology (C35B4C3 4M/2P/HR/5V).
Preliminary simulation results show the instrumentation achieves a thermal noise floor of 45 nV<sub>rms<sub>/\\(√{\text{Hz}}\\) and uses 2.25μ A of current from a 1.5 V supply including also the decimation filter. This indicates a 3.4 μ W power budget per recording channel. The decimated output is shown in Fig. 7, achieving a dynamic range larger than 80 dB since the maximum modulator input range is \\(\pm\\)6 mV excluding the \\(\pm\\)100 mV linear range of the charge pump feedback.
The designed reference circuit consumes a bias current of 5 μ A and generates an output nominal voltage V\tss{REF,μ}=1.208 V with a standard deviation of σ =10.87 mV as shown by post-layout Monte Carlo simulation of 500 runs. Similarly, the output bias current was found to be I\tss{REF,μ}=150.4 nA and σ <sub>IREF<sub>=15.6 nA. The mismatch between two different bias currents has a standard deviation of σ \tss{\\(\Delta\\)IREF}=5.35 nA. The PSRR of the reference voltage with respect to frequency can be seen in Fig. 8. This shows that the reference circuit features an almost flat frequency response and a PSRR higher than 70 dB at small and high frequencies.
The overall system specifications are summarised in Table 1. Comparing the ENGINI system with other SoCs for brain machine interfaces demonstrates an increase in dynamic range and reduction in core size for equivalent noise performance as a result of the proposed architecture. The active silicon CMOS is currently being fabricated and will be flip-chip bonded onto a silicon based carrier. The two dies are illustrated and annotated in Fig. 9. Both dies are 16 mm² in size however the interposer is passive and only needs to embed the seal, coil, and electrode interconnect metallisation. Preliminary characterisation has shown that the L<sub>2<sub> can have an inductance of 5 nH with a Q-factor \textgreater12.
{{< figure src="Figures/SPEC.pdf" title="Figure 7: Output spectrum of the \\(\Delta\Sigma\\) instrumentation circuit from transient simulation using a 10 mVpp sinusoidal input tone at 210 Hz." width="500" >}}
{{< figure src="Figures/PSRR.pdf" title="Figure 8: PSRR (Power Supply Ripple Rejection) at V<sub>REF<sub>. This shows a PSRR of μ =78.29 dB & σ =1.58 dB, μ =69.94 dB & σ =1.59 dB and μ =79.95 dB & σ =0.52 dB at DC, 64 kHz and 433 MHz respectively." width="500" >}}
Table 1: System Characteristics and Comparison with State-of-the-Art
| Parameter [unit] | This Work \\(\dagger\\) | [^1] | [^16] | [^3]|
|----|----|----|----|----|
| Year | **2017** | 2017 | 2015 | 2016 |
| Application | **LFP** | ECoG | ECoG | EAP |
| Tech.[nm] | **350** | 180 | 65 | 350 |
| Supply-V[V] | **1.5** | 0.8 | 0.5 | 1.8|
| Total-P[W] | \textbf{80 μ}(\star) | 0.1 m | 0.2 m | 51 m |
| Core-A[mm²] | **2.1** | 9 | 5.8 | 12.5 |
| \# Channels | **8** | 16 | 64 | 8|
| Bandwidth[Hz] | **825** | 1 k | 500 | 11 k|
| DR[dB] | **85** | 55 | 52 | 50 |
| IRN [μ V<sub>rms<sub>] | **1.3** | 1.5 | 1.3 | 2.9 |
\\(\dagger\\) Based on preliminary simulation results. \\(\star\\) Includes rectifier loss.
{{< figure src="Figures/D2D.pdf" title="Figure 9: Annotated design for each silicon die that will be flip-chip bonded together. This shows the bonding pads, inductive coil, seal ring, and core ENGINI system to scale." width="500" >}}
# 9 Conclusion
This work demonstrates a compact system on chip architecture for LFP based recording systems that aims to distribute several implantable probes into the cortical tissue in a scalable fashion by relying on autonomous sensor operation. Using the resonant tuning for supply regulation and \\(\Delta\Sigma\\) modulator instrumentation has lead to a significant reduction in system complexity typically seen in BMI SoCs. Moreover this configuration is able to operate at high efficiency without much constraint on technology requirements since the overall system power budget is estimated to be 80 μ W from preliminary simulation results. The approach to brain machine interfaces presented here will lead to safer and simpler systems while delivering high fidelity multi-electrode recordings which is essential for applications in a clinical environment.%
# 10 Acknowledgement
This work was supported by EPSRC grant EP/M020975/1.
# References:
[^9]: M.A.B. Altaf, C.Zhang, and J.Yoo, ''A 16-channel patient-specific seizure onset and termination detection SoC with impedance-adaptive transcranial electrical stimulator,'' IEEE J. Solid-State Circuits, vol.50, no.11, pp. 2728--2740, Nov 2015.
[^1]: S.Ha etal., ''Silicon-integrated high-density electrocortical interfaces,'' Proc. IEEE, vol. 105, no.1, pp. 11--33, Jan 2017.
[^16]: R.Muller etal., ''A minimally invasive 64-channel wireless $\mu$ECoG implant,'' IEEE J. Solid-State Circuits, vol.50, no.1, pp. 344--359, 2015.
[^8]: A.Khalifa, J.Zhang, M.Leistner, and R.Etienne-Cummings, ''A compact, low-power, fully analog implantable microstimulator,'' in IEEE Proc. ISCAS, May 2016, pp. 2435--2438.
[^7]: E.Moradi etal., ''Backscattering neural tags for wireless brain-machine interface systems,'' IEEE Trans. Antennas Propag., vol.63, no.2, pp. 719--726, Feb 2015.
[^6]: Y.K. Lo etal., ''A fully integrated wireless SoC for motor function recovery after spinal cord injury,'' IEEE Trans. Biomed. Circuits Syst., vol.11, no.3, pp. 497--509, June 2017.
[^11]: L.Leene, T.Constandinou etal., ''A 0.5 V time-domain instrumentation circuit with clocked and unclocked operation,'' in IEEE Proc. ISCAS, May 2017, pp. 2619--2622.
[^5]: C.M. Lopez etal., ''A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13$\mu$m SOI CMOS,'' IEEE Trans. Biomed. Circuits Syst., vol.11, no.3, pp. 510--522, June 2017.
[^4]: S.A. Mirbozorgi etal., ''A single-chip full-duplex high speed transceiver for multi-site stimulating and recording neural implants,'' IEEE Trans. Biomed. Circuits Syst., vol.10, no.3, pp. 643--653, June 2016.
[^12]: H.Kassiri etal., ''27.3 all-wireless 64-channel 0.013mm$^2$/ch closed-loop neurostimulator with rail-to-rail DC offset removal,'' in IEEE Proc. ISSCC, Feb 2017, pp. 452--453.
[^2]: D.A. Schwarz etal., ''Chronic, wireless recordings of large-scale brain activity in freely moving rhesus monkeys,'' Nature Methods, vol.11, pp. 670--676, April 2014.
[^15]: M.H. Cho etal., ''Development of undervoltage lockout (UVLO) circuit configurated schmitt trigger,'' in IEEE Proc. ISOCC, Nov 2015, pp. 59--60.
[^14]: G.Giustolisi and G.Palumbo, ''A detailed analysis of power-supply noise attenuation in bandgap voltage references,'' IEEE Trans. Circuits Syst. I, vol.50, no.2, pp. 185--197, Feb 2003.
[^13]: Y.Osaki, T.Hirose, N.Kuroki, and M.Numa, ''1.2-V supply, 100-nW, 1.09-V bandgap and 0.7-V supply, 52.5-nW, 0.55-V subbandgap reference circuits for nanowatt CMOS LSIs,'' IEEE J. Solid-State Circuits, vol.48, no.6, pp. 1530--1538, June 2013.
[^10]: S.Houri etal., ''Limits of CMOS technology and interest of NEMS relays for adiabatic logic applications,'' IEEE Trans. Circuits Syst. I, vol.62, no.6, pp. 1546--1554, June 2015.
[^3]: S.B. Lee etal., ''An inductively-powered wireless neural recording system with a charge sampling analog front-end,'' IEEE Sensors J., vol.16, no.2, pp. 475--484, Jan 2016.

137
content/publications/2018/direct-digital-wavelet-synthesis-for-embedded-biomedical-microsystems.md Normal file
View File

@ -0,0 +1,137 @@
---
title: "Direct Digital Wavelet Synthesis for Embedded Biomedical Microsystems"
date: 2018-10-17T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
- publication
- CMOS
- digital-logic
- signal-synthesis
- wavelets
---
Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
This paper presents a compact direct digital wavelet synthesizer for extracting phase and amplitude data from cortical recordings using a feed-forward recurrent digital oscillator. These measurements are essential for accurately decoding local-field-potentials in selected frequency bands. Current systems extensively to rely large digital cores to efficiently perform Fourier or wavelet transforms which is not viable for many implants. The proposed system dynamically controls oscillation to generate frequency selective quadrature wavelets instead of using memory intensive sinusoid/cordic look-up-tables while retaining robust digital operation. A MachXO3LF Lattice FPGA is used to present the results for a 16 bit implementation. This configuration requires 401 registers combined with 283 logic elements and also accommodates real-time reconfigurability to allow ultra-low-power sensors to perform spectroscopy with high-fidelity.
# 2 Introduction
Spectrum analysis is an essential tool for many biomedical applications to provide electrode impedance characteristics[^2][^1] and assist in signal decomposition for brain machine interfaces (BMI)[^4][^3]. These techniques typically rely on generating a precise reference tone to characterise the spectral power distribution of a signal or analyse the frequency dependent response of a subsystem. However generating a sinusoid demands a significant mount of valuable hardware resources for both analogue[^5] and digital[^6] implementations and can inhibit an efficient solution. For this reason numerous techniques such as ΔΣ\:modulation[^7] and closed loop adaptive filtering[^8] have been proposed to reduce system integration costs and enhance the capability of biomedical sensing systems.
In line with these developments, this work proposes a hardware efficient direct digital wavelet synthesizer (DDWS) to extract both time and frequency information simultaneously. The DDWS extends on conventional direct digital frequency synthesis (DDFS) systems[^9] the same way the generalised s-transform[^10] extends on the Fourier transform by resolving the time-evolving frequency content of non-stationary signals. Current systems typically use the CT/DT wavelet-transform to extract this type of information because it is more hardware efficient than the windowed/short-time Fourier transform[^11]. However for applications like electrode-impedance spectroscopy and measuring phase synchrony in brain activity, wavelets cannot be used because the phase information is either not preserved or does not use a global reference leading to incomplete measurements. This presents an opportunity for mixed signal techniques to be used instead of resorting to transforms in the digital domain to extract time-frequency-phase signal components[^12]. The DDWS presents one approach to reduce hardware requirements for this type of measurement because it allows the direct extraction of a specific signal band but also appropriately decimates the output as each wavelet correlation yields a single result for that particular time-frame thereby reducing overall data rate.
{{< figure src="/images/biocas2018/concept.svg" title="Figure 1: Instrumentation system that extracts non-stationary frequency components from electrode recordings using wavelets that are generated by the proposed DDWS." width="500" >}}
The overall system architecture is shown in Fig. 1. This represents the front-end for a local-field-potential decoding system for BMIs[^13]. After amplification the electrode potential is mixed with two quadrature wavelets that have 50% overlapping time-frames. Similar to conventional spectroscopy[^6], the phase and amplitude can be recovered for each frame by evaluating the down-converted DC-component and will correspond to the frequency band set by the DDWS configuration. The DDWS will generate timing information for each frame that can be used to reset an analogue integrator that proceeds the mixing process and accurately extract the DC value. The proposed topology follows the principle of analogue-to-information conversion where the input signal is mixed linearly/non-linearly to maximally reduce the sampling speed of the data converter and optimise the spectral efficiency at the output. This alleviates the speed of signal conversion and digital processing. If the synthesis of these wavelets can be made highly resource efficient and programmable, several signal features can be directly extracted in the analogue domain by using multiple DDWS modules in parallel.
The rest of this paper if organised as follows: Sec 3 will introduce a recurrent digital oscillator core that forms the basis of the DDWS. Sec 4 describes the DDWS topology and Sec 5 presents synthesis data together with simulation results. Finally, Sec 6 will conclude this work.
# 3 A Feed-Forward Digital Oscillator Core
{{< figure src="/images/biocas2018/core.svg" title="Figure 2: Feed-forward digital oscillator showing the block diagram in (a) and the z-domain pole-zero plot of the feedback loop in (b) with decreasing k for a fixed frequency." width="500" >}}
There are a number of recursive oscillator topologies available in the literature with two identifiable basis; biquads and waveguides[^9]. The feed-forward structure proposed here is derived from the standard coupled quadrature structure that provides feedback with equi-amplitude quadrature outputs. This structure is shown in Fig. 2a. The feed-forward configuration uses two integrators in negative feedback with two coefficients f and k to specify frequency and Q-factor respectively. This will require the same number of coefficient multiplications as the coupled quadrature configuration but uses 4 2-input summation nodes opposed to 2. The benefit here is that there are only 2 scaling coefficients and they are linearly dependent on the desired oscillation frequency. The conventional structure has f²\:dependence that requires excessive integrator precision to accurately resolve very small frequencies typically of interest for biomedical signals.
$$ \begin{bmatrix}\hat{x}_Q \hat{x}_I\end{bmatrix} =\underbrace{\begin{bmatrix}(1-k f) & -f f & (1-k f)\end{bmatrix}}_{\mathbf{R}(k,f)}\cdot\begin{bmatrix}x_Q x_I\end{bmatrix} $$
Digital oscillators are usually characterised in terms of a rotation matrix \\(\mathbf{R}\\)(k,f) that is applied to two state variables x<sub>Q<sub> and x<sub>I<sub>. This representation is formulated in Eq. 1. For clarity the k²\: factor is ignored in this analysis since it yields a simpler solution to the basic feed-forward configuration. In this case we are interested in manipulating the pole location adaptively which is why we will solve for the complex pole positions of this dynamic system below.
$$ D_O(z) = f^2 \left(\frac{z^{-1}}{1-z^{-1}} \right)^2 + 2k f \frac{z^{-1}}{1-z^{-1}} $$
$$ denum\left(\frac{1}{1+D_O(z)}\right) = z^2 + (2 f k - 2)z + (f^2 - 2 f k + 1 ) $$
The z-domain representation of the open loop response D<sub>O<sub> is shown in Eq. 2 and the the corresponding expression for the denumerator of the closed loop response is shown in Eq. 3.
$$ \begin{split}poles\left(\frac{1}{1+D_O(z)}\right) = 1 - k f \pm √{ f^2 k^2 - f^2}\end{split} $$
Finding the poles yields the two solutions in Eq. 4 that correspond to the complex pair P\tss{Q/I} which dictate the oscillatory behaviour of this circuit. This reveals the behaviour shown in Fig. 2b which is that adjusting k will rotate the pole-pair in and out of the unit circle resulting in a growing or receding complex exponential or oscillation. It is also readily seen that for the case k=0 the pole locations lie outside the unit circle. Solving for a steady state solution where P\tss{Q/I} are on the unit circle gives k=f/2.
# 4 DDWS Core]{\\(\Delta\Sigma^2\\) type DDWS Core
In order to realise the proposed multiplier-free DDWS, two additional components will be introduced. The first is a second order digital ΔΣ \: modulator that will allow us to mitigate the need to for high-precision multipliers and the second is a controller module that will regulate the dynamic oscillatory behaviour given a set input parameters. This configuration is shown in Fig. 3 together with sub-blocks for amplitude tracking and noise shaping.
{{< figure src="/images/biocas2018/ddws-core.svg" title="Figure 3: Block diagram of the direct-digital wavelet synthesizer showing the system in (a), the amplitude tracking logic in (b) and the ΔΣ² \: modulator in (c)." width="500" >}}
Introducing a ΔΣ \: modulator is a well established means reduce hardware complexity for multiplication as the \\(\pm\\)1 single bit-stream implies that the coefficients (f & k) can be directly accumulated accordingly [^14]. This is particularly appropriate here because the typical clock speed will be at a substantially higher frequency than the signal bandwidth of interest. For biomedical systems these frequencies are almost always sub-10 kHz. Hence we can freely choose an oversampling ratio (OSR) according to our dynamic range requirement using DR=-11 dB+50 log(OSR)[^15].
The block diagram in Fig. 3 also includes logic for tracking the peak to peak amplitude of the internal oscillation. This is done by detecting zero-crossings of either integrator and latching the other that will at that moment be at the peak amplitude. The oscillation amplitude is used to control the dynamics of the wavelet generator and prevents saturation.
\begin{algorithm}
\DontPrintSemicolon
\KwIn{Wavelet synthesis parameters (f, c<sub>bw<sub>, ic, vpp)}
\KwResult{Quadrature bit-streams (D1\tss{Q/I}, D2\tss{Q/I})}
**Initialise:** x1<sub>Q<sub>=ic, x1<sub>I<sub>=0, x2<sub>Q<sub>=vpp/2, x2<sub>I<sub>=0, s1=c<sub>bw<sub>, s2=-c<sub>bw<sub>
\Begin{
\ShowLn
k1 = 0.5 + s1(D1<sub>PP<sub> - vpp)
k2 = 0.5 + s2(D2<sub>PP<sub> - vpp)
\\(\mathbf{x1}\\)\tss{Q/I}[n] = \\(\mathbf{R}\\)(k1,f) \\(\cdot\\) \\(\mathbf{x1}\\)\tss{Q/I}[n-1]
\\(\mathbf{x2}\\)\tss{Q/I}[n] = \\(\mathbf{R}\\)(k2,f) \\(\cdot\\) \\(\mathbf{x2}\\)\tss{Q/I}[n-1]
\uIf{ D1<sub>PP<sub> \textgreater vpp **or** $|\\(k1\\)|$ \textless c<sub>bw<sub>/2}{s1=-c<sub>bw<sub>}
\ElseIf{ D1<sub>PP<sub> \textless ic **and** s2\textless0 }{s1=c<sub>bw<sub>}
\uIf{ D2<sub>PP<sub> \textgreater vpp **or** $|\\(k2\\)|$ \textless c<sub>bw<sub>/2}{s2=-c<sub>bw<sub>}
\ElseIf{ D2<sub>PP<sub> \textless ic **and** s1\textless0 }{s2=c<sub>bw<sub>}
}
\BlankLine
\caption{DDWS Controller}
\label{algo:ddws-control}
\end{algorithm}
An overview of the control logic is described in Alg. 1. Here the notation from Eq. 1 is used to simplify how the oscillator states evolve by using the rotation matrix. In the behavioural implementation lines 5-6 are realised by a series of conditional statements that increment/decrement the oscillator states \\(\mathbf{x}\\)\tss{Q/I} and then compute the feed forward value by adding or subtracting k1/k2. Notice that we use the state variable s1/s2 to iteratively make sure only one oscillator is growing in amplitude while the other is shrinking in amplitude but at all times the growth is bounded by how close the peak to peak value is to the target maximum vpp. In fact several configurable parameters are used here in addition to vpp to specify the wavelet dynamics. Like before f controls the oscillation frequency in rads per second. The parameter ic determines the extinction ratio between the minimum and maximum oscillation amplitudes and c<sub>bw<sub> controls the window bandwidth together with ic to allow high or low out-of-band rejection.
Let us briefly identify the type of envelope modulation used here that allows these wavelets to perform time-frequency analysis. First it is important to point out that the phase state of each oscillator is not effected by small changes in k during operation. This means that the phase of the quadrature oscillator always accumulates with respect to the global reset. From our derivation in Sec 3 we can evaluate that, while s1/s2 does not change, the change in envelope can be expressed as Eq. 5 and which is resolved in Eq. 6 to show that the envelope has a sigmoid characteristic. In fact, As s1/s2 toggles the DDWS generates double sided sigmoid with a small discontinuity in the derivative the sinusoids that is proportional to c<sub>bw<sub>.
$$ \frac{dx(t)}{dt} = a x \cdot (b - x(t)) $$
$$ x(t) = \frac{b}{1+(b)e^{-a b x(t)}} $$
# 5 Implementation Results
A behavioural verilog model of the proposed wavelet generator has been implemented and synthesized using a low-power, small-footprint, LCMXO3LF FPGA device from Lattice Semiconductor and the Lattice Synthesis Engine (Version 3.10.2). The logic requirements and simulation results provide preliminary validation and can be further optimised given application constraints such as precision or resource limitations. The synthesis results are presented in Table 1 to show the relative hardware complexity for the 4-ΔΣ\: modulators, the two quadrature oscillators DX 1 & 2, and the top level FSM that controls the dynamics according to the input parameters. These requirements can be further compared using the pie chart in figure 4. Including the modulator hardware is useful if analogue requirements need to be relaxed to 1-bit digital-to-analogue conversion but this may not always be applicable. In fact, if a multi-bit output can be used instead, the modulators can be replaced by two multipliers to further optimise the resource requirements.
Table 1: Synthesis Summary
| Resource | LUT4 | Register | SLICE |
|----|----|----|----|
| FSM | 10 | 24 | 10 |
| DX \: (2x) | 5 | 217 | 125 |
| ΔΣ \: (4x) | 16 | 160 | 112 |
| DDWS Total | 31 | 401 | 252|
{{< figure src="/images/biocas2018/resource.svg" title="Figure 4: Resource distribution for the DDWS with the cost each sub-system annotated." width="500" >}}
Using a hypothetical configuration, the model was also simulated to demonstrate overall characteristics to filter out a specific 3.5 mHz normalised frequency band. The later implies that a 1.4 kHz system clock yields a 5 Hz center frequency. With reference to Algo \ref{algo:ddws-control} we used the following parameters: f=0.011, OSR=32, vpp=1, ic=2\\(^{-6}\\). In figure 5 c<sub>bw<sub>=2\\(^{-2}\\) and in figure 6 c<sub>bw<sub>=2\\(^{-6}\\) in order to show narrow and wide bandpass selection settings. Both figures show the time & frequency domain characteristics as well as the dynamic change in the pre-scaled feed-forward factor as the amplitude of oscillation increases before the controller changes state and starts suppressing the oscillation to near the end of the time window.
{{< figure src="/images/biocas2018/narrow.svg" title="Figure 5: Simulation result showing the transient output after decimation of the two quadrature bit-streams (top), the adaptive control of k (middle), and the frequency response of the generated wavelet. " width="500" >}}
{{< figure src="/images/biocas2018/wide.svg" title="Figure 6: Simulation result showing similar results as in figure 5 but with a smaller value of c<sub>bw<sub>." width="500" >}}
# 6 Conclusion
This work demonstrated a novel approach to generate wavelets using direct digital synthesis opposed to storing them in memory which is particularly useful for ultra-low-power medical devices that need to perform coherent time-resolved analysis of low frequencies. The synthesis results demonstrate that the dynamic approach avoids large memory requirements and digital complexity while retaining high precision frequency selection with reconfigurable bandwidths.
# Refernces:
[^11]: I.Daubechies, ''The wavelet transform, time-frequency localization and signal analysis,'' IEEE Trans. Inf. Theory, vol.36, no.5, pp. 961--1005, Sep 1990. [Online]: http://dx.doi.org/10.1109/18.57199
[^15]: R.Schreier, ''An empirical study of high-order single-bit delta-sigma modulators,'' IEEE Trans. Circuits Syst. II, vol.40, no.8, pp. 461--466, Aug 1993. [Online]: http://dx.doi.org/10.1109/82.242348
[^13]: A.Jackson and T.M. Hall, ''Decoding local field potentials for neural interfaces,'' IEEE Trans. Neural Syst. Rehabil. Eng., vol.25, no.10, pp. 1705--1714, Oct 2017. [Online]: http://dx.doi.org/10.1109/TNSRE.2016.2612001
[^10]: R.A. Brown, M.L. Lauzon, and R.Frayne, ''A general description of linear time-frequency transforms and formulation of a fast, invertible transform that samples the continuous S-Transform spectrum nonredundantly,'' IEEE Trans. Signal Process., vol.58, no.1, pp. 281--290, Jan 2010. [Online]: http://dx.doi.org/10.1109/TSP.2009.2028972
[^14]: C.Basetas, N.Temenos, and P.P. Sotiriadis, ''Comparison of recently developed single-bit all-digital frequency synthesizers in terms of hardware complexity and performance,'' in IEEE Proc. ISCAS, May 2018, pp. 1--5. [Online]: http://dx.doi.org/10.1109/ISCAS.2018.8351798
[^6]: A.Yufera etal., ''A tissue impedance measurement chip for myocardial ischemia detection,'' IEEE Trans. Circuits Syst. I, vol.52, no.12, pp. 2620--2628, Dec 2005. [Online]: http://dx.doi.org/10.1109/TCSI.2005.857542
[^5]: S.Rodriguez, S.Ollmar, M.Waqar, and A.Rusu, ''A batteryless sensor ASIC for implantable bio-impedance applications,'' IEEE Trans. Biomed. Circuits Syst., vol.10, no.3, pp. 533--544, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2456242
[^2]: A.Sun, A.G. Venkatesh, and D.A. Hall, ''A multi-technique reconfigurable electrochemical biosensor: Enabling personal health monitoring in mobile devices,'' IEEE Trans. Biomed. Circuits Syst., vol.10, no.5, pp. 945--954, Oct 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2016.2586504
[^12]: G.O'Leary etal., ''A recursive-memory brain-state classifier with 32-channel track-and-zoom $\Delta^2\Sigma$ ADCs and charge-balanced programmable waveform neurostimulators,'' in IEEE Proc. ISSCC, Feb 2018, pp. 296--298. [Online]: http://dx.doi.org/10.1109/ISSCC.2018.8310301
[^8]: M.Rajabzadeh, J.Becker, and M.Ortmanns, ''Evaluation of single-bit sigma-delta modulator DAC for electrical impedance spectroscopy,'' in IEEE Proc. BIOCAS, Oct 2017, pp. 1--4. [Online]: http://dx.doi.org/10.1109/BIOCAS.2017.8325063
[^7]: N.Ivanisevic, S.Rodriguez, and A.Rusu, ''Impedance spectroscopy systems: Review and an all-digital adaptive IIR filtering approach,'' in IEEE Proc. BIOCAS, Oct 2017, pp. 1--4. [Online]: http://dx.doi.org/10.1109/BIOCAS.2017.8325148
[^9]: C.S. Turner, ''Recursive discrete-time sinusoidal oscillators,'' IEEE Signal Process. Mag., vol.20, no.3, pp. 103--111, May 2003. [Online]: http://dx.doi.org/10.1109/MSP.2003.1203213
[^4]: Z.Zhang and K.K. Parhi, ''Low-complexity seizure prediction from iEEG/sEEG using spectral power and ratios of spectral power,'' IEEE Trans. Biomed. Circuits Syst., vol.10, no.3, pp. 693--706, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2477264
[^3]: S.R. Sridhara etal., ''Microwatt embedded processor platform for medical system-on-chip applications,'' IEEE J. Solid-State Circuits, vol.46, no.4, pp. 721--730, April 2011. [Online]: http://dx.doi.org/10.1109/JSSC.2011.2108910
[^1]: W.Franks, I.Schenker, P.Schmutz, and A.Hierlemann, ''Impedance characterization and modeling of electrodes for biomedical applications,'' IEEE Rev. Biomed. Eng., vol.52, no.7, pp. 1295--1302, July 2005. [Online]: http://dx.doi.org/10.1109/TBME.2005.847523

126
content/publications/2019/a-3rd-order-time-domain-delta-sigma-modulator-with-extended-phase-detection.md Normal file
View File

@ -0,0 +1,126 @@
---
title: "A 3rd order time domain delta sigma modulator with extended-phase detection"
date: 2019-05-26T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
- publication
- CMOS
- time-domain
- instrumentation
- circuit
---
Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
This paper presents a novel analogue to digital converter using an oscillator-based loop filter for high-dynamic range bio-sensing applications. This is the first third-order feed-forward ΔΣ modulator that strictly uses time domain integration for quantisation noise shaping. Furthermore we propose a new asynchronous extended-phase detection technique that increases the resolution of the 4 bit phase quantiser by another 5 bits to significantly improve both dynamic range and reduce the noise-shaping requirements. Preliminary simulation results show that this type of loop-filter can virtually prevent integrator saturation and achieves a peak 88 dB SNDR for kHz signals. The proposed system has been implemented using a 180 nm CMOS technology occupying 0.102 mm² and consumes 13.7 μ W of power to digitise the 15 kHz signal bandwidth using a 2 MHz sampling clock.
# 2 Introduction
Time and frequency based circuit techniques have received considerable interest in the recent years as a means to solve key challenges with integrating traditional analogue functionality into digital systems and take advantage of technology scaling [^1]. A feature in many of these developments relies on the ease by which an analogue voltage or current can be converted into time encoded signals using a simple digital ring oscillator that interfaces directly with standard logic elements. Generally time encoding implies that the analogue signal is represented by the time interval between digital events where we may use the frequency or phase difference to encode digital bit streams that are termed continuous time binary value (CTBV) signals.
In ADCs specifically, frequency readout carefully counts the number of oscillations relative to a precise reference clock period[^2] while phase readout digitises the relative phase difference of two matched oscillators using an array of phase detectors [^3]. Seemingly the advantage of using a counter is that the dynamic range of the output is more flexible in the sense that the counter depth is adjustable to realise low or high precision readout. In contrast phase readout directly relates the number of delay stages to the number of quantisation levels which makes high resolution phase quantisation resource intensive in the analogue sense as these delay stages should be matched to avoid off-sets and spurious tones. The advantage of the later is that the output is unary encoded with inherent mismatch averaging properties that simplifies the feedback circuitry during digital to analogue conversion [^3]. That said, effort has been made to improve the phase digitisation in other ways but has been limited to single bit improvements [^4] or constrains the system to use synchronous operation [^5].
Both readout techniques conventionally use synchronous circuits where the the timing information is latched which makes it difficult to further process signals in the time-domain without incurring quantisation noise. This can obstruct higher order noise shaping schemes although several solutions have already been proposed. For instance [^6] uses gated ring oscillators to realise a multi-stage noise shaping (MASH) topology and [^7] uses a higher-order analogue loop-filter to precede the oscillator to improve dynamic range. However both have yet to demonstrate the feasibility for high dynamic range data conversion and the analogue reliance limits the scalability of time-based operation in a way that is characteristically more useful for digital systems.
More recent work considers the use of asynchronous readout that may be able to process signals entirely in the time-domain with reduced analogue complexity [^10][^8][^9]. This is promising as a variety of specialised loop filter topologies can not be realised using synchronous prior art. Moreover asynchronous digital systems can utilise a number of power-saving techniques such as signal-activity dependent processing [^11] or event driven control to reduce complexity and speed up operation [^12].
{{< figure src="/images/iscas2019/td_sdm.svg" title="Figure 1: Block diagram of the third-order \\(\Sigma\Delta\\) instrumentation loop that uses time-domain integrator for noise shaping and an extended phase detector for high-resolution phase digitisation." width="500" >}}
The system proposed here is shown in Fig. 1. This represents a third-order time domain ΔΣ modulator that uses capacitive feedback to linearise the digitisation process similar to [^9]. The primary contributions here aim to make improvements in the overall dynamic range of time based ADCs that use oversampled noise shaping. The negative feedback mechanism uses the error signal appearing on V<sub>x<sub> to feed a cascade of oscillator-based integrators inside the continuous-time (CT) loop filter H(s) that accumulates quantisation errors. This is followed by a phase detector that digitises the phase difference of a pseudo-differential oscillator. The distinction is that the loop filter uses a feed-forward topology with better noise-shaping dynamics than prior-art together with an extended-phase-detector (EPD) that asynchronously accounts for phase overflow without incurring distortion. Both of these innovations result in higher dynamic range by performing higher-order quantisation noise-shaping and resolving the baseline phase state with a total precision of 9 bits.
This paper is organised as follows: Sec 3 will present the operating principle of oscillator-based ΔΣ modulation which guides the design for the proposed circuit described in Sec 4. Sec 5 will then demonstrate operating characteristics followed by Sec 7 that concludes this work.
# 3 Oscillator Based \\(\Delta\Sigma\\) Conversion
The design procedure of an oscillator based loop filter follows closely to that of conventional Gm-C based CT modulators as the anti-aliasing properties are retained with similar concerns for paracitic pole locations. The difference is that the small-signal currents are integrated by modulating the phase of a current controlled oscillator (CCO) instead of the voltage on a capacitor. This results in better output dynamic range as the oscillator based integrator can be full swing while Gm-C integrators usually have limited voltage-swing for intermediate stages to avoid non-linear behaviour of the proceeding stage. The large signal swing can be tolerated by using a digital current DAC inside intermediate integration stages that exhibit better linearity with a full-swing input. Arguably Gm-C integrators will exhibit better noise performance than current DACs which is why the first stage of the oscillator-based loop filter also uses a transconductor in sub-threshold operation to maximise noise efficiency of the overall system.
$$ \phi (t) = \frac{f_{osc}}{I_{bias}} \int_{-\infty}^{t} i_{\Delta}(\tau) \: d\tau $$
As a basis for oscillator based circuits, Equation 1 formulates the small-signal phase response φ(t) of a CCO in terms of the oscillation frequency f<sub>osc<sub>, the static bias current I<sub>bias<sub>, and the small-signal current input i\tss{Δ}[^13]. This simply tells us that the total amount of charge injected over time is accumulated and scaled by an integration factor. It is interesting to note that φ\: is dimensionless and represents a unit of time relative to the oscillator period. The signal driving this circuit is typically a transconductor or a current-steering DAC while the output φ\: can be read using a phase detector. Realising the loop filter uses the coefficients from an optimised CT-ΔΣ signal flow-graph for a 16 level quantiser and scales the transconductive elements according for a given set of oscillator frequencies.
While this integration property is well established, it is important to point out that the oscillator output is inherently discretised in the value domain in a non-linear fashion before it is clocked. This process generates distortion tones at harmonics of the oscillation frequency and can be interpreted in terms of a pulse-width-modulation process. Consolidating the impact of these out-of-band spurs does not have an established framework for analysis for more complex oscillator configurations and extensively relies on simulator based validation. Some progress has been made for analysing open loop configurations[^14] that use frequency readout. In a closed loop environment however the oscillator frequency is not stationary but instead modulated by the signal and quantisation errors which is in turn dithered by the oscillation. The main concern here is down conversion of tones into the signal band although they are actively suppressed during closed loop operation. Choosing co-prime frequency ratios through scaled bias currents such as 2:3:13 as is used here is best way to avoid undesirable oscillator interaction.
# 4 Circuit Implementation
The proposed instrumentation circuit can be split into three sub-circuits and will be detailed following the sequence by which the analogue input signal is processed. The first stage is the capacitive feedback structure shown in Fig. 2. This figure shows the input analogue signal being chopped and coupled though C<sub>IN<sub> while a capacitor array also feeds the chopped digital codes which will allow the flicker noise of the input-transconductor to be modulated out of the signal-band. The digitised output Q\tss{9-5} uses binary weighting while the PWM signals \\(\Phi\\)\tss{1-15} use unary weighting and together they evaluate the quantisation error. The PWM encoded signals \\(\Phi\\)\tss{1-15} are used to compute the remaining binary least-significant codes for Q\tss{4-1} seen at the ADC output. The unary weighting averages out any mismatch components and will also assist in performing foreground calibration of binary weighted DAC by correlating the output derivative code transitions in Q\tss{9-5}[^15].
{{< figure src="/images/iscas2019/td_cdac.svg" title="Figure 2: Capacitive feedback network that resolves the error signal when comparing the analogue input with the digitised output." width="500" >}}
The error signal on the capacitive DAC can be directly applied to the loop filter used here. This structure is shown in Fig. 3. The first stage of the feed-forward topology is a high-power transconductor that boosts the noise efficiency factor of this structure and dominates the overall noise performance as it directly drives the first and last differential oscillator through the current biasing terminal. All oscillating taps of X\tss{1-2} are buffered and processed by a XOR phase-detector to evaluate the phase-state. This controls the current-output from each DAC and enables us to cascade several time-based integrators without inducing quantisation errors or requiring strict digital timing requirements. It is important to point out that in this case the extended phase-detection is only applied to the last integrator and thus the limited dynamic range of X\tss{1-2} can result in undesirable modulator dynamics for high-frequency inputs. For this reason the second-order integration component is derived by feeding the first integration state forward instead of the input component. In addition the last oscillator presents a \\(4\times\\) smaller integration load thereby inducing additional gain at the output. This strategy is also found in conventional CT-\\(\Delta\Sigma\\) modulators as its allows the integration constants for the first two stages to be reduced giving more headroom for signal dynamics.
{{< figure src="/images/iscas2019/td_lf.svg" title="Figure 3: Configuration of the third-order modulator that uses a cascade of integrators with feed-forward compensation." width="500" >}}
Fig. 4 shows the circuit implementation of the EPD that similarly monitors each oscillating tap of X<sub>3<sub>. Clearly the phase difference is also being detected using an XOR gate however this circuit also generates overflow and underflow events as UP and DN signals. These are generated by combining a double-edge sensitive flip-flop with time-domain processing to perform level detection[^13]. The principle of operation here is that the Q<sub>5<sub> will always track whichever oscillator in the differential structure is leading. When the XOR gate indicates a change has occurred, a phase-overflow will be triggered when the AND level detector is high otherwise the NOR level detector triggers a phase-underflow. These events trigger a counter that will increment or decrement accordingly thereby also correcting Q<sub>5<sub> and setting the overflow event indicators low. In high-speed scenarios a unary counter can also be used to generate thermometer codes directly at the cost of added circuit complexity to speed up code transitions in the feedback DAC.
{{< figure src="/images/iscas2019/td_epd.svg" title="Figure 4: Schematic of the extended-phase read-out circuit that extracts both phase information and detects cycle over-flow for the N<sup>th<sup> section." width="500" >}}
Fig. 5 shows the internal EPD signals during closed loop operation to clarify the circuit behaviour. This also shows that several phase-overflow events can be generated as X<sub>3<sub> undergoes cycle slipping. Note that only the digital output is clocked and the internal counter state generates Q asynchronously in response to these events. Due to quantisation noise modulation multiple UP/DN events can be generated but this configuration processes the digital control in a feed-forward manner allowing tight timing control to guarantee a glitch free output. This is done by using a 2 ns window during every rising clock edge that holds the UP/DN signal in a tri-state to prevent latching invalid counter codes.
{{< figure src="/images/iscas2019/transition.svg" title="Figure 5: Transient waveform showing from top to bottom the pseudo differential oscillator output in volts, the phase-overflow trigger signal, and the two digital output codes \\(\Phi\\)1-15 & Q9-5." width="500" >}}
Table 1: Performance summary and comparison with state of the art
| Specification | This Work | [^9] | [^8] | [^7] | [^16] | [^4] | [^17] | [^3] |
|----|----|----|----|----|----|----|----|----|
| Year | 2018 | 2018 | 2018 | 2018 | 2017 | 2017 | 2015 | 2008 |
| Tech.[nm] | 180 | 65 | 130 | 65 | 40 | 130 | 180 | 130 |
| Supply[V] | 1.8/1.2 | 0.5 | 1.8 | - | 0.6 | 1.2 | 5/1.8 | 1.2 |
| Power[W] | 13.6μ | 1.28μ | 0.56m | 51.8m | 3.3μ | 1.05m | 140μ | 40m |
| Phase/Freq. | Φ-VCO | Φ-VCO | F-VCO | Φ-VCO | - | Φ-VCO | F-VCO | Φ-VCO |
| Calibration | Yes | No | No | Yes | No | No | No | No |
| NS-Order | 3 | 1 | 2 | 3 | 1 | 1 | 2 | 1 |
| OSR | 64 | 128 | 500 | 15 | 83k | 313 | 64k | 100 |
| BW[Hz] | 15.6k | 11k | 20k | 50M | 150 | 0.4M | 1.25 | 10M |
| SNDR[dB] | 88 | 54 | 77 | 72 | 56 | 83 | 73 | 72 |
| Area[mm²] | 0.102 | 0.006 | 0.04 | 0.35 | 0.015 | 0.13 | 0.36 | 0.01 |
| FoM<sub>S<sub>[dB] | 178(^\star) | 153 | 152 | 162 | 133 | 169 | 97 | 156 |
\\(^\star\\) Estimated based on simulation results where FoM<sub>S<sub> = SNDR + 10log<sub>10<sub>(BW/P).
# 5 Simulation Results
The time domain modulator presented here has been designed and validated using a commercially available 180 nm TSMC technology (1P6M HV BCD GEN II). The ADC core is configured to use a 1.8 V analogue supply to power the low noise transconductor as well as perform current biasing for each of the switched current DAC while using a 500 nA external reference current. The 1.8 V supply is also used as reference voltage when the digital codes are coupled onto V<sub>X<sub> using an array of level shifters since all the digital logic runs at 1.2 V to save power. A differential 2 kHz sinusoid at -3 dBFS (900 mVpp) is used during transient simulations to show preliminary performance characteristics. Fig. 6 shows one cycle where all three integrators are processing quantisation errors that are accumulated in X<sub>3<sub>. This also shows X<sub>3<sub> rapidly overflowing multiple times while triggering increments in the binary codes. At maximum input swing the speed is limited due to the slewing of X<sub>3<sub> but we do not expect such rapid signal dynamics for our application. Instead this extended dynamic range will capture drift and electrode offset components while the artefacts are typically 10 to 100 mV that the modulator can track at full-speed. The photo in Fig. 7 shows the floor plan as well as the layout of the fabricated prototype.
{{< figure src="/images/iscas2019/sim_tran.svg" title="Figure 6: Simulation result transient behaviour of the time based integration where each phase state is asynchronously PWM encoded but only the output X<sub>3<sub> uses extended phase detection to allow overflow." width="500" >}}
{{< figure src="/images/iscas2019/floor_plan.svg" title="Figure 7: Micro-photograph showing labelled blocks in relation to the schematics in Sec. 4." width="500" >}}
The spectral characteristics are summarised in Fig. 8. We can observe that third-order noise shaping can be achieved but some of the oscillator spurs are still present in high-frequency bands. However the components close to the signal band are significantly suppressed. The oscillator frequencies have also been annotated where X1 is around 78 kHz, X2 is around 117 kHz, and X3 is around 507 kHz. The chopper tones are still present outside the signal band since no off-set cancellation is performed which will be considered at a later point. The performance metrics are compared with other time based data converters in Table 1. While the figure of merit (FOM) seems to favour this work, the calibration mechanism is not yet integrated and measurements will need to confirm the these figures using a prototype that is currently in the process of being fabricated.
{{< figure src="/images/iscas2019/sim_thd.svg" title="Figure 8: Simulation result showing the noise-shaped output spectrum from a -3 dBFS input sinusoid at 2 kHz." width="500" >}}
# 6 Acknowledgement
This work was supported by the UK Engineering and Physical Sciences Research Council (EPSRC) grants EP/M020975/1 & EP/R024642/1.
# 7 Conclusion
We have presented the implementation and operation of a third-order ΣΔ ADC that uses an oscillator based loop filter with extended phase detection. As a result this work shows a significant improvement in precision over prior-art that strictly uses time-based signal processing. While the preliminary results show the performance for an analogue 180 nm CMOS technology, the digital operation of these circuits will enable these ideas to easily be adopted in a modern digital process or target high-speed applications. More importantly this work demonstrates that asynchronous time domain systems can be configured to achieve well over 80 dB dynamic range and realise intergrators that will not induce distortion due to saturation or phase-overflow.
# Refernces:
[^17]: P.Prabha etal., ''A highly digital VCO-based ADC architecture for current sensing applications,'' IEEE J. Solid-State Circuits, vol.50, no.8, pp. 1785--1795, Aug 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2414428
[^7]: S.Dey, K.Reddy, K.Mayaram, and T.S. Fiez, ''A 50 MHz BW 76.1 dB DR two-stage continuous-time delta-sigma modulator with VCO quantizer nonlinearity cancellation,'' IEEE J. Solid-State Circuits, vol.53, no.3, pp. 799--813, March 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2777455
[^2]: R.Naiknaware, H.Tang, and T.S. Fiez, ''Time-referenced single-path multi-bit $\Delta \Sigma$ ADC using a VCO-based quantizer,'' IEEE Trans. Circuits Syst. II, vol.47, no.7, pp. 596--602, July 2000. [Online]: http://dx.doi.org/10.1109/82.850418
[^3]: M.Z. Straayer and M.H. Perrott, ''A 12 bit, 10 MHz bandwidth, continuous-time $\Sigma\Delta$ ADC with a 5 bit, 950 MS/s VCO-based quantizer,'' IEEE J. Solid-State Circuits, vol.43, no.4, pp. 805--814, April 2008. [Online]: http://dx.doi.org/10.1109/JSSC.2008.917500
[^16]: R.Mohan etal., ''A 0.6 V, 0.015 mm sqrd, time-based ECG readout for ambulatory applications in 40 nm CMOS,'' IEEE J. Solid-State Circuits, vol.52, no.1, pp. 298--308, Jan 2017. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2615320
[^10]: S.Ziabakhsh, G.Gagnon, and G.W. Roberts, ''A time-mode LDI-based resonator for a band-pass $\Delta\Sigma$ TDC,'' Aug 2017, pp. 1296--1299. [Online]: http://dx.doi.org/10.1109/MWSCAS.2017.8053168
[^8]: F.Cardes etal., ''0.04 mm sqrd 103 dB-A dynamic range second-order VCO-based audio $\Sigma\Delta$ ADC in 0.13 $\mu$m CMOS,'' IEEE J. Solid-State Circuits, vol.53, no.6, pp. 1731--1742, June 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2018.2799938
[^9]: L.B. Leene and T.G. Constandinou, ''A 0.006 mm sqrd 1.2 $\mu$W analog-to-time converter for asynchronous bio-sensors,'' IEEE J. Solid-State Circuits, vol.53, no.9, pp. 2604--2613, Sept 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2018.2850918
[^1]: G.W. Roberts and M.Ali-Bakhshian, ''A brief introduction to time-to-digital and digital-to-time converters,'' IEEE Trans. Circuits Syst. II, vol.57, no.3, pp. 153--157, March 2010. [Online]: http://dx.doi.org/10.1109/TCSII.2010.2043382
[^13]: L.B. Leene and T.G. Constandinou, ''Time domain processing techniques using ring oscillator-based filter structures,'' IEEE Trans. Circuits Syst. I, vol.64, no.12, pp. 3003--3012, Dec 2017. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2715885
[^14]: E.Gutierrez, L.Hernandez, F.Cardes, and P.Rombouts, ''A pulse frequency modulation interpretation of VCOs enabling VCO-ADC architectures with extended noise shaping,'' IEEE Trans. Circuits Syst. I, vol.65, no.2, pp. 444--457, Feb 2018. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2737830
[^12]: J.Beaumont, A.Mokhov, D.Sokolov, and A.Yakovlev, ''High-level asynchronous concepts at the interface between analog and digital worlds,'' IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.37, no.1, pp. 61--74, Jan 2018. [Online]: http://dx.doi.org/10.1109/TCAD.2017.2748002
[^11]: B.Schell and Y.Tsividis, ''A continuous-time ADC/DSP/DAC system with no clock and with activity-dependent power dissipation,'' IEEE J. Solid-State Circuits, vol.43, no.11, pp. 2472--2481, Nov 2008. [Online]: http://dx.doi.org/10.1109/JSSC.2008.2005456
[^15]: L.B. Leene and T.G. Constandinou, ''A 0.016 mm sqrd12 b $\Delta \Sigma$ SAR with 14 fJ/conv. for ultra low power biosensor arrays,'' IEEE Trans. Circuits Syst. I, vol.64, no.10, pp. 2655--2665, Oct 2017. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2703580
[^5]: W.Jiang etal., ''A ±50 mV linear-input-range VCO-based neural-recording front-end with digital nonlinearity correction,'' IEEE J. Solid-State Circuits, vol.52, no.1, pp. 173--184, Jan 2017. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2624989
[^4]: S.Li, A.Mukherjee, and N.Sun, ''A 174.3 dB FoM VCO-based CT $\Delta \Sigma$ modulator with a fully-digital phase extended quantizer and tri-level resistor DAC in 130 nm CMOS,'' IEEE J. Solid-State Circuits, vol.52, no.7, pp. 1940--1952, July 2017. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2693244
[^6]: W.Yu, J.Kim, K.Kim, and S.Cho, ''A time-domain high-order MASH $\Delta\Sigma$ adc using voltage-controlled gated-ring oscillator,'' IEEE Trans. Circuits Syst. I, vol.60, no.4, pp. 856--866, April 2013. [Online]: http://dx.doi.org/10.1109/TCSI.2012.2209298

135
content/publications/2019/a-68-rmu-w-31-ks-s-fully-capacitive-noise-shaping-sar-adc-with-102-db-sndr.md Normal file
View File

@ -0,0 +1,135 @@
---
title: "A 68 μW 31 kS/s fully-capacitive noise-shaping SAR ADC with 102 dB SNDR"
date: 2019-05-26T15:26:46+01:00
draft: false
toc: true
math: true
type: posts
tags:
- publication
- CMOS
- data-converter
- instrumentation
- circuit
---
Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB. We propose a novel fully-capacitive topology which allows for high-speed asynchronous conversion together with a background calibration scheme to reduce the oversampling requirement by 10\\(\times\\) compared to prior-art. A 0.18μ m CMOS technology is used to demonstrate preliminary simulation results together with analytic measures that optimise parameter and topology selection. The proposed system is able to achieve a FoM<sub>S<sub> of 183 dB for a maximum signal bandwidth of 15.6 kHz while dissipating 68 μ W from a 1.8 V supply. A peak SNDR of 102 dB is demonstrated for this rate with a 0.201 mm² \:area requirement.
# 2 Introduction
Analogue-to-digital converter (ADC) efficiency remains to be the highlight for many current developments in both industry and academia. It used to be the case that oversampling converters (ΔΣ ADCs) and successive-approximation register converters (SAR ADCs) found separate application domains where this factor peaks. State-of-the-art ADCs however have mixed these two digitisation techniques to improve performance beyond a 170 dB Schreier Figure-of-Merit (FoM<sub>S<sub>)[^5][^4][^3][^1][^2]. This trend is in-part driven by the growing bio-metric and bio-medical electronics market that necessitates low-power high dynamic-range signal acquisition as many phenomena of interest exhibit signal dynamics with several orders of magnitude in variation. For example a peripheral neuro-modulation device with digitally assisted artifact rejection[^6] requires over \\(>\\)100 dB of dynamic range to detect micro-volt level sensory neuron activity in the presence of large mili-volt level interference from stimulation or motor-unit activity which is the application of interest that motivated this work.
The emerging ADC topologies for bio-sensors use multi-stage noise shaping or pipe-lined operation where multiple quantisers are integrated together and the quantisation error of the first quantiser is either resolved by another quantiser after amplification or may be used directly with an alternate feedback mechanism to similarly resolve additional bits. The noise-shaping SAR (NS-SAR) [^2][^7] however adopts a different approach by sampling and converting the input multiple times while simultaneously employing multiple feedback mechanisms that up-modulate any conversion errors out of the signal bandwidth. In this way the signal can be resolved with much finer precision once the output is decimated and the out-of-band frequency components are filtered out.
{{< figure src="/images/iscas2019/sar_sys.svg" title="Figure 1: Block diagram of the proposed high-resolution data converter showing the SAR digital controller applying feedback through 3 separate capacitor arrays and is augmented by the switched-capacitor loop filter H(z\tps{-1})." width="500" >}}
Here we present a novel fully-capacitive NS-SAR topology using active higher-order noise shaping that achieves state-of-the-art efficiency for high resolution signal acquisition. The proposed configuration is shown in Fig. 1. This figure summarises which signals are processed by each block in a closed-loop fashion to resolve the sampled analogue input signal V<sub>IN<sub>. The main data-conversion mechanism is based on the conventional SAR controller that uses the comparator decisions K to successively set the MSB and LSB bits[^8]. However to augment this operation two separate noise-shaping mechanisms are added; one for quantisation noise, H(z\tps{-1}), and another for mismatch noise by means of data-weighted averaging (DWA) together with mismatch-error shaping techniques (MES).
The NS-SAR approach is advantageous because the first several bits can be resolved rapidly using SAR and the remaining bits are resolved using ΔΣ modulation over several samples with reduced oversampling-ratio (OSR) to yield a significant overall improvement in conversion efficiency. Reusing the sampling mechanism of the SAR allows the quantisation residue left on V<sub>DAC<sub> to be directly integrated by the loop filter H(z\tps{-1}) that off-sets future conversions and shapes the quantisation noise as 1/(1+H(z\tps{-1})). The main drawback here in comparison to high-resolution \rDS\: modulators is that, while the conversion is faster, the mismatch in the high-resolution DAC must be carefully mitigated. This is where the DWA[^9] and MES[^10] are introduced to eliminate mismatch errors. DWA manipulates the selection of elements used within the MSB capacitive DAC such that the capacitor mismatch is not only decorrelated from the input but is also shaped with a (1-z\tps{-1}) characteristic. The MES module in the LSB section directly off-sets the sampled input using past conversion results to realise a FIR feedback structure such as (1-z\tps{-1}) or (1-2z\tps{-1}+z\tps{-2}) high-pass characteristics to minimise signal-band noise components.
The rest of this paper is organised as follows; Sec. 3 will relate the main design parameters to conversion precision in relation to primary noise sources. Once these are established the circuit implementation is presented in Sec. 4 together with simulation results in Sec. 5 and Sec. 7 will then conclude this work.
# 3 NS-SAR Design
Comparing with other data-converters, the NS-SAR topology is quite complex with a large number of design parameters that need to be optimised for efficient operation. Below, several of these parameters are discussed in relation to the ADC precision explaining the proposed configuration. Following the single-ended configuration shown in Fig. 1, we will estimate the expected sampling noise power (SNP), quantisation noise power (QNP), and mismatch noise power (MNP) for the signal bandwidth of fs/(2 OSR) where fs is the sampling speed. This formulation is purposely presented in brief since it based on established theory from [^11] but it does well to illustrate several trade-off considerations quantitatively when configuring this topology for a particular precision requirement.
$$ SNP \approx \frac{kT}{C_T} \cdot \frac{2.4}{OSR} $$
The expression in Eq. 1 should be a familiar representation for evaluating the input-referred sampling noise associated with a switched-capacitor integrator. In particular, this corresponds to the input being sampled with a total capacitive value of C<sub>T<sub> using kT as the Boltzman temperature factor. The second term simply arises from averaging the input over OSR cycles together with a correction factor of 2.4 due to the integrator topology in H(z\tps{-1})[^12]. Fig. 2 shows the estimated resolution for several capacitor values assuming we use an input sinusoid with maximum signal power (SP) given a 1.8 V ADC reference voltage as V<sub>DD<sub>. Inevitably, achieving high resolution implies a large sampling capacitance or a large oversampling ratio. Typically the former is preferred because increasing the capacitive load also decreases the mismatch power from the capacitive DACs.
$$ QNP \approx \underbrace{\left( V^2_{DD} e^{-3\tau} + \frac{V^2_{DD}}{2^{2N}} \right)}_{\text{SAR settling + quantisation }\epsilon} \cdot \frac{\pi^{2M}}{12 (1+2M) OSR^{1+2M}} $$
The expression in Eq. 2 parametrises the overall SAR resolution as N, the loop fillter order as M, and the number of time constants we allow the capacitive DAC to settle as τ \:in order to estimate QNP. This construction shows that settling and quantisation errors are shaped by the loop filter reducing the noise power by the term outside the brackets. Both in Fig. 3 and in the formulation we observe a strong dependency with regard to M as long as we provide sufficient settling time during SAR conversion. This result suggests that the noise-shaping feed-back must avoid driving the capacitive DAC with active amplifiers during successive-approximation to avoid slowing down the conversion speed or equivalently increasing the power requirement of each amplifier. We can also confirm here that the order of the loop filter does not need to be very high if the QNP needs to match the SNP.
$$ MNP \approx \underbrace{\left( \frac{\pi^2 2^{-2D}}{3 \cdot 2^K OSR^3} + \frac{\pi^{2E} 2^{-2K}}{(1+2E) OSR^{1+2E}} \right)}_{\text{DWA-MSB + MES-LSB DAC}} \frac{\sigma^2 V^2_{DD}}{3} $$
The MNP is evaluated in Eq. 3 with respect to the MES noise shaping order E, the number of bits D used to calibrate each capacitor in the MSB DAC in an idealised way. K represents the MSB DAC resolution in bits. Using a capacitor standard deviation \\(\sigma=0.5%\\) and K=4, the MNP of several configurations is shown in Fig. 4. The observation here is that for small OSR values the mismatch noise is typically dominated by the MSB DAC as the mismatch is not sufficiently shaped. It is relatively expensive to increase the number of elements in the MSB DAC since the scaling is linear and increasing the OSR diminishes the advantage of performing SAR. Instead we propose to calibrate the 15 capacitors in the MSB section as D will reduce the MNP more efficiently. The mismatch from the LSB section contains many more elements and is more effectively shaped using a second-order MES technique.
The above trends are used to optimise the FOM<sub>S<sub> in a similar fashion to [^3] by correlating hardware requirements with power and accuracy estimators for several configurations. Given an initial 18 bit target precision, we propose the following configuration: CT=50 pF, M=2,τ=5, K=5, D=4, E=2 with the OSR set to 16 to ease the decimation effort.
{{< figure src="/images/iscas2019/osr_snp.svg" title="Figure 2: ADC precision as a function of oversampling ratio with respect to SNP while varying sampling capacitance C<sub>T<sub>." width="500" >}}
{{< figure src="/images/iscas2019/osr_qnp.svg" title="Figure 3: ADC precision as a function of oversampling ratio with respect to QNP while varying settling times \\(\tau\\) and noise-shaping order M." width="500" >}}
{{< figure src="/images/iscas2019/osr_mnp.svg" title="Figure 4: ADC precision as a function of oversampling ratio with respect to MNP while varying calibration D and mismatch-shaping order E." width="500" >}}
# 4 Circuit Implementation
The analogue part of the ADC implementation is shown in Fig. 5. Note that the implemented ADC uses an equivalent fully-differential configuration to gain extra input-dynamic range as well as digital noise suppression. This realisation is entirely based on manipulating the capacitive DAC and enables low-power operation for varying sampling rates. A second distinguishing feature of the proposed topology is that the comparator only requires one input terminal opposed to two seen in prior-art [^2][^7] which leads to better linearity and noise performance. In addition the input is bottom plate sampled such that sensitivity to parasitic capacitance and comparator non-linearity is considerably reduced. This figure also shows three capacitor arrays where the DAC<sub>M<sub> section corresponds to the DWA modulated MSBs and the DAC\tss{L1/L2} section represents the MES modulated LSBs being fed back from the SAR controller. Implementing the second-order MES noise-shaping uses the ping-pong configuration from [^13].
{{< figure src="/images/iscas2019/sar_cdac.svg" title="Figure 5: Implementation of the capacitor network used to perform signal conversion using the bottom sampled capacitor arrays DAC<sub>M<sub> for the DWA bits and DAC<sub>L1<sub> & DAC<sub>L2<sub> for the MES bits. The loop filter is also shown where A<sub>1<sub> amplifies the quantisation residue that is then integrated by A<sub>2<sub> & A<sub>3<sub> for noise-shaping." width="500" >}}
Three switched-capacitor amplifiers are used to realise a second-order cascaded-feed-forward-integrator (CFFI) loop filter topology where the first stage provides auto-zeroing as well as signal amplification by \\(C_T/C_1\approx30\\). This design uses an asynchronous SAR conversion process [^14] which is why there are only 3 phases in the switched capacitor circuit; the sampling phase (SMP), the successive approximation phase (SAR), and the quantisation filtering phase (QNF). The SAR only takes 100 ns and the FSM immediately initiates the QNF phase reducing the input clock to twice the sampling rate. The three phases operate as follows:
\begin{enumerate}
\item[**SMP**] First A<sub>1<sub> actively samples its offset on the top plate while bottom plate samples V<sub>IN<sub> on DAC<sub>M<sub> together with the MES code on DAC\tss{L1/L2}. A\tss{2/3} are simultaneously integrating quantisation errors and sampling the result V\tss{X2/X3} with respect to V<sub>DAC<sub> on C<sub>6<sub> and C<sub>7<sub>.
\item[**SAR**] V<sub>DAC<sub> then converges to virtual ground by switching the input to DAC\tss{M/L1/L2} while quantisation errors from prior conversions are removed by grounding the bottom plate of C\tss{6/7}. This also disconnects A\tss{1/2/3} from V<sub>DAC<sub>.
\item[**QNF**] Finally DAC\tss{M/L1/L2} is held and the resulting quantisation residue left on V<sub>DAC<sub> is amplified by A{1} on V<sub>X1<sub>. C\tss{2/4} samples the voltages V\tss{X1/X2} which are used to integrate during the following SMP phase.
\end{enumerate}
This configuration scales well for varying loop filter structures as 80% of the power is dissipated by A<sub>1<sub> and the total sampling noise is dominated by C<sub>T<sub>. The comparator uses a conventional strong-arm topology that is carefully designed to minimise off-set since this off-set will be seen at the output of A<sub>3<sub> after amplification which can diminish the output-swing. Conversely the noise and distortion characteristics of the analogue filtering chain is proportionally reduced when the signal is fed back onto the capacitor array during sampling as the attenuation ratio \\(C_{6-7}/C_T\\) inverts the amplification ratio with good matching.
The MSB DAC calibration mechanism is uses a digital shuffling technique to identify mismatch by switching out different sets of capacitors that will only incur voltage fluctuation on V<sub>DAC<sub> in the presence of mismatch[^15]. These errors are then amplified by A<sub>1<sub> after the SAR & QNF process and digitally tunes each MSB capacitor using a capacitive sub-DAC. The sign of each shuffling result is accumulated to adjust the the 15 calibration codes thereby eliminating the mismatch in the MSB DAC. This process can be performed in the background without requirements on the input signal because DWA randomises the capacitor selection mechanism during shuffling.
Table 1: Performance summary and comparison with state of the art
| Spec. | This Work | [^16] | [^15] | [^4] | [^5] | [^3] | [^7] | [^2] |
|----|----|----|----|----|----|----|----|----|
| Year | 2018 | 2018 | 2018 | 2018 | 2018 | 2017 | 2016 | 2012 |
| Tech.[nm] | 180 | 180 | 180 | 28 | 40 | 180 | 55 | 65 |
| Supply[V] | 1.8 | 1.8 | 1.8/5 | 1.1/1.2 | 2.5/1.1 | 1.2 | 1.2 | 1.2 |
| Power[W] | 68μ | 7.93μ | 12.9m | 4.2m | 140μ | 5.16μ | 15.7μ | 806μ |
| Topology | NS-SAR | \rDS-SAR | SAR | CT-\rDS | \rDS-SAR | \rDS-SAR | NS-SAR | NS-SAR |
| DAC Res.[b] | 10 | 9 | 20 | 4 | 7 | 8 | 12 | 8 |
| NS-Order | 2(^\dagger) | 1 | 0 | 2(^\dagger) | 3 | 2 | 1(^\dagger) | 1(^\dagger) |
| OSR | 16 | 256 | 1 | 16 | 12 | 24 | 256 | 4 |
| BW[Hz] | 15.6k | 1k | 500k | 10M | 40k | 100k | 4k | 11M |
| SNDR[dB] | 102 | 85 | 102 | 94 | 84 | 67 | 96.1 | 62 |
| Area[mm²] | 0.201 | 0.68 | 4 | 0.1 | 0.07 | 0.02 | 0.07 | 0.03 |
| FoM<sub>S<sub>[dB] | 183(^\star) | 166 | 176 | 168 | 169 | 170 | 180 | 164 |
\\(^\star\\) Estimated based on post-layout simulation results where FoM<sub>S<sub> = SNDR + 10log<sub>10<sub>(BW/P). \\(^\dagger\\) FIR & digital noise-coupling poles excluded.
# 5 Simulation Results
The proposed NS-SAR has been designed and validated using a commercially available 180 nm TSMC technology (1P6M HV BCD GEN II). All sub-circuits have been integrated with reconfigurable ΔΣ, DWA, MES, and calibration modes to fully characterise post-silicon performance that will confirm the evaluation in Sec. 3. This circuit uses an analogue and digital supply at 1.8 V, a 1 μ A current reference to bias A\tss{1-3}, and a 0.9 V common-mode reference for V<sub>CM<sub>-based capacitor switching. Preliminary post-layout simulation results are shown in Fig. 6. This demonstrates the ADC can resolve 17 bits of precision without distortion while using an external clock of 1 MHz where one cycle is used to sample the input and one cycle is used for conversion plus quantisation noise shaping and another cycle is optionally used for background calibration. The last phase can be skipped if the MSB capacitors are already tuned to speed-up signal conversion to 31.25 kS/s since temperature and voltage variations over time during normal operation will typically not corrupt the calibrated capacitor characteristics.
{{< figure src="/images/iscas2019/sar_sim_thd.svg" title="Figure 6: Post-layout simulation result showing the noise-shaped output spectrum from a -3 dBFS input sinusoid at 6.5 kHz." width="500" >}}
{{< figure src="/images/iscas2019/sar_floor_plan.svg" title="Figure 7: ADC micro-photograph showing labelled blocks in relation to Fig 1 where the MES and DWA circuitry is included in the main digital core. Decoupling capacitors are placed over active circuitry or underneath active mim-caps." width="500" >}}
The layout for this ADC is shown in Fig. 7. A large majority of silicon area is dedicated towards the MSB capacitive array as the sampling noise must be suppressed. The switched capacitor integrator can be relatively small because the internal loop-filter gain reduces its sampling noise. The digital core takes up a considerable amount of area and power budget primarily as a result of using a 180 nm CMOS technology where more advanced technologies may lead to further improvements if the 1.8 V rating can be maintained. Each MSB capacitor is trimmed using a 8 bit sub-DAC that tunes about 5% of the 1.7 pF unit capacitance which accommodates well over 3σ of the expected capacitor mismatch as well as wafer level variations that may not be captured by the typical mismatch model. The performance measures for the proposed ADC are shown in Table 1. Again we highlight the fact that while all these works have highly optimised power budgets, this topology is able to achieve over 100 dB SNDR with a 10\\(\times\\) lower oversampling ratio than prior art for this level precision. While this does imply a marginally increased area requirement, the peak efficiency can be achieved over a greater span of sampling frequencies. Note that this particular TSMC process kit does not allow post-layout Monte-Carlo so the calibration will be validated using post-silicon results.
# 6 Acknowledgement
This work was supported by the UK Engineering and Physical Sciences Research Council (EPSRC) grants EP/M020975/1 & EP/R024642/1.
# 7 Conclusion
This works presents a 17 bit Noise Shaping SAR ADC with reduced oversampling ratio and a purely capacitive implementation which enables in state-of-the-art conversion efficiency over a large range of sampling frequencies. In comparison with conventional over-sampling ADCs simulation results suggest this NS-SAR is able to achieve 102 dB SNDR with substantially lower noise-shaping requirements with comparable or reduced circuit complexity while achieving better power efficiency. We also demonstrated a high-level parameter selection methodology that is used to optimise the FoM<sub>S<sub> and identify the factors limiting ADC precision.
# Refernces:
[^11]: S.Pavan, R.Schreier, and G.C. Temes, Understanding Delta-Sigma Data Converters.\hskip 1em plus 0.5em minus 0.4em elax IEEE, 2017. [Online]: http://dx.doi.org/10.1002/9781119258308
[^12]: R.Schreier, J.Silva, J.Steensgaard, and G.C. Temes, ''Design-oriented estimation of thermal noise in switched-capacitor circuits,'' IEEE Trans. Circuits Syst. I, vol.52, no.11, pp. 2358--2368, Nov 2005. [Online]: http://dx.doi.org/10.1109/TCSI.2005.853909
[^10]: M.Aboudina and B.Razavi, ''A new DAC mismatch shaping technique for sigma–delta modulators,'' IEEE Trans. Circuits Syst. II, vol.57, no.12, pp. 966--970, Dec 2010. [Online]: http://dx.doi.org/10.1109/TCSII.2010.2083172
[^13]: J.Liu, G.Wen, and N.Sun, ''Second-order DAC MES for SAR ADCs,'' IET Elec. Letters, vol.53, no.24, pp. 1570--1572, 2017. [Online]: http://dx.doi.org/10.1049/el.2017.3138
[^9]: B.H. Leung and S.Sutarja, ''Multibit sigma - delta A/D converter incorporating a novel class of dynamic element matching techniques,'' IEEE Trans. Circuits Syst. II, vol.39, no.1, pp. 35--51, Jan 1992. [Online]: http://dx.doi.org/10.1109/82.204108
[^8]: B.P. Ginsburg and A.P. Chandrakasan, ''500 MS/s 5 bit ADC in 65 nm CMOS with split capacitor array DAC,'' IEEE J. Solid-State Circuits, vol.42, no.4, pp. 739--747, April 2007. [Online]: http://dx.doi.org/10.1109/JSSC.2007.892169
[^5]: A.AlMarashli, J.Anders, J.Becker, and M.Ortmanns, ''A nyquist rate SAR ADC employing incremental sigma delta DAC achieving peak SFDR=107 dB at 80 kS/s,'' IEEE J. Solid-State Circuits, vol.53, no.5, pp. 1493--1507, May 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2776299
[^4]: I.Jang etal., ''A 4.2 mW 10 MHz BW 74.4 dB SNDR continuous-time delta-sigma modulator with SAR-assisted digital-domain noise coupling,'' IEEE J. Solid-State Circuits, vol.53, no.4, pp. 1139--1148, April 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2778284
[^3]: L.B. Leene and T.G. Constandinou, ''A 0.016 mm sqrd 12 b $\Delta\Sigma$ SAR with 14 fJ/conv. for ultra low power biosensor arrays,'' IEEE Trans. Circuits Syst. I, vol.64, no.10, pp. 2655--2665, Oct 2017. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2703580
[^1]: Y.Chae, K.Souri, and K.A.A. Makinwa, ''A 6.3 mu W 20 bit incremental zoom-ADC with 6 ppm INL and 1 mu V offset,'' IEEE J. Solid-State Circuits, vol.48, no.12, pp. 3019--3027, Dec 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2278737
[^16]: S.Choi etal., ''An 84.6 dB-SNDR and 98.2 dB-SFDR residue-integrated SAR ADC for low-power sensor applications,'' IEEE J. Solid-State Circuits, vol.53, no.2, pp. 404--417, Feb 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2774287
[^2]: Y.Shu, L.Kuo, and T.Lo, ''An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS,'' IEEE J. Solid-State Circuits, vol.51, no.12, pp. 2928--2940, Dec 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2592623
[^7]: J.A. Fredenburg and M.P. Flynn, ''A 90 MS/s 11 MHz bandwidth 62 dB SNDR noise-shaping SAR ADC,'' IEEE J. Solid-State Circuits, vol.47, no.12, pp. 2898--2904, Dec 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2217874
[^6]: A.E. Mendrela etal., ''A bidirectional neural interface circuit with active stimulation artifact cancellation and cross-channel common-mode noise suppression,'' IEEE J. Solid-State Circuits, vol.51, no.4, pp. 955--965, April 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2506651
[^15]: H.Li etal., ''A signal-independent background-calibrating 20 b 1 MS/S SAR ADC with 0.3ppm INL,'' in IEEE Proc. ISSCC, Feb 2018, pp. 242--244. [Online]: http://dx.doi.org/10.1109/ISSCC.2018.8310274
[^14]: R.Sekimoto etal., ''A 0.5 V 5.2 fJ/conversion-step full asynchronous SAR ADC with leakage power reduction down to 650 pW by boosted self-power gating in 40 nm CMOS,'' IEEE J. Solid-State Circuits, vol.48, no.11, pp. 2628--2636, Nov 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2274851

14
content/publications/2019/an-oscillator-based-potentiostat-with-switch-cap-feedback-for-current-sensing-applications.md Normal file
View File

@ -0,0 +1,14 @@
---
title: "An Oscillator Based Potentiostat with Switch-Cap Feedback for Current Sensing Applications"
date: 2019-05-26T15:26:46+01:00
draft: true
toc: true
type: posts
math: true
tags:
- publication
- CMOS
- data-converter
- instrumentation
- circuit
---

13
content/publications/2019/towards-a-distributed-chronically-implantable-neural-interface.md Normal file
View File

@ -0,0 +1,13 @@
---
title: "Towards a distributed, chronically-implantable neural interface"
date: 2019-03-20T15:26:46+01:00
draft: true
toc: true
type: posts
math: true
tags:
- chapter
- packaging
- biomedical
- instrumentation
---

13
content/publications/2021/analogue-front-end-design-for-neural-recording.md Normal file
View File

@ -0,0 +1,13 @@
---
title: "Analogue Front-End Design for Neural Recording"
date: 2020-01-10T15:26:46+01:00
draft: true
toc: true
type: posts
math: true
tags:
- chapter
- circuit
- biomedical
- instrumentation
---

13
content/publications/2021/design-flow-for-hybrid-cmos-memristor-systems-part-i-modelling-and-verification-steps.md Normal file
View File

@ -0,0 +1,13 @@
---
title: "Design Flow for Hybrid CMOS/Memristor Systems—Part I: Modeling and Verification Steps"
date: 2021-11-13T15:26:46+01:00
draft: true
toc: true
math: true
type: posts
tags:
- publication
- CMOS
- process-integration
- memsistors
---

13
content/publications/2021/design-flow-for-hybrid-cmos-memristor-systems-part-ii-circuit-schematics-and-layout.md Normal file
View File

@ -0,0 +1,13 @@
---
title: "Design Flow for Hybrid CMOS/Memristor Systems—Part II: Circuit Schematics and Layout"
date: 2021-11-13T15:26:46+01:00
draft: true
toc: true
math: true
type: posts
tags:
- publication
- CMOS
- process-integration
- memsistors
---

201
content/resume.md Normal file
View File

@ -0,0 +1,201 @@
---
title: "Lieuwe Leene PhD. MSc. BEng."
date: 2021-08-23T17:52:07+02:00
draft: false
toc: true
tags:
- personal
- resume
- employment
---
Since 2019, I have been part of the [Novelda](https://novelda.com/) RFIC design
group where we design the most accurate human presence sensor in the world based
on ultra wide band technology. We are a team of 8 designing a IEEE 802.15
compliant single-chip solution for short-range radar applications using a
custom transceiver. I primarily work on the critical timing circuits for clock
redistribution, frequency scaling, and synchronization taking custom
mixed-signal circuits from concept and layout implementation all the way to
characterization and wafer sort planning.
Prior to 2019 I was with the [NGNI](https://www.imperial.ac.uk/next-generation-neural-interfaces)
lab at Imperial College London developing implantable medical devices
specialized for neuro-scientific studies and electroceutical therapies such as
deep-brain-stimulation and brain-machine-interfaces. I specialized in realizing
ultra-low-power instrumentation systems that can be implanted and innovated circuit
techniques for efficiently processing biomedical signals. Most of my success
came from applying time-domain techniques to realize sensing circuits with
exceptional dynamic range such that a wider variety of neurological components
can be picked up during recording or stimulation.
# Employment Record
{{< columns src="/images/about/novelda_logo_white.svg" >}}
```
Senior IC Design Engineer
IC Design Team Oslo Office,
Novelda AS Oslo, Norway
Aug. 2019 - Now
```
- Responsible for RF transceiver clocking module and phase locked loop design
for a Ultra-Wideband human presence sensor operating in the 7.8 GHz band.
- Acting as System and IP integration lead handling design delivery such as
netlist, layout, timing, and constraint files along with sign-off reports.
- Designing full-custom high-speed digital logic for both asynchronous and
timing critical modules.
{{< /columns >}}
{{< columns src="/images/about/IC_white.svg" >}}
```
Research Associate
Centre for Bio-Inspired Technology,
Imperial College London, United Kingdom
Dec. 2016 – Dec. 2019
```
- System architect for the ENGINI project worked towards a wireless
chip scale neural implant for chronic neuroscience and healthcare applications.
- CMOS fabrication and CAD tool integration lead for the FORTE project
which aims to integrate memristive devices with standard CMOS.
- Lead designer for ASIC implementation and defined target deliverables
Contributed to publications, grants, and the development of intellectual property
- Facilitated goal driven team management and technical project planning
Presented at conferences to communicate findings to the academic community
```
Analog Signal Processing Technical Committee Member
Centre for Bio-Inspired Technology,
Imperial College London, United Kingdom
Dec. 2015 – Dec. 2019
```
- Reviewed 40+ manuscripts in the past 5 years from JSSC, TCASI, TCASII, and TBCAS journals
- Facilitated ISCAS conference review process for selected analogue signal processing tracks
- Coordinated a ICECS conference special session on Oscillator Based Computing
```
Cadence System Administrator
Centre for Bio-Inspired Technology,
Imperial College London, United Kingdom
Sept. 2012 – Dec. 2019
```
- Served as contact for the maintenance of IT infrastructure for research group
- Provided support for computing solutions and tool configuration
- Maintained a Linux build for CAD tools (i.e. Cadence, Synopsys, Mentor, CST)
- Maintained process development kits for core IC technologies (TSMC, AMS, UMC)
```
Graduate Teaching Assistant
Department of Electrical and Electronic Engineering,
Imperial College London, United Kingdom
Sept. 2013 – Dec. 2018
```
- Supervised & mentored master student final year projects
- Assisted for laboratory/tutorial IC design sessions as demonstrator
- Assessed of oral and written work for EE4-20 & EE9-ALAB
- Lectured analogue IC design topics for EE4-20
{{< /columns >}}
{{< columns src="/images/about/hkust_logo.svg" >}}
```
Undergraduate Research Assistant
Department of Electrical and Electronic Engineering,
Hong Kong University of Science and Technology, China
Aug. 2010 – May 2011
```
- Project Topic: ASIC development for micro electrode array based testing platforms for the study of cell cultures involving low-noise front-end design and analogue-to-digital conversion.
```
Undergraduate Research Assistant
Department of Electrical and Electronic Engineering,
Hong Kong University of Science and Technology, China
Jun. 2010 – Dec. 2010
```
- Project Topic: Feasibility study of opto-mechanical CMOS structures for
detecting aerosol micro-particles actuated by photonics involving modelling
of micro-scale mechanical oscillators for phonon emission.
{{< /columns >}}
# Academic Record
{{< columns src="/images/about/IC_white.svg" >}}
```
PhD Electrical Engineering
Department of Electrical and Electronic Engineering,
Imperial College London, United Kingdom,
Sept. 2012 – Aug. 2016
```
- Engineering & Physical Sciences Research Council studentship (EPRC-1676620)
- Thesis Topic: Large scale integration of CMOS based sensors for brain machine interfaces.
```
MSc Analogue and Digital IC Design
Department of Electrical and Electronic Engineering,
Imperial College London, United Kingdom,
Sept. 2011 – Aug. 2012
```
- Graduated with Distinction
- Thesis Topic: Ultra-wideband radio and telemetry for medical implants
- Outstanding achievement prize for the MSc in A&D IC Design
- Integrated circuit design lab prize for the MSc in A&D IC Design
{{< /columns >}}
{{< columns src="/images/about/hkust_logo.svg" >}}
```
BEng Analogue and Digital IC Design
Department of Electrical and Electronic Engineering,
Hong Kong University of Science and Technology, China
Aug. 2008 – May 2011
```
- Graduated with First-Class Honours
- Thesis Topic: CMOS Instrumentation for biological in-vitro multi-electrode systems.
- Swire international young fellows program scholarship
{{< /columns >}}
# Personal Achievements
{{< columns src="/images/about/sscs_logo.svg" >}}
One of my main aspirations during my PhD was to publish in the prestigious
[IEEE Journal of Solid-State Circuits](https://sscs.ieee.org/publications/ieee-journal-of-solid-state-circuits-jssc)
which I successfully did 2018 on my second attempt. The publication presented
a voltage-controlled oscillator circuit for sensing neural activity with
integrated off-set rejection. The publication process took well over half a year
with the two rounds of peer-review in order to improve the article's presentation.
{{< /columns >}}
{{< columns src="/images/about/isa_logo.svg" >}}
In 2008, together with a couple of friends I founded the
[International Student Association](https://isa.hkust.edu.hk/) at HKUST which
as of 2022 is the 3rd largest student organization at the University. When
I started my studies in Hong Kong the international student community was still
relatively small and we mostly organized events among our selves. Encouraged
by the student-office we formed a group to represent the growing body of
international student and help each other adapt to the university lifestyle
away from home.
{{< /columns >}}

0
build.sh → scripts/build.sh
View File

0
static/images/replace_style.awk → scripts/replace_style.awk
View File

34
static/images/about/IC_black.svg Normal file
View File

@ -0,0 +1,34 @@
<?xml version='1.0' encoding='UTF-8'?>
<!-- This file was generated by dvisvgm 2.9.1 -->
<svg version='1.1' xmlns='http://www.w3.org/2000/svg' xmlns:xlink='http://www.w3.org/1999/xlink' width='361pt' height='95pt' viewBox='0 -95 361 95'>
<defs>
<clipPath id='clip1'>
<path d='M0 94.687501V0H360.922V94.687501Z'/>
</clipPath>
</defs>
<g id='page1'>
<g transform='matrix(1 0 0 -1 0 0)'>
<path d='M0 54.8477V92.78906H7.44141V54.8477H0Z' clip-path='url(#clip1)'/>
<path d='M18.3555 78.7539H18.4648C20.2578 81.1914 23.6836 82.6016 26.8008 82.6016C30.1211 82.6016 32.9688 81.2461 34.5547 78.7539C36.7734 80.918 40.1992 82.5469 43.3164 82.6016C49.2695 82.6563 52.3906 78.9141 52.4961 72.6836V54.9023H45.4727V71.3789C45.4727 74.5234 44.418 77.7734 40.9414 77.7734C37.5625 77.7734 35.4531 75.7188 35.4531 71.0039V54.8477H28.4336V71.3789C28.4336 75.1719 26.8008 77.7734 23.793 77.7734C20.4648 77.7734 18.4102 75.4453 18.4102 70.8398V54.8477H11.3945V81.9492H18.3555V78.7539Z' clip-path='url(#clip1)'/>
<path d='M63.3867 81.9492H56.375V41.2969H63.3867V58.2109C65.3438 55.8203 68.082 54.1992 71.2969 54.1992C78.8438 54.1992 83.5938 61.8398 83.5938 68.9961C83.5938 74.957 80.2188 82.6016 71.9375 82.6016C68.7695 82.6016 65.3438 80.9727 63.4922 78.2109H63.3867V81.9492ZM70.1406 78.2617C74.1484 78.2617 76.1523 73.6016 76.1523 68.9414C76.1523 64.1719 74.5742 58.5352 69.8789 58.5352C66.0781 58.5352 63.3867 62.3828 63.3867 68.0742C63.3867 74.3086 65.7109 78.2617 70.1406 78.2617Z' clip-path='url(#clip1)'/>
<path d='M110.641 67.75C111.16 75.8242 107.73 82.6016 99.5039 82.6016C91.9609 82.6016 86.0508 77.2891 86.0508 68.9414C86.0508 59.9961 92.0117 54.1992 99.9766 54.1992C102.984 54.1992 106.73 55.0664 110.316 57.2344L108.313 61.0273C106.574 59.7813 103.824 58.8555 101.242 58.8555C96.8633 58.8555 93.3867 62.6523 93.543 67.75H110.641ZM93.6484 71.6523C93.5977 75.2773 95.3867 78.5898 99.3984 78.5898C102.879 78.5898 104.305 75.7695 104.039 71.6523H93.6484Z' clip-path='url(#clip1)'/>
<path d='M120.988 77.1797H121.098L122.52 79.293C123.359 80.4336 124.895 82.6016 127.055 82.6016C128.641 82.6016 130.324 81.7305 131.805 80.1641L129.168 75.1719C128.008 75.7695 127.27 76.0977 125.844 76.0977C123.418 76.0977 121.039 74.0898 121.039 68.2383V54.8477H114.023V81.9492H120.988V77.1797Z' clip-path='url(#clip1)'/>
<path d='M133.367 90.07813C133.367 92.14063 135.055 94.250001 137.43 94.250001C139.855 94.250001 141.758 92.19141 141.758 90.07813C141.758 87.75 140.117 85.52734 137.531 85.52734C135.055 85.52734 133.367 87.75 133.367 90.07813ZM141.066 81.9492V54.8477H134.055V81.9492H141.066Z' clip-path='url(#clip1)'/>
<path d='M160.02 58.8047C160.02 57.3438 160.176 55.7695 160.699 54.8477H168.145C167.297 56.7461 167.031 59.293 167.031 61.4609V72.5156C167.031 80.9727 161.074 82.6016 156.219 82.6016C152.578 82.6016 149.363 81.6797 146.09 78.9141L148.355 75.5C150.203 77.125 152.316 78.2617 155.324 78.2617C157.594 78.2617 159.754 76.6914 160.121 74.1992L153.895 72.3008C147.773 70.5156 144.137 67.5859 144.137 62.4336C144.137 57.4531 147.563 54.1992 151.68 54.1992C154.105 54.1992 156.484 55.8789 158.438 57.4531L160.02 58.8047ZM160.121 70.5664C160.648 62.6016 157.016 59.0234 154.219 59.0234C152.527 59.0234 151.047 60.6484 151.047 63.0352C151.047 66.1211 152.789 68.1797 156.219 69.2695L160.121 70.5664Z' clip-path='url(#clip1)'/>
<path d='M171.414 54.8477V94.687501H178.426V54.8477H171.414Z' clip-path='url(#clip1)'/>
<path d='M224.734 85.90625C222.934 86.88281 219.93 88.01953 217.078 88.01953C209.484 88.01953 204 82.5469 204 73.9258C204 64.9297 210.066 59.6172 217.289 59.6172C220.141 59.6172 222.777 60.4336 224.734 61.5156L226.789 56.8008C224.523 55.4453 220.566 54.1992 216.977 54.1992C204.152 54.1992 196.082 62.8711 196.082 74.0352C196.082 84.3867 204.105 93.44141 217.078 93.44141C220.934 93.44141 224.523 92.03125 227.051 90.51172L224.734 85.90625Z' clip-path='url(#clip1)'/>
<path d='M240.711 54.1992C249 54.1992 254.582 60.3203 254.582 68.7227C254.582 77.5039 247.836 82.6016 240.711 82.6016C233.641 82.6016 226.891 77.5039 226.891 68.7227C226.891 60.3203 232.48 54.1992 240.711 54.1992ZM240.711 58.2109C235.699 58.2109 234.328 63.9531 234.328 68.7227C234.328 73.2227 235.91 78.5898 240.711 78.5898C245.617 78.5898 247.145 73.2227 247.145 68.7227C247.145 63.9531 245.828 58.2109 240.711 58.2109Z' clip-path='url(#clip1)'/>
<path d='M257.609 54.8477V94.687501H264.629V54.8477H257.609Z' clip-path='url(#clip1)'/>
<path d='M269.051 54.8477V94.687501H276.066V54.8477H269.051Z' clip-path='url(#clip1)'/>
<path d='M303.566 67.75C304.098 75.8242 300.668 82.6016 292.438 82.6016C284.895 82.6016 278.977 77.2891 278.977 68.9414C278.977 59.9961 284.941 54.1992 292.91 54.1992C295.914 54.1992 299.66 55.0664 303.254 57.2344L301.246 61.0273C299.508 59.7813 296.762 58.8555 294.176 58.8555C289.801 58.8555 286.313 62.6523 286.473 67.75H303.566ZM286.582 71.6523C286.523 75.2773 288.32 78.5898 292.328 78.5898C295.813 78.5898 297.234 75.7695 296.973 71.6523H286.582Z' clip-path='url(#clip1)'/>
<path d='M360.871 67.75C361.398 75.8242 357.973 82.6016 349.742 82.6016C342.195 82.6016 336.285 77.2891 336.285 68.9414C336.285 59.9961 342.246 54.1992 350.215 54.1992C353.223 54.1992 356.969 55.0664 360.555 57.2344L358.551 61.0273C356.809 59.7813 354.066 58.8555 351.48 58.8555C347.102 58.8555 343.625 62.6523 343.777 67.75H360.871ZM343.883 71.6523C343.832 75.2773 345.625 78.5898 349.637 78.5898C353.113 78.5898 354.543 75.7695 354.277 71.6523H343.883Z' clip-path='url(#clip1)'/>
<path d='M333.371 81.9492H326.352V78.6445H326.25C324.773 81.082 321.605 82.6016 318.387 82.6016C311.211 82.6016 306.145 75.7695 306.145 68.7227C306.145 60.0508 310.738 54.1992 317.754 54.1992C321.766 54.1992 324.508 56.4766 326.25 58.7539H326.352V55.1758C326.352 48.8867 322.766 45.9609 318.121 45.9609C314.535 45.9609 311.527 46.6641 308.945 48.2891L307.57 43.8477C310.684 42.2227 314.695 41.2969 318.648 41.2969C326.512 41.2969 333.371 45.2539 333.371 57.2852V81.9492ZM319.969 78.2617C324.191 78.2617 326.352 73.8711 326.352 69.1563C326.352 63.7383 324.348 58.5352 319.648 58.5352C315.59 58.5352 313.586 63.6289 313.586 68.8867S315.434 78.2617 319.969 78.2617Z' clip-path='url(#clip1)'/>
<path d='M0 38.5859H7.49219V5.7461H23.2656V.6484H0V38.5859Z' clip-path='url(#clip1)'/>
<path d='M64.4336 24.5508C66.9375 27.1523 70.4297 28.4023 73.9297 28.4023C80.4258 28.4023 83.5352 24.9297 83.5352 18.1016V.6484H76.4844V17.2852C76.4844 21.0781 74.7617 23.5742 70.9297 23.5742C67.3203 23.5742 64.4883 21.2461 64.4883 16.8008V.6484H57.4375V27.7461H64.4336V24.5508Z' clip-path='url(#clip1)'/>
<path d='M108.516 .6484H115.566V40.4805H108.516V24.6016H108.402C106.738 26.9922 103.52 28.4023 99.9102 28.4023C92.4688 28.4023 87.25 21.5703 87.25 14.5234C87.25 5.8516 92.0781 0 99.3555 0C103.688 0 106.574 2.2773 108.402 4.5547H108.516V.6484ZM101.797 24.0586C106.242 24.0586 108.516 19.668 108.516 14.957C108.516 9.5352 106.41 4.3359 101.465 4.3359C97.1914 4.3359 95.082 9.4297 95.082 14.6875C95.082 19.9414 97.0273 24.0586 101.797 24.0586Z' clip-path='url(#clip1)'/>
<path d='M133.895 0C142.609 0 148.492 6.125 148.492 14.5234C148.492 23.3008 141.391 28.4023 133.895 28.4023C126.449 28.4023 119.344 23.3008 119.344 14.5234C119.344 6.125 125.23 0 133.895 0ZM133.895 4.0117C128.621 4.0117 127.172 9.7539 127.172 14.5234C127.172 19.0195 128.836 24.3867 133.895 24.3867C139.059 24.3867 140.664 19.0195 140.664 14.5234C140.664 9.7539 139.281 4.0117 133.895 4.0117Z' clip-path='url(#clip1)'/>
<path d='M159.324 24.5508C161.824 27.1523 165.32 28.4023 168.816 28.4023C175.313 28.4023 178.426 24.9297 178.426 18.1016V.6484H171.375V17.2852C171.375 21.0781 169.652 23.5742 165.82 23.5742C162.215 23.5742 159.379 21.2461 159.379 16.8008V.6484H152.328V27.7461H159.324V24.5508Z' clip-path='url(#clip1)'/>
<path d='M38.8828 0C47.5977 0 53.4844 6.125 53.4844 14.5234C53.4844 23.3008 46.3789 28.4023 38.8828 28.4023C31.4414 28.4023 24.3359 23.3008 24.3359 14.5234C24.3359 6.125 30.2188 0 38.8828 0ZM38.8828 4.0117C33.6016 4.0117 32.1641 9.7539 32.1641 14.5234C32.1641 19.0195 33.8281 24.3867 38.8828 24.3867C44.0469 24.3867 45.6563 19.0195 45.6563 14.5234C45.6563 9.7539 44.2656 4.0117 38.8828 4.0117Z' clip-path='url(#clip1)'/>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 8.0 KiB

34
static/images/about/IC_blue.svg Normal file
View File

@ -0,0 +1,34 @@
<?xml version='1.0' encoding='UTF-8'?>
<!-- This file was generated by dvisvgm 2.9.1 -->
<svg version='1.1' xmlns='http://www.w3.org/2000/svg' xmlns:xlink='http://www.w3.org/1999/xlink' width='361pt' height='95pt' viewBox='0 -95 361 95'>
<defs>
<clipPath id='clip1'>
<path d='M0 94.687501V0H360.922V94.687501Z'/>
</clipPath>
</defs>
<g id='page1'>
<g transform='matrix(1 0 0 -1 0 0)'>
<path d='M0 54.8477V92.78906H7.44141V54.8477H0Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M18.3555 78.7539H18.4648C20.2578 81.1914 23.6836 82.6016 26.8008 82.6016C30.1211 82.6016 32.9688 81.2461 34.5547 78.7539C36.7734 80.918 40.1992 82.5469 43.3164 82.6016C49.2695 82.6563 52.3906 78.9141 52.4961 72.6836V54.9023H45.4727V71.3789C45.4727 74.5234 44.418 77.7734 40.9414 77.7734C37.5625 77.7734 35.4531 75.7188 35.4531 71.0039V54.8477H28.4336V71.3789C28.4336 75.1719 26.8008 77.7734 23.793 77.7734C20.4648 77.7734 18.4102 75.4453 18.4102 70.8398V54.8477H11.3945V81.9492H18.3555V78.7539Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M63.3867 81.9492H56.375V41.2969H63.3867V58.2109C65.3438 55.8203 68.082 54.1992 71.2969 54.1992C78.8438 54.1992 83.5938 61.8398 83.5938 68.9961C83.5938 74.957 80.2188 82.6016 71.9375 82.6016C68.7695 82.6016 65.3438 80.9727 63.4922 78.2109H63.3867V81.9492ZM70.1406 78.2617C74.1484 78.2617 76.1523 73.6016 76.1523 68.9414C76.1523 64.1719 74.5742 58.5352 69.8789 58.5352C66.0781 58.5352 63.3867 62.3828 63.3867 68.0742C63.3867 74.3086 65.7109 78.2617 70.1406 78.2617Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M110.641 67.75C111.16 75.8242 107.73 82.6016 99.5039 82.6016C91.9609 82.6016 86.0508 77.2891 86.0508 68.9414C86.0508 59.9961 92.0117 54.1992 99.9766 54.1992C102.984 54.1992 106.73 55.0664 110.316 57.2344L108.313 61.0273C106.574 59.7813 103.824 58.8555 101.242 58.8555C96.8633 58.8555 93.3867 62.6523 93.543 67.75H110.641ZM93.6484 71.6523C93.5977 75.2773 95.3867 78.5898 99.3984 78.5898C102.879 78.5898 104.305 75.7695 104.039 71.6523H93.6484Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M120.988 77.1797H121.098L122.52 79.293C123.359 80.4336 124.895 82.6016 127.055 82.6016C128.641 82.6016 130.324 81.7305 131.805 80.1641L129.168 75.1719C128.008 75.7695 127.27 76.0977 125.844 76.0977C123.418 76.0977 121.039 74.0898 121.039 68.2383V54.8477H114.023V81.9492H120.988V77.1797Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M133.367 90.07813C133.367 92.14063 135.055 94.250001 137.43 94.250001C139.855 94.250001 141.758 92.19141 141.758 90.07813C141.758 87.75 140.117 85.52734 137.531 85.52734C135.055 85.52734 133.367 87.75 133.367 90.07813ZM141.066 81.9492V54.8477H134.055V81.9492H141.066Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M160.02 58.8047C160.02 57.3438 160.176 55.7695 160.699 54.8477H168.145C167.297 56.7461 167.031 59.293 167.031 61.4609V72.5156C167.031 80.9727 161.074 82.6016 156.219 82.6016C152.578 82.6016 149.363 81.6797 146.09 78.9141L148.355 75.5C150.203 77.125 152.316 78.2617 155.324 78.2617C157.594 78.2617 159.754 76.6914 160.121 74.1992L153.895 72.3008C147.773 70.5156 144.137 67.5859 144.137 62.4336C144.137 57.4531 147.563 54.1992 151.68 54.1992C154.105 54.1992 156.484 55.8789 158.438 57.4531L160.02 58.8047ZM160.121 70.5664C160.648 62.6016 157.016 59.0234 154.219 59.0234C152.527 59.0234 151.047 60.6484 151.047 63.0352C151.047 66.1211 152.789 68.1797 156.219 69.2695L160.121 70.5664Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M171.414 54.8477V94.687501H178.426V54.8477H171.414Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M224.734 85.90625C222.934 86.88281 219.93 88.01953 217.078 88.01953C209.484 88.01953 204 82.5469 204 73.9258C204 64.9297 210.066 59.6172 217.289 59.6172C220.141 59.6172 222.777 60.4336 224.734 61.5156L226.789 56.8008C224.523 55.4453 220.566 54.1992 216.977 54.1992C204.152 54.1992 196.082 62.8711 196.082 74.0352C196.082 84.3867 204.105 93.44141 217.078 93.44141C220.934 93.44141 224.523 92.03125 227.051 90.51172L224.734 85.90625Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M240.711 54.1992C249 54.1992 254.582 60.3203 254.582 68.7227C254.582 77.5039 247.836 82.6016 240.711 82.6016C233.641 82.6016 226.891 77.5039 226.891 68.7227C226.891 60.3203 232.48 54.1992 240.711 54.1992ZM240.711 58.2109C235.699 58.2109 234.328 63.9531 234.328 68.7227C234.328 73.2227 235.91 78.5898 240.711 78.5898C245.617 78.5898 247.145 73.2227 247.145 68.7227C247.145 63.9531 245.828 58.2109 240.711 58.2109Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M257.609 54.8477V94.687501H264.629V54.8477H257.609Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M269.051 54.8477V94.687501H276.066V54.8477H269.051Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M303.566 67.75C304.098 75.8242 300.668 82.6016 292.438 82.6016C284.895 82.6016 278.977 77.2891 278.977 68.9414C278.977 59.9961 284.941 54.1992 292.91 54.1992C295.914 54.1992 299.66 55.0664 303.254 57.2344L301.246 61.0273C299.508 59.7813 296.762 58.8555 294.176 58.8555C289.801 58.8555 286.313 62.6523 286.473 67.75H303.566ZM286.582 71.6523C286.523 75.2773 288.32 78.5898 292.328 78.5898C295.813 78.5898 297.234 75.7695 296.973 71.6523H286.582Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M360.871 67.75C361.398 75.8242 357.973 82.6016 349.742 82.6016C342.195 82.6016 336.285 77.2891 336.285 68.9414C336.285 59.9961 342.246 54.1992 350.215 54.1992C353.223 54.1992 356.969 55.0664 360.555 57.2344L358.551 61.0273C356.809 59.7813 354.066 58.8555 351.48 58.8555C347.102 58.8555 343.625 62.6523 343.777 67.75H360.871ZM343.883 71.6523C343.832 75.2773 345.625 78.5898 349.637 78.5898C353.113 78.5898 354.543 75.7695 354.277 71.6523H343.883Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M333.371 81.9492H326.352V78.6445H326.25C324.773 81.082 321.605 82.6016 318.387 82.6016C311.211 82.6016 306.145 75.7695 306.145 68.7227C306.145 60.0508 310.738 54.1992 317.754 54.1992C321.766 54.1992 324.508 56.4766 326.25 58.7539H326.352V55.1758C326.352 48.8867 322.766 45.9609 318.121 45.9609C314.535 45.9609 311.527 46.6641 308.945 48.2891L307.57 43.8477C310.684 42.2227 314.695 41.2969 318.648 41.2969C326.512 41.2969 333.371 45.2539 333.371 57.2852V81.9492ZM319.969 78.2617C324.191 78.2617 326.352 73.8711 326.352 69.1563C326.352 63.7383 324.348 58.5352 319.648 58.5352C315.59 58.5352 313.586 63.6289 313.586 68.8867S315.434 78.2617 319.969 78.2617Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M0 38.5859H7.49219V5.7461H23.2656V.6484H0V38.5859Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M64.4336 24.5508C66.9375 27.1523 70.4297 28.4023 73.9297 28.4023C80.4258 28.4023 83.5352 24.9297 83.5352 18.1016V.6484H76.4844V17.2852C76.4844 21.0781 74.7617 23.5742 70.9297 23.5742C67.3203 23.5742 64.4883 21.2461 64.4883 16.8008V.6484H57.4375V27.7461H64.4336V24.5508Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M108.516 .6484H115.566V40.4805H108.516V24.6016H108.402C106.738 26.9922 103.52 28.4023 99.9102 28.4023C92.4688 28.4023 87.25 21.5703 87.25 14.5234C87.25 5.8516 92.0781 0 99.3555 0C103.688 0 106.574 2.2773 108.402 4.5547H108.516V.6484ZM101.797 24.0586C106.242 24.0586 108.516 19.668 108.516 14.957C108.516 9.5352 106.41 4.3359 101.465 4.3359C97.1914 4.3359 95.082 9.4297 95.082 14.6875C95.082 19.9414 97.0273 24.0586 101.797 24.0586Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M133.895 0C142.609 0 148.492 6.125 148.492 14.5234C148.492 23.3008 141.391 28.4023 133.895 28.4023C126.449 28.4023 119.344 23.3008 119.344 14.5234C119.344 6.125 125.23 0 133.895 0ZM133.895 4.0117C128.621 4.0117 127.172 9.7539 127.172 14.5234C127.172 19.0195 128.836 24.3867 133.895 24.3867C139.059 24.3867 140.664 19.0195 140.664 14.5234C140.664 9.7539 139.281 4.0117 133.895 4.0117Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M159.324 24.5508C161.824 27.1523 165.32 28.4023 168.816 28.4023C175.313 28.4023 178.426 24.9297 178.426 18.1016V.6484H171.375V17.2852C171.375 21.0781 169.652 23.5742 165.82 23.5742C162.215 23.5742 159.379 21.2461 159.379 16.8008V.6484H152.328V27.7461H159.324V24.5508Z' fill='#000d9e' clip-path='url(#clip1)'/>
<path d='M38.8828 0C47.5977 0 53.4844 6.125 53.4844 14.5234C53.4844 23.3008 46.3789 28.4023 38.8828 28.4023C31.4414 28.4023 24.3359 23.3008 24.3359 14.5234C24.3359 6.125 30.2188 0 38.8828 0ZM38.8828 4.0117C33.6016 4.0117 32.1641 9.7539 32.1641 14.5234C32.1641 19.0195 33.8281 24.3867 38.8828 24.3867C44.0469 24.3867 45.6563 19.0195 45.6563 14.5234C45.6563 9.7539 44.2656 4.0117 38.8828 4.0117Z' fill='#000d9e' clip-path='url(#clip1)'/>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 8.3 KiB

34
static/images/about/IC_white.svg Normal file
View File

@ -0,0 +1,34 @@
<?xml version='1.0' encoding='UTF-8'?>
<!-- This file was generated by dvisvgm 2.9.1 -->
<svg version='1.1' xmlns='http://www.w3.org/2000/svg' xmlns:xlink='http://www.w3.org/1999/xlink' width='361pt' height='95pt' viewBox='0 -95 361 95'>
<defs>
<clipPath id='clip1'>
<path d='M0 94.687501V0H360.922V94.687501Z'/>
</clipPath>
</defs>
<g id='page1'>
<g transform='matrix(1 0 0 -1 0 0)'>
<path d='M0 54.8477V92.78906H7.44141V54.8477H0Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M18.3555 78.7539H18.4648C20.2578 81.1914 23.6836 82.6016 26.8008 82.6016C30.1211 82.6016 32.9688 81.2461 34.5547 78.7539C36.7734 80.918 40.1992 82.5469 43.3164 82.6016C49.2695 82.6563 52.3906 78.9141 52.4961 72.6836V54.9023H45.4727V71.3789C45.4727 74.5234 44.418 77.7734 40.9414 77.7734C37.5625 77.7734 35.4531 75.7188 35.4531 71.0039V54.8477H28.4336V71.3789C28.4336 75.1719 26.8008 77.7734 23.793 77.7734C20.4648 77.7734 18.4102 75.4453 18.4102 70.8398V54.8477H11.3945V81.9492H18.3555V78.7539Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M63.3867 81.9492H56.375V41.2969H63.3867V58.2109C65.3438 55.8203 68.082 54.1992 71.2969 54.1992C78.8438 54.1992 83.5938 61.8398 83.5938 68.9961C83.5938 74.957 80.2188 82.6016 71.9375 82.6016C68.7695 82.6016 65.3438 80.9727 63.4922 78.2109H63.3867V81.9492ZM70.1406 78.2617C74.1484 78.2617 76.1523 73.6016 76.1523 68.9414C76.1523 64.1719 74.5742 58.5352 69.8789 58.5352C66.0781 58.5352 63.3867 62.3828 63.3867 68.0742C63.3867 74.3086 65.7109 78.2617 70.1406 78.2617Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M110.641 67.75C111.16 75.8242 107.73 82.6016 99.5039 82.6016C91.9609 82.6016 86.0508 77.2891 86.0508 68.9414C86.0508 59.9961 92.0117 54.1992 99.9766 54.1992C102.984 54.1992 106.73 55.0664 110.316 57.2344L108.313 61.0273C106.574 59.7813 103.824 58.8555 101.242 58.8555C96.8633 58.8555 93.3867 62.6523 93.543 67.75H110.641ZM93.6484 71.6523C93.5977 75.2773 95.3867 78.5898 99.3984 78.5898C102.879 78.5898 104.305 75.7695 104.039 71.6523H93.6484Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M120.988 77.1797H121.098L122.52 79.293C123.359 80.4336 124.895 82.6016 127.055 82.6016C128.641 82.6016 130.324 81.7305 131.805 80.1641L129.168 75.1719C128.008 75.7695 127.27 76.0977 125.844 76.0977C123.418 76.0977 121.039 74.0898 121.039 68.2383V54.8477H114.023V81.9492H120.988V77.1797Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M133.367 90.07813C133.367 92.14063 135.055 94.250001 137.43 94.250001C139.855 94.250001 141.758 92.19141 141.758 90.07813C141.758 87.75 140.117 85.52734 137.531 85.52734C135.055 85.52734 133.367 87.75 133.367 90.07813ZM141.066 81.9492V54.8477H134.055V81.9492H141.066Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M160.02 58.8047C160.02 57.3438 160.176 55.7695 160.699 54.8477H168.145C167.297 56.7461 167.031 59.293 167.031 61.4609V72.5156C167.031 80.9727 161.074 82.6016 156.219 82.6016C152.578 82.6016 149.363 81.6797 146.09 78.9141L148.355 75.5C150.203 77.125 152.316 78.2617 155.324 78.2617C157.594 78.2617 159.754 76.6914 160.121 74.1992L153.895 72.3008C147.773 70.5156 144.137 67.5859 144.137 62.4336C144.137 57.4531 147.563 54.1992 151.68 54.1992C154.105 54.1992 156.484 55.8789 158.438 57.4531L160.02 58.8047ZM160.121 70.5664C160.648 62.6016 157.016 59.0234 154.219 59.0234C152.527 59.0234 151.047 60.6484 151.047 63.0352C151.047 66.1211 152.789 68.1797 156.219 69.2695L160.121 70.5664Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M171.414 54.8477V94.687501H178.426V54.8477H171.414Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M224.734 85.90625C222.934 86.88281 219.93 88.01953 217.078 88.01953C209.484 88.01953 204 82.5469 204 73.9258C204 64.9297 210.066 59.6172 217.289 59.6172C220.141 59.6172 222.777 60.4336 224.734 61.5156L226.789 56.8008C224.523 55.4453 220.566 54.1992 216.977 54.1992C204.152 54.1992 196.082 62.8711 196.082 74.0352C196.082 84.3867 204.105 93.44141 217.078 93.44141C220.934 93.44141 224.523 92.03125 227.051 90.51172L224.734 85.90625Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M240.711 54.1992C249 54.1992 254.582 60.3203 254.582 68.7227C254.582 77.5039 247.836 82.6016 240.711 82.6016C233.641 82.6016 226.891 77.5039 226.891 68.7227C226.891 60.3203 232.48 54.1992 240.711 54.1992ZM240.711 58.2109C235.699 58.2109 234.328 63.9531 234.328 68.7227C234.328 73.2227 235.91 78.5898 240.711 78.5898C245.617 78.5898 247.145 73.2227 247.145 68.7227C247.145 63.9531 245.828 58.2109 240.711 58.2109Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M257.609 54.8477V94.687501H264.629V54.8477H257.609Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M269.051 54.8477V94.687501H276.066V54.8477H269.051Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M303.566 67.75C304.098 75.8242 300.668 82.6016 292.438 82.6016C284.895 82.6016 278.977 77.2891 278.977 68.9414C278.977 59.9961 284.941 54.1992 292.91 54.1992C295.914 54.1992 299.66 55.0664 303.254 57.2344L301.246 61.0273C299.508 59.7813 296.762 58.8555 294.176 58.8555C289.801 58.8555 286.313 62.6523 286.473 67.75H303.566ZM286.582 71.6523C286.523 75.2773 288.32 78.5898 292.328 78.5898C295.813 78.5898 297.234 75.7695 296.973 71.6523H286.582Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M360.871 67.75C361.398 75.8242 357.973 82.6016 349.742 82.6016C342.195 82.6016 336.285 77.2891 336.285 68.9414C336.285 59.9961 342.246 54.1992 350.215 54.1992C353.223 54.1992 356.969 55.0664 360.555 57.2344L358.551 61.0273C356.809 59.7813 354.066 58.8555 351.48 58.8555C347.102 58.8555 343.625 62.6523 343.777 67.75H360.871ZM343.883 71.6523C343.832 75.2773 345.625 78.5898 349.637 78.5898C353.113 78.5898 354.543 75.7695 354.277 71.6523H343.883Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M333.371 81.9492H326.352V78.6445H326.25C324.773 81.082 321.605 82.6016 318.387 82.6016C311.211 82.6016 306.145 75.7695 306.145 68.7227C306.145 60.0508 310.738 54.1992 317.754 54.1992C321.766 54.1992 324.508 56.4766 326.25 58.7539H326.352V55.1758C326.352 48.8867 322.766 45.9609 318.121 45.9609C314.535 45.9609 311.527 46.6641 308.945 48.2891L307.57 43.8477C310.684 42.2227 314.695 41.2969 318.648 41.2969C326.512 41.2969 333.371 45.2539 333.371 57.2852V81.9492ZM319.969 78.2617C324.191 78.2617 326.352 73.8711 326.352 69.1563C326.352 63.7383 324.348 58.5352 319.648 58.5352C315.59 58.5352 313.586 63.6289 313.586 68.8867S315.434 78.2617 319.969 78.2617Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M0 38.5859H7.49219V5.7461H23.2656V.6484H0V38.5859Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M64.4336 24.5508C66.9375 27.1523 70.4297 28.4023 73.9297 28.4023C80.4258 28.4023 83.5352 24.9297 83.5352 18.1016V.6484H76.4844V17.2852C76.4844 21.0781 74.7617 23.5742 70.9297 23.5742C67.3203 23.5742 64.4883 21.2461 64.4883 16.8008V.6484H57.4375V27.7461H64.4336V24.5508Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M108.516 .6484H115.566V40.4805H108.516V24.6016H108.402C106.738 26.9922 103.52 28.4023 99.9102 28.4023C92.4688 28.4023 87.25 21.5703 87.25 14.5234C87.25 5.8516 92.0781 0 99.3555 0C103.688 0 106.574 2.2773 108.402 4.5547H108.516V.6484ZM101.797 24.0586C106.242 24.0586 108.516 19.668 108.516 14.957C108.516 9.5352 106.41 4.3359 101.465 4.3359C97.1914 4.3359 95.082 9.4297 95.082 14.6875C95.082 19.9414 97.0273 24.0586 101.797 24.0586Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M133.895 0C142.609 0 148.492 6.125 148.492 14.5234C148.492 23.3008 141.391 28.4023 133.895 28.4023C126.449 28.4023 119.344 23.3008 119.344 14.5234C119.344 6.125 125.23 0 133.895 0ZM133.895 4.0117C128.621 4.0117 127.172 9.7539 127.172 14.5234C127.172 19.0195 128.836 24.3867 133.895 24.3867C139.059 24.3867 140.664 19.0195 140.664 14.5234C140.664 9.7539 139.281 4.0117 133.895 4.0117Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M159.324 24.5508C161.824 27.1523 165.32 28.4023 168.816 28.4023C175.313 28.4023 178.426 24.9297 178.426 18.1016V.6484H171.375V17.2852C171.375 21.0781 169.652 23.5742 165.82 23.5742C162.215 23.5742 159.379 21.2461 159.379 16.8008V.6484H152.328V27.7461H159.324V24.5508Z' fill='#fff' clip-path='url(#clip1)'/>
<path d='M38.8828 0C47.5977 0 53.4844 6.125 53.4844 14.5234C53.4844 23.3008 46.3789 28.4023 38.8828 28.4023C31.4414 28.4023 24.3359 23.3008 24.3359 14.5234C24.3359 6.125 30.2188 0 38.8828 0ZM38.8828 4.0117C33.6016 4.0117 32.1641 9.7539 32.1641 14.5234C32.1641 19.0195 33.8281 24.3867 38.8828 24.3867C44.0469 24.3867 45.6563 19.0195 45.6563 14.5234C45.6563 9.7539 44.2656 4.0117 38.8828 4.0117Z' fill='#fff' clip-path='url(#clip1)'/>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 8.2 KiB

285
static/images/about/hkust_logo.svg Normal file
View File

@ -0,0 +1,285 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
sodipodi:docname="hkust_logo.svg"
inkscape:version="1.0 (4035a4fb49, 2020-05-01)"
id="svg1051"
version="1.1"
viewBox="0 0 69.821869 16.87047"
height="16.87047mm"
width="69.821869mm">
<defs
id="defs1045" />
<sodipodi:namedview
inkscape:window-maximized="1"
inkscape:window-y="-8"
inkscape:window-x="-8"
inkscape:window-height="1027"
inkscape:window-width="1920"
fit-margin-bottom="0"
fit-margin-right="0"
fit-margin-left="0"
fit-margin-top="0"
inkscape:pagecheckerboard="true"
showgrid="false"
inkscape:document-rotation="0"
inkscape:current-layer="layer1"
inkscape:document-units="mm"
inkscape:cy="23.309776"
inkscape:cx="-722.33888"
inkscape:zoom="0.35"
inkscape:pageshadow="2"
inkscape:pageopacity="0.0"
borderopacity="1.0"
bordercolor="#666666"
pagecolor="#ffffff"
id="base" />
<metadata
id="metadata1048">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title></dc:title>
</cc:Work>
</rdf:RDF>
</metadata>
<g
transform="translate(-76.97002,-141.99929)"
id="layer1"
inkscape:groupmode="layer"
inkscape:label="Layer 1">
<g
transform="translate(-147.81923,-9.2980316)"
id="g979">
<path
d="m 239.26301,155.78914 h -0.47872 v -3.40219 h -0.91228 v -0.43815 h 2.30258 v 0.43815 h -0.91158 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path72" />
<path
d="m 242.86864,153.49724 v -1.54834 h 0.47872 v 3.84034 h -0.47872 v -1.84397 h -1.82845 v 1.84397 h -0.47836 v -3.84034 h 0.47836 v 1.54834 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path76" />
<path
d="m 244.09137,151.9488 h 2.06269 v 0.43815 h -1.58432 v 1.07456 h 1.53846 v 0.43815 h -1.53846 v 1.45133 h 1.58432 v 0.43815 h -2.06269 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path80" />
<path
d="m 250.58509,153.49724 v -1.54834 h 0.47837 v 3.84034 h -0.47837 v -1.84397 h -1.82845 v 1.84397 h -0.47872 v -3.84034 h 0.47872 v 1.54834 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path84" />
<path
d="m 255.56117,153.86872 c 0,1.14124 -0.9017,2.00201 -2.01189,2.00201 -1.11055,0 -2.01189,-0.86077 -2.01189,-2.00201 0,-1.09996 0.91122,-2.00131 2.01189,-2.00131 1.09996,0 2.01189,0.90135 2.01189,2.00131 m -0.47872,0 c 0,-0.84526 -0.63182,-1.55363 -1.53317,-1.55363 -0.9017,0 -1.53317,0.70837 -1.53317,1.55363 0,0.8763 0.70273,1.55328 1.53317,1.55328 0.82973,0 1.53317,-0.67698 1.53317,-1.55328"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path96" />
<path
d="m 256.02958,151.76532 2.88255,3.02048 v -2.83704 h 0.47907 v 3.99839 l -2.8829,-3.02013 v 2.86208 h -0.47872 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path100" />
<path
d="m 263.62376,153.8538 v 0.15275 c 0,1.0541 -0.74401,1.86408 -1.81786,1.86408 -1.07527,0 -1.94134,-0.92675 -1.94134,-1.99143 0,-1.10525 0.88688,-2.01189 1.99108,-2.01189 0.59655,0 1.18745,0.26987 1.56421,0.74401 l -0.33619,0.32067 c -0.27552,-0.37712 -0.73872,-0.62653 -1.20721,-0.62653 -0.86042,0 -1.53246,0.69744 -1.53246,1.55822 0,0.80504 0.66216,1.5688 1.49154,1.5688 0.5969,0 1.23719,-0.5147 1.25801,-1.14053 h -0.99343 v -0.43815 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path112" />
<path
d="m 267.77885,151.9488 h 0.62653 l -1.72649,1.72649 1.75718,2.11385 h -0.64628 l -1.4471,-1.78753 -0.19297,0.18345 v 1.60408 h -0.47942 v -3.84034 h 0.47942 v 1.66546 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path116" />
<path
d="m 272.53069,153.86872 c 0,1.14124 -0.90099,2.00201 -2.01083,2.00201 -1.10984,0 -2.01189,-0.86077 -2.01189,-2.00201 0,-1.09996 0.91193,-2.00131 2.01189,-2.00131 1.09996,0 2.01083,0.90135 2.01083,2.00131 m -0.47731,0 c 0,-0.84526 -0.63253,-1.55363 -1.53352,-1.55363 -0.901,0 -1.53353,0.70837 -1.53353,1.55363 0,0.8763 0.70309,1.55328 1.53353,1.55328 0.82938,0 1.53352,-0.67698 1.53352,-1.55328"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path128" />
<path
d="m 273.00006,151.76532 2.88219,3.02048 v -2.83704 h 0.47943 v 3.99839 l -2.88325,-3.02013 v 2.86208 h -0.47837 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path132" />
<path
d="m 280.59424,153.8538 v 0.15275 c 0,1.0541 -0.74401,1.86408 -1.81786,1.86408 -1.07633,0 -1.94134,-0.92675 -1.94134,-1.99143 0,-1.10525 0.88618,-2.01189 1.99108,-2.01189 0.59655,0 1.18745,0.26987 1.56421,0.74401 l -0.33619,0.32067 c -0.27552,-0.37712 -0.73872,-0.62653 -1.20721,-0.62653 -0.86042,0 -1.53246,0.69744 -1.53246,1.55822 0,0.80504 0.66216,1.5688 1.49154,1.5688 0.59584,0 1.23719,-0.5147 1.25801,-1.14053 h -0.99343 v -0.43815 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path144" />
<path
d="m 238.64141,158.05912 v 2.26589 c 0,0.62653 0.18838,1.20756 0.92675,1.20756 0.73871,0 0.9271,-0.58103 0.9271,-1.20756 v -2.26589 h 0.47872 v 2.42923 c 0,0.84525 -0.52458,1.4926 -1.40582,1.4926 -0.88089,0 -1.40547,-0.64735 -1.40547,-1.4926 v -2.42923 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path148" />
<path
d="m 241.64137,157.87564 2.88255,3.02048 v -2.83704 h 0.47907 v 3.99839 l -2.8829,-3.02013 v 2.86208 h -0.47872 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path152" />
<path
id="path154"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
d="m 246.19968,161.8996 h -0.47872 v -3.84034 h 0.47872 z" />
<path
d="m 248.23704,160.90096 1.14088,-2.84198 h 0.52458 l -1.66546,4.04425 -1.67076,-4.04425 h 0.52459 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path158" />
<path
d="m 250.27927,158.05912 h 2.06269 v 0.43815 h -1.58397 v 1.07456 h 1.53811 v 0.43815 h -1.53811 v 1.45098 h 1.58397 v 0.4385 h -2.06269 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path162" />
<path
d="m 255.37268,161.89946 h -0.58067 l -1.13101,-1.62419 h -0.19826 v 1.62419 h -0.47872 v -3.84034 h 0.58067 c 0.34114,0 0.70768,0.005 1.01353,0.17851 0.32068,0.18803 0.50412,0.54998 0.50412,0.91651 0,0.54998 -0.36688,1.00789 -0.9218,1.07456 z m -1.90994,-2.02177 h 0.15275 c 0.4886,0 1.01883,-0.0921 1.01883,-0.70309 0,-0.60078 -0.5708,-0.68791 -1.04423,-0.68791 h -0.12735 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path174" />
<path
d="m 257.50645,158.78761 c -0.14217,-0.23954 -0.32561,-0.36195 -0.61595,-0.36195 -0.30586,0 -0.64206,0.20884 -0.64206,0.54504 0,0.30057 0.29563,0.45826 0.53517,0.55033 l 0.27481,0.1069 c 0.54504,0.21378 0.95215,0.51435 0.95215,1.15675 0,0.69709 -0.5394,1.19627 -1.22696,1.19627 -0.6216,0 -1.10561,-0.45825 -1.1871,-1.07491 l 0.48366,-0.1016 c -0.005,0.42263 0.33126,0.72813 0.74401,0.72813 0.41275,0 0.70802,-0.34607 0.70802,-0.74789 0,-0.4138 -0.33126,-0.5909 -0.66216,-0.72919 l -0.26529,-0.11147 c -0.43744,-0.18874 -0.83467,-0.43851 -0.83467,-0.97332 0,-0.62124 0.54998,-0.99307 1.13065,-0.99307 0.42757,0 0.77929,0.20885 0.98813,0.58067 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path178" />
<path
id="path180"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
d="m 259.04996,161.8996 h -0.47872 v -3.84034 h 0.47872 z" />
<path
d="m 260.85301,161.89946 h -0.47942 v -3.40219 h -0.91158 v -0.43815 h 2.30187 v 0.43815 h -0.91087 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path184" />
<path
d="m 261.79482,158.05912 h 0.54998 l 0.94262,1.64006 0.94192,-1.64006 h 0.54998 l -1.25307,2.16958 v 1.67076 h -0.47836 v -1.67076 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path188" />
<path
d="m 270.43819,159.97904 c 0,1.14159 -0.90099,2.00201 -2.01189,2.00201 -1.1109,0 -2.01189,-0.86042 -2.01189,-2.00201 0,-1.09996 0.91193,-2.00131 2.01189,-2.00131 1.10102,0 2.01189,0.90135 2.01189,2.00131 m -0.47942,0 c 0,-0.84526 -0.63042,-1.55363 -1.53247,-1.55363 -0.90205,0 -1.53247,0.70837 -1.53247,1.55363 0,0.8763 0.70203,1.55328 1.53247,1.55328 0.83044,0 1.53247,-0.67698 1.53247,-1.55328"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path200" />
<path
d="m 271.42675,158.4972 v 1.0795 h 1.3335 v 0.43815 h -1.3335 v 1.88454 h -0.47942 v -3.84034 h 1.85984 v 0.43815 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path204" />
<path
d="m 276.64599,158.78761 c -0.14111,-0.23954 -0.32526,-0.36195 -0.6156,-0.36195 -0.30515,0 -0.64135,0.20884 -0.64135,0.54504 0,0.30057 0.29528,0.45826 0.53481,0.55033 l 0.27447,0.1069 c 0.54504,0.21378 0.95285,0.51435 0.95285,1.15675 0,0.69709 -0.5401,1.19627 -1.22732,1.19627 -0.6223,0 -1.10595,-0.45825 -1.18745,-1.07491 l 0.48437,-0.1016 c -0.005,0.42263 0.33126,0.72813 0.74295,0.72813 0.41381,0 0.70802,-0.34607 0.70802,-0.74789 0,-0.4138 -0.3302,-0.5909 -0.66216,-0.72919 l -0.26458,-0.11147 c -0.4378,-0.18874 -0.83538,-0.43851 -0.83538,-0.97332 0,-0.62124 0.55104,-0.99307 1.13171,-0.99307 0.42757,0 0.77858,0.20885 0.98742,0.58067 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path216" />
<path
d="m 280.52263,158.79255 c -0.27446,-0.24447 -0.65229,-0.37677 -1.01353,-0.37677 -0.86007,0 -1.51836,0.71791 -1.51836,1.56845 0,0.84032 0.65229,1.55822 1.50742,1.55822 0.37818,0 0.73907,-0.14217 1.02447,-0.39687 v 0.56585 c -0.29527,0.17322 -0.67239,0.26953 -1.00859,0.26953 -1.09467,0 -2.00096,-0.87101 -2.00096,-1.9812 0,-1.13595 0.91123,-2.02213 2.04188,-2.02213 0.3362,0 0.67733,0.0815 0.96767,0.26 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path220" />
<path
id="path222"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
d="m 281.60763,161.8996 h -0.47837 v -3.84034 h 0.47837 z" />
<path
d="m 282.37644,158.05912 h 2.06269 v 0.43815 h -1.58327 v 1.07456 h 1.53741 v 0.43815 h -1.53741 v 1.45098 h 1.58327 v 0.4385 h -2.06269 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path226" />
<path
d="m 285.03575,157.87564 2.88219,3.02048 v -2.83704 h 0.47943 v 3.99839 l -2.88325,-3.02013 v 2.86208 h -0.47837 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path230" />
<path
d="m 291.92578,158.79255 c -0.27446,-0.24447 -0.65123,-0.37677 -1.01247,-0.37677 -0.86113,0 -1.51871,0.71791 -1.51871,1.56845 0,0.84032 0.65158,1.55822 1.50777,1.55822 0.37712,0 0.73907,-0.14217 1.02341,-0.39687 v 0.56585 c -0.29422,0.17322 -0.67239,0.26953 -1.00859,0.26953 -1.09397,0 -2.00096,-0.87101 -2.00096,-1.9812 0,-1.13595 0.91123,-2.02213 2.04294,-2.02213 0.3362,0 0.67627,0.0815 0.96661,0.26 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path242" />
<path
d="m 292.54737,158.05912 h 2.06375 v 0.43815 h -1.58538 v 1.07456 h 1.53952 v 0.43815 h -1.53952 v 1.45098 h 1.58538 v 0.4385 h -2.06375 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path246" />
<path
d="m 238.77367,167.04712 -0.43744,0.96273 h -0.51471 l 1.83339,-4.00297 1.83374,4.00297 h -0.51471 l -0.43815,-0.96273 z m 0.88124,-1.99214 -0.68227,1.55364 h 1.36489 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path250" />
<path
d="m 241.81444,163.98596 2.88255,3.02048 v -2.83633 h 0.47907 v 3.99768 l -2.8829,-3.02013 v 2.86208 h -0.47872 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path254" />
<path
d="m 245.86856,164.16997 h 0.79481 c 1.17651,0 2.15441,0.62054 2.15441,1.89936 0,1.3088 -0.95779,1.94063 -2.16993,1.94063 h -0.77929 z m 0.47872,3.40113 h 0.16827 c 0.9779,0 1.82351,-0.36583 1.82351,-1.48167 0,-1.11971 -0.84561,-1.48202 -1.82351,-1.48202 h -0.16827 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path266" />
<path
d="m 251.90381,168.00978 h -0.47837 v -3.40219 h -0.91193 v -0.4378 h 2.30223 v 0.4378 h -0.91193 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path270" />
<path
d="m 253.24345,164.16997 h 2.06269 v 0.43744 h -1.58397 v 1.07421 h 1.53811 v 0.43851 h -1.53811 v 1.45097 h 1.58397 v 0.43886 h -2.06269 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path274" />
<path
d="m 258.74414,164.9029 c -0.27517,-0.24483 -0.65193,-0.37677 -1.01353,-0.37677 -0.86078,0 -1.51765,0.71791 -1.51765,1.56916 0,0.83926 0.65193,1.55751 1.50742,1.55751 0.37677,0 0.73872,-0.14217 1.02376,-0.39687 v 0.56585 c -0.29527,0.17322 -0.67239,0.26953 -1.00859,0.26953 -1.09467,0 -2.00131,-0.87101 -2.00131,-1.98191 0,-1.13594 0.91158,-2.02106 2.04223,-2.02106 0.3362,0 0.67733,0.0815 0.96767,0.25964 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path286" />
<path
d="m 261.63272,165.71743 v -1.54764 h 0.47731 v 3.83999 h -0.47731 v -1.84397 h -1.8288 v 1.84397 h -0.47907 v -3.83999 h 0.47907 v 1.54764 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path290" />
<path
d="m 262.80824,163.98596 2.88325,3.02048 v -2.83633 h 0.47837 v 3.99768 l -2.8822,-3.02013 v 2.86208 h -0.47942 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path294" />
<path
d="m 270.65698,166.0894 c 0,1.14159 -0.90099,2.00201 -2.01189,2.00201 -1.10984,0 -2.01189,-0.86042 -2.01189,-2.00201 0,-1.09996 0.91193,-2.00096 2.01189,-2.00096 1.10102,0 2.01189,0.901 2.01189,2.00096 m -0.47837,0 c 0,-0.84526 -0.63147,-1.55328 -1.53352,-1.55328 -0.901,0 -1.53247,0.70802 -1.53247,1.55328 0,0.8763 0.70203,1.55328 1.53247,1.55328 0.83044,0 1.53352,-0.67698 1.53352,-1.55328"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path306" />
<path
d="m 271.65051,167.57121 h 1.16664 v 0.4385 h -1.64501 v -3.83963 h 0.47837 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path310" />
<path
d="m 276.93639,166.0894 c 0,1.14159 -0.90099,2.00201 -2.01083,2.00201 -1.10984,0 -2.01189,-0.86042 -2.01189,-2.00201 0,-1.09996 0.91193,-2.00096 2.01189,-2.00096 1.09996,0 2.01083,0.901 2.01083,2.00096 m -0.47837,0 c 0,-0.84526 -0.63147,-1.55328 -1.53246,-1.55328 -0.90206,0 -1.53353,0.70802 -1.53353,1.55328 0,0.8763 0.70309,1.55328 1.53353,1.55328 0.82938,0 1.53246,-0.67698 1.53246,-1.55328"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path322" />
<path
d="m 280.9503,166.07444 v 0.15205 c 0,1.05445 -0.74401,1.86478 -1.81786,1.86478 -1.07421,0 -1.94134,-0.92675 -1.94134,-1.99178 0,-1.1049 0.88688,-2.01119 1.99178,-2.01119 0.59585,0 1.18675,0.26952 1.56457,0.74401 l -0.33619,0.32032 c -0.27552,-0.37712 -0.73978,-0.62653 -1.20721,-0.62653 -0.86148,0 -1.53352,0.69815 -1.53352,1.55822 0,0.80468 0.66216,1.56845 1.49154,1.56845 0.5969,0 1.23825,-0.51435 1.25906,-1.13983 h -0.99342 v -0.4385 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path326" />
<path
d="m 281.07758,164.16997 h 0.55104 l 0.94086,1.63901 0.94262,-1.63901 h 0.55104 l -1.25307,2.16888 v 1.67111 h -0.47942 v -1.67111 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path330" />
<path
d="m 232.48385,154.7404 c 0.0794,-0.0995 0.1076,-0.27658 0.1076,-0.27658 h -4.76391 c 0,0 0.0586,0.19721 0.1083,0.27658 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path342" />
<path
d="m 232.20735,155.14518 c 0.0885,-0.0787 0.17815,-0.23777 0.17815,-0.23777 h -4.36104 c 0,0 0.0487,0.11959 0.15805,0.23777 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path346" />
<path
d="m 231.86325,155.51016 c 0.1083,-0.0575 0.19579,-0.17815 0.19579,-0.17815 h -3.72921 c 0,0 0.0893,0.0984 0.17674,0.17815 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path350" />
<path
d="m 231.42866,155.85623 c 0.10654,-0.0409 0.22684,-0.13935 0.22684,-0.13935 h -2.91007 c 0,0 0,0.0219 0.20673,0.13935 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path354" />
<path
d="m 229.28645,156.07206 c 0,0 0.30621,0.17886 0.90805,0.17886 0.60254,0 0.98637,-0.17886 0.98637,-0.17886 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path358" />
<path
d="m 229.23773,156.47684 c 0,0 0.36512,0.0198 0.58173,0.18697 0.20673,0.17886 0.36618,0.47343 0.36618,0.47343 0,0 0.127,-0.28434 0.33514,-0.43251 0.20779,-0.15945 0.54293,-0.22789 0.54293,-0.22789 h 3.7592 l 0.74013,1.09608 h -3.37574 c 0,0 -0.23671,0.01 -0.5916,0.21766 -0.18803,0.10654 -0.32632,0.29528 -0.32632,0.29528 0,0 -0.0279,0.0885 -0.0695,0.13723 -0.0388,0.0497 -0.0684,0.0896 -0.11748,0.10866 -0.0497,0.0208 -0.0395,0.009 -0.0395,0.009 h -1.75648 c 0,0 -0.0705,-0.0279 -0.10724,-0.0885 -0.0399,-0.0586 -0.0109,-0.0388 -0.0497,-0.0864 -0.03,-0.0497 -0.0995,-0.17921 -0.36619,-0.35596 -0.27552,-0.17921 -0.54292,-0.1972 -0.54292,-0.1972 h -3.43112 l 0.74789,-1.13559 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path362" />
<path
d="m 226.58234,158.02628 v 5.60246 c 0,0 0.0198,0.4953 0.43462,1.16558 0.41452,0.67063 1.01635,0.97684 1.01635,0.97684 l 0.47343,-0.74012 c 0,0 -0.41381,-0.2466 -0.72989,-0.72002 -0.30551,-0.47308 -0.30551,-0.87913 -0.30551,-0.87913 v -5.40561 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path366" />
<path
d="m 232.93732,158.00642 v 5.40561 c 0,0 -0.0688,0.54328 -0.32526,0.92887 -0.25647,0.39405 -0.68227,0.71014 -0.68227,0.71014 l 0.45543,0.7299 c 0,0 0.69039,-0.50306 1.02659,-1.03611 0.33408,-0.53305 0.41557,-1.3328 0.41557,-1.3328 v -5.40561 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path370" />
<path
d="m 225.1731,158.02628 v 5.62469 c 0,0 0.0575,0.86889 0.60078,1.77588 0.54398,0.90699 1.52964,1.53952 1.52964,1.53952 l 0.46426,-0.73977 c 0,0 -0.63147,-0.3362 -1.13489,-1.10596 -0.51505,-0.77964 -0.54292,-1.4919 -0.54292,-1.4919 v -5.60246 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path374" />
<path
d="m 229.23773,158.61803 v 5.93972 c 0,0 -0.0219,0.0197 -0.0289,0.1076 -0.0109,0.0893 -0.0695,0.14887 -0.0695,0.14887 l -1.98297,3.28612 h 6.07836 l -1.98402,-3.35562 -0.0589,-0.14922 -0.0198,-0.15699 v -5.80954 h -0.73977 v 6.02826 c 0,0 0,0.0875 0.0296,0.15699 0.018,0.0699 0.0589,0.17709 0.0589,0.17709 l 1.22202,2.01295 h -3.09774 l 1.20439,-2.00307 c 0,0 0.0395,-0.0674 0.0695,-0.16686 0.0198,-0.0896 0.0279,-0.1771 0.0279,-0.1771 v -6.0392 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path378" />
<path
d="m 234.30877,158.00642 v 5.52521 c 0,0 -0.008,0.70978 -0.53199,1.52929 -0.52211,0.8195 -1.12501,1.16557 -1.12501,1.16557 l 0.4445,0.74789 c 0,0 0.90629,-0.57255 1.47991,-1.47955 0.56197,-0.90734 0.63182,-1.9632 0.63182,-1.9632 v -5.52521 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path382" />
<path
d="m 227.79664,154.30581 c 0,0 -0.30445,-1.66582 0.91793,-2.49731 0,0 0.5528,-0.51118 1.44991,-0.51118 0.9578,0 1.50989,0.50236 1.50989,0.50236 1.33174,0.97543 0.93769,2.50613 0.93769,2.50613 z"
style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.352778"
id="path386" />
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 22 KiB

92
static/images/about/isa_logo.svg Normal file
View File

@ -0,0 +1,92 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="20.426556mm"
height="37.573151mm"
viewBox="0 0 20.426556 37.573151"
version="1.1"
id="svg8"
inkscape:version="1.0 (4035a4fb49, 2020-05-01)"
sodipodi:docname="isa_logo.svg">
<defs
id="defs2">
<inkscape:path-effect
effect="powermask"
id="path-effect4272"
is_visible="true"
lpeversion="1"
uri="#mask-powermask-path-effect4272"
invert="false"
hide_mask="false"
background="true"
background_color="#ffffffff" />
</defs>
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="5.6568542"
inkscape:cx="31.383327"
inkscape:cy="82.558209"
inkscape:document-units="mm"
inkscape:current-layer="layer1"
inkscape:document-rotation="0"
showgrid="false"
inkscape:pagecheckerboard="true"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0"
inkscape:window-width="1920"
inkscape:window-height="1027"
inkscape:window-x="-8"
inkscape:window-y="-8"
inkscape:window-maximized="1" />
<metadata
id="metadata5">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title></dc:title>
</cc:Work>
</rdf:RDF>
</metadata>
<g
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(-101.89083,-103.44166)">
<path
style="fill:#eeeeec;stroke:none;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 112.39667,131.72942 c -1.95918,2.02964 -3.45611,1.85209 -3.45611,1.85209 l 3.57186,2.87734 c 0,0 1.44534,-1.46421 2.21589,-3.80338 0.92605,-2.8112 0.6284,-5.65547 0.6284,-5.65547 0,0 -0.66147,2.34818 -2.96004,4.72942 z"
id="path3934"
sodipodi:nodetypes="sccscs" />
<path
style="fill:#eeeeec;stroke:none;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 101.98618,103.44166 c 0,0 4.41703,3.19997 4.23873,9.65437 -0.1783,6.45439 -4.39779,11.83823 -4.33335,17.69661 0.0516,4.6866 3.67664,9.31935 9.7069,10.12116 6.03027,0.80181 8.9311,-3.35282 10.00018,-5.99211 1.06908,-2.63929 0.62903,-5.47923 0.62903,-5.47923 0,0 -0.27024,1.89646 -2.56752,4.01409 -2.29727,2.11763 -5.02164,2.1111 -7.7093,1.17544 -2.68767,-0.93565 -5.16772,-3.22985 -5.03296,-7.56609 0.13477,-4.33624 1.76262,-4.78573 2.01836,-12.12638 0.25575,-7.34064 -6.95007,-11.49786 -6.95007,-11.49786 z"
id="path3930"
sodipodi:nodetypes="czszzczzzzc" />
<path
style="fill:#ffffff;stroke:none;stroke-width:0.499999;stop-color:#000000"
d="m 121.02464,126.66536 a 6.1515627,6.1515627 0 0 1 -6.15157,6.15156 6.1515627,6.1515627 0 0 1 -6.15156,-6.15156 6.1515627,6.1515627 0 0 1 6.15156,-6.15157 6.1515627,6.1515627 0 0 1 6.15157,6.15157"
id="path3936-9"
mask="none" />
<path
style="fill:#eeeeec;stroke:none;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 108.14591,131.73047 c -1.72055,3.10701 -2.43884,6.71514 -2.43884,6.71514 0,0 0.3842,0.50114 1.93771,1.25283 1.5535,0.75169 2.91499,1.03377 2.91499,1.03377 0,0 -0.71002,-2.38682 -0.0251,-6.11189 0.68487,-3.72507 2.75384,-10.66313 2.75384,-10.66313 0,0 -3.42206,4.66627 -5.1426,7.77328 z"
id="path3932"
sodipodi:nodetypes="scscscs" />
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 4.0 KiB

94
static/images/about/novelda_logo_black.svg Normal file
View File

@ -0,0 +1,94 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
inkscape:version="1.0 (4035a4fb49, 2020-05-01)"
height="183.5"
width="221.5"
sodipodi:docname="Novelda_logo_sort.svg"
xml:space="preserve"
viewBox="0 0 221.49999 183.5"
y="0px"
x="0px"
id="Layer_1"
version="1.1"><metadata
id="metadata37"><rdf:RDF><cc:Work
rdf:about=""><dc:format>image/svg+xml</dc:format><dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" /><dc:title></dc:title></cc:Work></rdf:RDF></metadata><defs
id="defs35" /><sodipodi:namedview
inkscape:current-layer="Layer_1"
inkscape:window-maximized="0"
inkscape:window-y="0"
inkscape:window-x="0"
inkscape:cy="37.61879"
inkscape:cx="107.5864"
inkscape:zoom="0.64415829"
inkscape:pagecheckerboard="true"
fit-margin-bottom="0"
fit-margin-right="0"
fit-margin-left="0"
fit-margin-top="0"
showgrid="false"
id="namedview33"
inkscape:window-height="480"
inkscape:window-width="999"
inkscape:pageshadow="2"
inkscape:pageopacity="0"
guidetolerance="10"
gridtolerance="10"
objecttolerance="10"
borderopacity="1"
bordercolor="#666666"
pagecolor="#ffffff" />
<g
transform="translate(-144.4,-149.2)"
id="g30">
<g
id="g18">
<g
id="g16">
<path
id="path2"
d="m 144.4,332.4 v -28.9 h 5.6 l 12.2,18.2 v -18.2 h 6.1 v 28.9 h -5.7 l -12.2,-18.2 v 18.2 z" />
<path
id="path4"
d="m 192.6,332.7 c -8.5,0 -14.3,-6.3 -14.3,-14.7 0,-8.4 5.8,-14.7 14.3,-14.7 8.5,0 14.3,6.3 14.3,14.7 0,8.4 -5.8,14.7 -14.3,14.7 z m 0,-5.3 c 4.8,0 8,-4 8,-9.4 0,-5.4 -3.1,-9.4 -8,-9.4 -4.9,0 -8,4 -8,9.4 0,5.4 3.1,9.4 8,9.4 z" />
<path
id="path6"
d="m 213,303.5 h 6.6 l 6.9,21.4 7.1,-21.4 h 6.4 l -9.8,28.9 h -7.4 z" />
<path
id="path8"
d="M 248.7,303.5 H 268 v 5.3 h -13.2 v 6.5 h 10.7 v 5.1 h -10.7 v 6.7 h 13.6 v 5.3 h -19.8 v -28.9 z" />
<path
id="path10"
d="m 278.4,332.4 v -28.9 h 6.2 V 327 H 296 v 5.3 h -17.6 z" />
<path
id="path12"
d="M 305.5,332.4 V 303.5 H 316 c 9,0 15,5.9 15,14.4 0,8.5 -6,14.5 -15,14.5 z m 6.2,-5.1 h 4.3 c 5.5,0 8.6,-3.8 8.6,-9.3 0,-5.5 -3.1,-9.2 -8.6,-9.2 h -4.3 z" />
<path
id="path14"
d="M 337.4,332.4 348,303.5 h 7.4 l 10.5,28.9 h -6.6 l -2.2,-6.3 h -11 l -2.2,6.3 z m 10.3,-11.3 h 7.6 l -3.8,-11 z" />
</g>
</g>
<g
id="g28">
<g
id="g26">
<path
id="path20"
d="m 312.8,200.3 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 11 c 0,3.4 -2.8,6.2 -6.2,6.2 h -8.8 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -11 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -11 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -11 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -11 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -11 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 38.8 c 0,4.6 3.7,8.3 8.3,8.3 H 234 c 3.4,0 6.2,2.8 6.2,6.2 v 11 c 0,4.6 3.7,8.3 8.3,8.3 h 11 c 3.4,0 6.2,2.8 6.2,6.2 v 11 c 0,4.6 3.7,8.3 8.3,8.3 h 11 c 3.4,0 6.2,2.8 6.2,6.2 v 11 c 0,4.6 3.7,8.3 8.3,8.3 h 13.2 c 4.6,0 8.3,-3.7 8.3,-8.3 v -13.2 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -11 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -8.8 c 0,-3.4 2.8,-6.2 6.2,-6.2 h 11 c 4.6,0 8.3,-3.7 8.3,-8.3 v -13.2 c 0.1,-4.7 -3.6,-8.4 -8.2,-8.4 z" />
<path
id="path22"
d="m 210.7,225.8 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 38.8 c 0,4.6 3.7,8.3 8.3,8.3 h 13.2 c 4.6,0 8.3,-3.7 8.3,-8.3 v -38.8 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 z" />
<path
id="path24"
d="m 312.8,149.2 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 13.2 c 0,4.6 3.7,8.3 8.3,8.3 h 13.2 c 4.6,0 8.3,-3.7 8.3,-8.3 v -13.2 c 0,-4.5 -3.7,-8.3 -8.3,-8.3 z" />
</g>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 3.8 KiB

109
static/images/about/novelda_logo_dark_blue.svg Normal file
View File

@ -0,0 +1,109 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
inkscape:version="1.0 (4035a4fb49, 2020-05-01)"
height="183.5"
width="221.5"
sodipodi:docname="Novelda_logo_RGB negativ.svg"
xml:space="preserve"
viewBox="0 0 221.49999 183.5"
y="0px"
x="0px"
id="Layer_1"
version="1.1"><metadata
id="metadata39"><rdf:RDF><cc:Work
rdf:about=""><dc:format>image/svg+xml</dc:format><dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" /><dc:title></dc:title></cc:Work></rdf:RDF></metadata><defs
id="defs37" /><sodipodi:namedview
inkscape:current-layer="Layer_1"
inkscape:window-maximized="0"
inkscape:window-y="106"
inkscape:window-x="577"
inkscape:cy="55.244332"
inkscape:cx="967.23923"
inkscape:zoom="0.16103957"
fit-margin-bottom="0"
fit-margin-right="0"
fit-margin-left="0"
fit-margin-top="0"
inkscape:pagecheckerboard="true"
showgrid="false"
id="namedview35"
inkscape:window-height="480"
inkscape:window-width="999"
inkscape:pageshadow="2"
inkscape:pageopacity="0"
guidetolerance="10"
gridtolerance="10"
objecttolerance="10"
borderopacity="1"
bordercolor="#666666"
pagecolor="#ffffff" />
<style
id="style2"
type="text/css">
.st0{fill:#17D3E2;}
</style>
<g
transform="translate(-144.4,-149.2)"
id="g32">
<g
id="g20">
<g
id="g18">
<path
id="path4"
d="m 144.4,332.4 v -28.9 h 5.6 l 12.2,18.2 v -18.2 h 6.1 v 28.9 h -5.7 l -12.2,-18.2 v 18.2 z"
class="st0" />
<path
id="path6"
d="m 192.6,332.7 c -8.5,0 -14.3,-6.3 -14.3,-14.7 0,-8.4 5.8,-14.7 14.3,-14.7 8.5,0 14.3,6.3 14.3,14.7 0,8.4 -5.8,14.7 -14.3,14.7 z m 0,-5.3 c 4.8,0 8,-4 8,-9.4 0,-5.4 -3.1,-9.4 -8,-9.4 -4.9,0 -8,4 -8,9.4 0,5.4 3.1,9.4 8,9.4 z"
class="st0" />
<path
id="path8"
d="m 213,303.5 h 6.6 l 6.9,21.4 7.1,-21.4 h 6.4 l -9.8,28.9 h -7.4 z"
class="st0" />
<path
id="path10"
d="M 248.7,303.5 H 268 v 5.3 h -13.2 v 6.5 h 10.7 v 5.1 h -10.7 v 6.7 h 13.6 v 5.3 h -19.8 v -28.9 z"
class="st0" />
<path
id="path12"
d="m 278.4,332.4 v -28.9 h 6.2 V 327 H 296 v 5.3 h -17.6 z"
class="st0" />
<path
id="path14"
d="M 305.5,332.4 V 303.5 H 316 c 9,0 15,5.9 15,14.4 0,8.5 -6,14.5 -15,14.5 z m 6.2,-5.1 h 4.3 c 5.5,0 8.6,-3.8 8.6,-9.3 0,-5.5 -3.1,-9.2 -8.6,-9.2 h -4.3 z"
class="st0" />
<path
id="path16"
d="M 337.4,332.4 348,303.5 h 7.4 l 10.5,28.9 h -6.6 l -2.2,-6.3 h -11 l -2.2,6.3 z m 10.3,-11.3 h 7.6 l -3.8,-11 z"
class="st0" />
</g>
</g>
<g
id="g30">
<g
id="g28">
<path
id="path22"
d="m 312.8,200.3 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 11 c 0,3.4 -2.8,6.2 -6.2,6.2 h -8.8 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -11 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -11 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -11 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -11 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -11 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 38.8 c 0,4.6 3.7,8.3 8.3,8.3 H 234 c 3.4,0 6.2,2.8 6.2,6.2 v 11 c 0,4.6 3.7,8.3 8.3,8.3 h 11 c 3.4,0 6.2,2.8 6.2,6.2 v 11 c 0,4.6 3.7,8.3 8.3,8.3 h 11 c 3.4,0 6.2,2.8 6.2,6.2 v 11 c 0,4.6 3.7,8.3 8.3,8.3 h 13.2 c 4.6,0 8.3,-3.7 8.3,-8.3 v -13.2 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -11 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -8.8 c 0,-3.4 2.8,-6.2 6.2,-6.2 h 11 c 4.6,0 8.3,-3.7 8.3,-8.3 v -13.2 c 0.1,-4.7 -3.6,-8.4 -8.2,-8.4 z"
class="st0" />
<path
id="path24"
d="m 210.7,225.8 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 38.8 c 0,4.6 3.7,8.3 8.3,8.3 h 13.2 c 4.6,0 8.3,-3.7 8.3,-8.3 v -38.8 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 z"
class="st0" />
<path
id="path26"
d="m 312.8,149.2 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 13.2 c 0,4.6 3.7,8.3 8.3,8.3 h 13.2 c 4.6,0 8.3,-3.7 8.3,-8.3 v -13.2 c 0,-4.5 -3.7,-8.3 -8.3,-8.3 z"
class="st0" />
</g>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 4.1 KiB

109
static/images/about/novelda_logo_light_blue.svg Normal file
View File

@ -0,0 +1,109 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
inkscape:version="1.0 (4035a4fb49, 2020-05-01)"
height="183.5"
width="221.5"
sodipodi:docname="Novelda_logo_RGB positiv.svg"
xml:space="preserve"
viewBox="0 0 221.49999 183.5"
y="0px"
x="0px"
id="Layer_1"
version="1.1"><metadata
id="metadata39"><rdf:RDF><cc:Work
rdf:about=""><dc:format>image/svg+xml</dc:format><dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" /><dc:title></dc:title></cc:Work></rdf:RDF></metadata><defs
id="defs37" /><sodipodi:namedview
inkscape:current-layer="Layer_1"
inkscape:window-maximized="0"
inkscape:window-y="0"
inkscape:window-x="0"
inkscape:cy="91.749997"
inkscape:cx="110.70001"
inkscape:zoom="1.8219548"
fit-margin-bottom="0"
fit-margin-right="0"
fit-margin-left="0"
fit-margin-top="0"
inkscape:pagecheckerboard="true"
showgrid="false"
id="namedview35"
inkscape:window-height="480"
inkscape:window-width="999"
inkscape:pageshadow="2"
inkscape:pageopacity="0"
guidetolerance="10"
gridtolerance="10"
objecttolerance="10"
borderopacity="1"
bordercolor="#666666"
pagecolor="#ffffff" />
<style
id="style2"
type="text/css">
.st0{fill:#041E2E;}
</style>
<g
transform="translate(-144.4,-149.2)"
id="g32">
<g
id="g20">
<g
id="g18">
<path
id="path4"
d="m 144.4,332.4 v -28.9 h 5.6 l 12.2,18.2 v -18.2 h 6.1 v 28.9 h -5.7 l -12.2,-18.2 v 18.2 z"
class="st0" />
<path
id="path6"
d="m 192.6,332.7 c -8.5,0 -14.3,-6.3 -14.3,-14.7 0,-8.4 5.8,-14.7 14.3,-14.7 8.5,0 14.3,6.3 14.3,14.7 0,8.4 -5.8,14.7 -14.3,14.7 z m 0,-5.3 c 4.8,0 8,-4 8,-9.4 0,-5.4 -3.1,-9.4 -8,-9.4 -4.9,0 -8,4 -8,9.4 0,5.4 3.1,9.4 8,9.4 z"
class="st0" />
<path
id="path8"
d="m 213,303.5 h 6.6 l 6.9,21.4 7.1,-21.4 h 6.4 l -9.8,28.9 h -7.4 z"
class="st0" />
<path
id="path10"
d="M 248.7,303.5 H 268 v 5.3 h -13.2 v 6.5 h 10.7 v 5.1 h -10.7 v 6.7 h 13.6 v 5.3 h -19.8 v -28.9 z"
class="st0" />
<path
id="path12"
d="m 278.4,332.4 v -28.9 h 6.2 V 327 H 296 v 5.3 h -17.6 z"
class="st0" />
<path
id="path14"
d="M 305.5,332.4 V 303.5 H 316 c 9,0 15,5.9 15,14.4 0,8.5 -6,14.5 -15,14.5 z m 6.2,-5.1 h 4.3 c 5.5,0 8.6,-3.8 8.6,-9.3 0,-5.5 -3.1,-9.2 -8.6,-9.2 h -4.3 z"
class="st0" />
<path
id="path16"
d="M 337.4,332.4 348,303.5 h 7.4 l 10.5,28.9 h -6.6 l -2.2,-6.3 h -11 l -2.2,6.3 z m 10.3,-11.3 h 7.6 l -3.8,-11 z"
class="st0" />
</g>
</g>
<g
id="g30">
<g
id="g28">
<path
id="path22"
d="m 312.8,200.3 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 11 c 0,3.4 -2.8,6.2 -6.2,6.2 h -8.8 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -11 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -11 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -11 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -11 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -11 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 38.8 c 0,4.6 3.7,8.3 8.3,8.3 H 234 c 3.4,0 6.2,2.8 6.2,6.2 v 11 c 0,4.6 3.7,8.3 8.3,8.3 h 11 c 3.4,0 6.2,2.8 6.2,6.2 v 11 c 0,4.6 3.7,8.3 8.3,8.3 h 11 c 3.4,0 6.2,2.8 6.2,6.2 v 11 c 0,4.6 3.7,8.3 8.3,8.3 h 13.2 c 4.6,0 8.3,-3.7 8.3,-8.3 v -13.2 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -11 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -8.8 c 0,-3.4 2.8,-6.2 6.2,-6.2 h 11 c 4.6,0 8.3,-3.7 8.3,-8.3 v -13.2 c 0.1,-4.7 -3.6,-8.4 -8.2,-8.4 z"
class="st0" />
<path
id="path24"
d="m 210.7,225.8 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 38.8 c 0,4.6 3.7,8.3 8.3,8.3 h 13.2 c 4.6,0 8.3,-3.7 8.3,-8.3 v -38.8 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 z"
class="st0" />
<path
id="path26"
d="m 312.8,149.2 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 13.2 c 0,4.6 3.7,8.3 8.3,8.3 h 13.2 c 4.6,0 8.3,-3.7 8.3,-8.3 v -13.2 c 0,-4.5 -3.7,-8.3 -8.3,-8.3 z"
class="st0" />
</g>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 4.0 KiB

109
static/images/about/novelda_logo_white.svg Normal file
View File

@ -0,0 +1,109 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
inkscape:version="1.0 (4035a4fb49, 2020-05-01)"
height="183.5"
width="221.5"
sodipodi:docname="Novelda_logo_hvit.svg"
xml:space="preserve"
viewBox="0 0 221.49999 183.5"
y="0px"
x="0px"
id="Layer_1"
version="1.1"><metadata
id="metadata39"><rdf:RDF><cc:Work
rdf:about=""><dc:format>image/svg+xml</dc:format><dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" /><dc:title></dc:title></cc:Work></rdf:RDF></metadata><defs
id="defs37" /><sodipodi:namedview
inkscape:current-layer="Layer_1"
inkscape:window-maximized="1"
inkscape:window-y="-8"
inkscape:window-x="-8"
inkscape:cy="91.749997"
inkscape:cx="182.07701"
inkscape:zoom="1.8219548"
fit-margin-bottom="0"
fit-margin-right="0"
fit-margin-left="0"
fit-margin-top="0"
inkscape:pagecheckerboard="true"
showgrid="false"
id="namedview35"
inkscape:window-height="1027"
inkscape:window-width="1920"
inkscape:pageshadow="2"
inkscape:pageopacity="0"
guidetolerance="10"
gridtolerance="10"
objecttolerance="10"
borderopacity="1"
bordercolor="#666666"
pagecolor="#ffffff" />
<style
id="style2"
type="text/css">
.st0{fill:#FFFFFF;}
</style>
<g
transform="translate(-144.4,-149.2)"
id="g32">
<g
id="g20">
<g
id="g18">
<path
id="path4"
d="m 144.4,332.4 v -28.9 h 5.6 l 12.2,18.2 v -18.2 h 6.1 v 28.9 h -5.7 l -12.2,-18.2 v 18.2 z"
class="st0" />
<path
id="path6"
d="m 192.6,332.7 c -8.5,0 -14.3,-6.3 -14.3,-14.7 0,-8.4 5.8,-14.7 14.3,-14.7 8.5,0 14.3,6.3 14.3,14.7 0,8.4 -5.8,14.7 -14.3,14.7 z m 0,-5.3 c 4.8,0 8,-4 8,-9.4 0,-5.4 -3.1,-9.4 -8,-9.4 -4.9,0 -8,4 -8,9.4 0,5.4 3.1,9.4 8,9.4 z"
class="st0" />
<path
id="path8"
d="m 213,303.5 h 6.6 l 6.9,21.4 7.1,-21.4 h 6.4 l -9.8,28.9 h -7.4 z"
class="st0" />
<path
id="path10"
d="M 248.7,303.5 H 268 v 5.3 h -13.2 v 6.5 h 10.7 v 5.1 h -10.7 v 6.7 h 13.6 v 5.3 h -19.8 v -28.9 z"
class="st0" />
<path
id="path12"
d="m 278.4,332.4 v -28.9 h 6.2 V 327 H 296 v 5.3 h -17.6 z"
class="st0" />
<path
id="path14"
d="M 305.5,332.4 V 303.5 H 316 c 9,0 15,5.9 15,14.4 0,8.5 -6,14.5 -15,14.5 z m 6.2,-5.1 h 4.3 c 5.5,0 8.6,-3.8 8.6,-9.3 0,-5.5 -3.1,-9.2 -8.6,-9.2 h -4.3 z"
class="st0" />
<path
id="path16"
d="M 337.4,332.4 348,303.5 h 7.4 l 10.5,28.9 h -6.6 l -2.2,-6.3 h -11 l -2.2,6.3 z m 10.3,-11.3 h 7.6 l -3.8,-11 z"
class="st0" />
</g>
</g>
<g
id="g30">
<g
id="g28">
<path
id="path22"
d="m 312.8,200.3 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 11 c 0,3.4 -2.8,6.2 -6.2,6.2 h -8.8 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -11 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -11 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -11 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -11 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -11 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 38.8 c 0,4.6 3.7,8.3 8.3,8.3 H 234 c 3.4,0 6.2,2.8 6.2,6.2 v 11 c 0,4.6 3.7,8.3 8.3,8.3 h 11 c 3.4,0 6.2,2.8 6.2,6.2 v 11 c 0,4.6 3.7,8.3 8.3,8.3 h 11 c 3.4,0 6.2,2.8 6.2,6.2 v 11 c 0,4.6 3.7,8.3 8.3,8.3 h 13.2 c 4.6,0 8.3,-3.7 8.3,-8.3 v -13.2 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 h -11 c -3.4,0 -6.2,-2.8 -6.2,-6.2 v -8.8 c 0,-3.4 2.8,-6.2 6.2,-6.2 h 11 c 4.6,0 8.3,-3.7 8.3,-8.3 v -13.2 c 0.1,-4.7 -3.6,-8.4 -8.2,-8.4 z"
class="st0" />
<path
id="path24"
d="m 210.7,225.8 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 38.8 c 0,4.6 3.7,8.3 8.3,8.3 h 13.2 c 4.6,0 8.3,-3.7 8.3,-8.3 v -38.8 c 0,-4.6 -3.7,-8.3 -8.3,-8.3 z"
class="st0" />
<path
id="path26"
d="m 312.8,149.2 h -13.2 c -4.6,0 -8.3,3.7 -8.3,8.3 v 13.2 c 0,4.6 3.7,8.3 8.3,8.3 h 13.2 c 4.6,0 8.3,-3.7 8.3,-8.3 v -13.2 c 0,-4.5 -3.7,-8.3 -8.3,-8.3 z"
class="st0" />
</g>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 4.0 KiB

65
static/images/about/sscs_logo.svg Normal file
View File

File diff suppressed because one or more lines are too long
Side by Side

After

Width:  |  Height:  |  Size: 7.5 KiB

BIN
static/images/biocas2013/Area.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 234 KiB

BIN
static/images/biocas2013/Area1.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 206 KiB

BIN
static/images/biocas2013/Area2.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 217 KiB

BIN
static/images/biocas2013/F1.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 60 KiB

BIN
static/images/biocas2013/F2.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 44 KiB

BIN
static/images/biocas2013/F3.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 78 KiB

BIN
static/images/biocas2013/F4.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 9.5 KiB

BIN
static/images/biocas2013/F5.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 18 KiB

BIN
static/images/biocas2013/I1.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 46 KiB

BIN
static/images/biocas2013/I2.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 57 KiB

BIN
static/images/biocas2013/I3.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 65 KiB

BIN
static/images/biocas2013/I4.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 72 KiB

BIN
static/images/biocas2013/I5.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 102 KiB

BIN
static/images/biocas2013/I6.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 75 KiB

BIN
static/images/biocas2013/example.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 59 KiB

BIN
static/images/biocas2013/noise.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 28 KiB

BIN
static/images/biocas2013/os.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 32 KiB

BIN
static/images/biocas2016/Core.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 701 KiB

BIN
static/images/biocas2016/GUI.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 51 KiB

BIN
static/images/biocas2016/Lay_sH.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 113 KiB

644
static/images/biocas2016/Lay_sH.svg Normal file
View File

File diff suppressed because one or more lines are too long
Side by Side

After

Width:  |  Height:  |  Size: 734 KiB

1289
static/images/biocas2016/Lay_uC.svg Normal file
View File

File diff suppressed because one or more lines are too long
Side by Side

After

Width:  |  Height:  |  Size: 2.8 MiB

1361
static/images/biocas2016/NPI_TLT.svg Normal file
View File

File diff suppressed because it is too large Load Diff
Side by Side

After

Width:  |  Height:  |  Size: 158 KiB

87
static/images/biocas2016/Operations.svg Normal file
View File

File diff suppressed because one or more lines are too long
Side by Side

After

Width:  |  Height:  |  Size: 148 KiB

1391
static/images/biocas2016/Sys_iP.svg Normal file
View File

File diff suppressed because one or more lines are too long
Side by Side

After

Width:  |  Height:  |  Size: 244 KiB

1694
static/images/biocas2016/Sys_sH.svg Normal file
View File

File diff suppressed because it is too large Load Diff
Side by Side

After

Width:  |  Height:  |  Size: 315 KiB

1332
static/images/biocas2016/Sys_uC.svg Normal file
View File

File diff suppressed because it is too large Load Diff
Side by Side

After

Width:  |  Height:  |  Size: 236 KiB

14
static/images/biocas2016/TPhw.svg Normal file
View File

File diff suppressed because one or more lines are too long
Side by Side

After

Width:  |  Height:  |  Size: 873 KiB

982
static/images/biocas2016/TPlat.svg Normal file
View File

File diff suppressed because one or more lines are too long
Side by Side

After

Width:  |  Height:  |  Size: 127 KiB

149
static/images/biocas2016/drawing.svg Normal file
View File

@ -0,0 +1,149 @@
<?xml version="1.0" encoding="UTF-8"?>
<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" width="196.763458pt" height="104.726265pt" viewBox="0 0 196.763458 104.726265" version="1.1">
<defs>
<clipPath id="clip1">
<path d="M 149 0 L 196.761719 0 L 196.761719 16 L 149 16 Z M 149 0 "/>
</clipPath>
<clipPath id="clip2">
<path d="M 148 0 L 196.761719 0 L 196.761719 17 L 148 17 Z M 148 0 "/>
</clipPath>
<clipPath id="clip3">
<path d="M 51 72 L 124 72 L 124 104.726562 L 51 104.726562 Z M 51 72 "/>
</clipPath>
<clipPath id="clip4">
<path d="M 50 71 L 125 71 L 125 104.726562 L 50 104.726562 Z M 50 71 "/>
</clipPath>
<clipPath id="clip5">
<path d="M 140 88 L 189 88 L 189 104.726562 L 140 104.726562 Z M 140 88 "/>
</clipPath>
</defs>
<g id="surface1">
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 140.921875 7.519531 L 128.425781 7.519531 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 18.222656 4.816406 L 18.222656 10.898438 L 27.382812 10.898438 L 30.347656 7.933594 L 27.304688 4.894531 Z M 18.222656 4.816406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 50.433594 8.253906 L 42.363281 10.847656 L 42.363281 5.660156 Z M 50.433594 8.253906 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 42.800781 8.054688 L 30.203125 8.054688 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 38 13.851562 C 38 14.8125 37.21875 15.59375 36.257812 15.59375 C 35.292969 15.59375 34.511719 14.8125 34.511719 13.851562 C 34.511719 12.886719 35.292969 12.105469 36.257812 12.105469 C 37.21875 12.105469 38 12.886719 38 13.851562 Z M 38 13.851562 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 38 20.03125 C 38 20.996094 37.21875 21.777344 36.257812 21.777344 C 35.292969 21.777344 34.511719 20.996094 34.511719 20.03125 C 34.511719 19.066406 35.292969 18.285156 36.257812 18.285156 C 37.21875 18.285156 38 19.066406 38 20.03125 Z M 38 20.03125 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 18.222656 23.96875 L 18.222656 30.046875 L 27.382812 30.046875 L 30.347656 27.085938 L 27.304688 24.042969 Z M 18.222656 23.96875 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 50.433594 27.40625 L 42.363281 30 L 42.363281 24.8125 Z M 50.433594 27.40625 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 42.800781 27.207031 L 30.203125 27.207031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 2.941406 9.984375 L 0.457031 3.546875 L 1.378906 3.546875 L 3.050781 8.21875 C 3.183594 8.59375 3.292969 8.949219 3.378906 9.28125 C 3.480469 8.929688 3.601562 8.574219 3.738281 8.21875 L 5.472656 3.546875 L 6.347656 3.546875 L 3.816406 9.984375 Z M 2.941406 9.984375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 6.789062 7.429688 L 7.351562 7.429688 L 7.351562 11.726562 L 6.789062 11.726562 Z M 6.789062 7.429688 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 8.25 11.726562 L 8.25 7.429688 L 8.84375 7.429688 L 11.09375 10.804688 L 11.09375 7.429688 L 11.640625 7.429688 L 11.640625 11.726562 L 11.0625 11.726562 L 8.796875 8.351562 L 8.796875 11.726562 Z M 8.25 11.726562 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 12.183594 11.804688 L 12.449219 10.554688 L 11.949219 10.554688 L 11.949219 10.117188 L 12.527344 10.117188 L 12.746094 9.054688 L 11.949219 9.054688 L 11.949219 8.617188 L 12.839844 8.617188 L 13.089844 7.351562 L 13.527344 7.351562 L 13.277344 8.617188 L 14.199219 8.617188 L 14.449219 7.351562 L 14.902344 7.351562 L 14.636719 8.617188 L 15.152344 8.617188 L 15.152344 9.054688 L 14.558594 9.054688 L 14.339844 10.117188 L 15.152344 10.117188 L 15.152344 10.554688 L 14.246094 10.554688 L 13.996094 11.804688 L 13.558594 11.804688 L 13.808594 10.554688 L 12.886719 10.554688 L 12.621094 11.804688 Z M 12.964844 10.117188 L 13.886719 10.117188 L 14.105469 9.054688 L 13.183594 9.054688 Z M 12.964844 10.117188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 2.832031 29.277344 L 0.347656 22.839844 L 1.269531 22.839844 L 2.941406 27.511719 C 3.074219 27.886719 3.183594 28.242188 3.269531 28.574219 C 3.371094 28.222656 3.492188 27.867188 3.628906 27.511719 L 5.363281 22.839844 L 6.238281 22.839844 L 3.707031 29.277344 Z M 2.832031 29.277344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 6.679688 26.71875 L 7.242188 26.71875 L 7.242188 31.015625 L 6.679688 31.015625 Z M 6.679688 26.71875 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 8.140625 31.015625 L 8.140625 26.71875 L 8.734375 26.71875 L 10.984375 30.09375 L 10.984375 26.71875 L 11.53125 26.71875 L 11.53125 31.015625 L 10.953125 31.015625 L 8.6875 27.640625 L 8.6875 31.015625 Z M 8.140625 31.015625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 12.027344 29.875 L 12.558594 29.8125 C 12.621094 30.117188 12.722656 30.335938 12.871094 30.46875 C 13.015625 30.59375 13.191406 30.65625 13.402344 30.65625 C 13.652344 30.65625 13.859375 30.574219 14.027344 30.40625 C 14.191406 30.230469 14.277344 30.015625 14.277344 29.765625 C 14.277344 29.515625 14.199219 29.3125 14.042969 29.15625 C 13.886719 29 13.6875 28.921875 13.449219 28.921875 C 13.34375 28.921875 13.21875 28.945312 13.074219 28.984375 L 13.121094 28.515625 C 13.160156 28.527344 13.191406 28.53125 13.214844 28.53125 C 13.433594 28.53125 13.628906 28.476562 13.808594 28.359375 C 13.996094 28.234375 14.089844 28.054688 14.089844 27.8125 C 14.089844 27.617188 14.019531 27.453125 13.886719 27.328125 C 13.761719 27.203125 13.59375 27.140625 13.386719 27.140625 C 13.175781 27.140625 13.003906 27.203125 12.871094 27.328125 C 12.734375 27.453125 12.644531 27.648438 12.605469 27.90625 L 12.089844 27.8125 C 12.152344 27.460938 12.296875 27.1875 12.527344 27 C 12.753906 26.804688 13.035156 26.703125 13.371094 26.703125 C 13.609375 26.703125 13.828125 26.757812 14.027344 26.859375 C 14.222656 26.953125 14.375 27.089844 14.480469 27.265625 C 14.582031 27.445312 14.636719 27.625 14.636719 27.8125 C 14.636719 28 14.582031 28.171875 14.480469 28.328125 C 14.386719 28.476562 14.238281 28.59375 14.042969 28.6875 C 14.292969 28.75 14.484375 28.875 14.621094 29.0625 C 14.765625 29.242188 14.839844 29.46875 14.839844 29.75 C 14.839844 30.125 14.703125 30.445312 14.433594 30.703125 C 14.160156 30.964844 13.816406 31.09375 13.402344 31.09375 C 13.015625 31.09375 12.699219 30.984375 12.449219 30.765625 C 12.207031 30.539062 12.066406 30.242188 12.027344 29.875 Z M 12.027344 29.875 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 59.410156 1.652344 L 131.613281 1.652344 L 131.613281 33.574219 L 59.410156 33.574219 Z M 59.410156 1.652344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 148.960938 7.429688 L 140.890625 10.023438 L 140.890625 4.832031 L 144.925781 6.132812 Z M 148.960938 7.429688 "/>
<g clip-path="url(#clip1)" clip-rule="nonzero">
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 149.5 0.601562 L 196.164062 0.601562 L 196.164062 15.578125 L 149.5 15.578125 Z M 149.5 0.601562 "/>
</g>
<g clip-path="url(#clip2)" clip-rule="nonzero">
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 149.5 0.601562 L 196.164062 0.601562 L 196.164062 15.578125 L 149.5 15.578125 Z M 149.5 0.601562 "/>
</g>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 153.667969 10.410156 L 153.667969 3.972656 L 156.527344 3.972656 C 157.097656 3.972656 157.535156 4.03125 157.839844 4.144531 C 158.140625 4.261719 158.378906 4.464844 158.558594 4.753906 C 158.734375 5.046875 158.824219 5.371094 158.824219 5.722656 C 158.824219 6.183594 158.671875 6.566406 158.371094 6.878906 C 158.078125 7.191406 157.625 7.390625 157.011719 7.472656 C 157.230469 7.589844 157.402344 7.699219 157.527344 7.800781 C 157.777344 8.03125 158.011719 8.316406 158.230469 8.660156 L 159.355469 10.410156 L 158.277344 10.410156 L 157.417969 9.066406 C 157.175781 8.683594 156.972656 8.390625 156.808594 8.191406 C 156.652344 7.984375 156.503906 7.839844 156.371094 7.753906 C 156.246094 7.671875 156.121094 7.613281 155.996094 7.582031 C 155.890625 7.5625 155.730469 7.550781 155.511719 7.550781 L 154.527344 7.550781 L 154.527344 10.410156 Z M 154.527344 6.816406 L 156.355469 6.816406 C 156.75 6.816406 157.058594 6.777344 157.277344 6.691406 C 157.496094 6.609375 157.660156 6.480469 157.777344 6.300781 C 157.890625 6.125 157.949219 5.933594 157.949219 5.722656 C 157.949219 5.421875 157.832031 5.171875 157.605469 4.972656 C 157.386719 4.777344 157.035156 4.675781 156.558594 4.675781 L 154.527344 4.675781 Z M 154.527344 6.816406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 163.039062 8.910156 L 163.867188 9.003906 C 163.730469 9.484375 163.484375 9.859375 163.132812 10.128906 C 162.789062 10.390625 162.34375 10.519531 161.804688 10.519531 C 161.125 10.519531 160.585938 10.3125 160.179688 9.894531 C 159.78125 9.46875 159.585938 8.875 159.585938 8.113281 C 159.585938 7.332031 159.789062 6.730469 160.195312 6.300781 C 160.601562 5.863281 161.125 5.644531 161.773438 5.644531 C 162.398438 5.644531 162.902344 5.859375 163.289062 6.285156 C 163.683594 6.703125 163.882812 7.296875 163.882812 8.066406 C 163.882812 8.121094 163.882812 8.191406 163.882812 8.285156 L 160.398438 8.285156 C 160.429688 8.796875 160.574219 9.1875 160.835938 9.457031 C 161.09375 9.730469 161.421875 9.863281 161.820312 9.863281 C 162.109375 9.863281 162.355469 9.792969 162.554688 9.644531 C 162.761719 9.488281 162.921875 9.246094 163.039062 8.910156 Z M 160.445312 7.628906 L 163.054688 7.628906 C 163.023438 7.234375 162.921875 6.9375 162.757812 6.738281 C 162.507812 6.4375 162.179688 6.285156 161.773438 6.285156 C 161.40625 6.285156 161.101562 6.410156 160.851562 6.660156 C 160.609375 6.902344 160.476562 7.222656 160.445312 7.628906 Z M 160.445312 7.628906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 167.746094 8.707031 L 168.527344 8.800781 C 168.441406 9.34375 168.222656 9.765625 167.871094 10.066406 C 167.515625 10.371094 167.082031 10.519531 166.574219 10.519531 C 165.9375 10.519531 165.425781 10.3125 165.042969 9.894531 C 164.65625 9.480469 164.464844 8.878906 164.464844 8.097656 C 164.464844 7.589844 164.546875 7.144531 164.714844 6.769531 C 164.878906 6.394531 165.128906 6.113281 165.464844 5.925781 C 165.808594 5.738281 166.183594 5.644531 166.589844 5.644531 C 167.089844 5.644531 167.5 5.777344 167.824219 6.035156 C 168.144531 6.285156 168.355469 6.644531 168.449219 7.113281 L 167.683594 7.238281 C 167.609375 6.925781 167.480469 6.691406 167.292969 6.535156 C 167.105469 6.371094 166.878906 6.285156 166.621094 6.285156 C 166.214844 6.285156 165.886719 6.433594 165.636719 6.722656 C 165.394531 7.003906 165.277344 7.453125 165.277344 8.066406 C 165.277344 8.703125 165.394531 9.160156 165.636719 9.441406 C 165.875 9.722656 166.1875 9.863281 166.574219 9.863281 C 166.886719 9.863281 167.144531 9.769531 167.355469 9.582031 C 167.5625 9.394531 167.691406 9.105469 167.746094 8.707031 Z M 167.746094 8.707031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 168.757812 8.082031 C 168.757812 7.21875 168.996094 6.578125 169.476562 6.160156 C 169.882812 5.816406 170.371094 5.644531 170.945312 5.644531 C 171.589844 5.644531 172.117188 5.855469 172.523438 6.269531 C 172.929688 6.6875 173.132812 7.265625 173.132812 8.003906 C 173.132812 8.609375 173.039062 9.082031 172.851562 9.425781 C 172.671875 9.769531 172.414062 10.042969 172.070312 10.238281 C 171.726562 10.425781 171.351562 10.519531 170.945312 10.519531 C 170.289062 10.519531 169.757812 10.3125 169.351562 9.894531 C 168.953125 9.46875 168.757812 8.863281 168.757812 8.082031 Z M 169.570312 8.082031 C 169.570312 8.675781 169.699219 9.125 169.960938 9.425781 C 170.21875 9.71875 170.546875 9.863281 170.945312 9.863281 C 171.339844 9.863281 171.667969 9.71875 171.929688 9.425781 C 172.1875 9.125 172.320312 8.667969 172.320312 8.050781 C 172.320312 7.480469 172.1875 7.042969 171.929688 6.738281 C 171.667969 6.4375 171.339844 6.285156 170.945312 6.285156 C 170.546875 6.285156 170.21875 6.4375 169.960938 6.738281 C 169.699219 7.03125 169.570312 7.480469 169.570312 8.082031 Z M 169.570312 8.082031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 173.886719 10.410156 L 173.886719 5.738281 L 174.605469 5.738281 L 174.605469 6.457031 C 174.78125 6.125 174.949219 5.90625 175.105469 5.800781 C 175.261719 5.699219 175.433594 5.644531 175.621094 5.644531 C 175.878906 5.644531 176.152344 5.730469 176.433594 5.894531 L 176.152344 6.628906 C 175.964844 6.515625 175.769531 6.457031 175.574219 6.457031 C 175.40625 6.457031 175.25 6.511719 175.105469 6.613281 C 174.96875 6.71875 174.871094 6.863281 174.808594 7.050781 C 174.722656 7.332031 174.683594 7.640625 174.683594 7.972656 L 174.683594 10.410156 Z M 173.886719 10.410156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 179.839844 10.410156 L 179.839844 9.816406 C 179.535156 10.285156 179.097656 10.519531 178.527344 10.519531 C 178.160156 10.519531 177.824219 10.414062 177.511719 10.207031 C 177.199219 10 176.953125 9.714844 176.777344 9.347656 C 176.609375 8.984375 176.527344 8.5625 176.527344 8.082031 C 176.527344 7.613281 176.605469 7.191406 176.761719 6.816406 C 176.917969 6.433594 177.144531 6.140625 177.449219 5.941406 C 177.761719 5.746094 178.109375 5.644531 178.496094 5.644531 C 178.777344 5.644531 179.027344 5.703125 179.246094 5.816406 C 179.464844 5.933594 179.640625 6.089844 179.777344 6.285156 L 179.777344 3.972656 L 180.574219 3.972656 L 180.574219 10.410156 Z M 177.339844 8.082031 C 177.339844 8.675781 177.464844 9.125 177.714844 9.425781 C 177.964844 9.71875 178.261719 9.863281 178.605469 9.863281 C 178.949219 9.863281 179.238281 9.722656 179.480469 9.441406 C 179.730469 9.160156 179.855469 8.730469 179.855469 8.144531 C 179.855469 7.511719 179.730469 7.042969 179.480469 6.738281 C 179.230469 6.4375 178.925781 6.285156 178.574219 6.285156 C 178.21875 6.285156 177.921875 6.433594 177.683594 6.722656 C 177.453125 7.015625 177.339844 7.46875 177.339844 8.082031 Z M 177.339844 8.082031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 181.65625 4.878906 L 181.65625 3.972656 L 182.453125 3.972656 L 182.453125 4.878906 Z M 181.65625 10.410156 L 181.65625 5.738281 L 182.453125 5.738281 L 182.453125 10.410156 Z M 181.65625 10.410156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 183.597656 10.410156 L 183.597656 5.738281 L 184.316406 5.738281 L 184.316406 6.410156 C 184.648438 5.902344 185.144531 5.644531 185.800781 5.644531 C 186.082031 5.644531 186.335938 5.699219 186.566406 5.800781 C 186.804688 5.894531 186.980469 6.027344 187.097656 6.191406 C 187.210938 6.347656 187.292969 6.542969 187.347656 6.769531 C 187.378906 6.917969 187.394531 7.171875 187.394531 7.535156 L 187.394531 10.410156 L 186.597656 10.410156 L 186.597656 7.566406 C 186.597656 7.246094 186.566406 7.003906 186.503906 6.847656 C 186.441406 6.691406 186.332031 6.566406 186.175781 6.472656 C 186.019531 6.371094 185.835938 6.316406 185.628906 6.316406 C 185.292969 6.316406 185.003906 6.425781 184.753906 6.644531 C 184.511719 6.855469 184.394531 7.261719 184.394531 7.863281 L 184.394531 10.410156 Z M 183.597656 10.410156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 188.300781 10.800781 L 189.066406 10.910156 C 189.097656 11.148438 189.183594 11.320312 189.332031 11.425781 C 189.527344 11.570312 189.800781 11.644531 190.144531 11.644531 C 190.507812 11.644531 190.789062 11.570312 190.988281 11.425781 C 191.183594 11.277344 191.320312 11.074219 191.394531 10.816406 C 191.433594 10.648438 191.449219 10.3125 191.441406 9.800781 C 191.097656 10.207031 190.667969 10.410156 190.160156 10.410156 C 189.511719 10.410156 189.011719 10.183594 188.660156 9.722656 C 188.316406 9.253906 188.144531 8.699219 188.144531 8.050781 C 188.144531 7.605469 188.222656 7.191406 188.378906 6.816406 C 188.542969 6.441406 188.777344 6.15625 189.082031 5.957031 C 189.382812 5.75 189.742188 5.644531 190.160156 5.644531 C 190.710938 5.644531 191.164062 5.863281 191.519531 6.300781 L 191.519531 5.738281 L 192.253906 5.738281 L 192.253906 9.769531 C 192.253906 10.496094 192.175781 11.011719 192.019531 11.316406 C 191.871094 11.617188 191.636719 11.855469 191.316406 12.035156 C 191.003906 12.210938 190.613281 12.300781 190.144531 12.300781 C 189.582031 12.300781 189.128906 12.175781 188.785156 11.925781 C 188.449219 11.675781 188.289062 11.300781 188.300781 10.800781 Z M 188.957031 7.988281 C 188.957031 8.605469 189.074219 9.050781 189.316406 9.332031 C 189.554688 9.613281 189.855469 9.753906 190.222656 9.753906 C 190.585938 9.753906 190.894531 9.613281 191.144531 9.332031 C 191.394531 9.050781 191.519531 8.613281 191.519531 8.019531 C 191.519531 7.449219 191.386719 7.015625 191.128906 6.722656 C 190.878906 6.433594 190.574219 6.285156 190.222656 6.285156 C 189.867188 6.285156 189.566406 6.433594 189.316406 6.722656 C 189.074219 7.003906 188.957031 7.425781 188.957031 7.988281 Z M 188.957031 7.988281 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 56.769531 7.695312 L 128.972656 7.695312 L 128.972656 39.621094 L 56.769531 39.621094 Z M 56.769531 7.695312 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 54.273438 15.363281 L 126.476562 15.363281 L 126.476562 47.285156 L 54.273438 47.285156 Z M 54.273438 15.363281 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 18.203125 35.847656 L 18.203125 41.929688 L 27.363281 41.929688 L 30.324219 38.964844 L 27.285156 35.925781 Z M 18.203125 35.847656 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 50.414062 39.289062 L 46.378906 40.585938 L 42.339844 41.882812 L 42.339844 36.691406 L 46.378906 37.988281 Z M 50.414062 39.289062 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 42.78125 39.085938 L 30.179688 39.085938 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 2.492188 40.984375 L 0.0078125 34.546875 L 0.929688 34.546875 L 2.601562 39.21875 C 2.734375 39.59375 2.84375 39.949219 2.929688 40.28125 C 3.03125 39.929688 3.152344 39.574219 3.289062 39.21875 L 5.023438 34.546875 L 5.898438 34.546875 L 3.367188 40.984375 Z M 2.492188 40.984375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 6.339844 38.429688 L 6.902344 38.429688 L 6.902344 42.726562 L 6.339844 42.726562 Z M 6.339844 38.429688 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 7.800781 42.726562 L 7.800781 38.429688 L 8.394531 38.429688 L 10.644531 41.804688 L 10.644531 38.429688 L 11.191406 38.429688 L 11.191406 42.726562 L 10.613281 42.726562 L 8.347656 39.351562 L 8.347656 42.726562 Z M 7.800781 42.726562 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 14.453125 42.226562 L 14.453125 42.726562 L 11.625 42.726562 C 11.613281 42.601562 11.632812 42.484375 11.6875 42.367188 C 11.757812 42.171875 11.875 41.976562 12.03125 41.789062 C 12.1875 41.601562 12.414062 41.382812 12.71875 41.132812 C 13.1875 40.757812 13.5 40.460938 13.65625 40.242188 C 13.820312 40.015625 13.90625 39.800781 13.90625 39.601562 C 13.90625 39.382812 13.832031 39.207031 13.6875 39.070312 C 13.539062 38.925781 13.347656 38.851562 13.109375 38.851562 C 12.847656 38.851562 12.640625 38.929688 12.484375 39.085938 C 12.335938 39.234375 12.265625 39.441406 12.265625 39.710938 L 11.71875 39.648438 C 11.757812 39.253906 11.898438 38.953125 12.140625 38.742188 C 12.378906 38.523438 12.703125 38.414062 13.109375 38.414062 C 13.523438 38.414062 13.851562 38.53125 14.09375 38.757812 C 14.332031 38.988281 14.453125 39.269531 14.453125 39.601562 C 14.453125 39.78125 14.414062 39.953125 14.34375 40.117188 C 14.269531 40.285156 14.148438 40.460938 13.984375 40.648438 C 13.828125 40.828125 13.5625 41.078125 13.1875 41.398438 C 12.863281 41.660156 12.65625 41.835938 12.5625 41.929688 C 12.476562 42.023438 12.410156 42.125 12.359375 42.226562 Z M 14.453125 42.226562 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 51.695312 23.507812 L 123.898438 23.507812 L 123.898438 55.433594 L 51.695312 55.433594 Z M 51.695312 23.507812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 61.613281 52.085938 L 61.613281 45.648438 L 62.488281 45.648438 L 65.863281 50.695312 L 65.863281 45.648438 L 66.691406 45.648438 L 66.691406 52.085938 L 65.816406 52.085938 L 62.425781 47.023438 L 62.425781 52.085938 Z M 61.613281 52.085938 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 67.90625 52.085938 L 67.90625 45.648438 L 70.34375 45.648438 C 70.769531 45.648438 71.097656 45.671875 71.328125 45.710938 C 71.640625 45.765625 71.898438 45.863281 72.109375 46.007812 C 72.328125 46.15625 72.5 46.363281 72.625 46.632812 C 72.757812 46.894531 72.828125 47.1875 72.828125 47.507812 C 72.828125 48.0625 72.648438 48.523438 72.296875 48.898438 C 71.953125 49.273438 71.328125 49.460938 70.421875 49.460938 L 68.765625 49.460938 L 68.765625 52.085938 Z M 68.765625 48.710938 L 70.4375 48.710938 C 70.976562 48.710938 71.363281 48.609375 71.59375 48.398438 C 71.832031 48.191406 71.953125 47.90625 71.953125 47.539062 C 71.953125 47.269531 71.882812 47.039062 71.75 46.851562 C 71.613281 46.65625 71.429688 46.523438 71.203125 46.460938 C 71.066406 46.421875 70.800781 46.398438 70.40625 46.398438 L 68.765625 46.398438 Z M 68.765625 48.710938 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 73.878906 45.648438 L 74.722656 45.648438 L 74.722656 52.085938 L 73.878906 52.085938 Z M 73.878906 45.648438 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 78.710938 45.648438 L 79.554688 45.648438 L 79.554688 52.085938 L 78.710938 52.085938 Z M 78.710938 45.648438 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 80.875 52.085938 L 80.875 47.414062 L 81.59375 47.414062 L 81.59375 48.085938 C 81.925781 47.578125 82.421875 47.320312 83.078125 47.320312 C 83.359375 47.320312 83.613281 47.375 83.84375 47.476562 C 84.082031 47.570312 84.257812 47.703125 84.375 47.867188 C 84.488281 48.023438 84.570312 48.21875 84.625 48.445312 C 84.65625 48.59375 84.671875 48.847656 84.671875 49.210938 L 84.671875 52.085938 L 83.875 52.085938 L 83.875 49.242188 C 83.875 48.921875 83.84375 48.679688 83.78125 48.523438 C 83.71875 48.367188 83.609375 48.242188 83.453125 48.148438 C 83.296875 48.046875 83.113281 47.992188 82.90625 47.992188 C 82.570312 47.992188 82.28125 48.101562 82.03125 48.320312 C 81.789062 48.53125 81.671875 48.9375 81.671875 49.539062 L 81.671875 52.085938 Z M 80.875 52.085938 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 87.457031 51.382812 L 87.566406 52.070312 C 87.335938 52.121094 87.136719 52.148438 86.972656 52.148438 C 86.679688 52.148438 86.457031 52.101562 86.300781 52.007812 C 86.144531 51.914062 86.027344 51.796875 85.957031 51.648438 C 85.894531 51.503906 85.863281 51.195312 85.863281 50.726562 L 85.863281 48.039062 L 85.285156 48.039062 L 85.285156 47.414062 L 85.863281 47.414062 L 85.863281 46.257812 L 86.660156 45.789062 L 86.660156 47.414062 L 87.457031 47.414062 L 87.457031 48.039062 L 86.660156 48.039062 L 86.660156 50.757812 C 86.660156 50.988281 86.667969 51.132812 86.691406 51.195312 C 86.722656 51.257812 86.769531 51.3125 86.832031 51.351562 C 86.894531 51.394531 86.980469 51.414062 87.097656 51.414062 C 87.191406 51.414062 87.308594 51.40625 87.457031 51.382812 Z M 87.457031 51.382812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 91.328125 50.585938 L 92.15625 50.679688 C 92.019531 51.160156 91.773438 51.535156 91.421875 51.804688 C 91.078125 52.066406 90.632812 52.195312 90.09375 52.195312 C 89.414062 52.195312 88.875 51.988281 88.46875 51.570312 C 88.070312 51.144531 87.875 50.550781 87.875 49.789062 C 87.875 49.007812 88.078125 48.40625 88.484375 47.976562 C 88.890625 47.539062 89.414062 47.320312 90.0625 47.320312 C 90.6875 47.320312 91.191406 47.535156 91.578125 47.960938 C 91.972656 48.378906 92.171875 48.972656 92.171875 49.742188 C 92.171875 49.796875 92.171875 49.867188 92.171875 49.960938 L 88.6875 49.960938 C 88.71875 50.472656 88.863281 50.863281 89.125 51.132812 C 89.382812 51.40625 89.710938 51.539062 90.109375 51.539062 C 90.398438 51.539062 90.644531 51.46875 90.84375 51.320312 C 91.050781 51.164062 91.210938 50.921875 91.328125 50.585938 Z M 88.734375 49.304688 L 91.34375 49.304688 C 91.3125 48.910156 91.210938 48.613281 91.046875 48.414062 C 90.796875 48.113281 90.46875 47.960938 90.0625 47.960938 C 89.695312 47.960938 89.390625 48.085938 89.140625 48.335938 C 88.898438 48.578125 88.765625 48.898438 88.734375 49.304688 Z M 88.734375 49.304688 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 92.96875 52.085938 L 92.96875 47.414062 L 93.6875 47.414062 L 93.6875 48.132812 C 93.863281 47.800781 94.03125 47.582031 94.1875 47.476562 C 94.34375 47.375 94.515625 47.320312 94.703125 47.320312 C 94.960938 47.320312 95.234375 47.40625 95.515625 47.570312 L 95.234375 48.304688 C 95.046875 48.191406 94.851562 48.132812 94.65625 48.132812 C 94.488281 48.132812 94.332031 48.1875 94.1875 48.289062 C 94.050781 48.394531 93.953125 48.539062 93.890625 48.726562 C 93.804688 49.007812 93.765625 49.316406 93.765625 49.648438 L 93.765625 52.085938 Z M 92.96875 52.085938 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 96.082031 52.085938 L 96.082031 48.039062 L 95.378906 48.039062 L 95.378906 47.414062 L 96.082031 47.414062 L 96.082031 46.929688 C 96.082031 46.609375 96.105469 46.375 96.160156 46.226562 C 96.242188 46.019531 96.378906 45.851562 96.566406 45.726562 C 96.761719 45.601562 97.035156 45.539062 97.378906 45.539062 C 97.597656 45.539062 97.839844 45.566406 98.113281 45.617188 L 97.988281 46.304688 C 97.832031 46.273438 97.679688 46.257812 97.535156 46.257812 C 97.292969 46.257812 97.121094 46.3125 97.019531 46.414062 C 96.914062 46.519531 96.863281 46.710938 96.863281 46.992188 L 96.863281 47.414062 L 97.785156 47.414062 L 97.785156 48.039062 L 96.863281 48.039062 L 96.863281 52.085938 Z M 96.082031 52.085938 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 101.355469 51.507812 C 101.0625 51.757812 100.78125 51.9375 100.511719 52.039062 C 100.238281 52.140625 99.949219 52.195312 99.636719 52.195312 C 99.125 52.195312 98.730469 52.070312 98.449219 51.820312 C 98.175781 51.570312 98.042969 51.25 98.042969 50.851562 C 98.042969 50.625 98.09375 50.414062 98.199219 50.226562 C 98.300781 50.039062 98.4375 49.890625 98.605469 49.773438 C 98.769531 49.660156 98.957031 49.570312 99.167969 49.507812 C 99.324219 49.476562 99.558594 49.441406 99.871094 49.398438 C 100.515625 49.328125 100.988281 49.234375 101.292969 49.117188 C 101.292969 49.015625 101.292969 48.945312 101.292969 48.914062 C 101.292969 48.59375 101.21875 48.367188 101.074219 48.242188 C 100.863281 48.054688 100.5625 47.960938 100.167969 47.960938 C 99.792969 47.960938 99.515625 48.03125 99.339844 48.164062 C 99.160156 48.289062 99.03125 48.519531 98.949219 48.851562 L 98.183594 48.757812 C 98.246094 48.425781 98.355469 48.160156 98.511719 47.960938 C 98.675781 47.753906 98.910156 47.597656 99.214844 47.492188 C 99.527344 47.378906 99.878906 47.320312 100.277344 47.320312 C 100.683594 47.320312 101.003906 47.367188 101.246094 47.460938 C 101.496094 47.554688 101.675781 47.675781 101.792969 47.820312 C 101.917969 47.957031 102 48.132812 102.042969 48.351562 C 102.074219 48.488281 102.089844 48.726562 102.089844 49.070312 L 102.089844 50.132812 C 102.089844 50.863281 102.105469 51.328125 102.136719 51.523438 C 102.167969 51.722656 102.234375 51.910156 102.339844 52.085938 L 101.511719 52.085938 C 101.425781 51.921875 101.375 51.726562 101.355469 51.507812 Z M 101.292969 49.742188 C 101 49.859375 100.566406 49.957031 99.996094 50.039062 C 99.671875 50.09375 99.441406 50.148438 99.308594 50.210938 C 99.171875 50.265625 99.066406 50.347656 98.996094 50.460938 C 98.921875 50.578125 98.886719 50.703125 98.886719 50.835938 C 98.886719 51.046875 98.964844 51.222656 99.121094 51.367188 C 99.277344 51.503906 99.511719 51.570312 99.824219 51.570312 C 100.125 51.570312 100.394531 51.503906 100.636719 51.367188 C 100.875 51.234375 101.050781 51.050781 101.167969 50.820312 C 101.25 50.644531 101.292969 50.382812 101.292969 50.039062 Z M 101.292969 49.742188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 106.203125 50.382812 L 106.984375 50.476562 C 106.898438 51.019531 106.679688 51.441406 106.328125 51.742188 C 105.972656 52.046875 105.539062 52.195312 105.03125 52.195312 C 104.394531 52.195312 103.882812 51.988281 103.5 51.570312 C 103.113281 51.15625 102.921875 50.554688 102.921875 49.773438 C 102.921875 49.265625 103.003906 48.820312 103.171875 48.445312 C 103.335938 48.070312 103.585938 47.789062 103.921875 47.601562 C 104.265625 47.414062 104.640625 47.320312 105.046875 47.320312 C 105.546875 47.320312 105.957031 47.453125 106.28125 47.710938 C 106.601562 47.960938 106.8125 48.320312 106.90625 48.789062 L 106.140625 48.914062 C 106.066406 48.601562 105.9375 48.367188 105.75 48.210938 C 105.5625 48.046875 105.335938 47.960938 105.078125 47.960938 C 104.671875 47.960938 104.34375 48.109375 104.09375 48.398438 C 103.851562 48.679688 103.734375 49.128906 103.734375 49.742188 C 103.734375 50.378906 103.851562 50.835938 104.09375 51.117188 C 104.332031 51.398438 104.644531 51.539062 105.03125 51.539062 C 105.34375 51.539062 105.601562 51.445312 105.8125 51.257812 C 106.019531 51.070312 106.148438 50.78125 106.203125 50.382812 Z M 106.203125 50.382812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 110.699219 50.585938 L 111.527344 50.679688 C 111.390625 51.160156 111.144531 51.535156 110.792969 51.804688 C 110.449219 52.066406 110.003906 52.195312 109.464844 52.195312 C 108.785156 52.195312 108.246094 51.988281 107.839844 51.570312 C 107.441406 51.144531 107.246094 50.550781 107.246094 49.789062 C 107.246094 49.007812 107.449219 48.40625 107.855469 47.976562 C 108.261719 47.539062 108.785156 47.320312 109.433594 47.320312 C 110.058594 47.320312 110.5625 47.535156 110.949219 47.960938 C 111.34375 48.378906 111.542969 48.972656 111.542969 49.742188 C 111.542969 49.796875 111.542969 49.867188 111.542969 49.960938 L 108.058594 49.960938 C 108.089844 50.472656 108.234375 50.863281 108.496094 51.132812 C 108.753906 51.40625 109.082031 51.539062 109.480469 51.539062 C 109.769531 51.539062 110.015625 51.46875 110.214844 51.320312 C 110.421875 51.164062 110.582031 50.921875 110.699219 50.585938 Z M 108.105469 49.304688 L 110.714844 49.304688 C 110.683594 48.910156 110.582031 48.613281 110.417969 48.414062 C 110.167969 48.113281 109.839844 47.960938 109.433594 47.960938 C 109.066406 47.960938 108.761719 48.085938 108.511719 48.335938 C 108.269531 48.578125 108.136719 48.898438 108.105469 49.304688 Z M 108.105469 49.304688 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 57.679688 35.261719 L 116.734375 35.261719 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 75.171875 35.238281 L 79.828125 29.042969 L 89.039062 29.042969 L 89.039062 41.421875 L 79.828125 41.421875 Z M 75.171875 35.238281 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.207682;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 73.60922 35.328125 L 67.773498 38.695312 L 61.93382 42.066406 L 61.93382 28.585938 L 67.773498 31.957031 Z M 73.60922 35.328125 " transform="matrix(0.987319,0,0,1,0,0)"/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 93.5 28.953125 L 113.699219 28.953125 L 113.699219 41.371094 L 93.5 41.371094 Z M 93.5 28.953125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 95.300781 38.210938 L 95.300781 31.773438 L 97.519531 31.773438 C 98.027344 31.773438 98.414062 31.804688 98.675781 31.867188 C 99.039062 31.953125 99.351562 32.101562 99.613281 32.320312 C 99.957031 32.613281 100.210938 32.984375 100.378906 33.429688 C 100.542969 33.867188 100.628906 34.378906 100.628906 34.960938 C 100.628906 35.453125 100.570312 35.882812 100.457031 36.257812 C 100.339844 36.632812 100.195312 36.945312 100.019531 37.195312 C 99.839844 37.445312 99.644531 37.644531 99.425781 37.789062 C 99.214844 37.925781 98.960938 38.03125 98.660156 38.101562 C 98.367188 38.175781 98.023438 38.210938 97.628906 38.210938 Z M 96.160156 37.445312 L 97.535156 37.445312 C 97.960938 37.445312 98.292969 37.410156 98.535156 37.335938 C 98.773438 37.253906 98.964844 37.140625 99.113281 36.992188 C 99.308594 36.796875 99.464844 36.523438 99.582031 36.179688 C 99.695312 35.835938 99.753906 35.425781 99.753906 34.945312 C 99.753906 34.269531 99.644531 33.753906 99.425781 33.398438 C 99.207031 33.035156 98.933594 32.789062 98.613281 32.664062 C 98.382812 32.570312 98.019531 32.523438 97.519531 32.523438 L 96.160156 32.523438 Z M 96.160156 37.445312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 101.3125 36.148438 L 102.109375 36.070312 C 102.148438 36.394531 102.238281 36.660156 102.375 36.867188 C 102.519531 37.078125 102.738281 37.242188 103.03125 37.367188 C 103.320312 37.492188 103.648438 37.554688 104.015625 37.554688 C 104.335938 37.554688 104.625 37.507812 104.875 37.414062 C 105.125 37.320312 105.3125 37.191406 105.4375 37.023438 C 105.5625 36.847656 105.625 36.660156 105.625 36.460938 C 105.625 36.265625 105.5625 36.09375 105.4375 35.945312 C 105.320312 35.789062 105.128906 35.660156 104.859375 35.554688 C 104.691406 35.484375 104.3125 35.378906 103.71875 35.242188 C 103.125 35.097656 102.707031 34.960938 102.46875 34.835938 C 102.164062 34.679688 101.9375 34.484375 101.78125 34.242188 C 101.632812 34.003906 101.5625 33.734375 101.5625 33.429688 C 101.5625 33.109375 101.648438 32.804688 101.828125 32.523438 C 102.015625 32.242188 102.285156 32.03125 102.640625 31.882812 C 102.992188 31.738281 103.390625 31.664062 103.828125 31.664062 C 104.304688 31.664062 104.726562 31.742188 105.09375 31.898438 C 105.457031 32.046875 105.734375 32.269531 105.921875 32.570312 C 106.117188 32.875 106.226562 33.210938 106.25 33.585938 L 105.421875 33.648438 C 105.378906 33.242188 105.234375 32.9375 104.984375 32.726562 C 104.734375 32.519531 104.359375 32.414062 103.859375 32.414062 C 103.347656 32.414062 102.972656 32.507812 102.734375 32.695312 C 102.492188 32.882812 102.375 33.113281 102.375 33.382812 C 102.375 33.613281 102.457031 33.800781 102.625 33.945312 C 102.789062 34.101562 103.21875 34.257812 103.90625 34.414062 C 104.601562 34.570312 105.082031 34.707031 105.34375 34.820312 C 105.71875 34.988281 105.992188 35.207031 106.171875 35.476562 C 106.347656 35.738281 106.4375 36.046875 106.4375 36.398438 C 106.4375 36.734375 106.335938 37.054688 106.140625 37.367188 C 105.941406 37.671875 105.660156 37.90625 105.296875 38.070312 C 104.929688 38.234375 104.519531 38.320312 104.0625 38.320312 C 103.476562 38.320312 102.988281 38.234375 102.59375 38.070312 C 102.195312 37.894531 101.882812 37.640625 101.65625 37.304688 C 101.4375 36.960938 101.320312 36.578125 101.3125 36.148438 Z M 101.3125 36.148438 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 107.410156 38.210938 L 107.410156 31.773438 L 109.847656 31.773438 C 110.273438 31.773438 110.601562 31.796875 110.832031 31.835938 C 111.144531 31.890625 111.402344 31.988281 111.613281 32.132812 C 111.832031 32.28125 112.003906 32.488281 112.128906 32.757812 C 112.261719 33.019531 112.332031 33.3125 112.332031 33.632812 C 112.332031 34.1875 112.152344 34.648438 111.800781 35.023438 C 111.457031 35.398438 110.832031 35.585938 109.925781 35.585938 L 108.269531 35.585938 L 108.269531 38.210938 Z M 108.269531 34.835938 L 109.941406 34.835938 C 110.480469 34.835938 110.867188 34.734375 111.097656 34.523438 C 111.335938 34.316406 111.457031 34.03125 111.457031 33.664062 C 111.457031 33.394531 111.386719 33.164062 111.253906 32.976562 C 111.117188 32.78125 110.933594 32.648438 110.707031 32.585938 C 110.570312 32.546875 110.304688 32.523438 109.910156 32.523438 L 108.269531 32.523438 Z M 108.269531 34.835938 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 118.652344 35.136719 C 118.652344 35.988281 117.964844 36.675781 117.113281 36.675781 C 116.261719 36.675781 115.574219 35.988281 115.574219 35.136719 C 115.574219 34.285156 116.261719 33.597656 117.113281 33.597656 C 117.964844 33.597656 118.652344 34.285156 118.652344 35.136719 Z M 118.652344 35.136719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 58.738281 35.25 C 58.738281 36.101562 58.050781 36.792969 57.199219 36.792969 C 56.347656 36.792969 55.660156 36.101562 55.660156 35.25 C 55.660156 34.402344 56.347656 33.710938 57.199219 33.710938 C 58.050781 33.710938 58.738281 34.402344 58.738281 35.25 Z M 58.738281 35.25 "/>
<path style="fill:none;stroke-width:1.386682;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 81.29914 -114.476562 L 107.442557 -114.476562 " transform="matrix(0,0.748874,-1,0,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 114.566406 56.363281 L 113.269531 59.382812 L 111.972656 62.40625 L 117.164062 62.40625 L 115.867188 59.382812 Z M 114.566406 56.363281 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 119.75 61.589844 L 120.59375 61.589844 L 120.59375 68.027344 L 119.75 68.027344 Z M 119.75 61.589844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 121.917969 68.027344 L 121.917969 63.355469 L 122.636719 63.355469 L 122.636719 64.027344 C 122.96875 63.519531 123.464844 63.261719 124.121094 63.261719 C 124.402344 63.261719 124.65625 63.316406 124.886719 63.417969 C 125.125 63.511719 125.300781 63.644531 125.417969 63.808594 C 125.53125 63.964844 125.613281 64.160156 125.667969 64.386719 C 125.699219 64.535156 125.714844 64.789062 125.714844 65.152344 L 125.714844 68.027344 L 124.917969 68.027344 L 124.917969 65.183594 C 124.917969 64.863281 124.886719 64.621094 124.824219 64.464844 C 124.761719 64.308594 124.652344 64.183594 124.496094 64.089844 C 124.339844 63.988281 124.15625 63.933594 123.949219 63.933594 C 123.613281 63.933594 123.324219 64.042969 123.074219 64.261719 C 122.832031 64.472656 122.714844 64.878906 122.714844 65.480469 L 122.714844 68.027344 Z M 121.917969 68.027344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 126.453125 66.636719 L 127.234375 66.511719 C 127.273438 66.824219 127.394531 67.066406 127.59375 67.230469 C 127.800781 67.398438 128.082031 67.480469 128.4375 67.480469 C 128.800781 67.480469 129.070312 67.410156 129.25 67.261719 C 129.425781 67.117188 129.515625 66.945312 129.515625 66.746094 C 129.515625 66.558594 129.4375 66.417969 129.28125 66.324219 C 129.164062 66.253906 128.894531 66.160156 128.46875 66.042969 C 127.882812 65.898438 127.476562 65.773438 127.25 65.667969 C 127.03125 65.566406 126.863281 65.417969 126.75 65.230469 C 126.632812 65.042969 126.578125 64.835938 126.578125 64.605469 C 126.578125 64.398438 126.625 64.207031 126.71875 64.027344 C 126.8125 63.851562 126.941406 63.699219 127.109375 63.574219 C 127.234375 63.492188 127.398438 63.417969 127.609375 63.355469 C 127.828125 63.292969 128.054688 63.261719 128.296875 63.261719 C 128.660156 63.261719 128.976562 63.316406 129.25 63.417969 C 129.53125 63.523438 129.738281 63.664062 129.875 63.839844 C 130.007812 64.019531 130.101562 64.257812 130.15625 64.558594 L 129.375 64.667969 C 129.34375 64.429688 129.238281 64.242188 129.0625 64.105469 C 128.894531 63.972656 128.660156 63.902344 128.359375 63.902344 C 127.992188 63.902344 127.734375 63.964844 127.578125 64.089844 C 127.421875 64.207031 127.34375 64.347656 127.34375 64.511719 C 127.34375 64.617188 127.375 64.707031 127.4375 64.777344 C 127.5 64.871094 127.601562 64.945312 127.75 64.996094 C 127.820312 65.027344 128.050781 65.097656 128.4375 65.199219 C 129 65.347656 129.390625 65.464844 129.609375 65.558594 C 129.835938 65.652344 130.015625 65.792969 130.140625 65.980469 C 130.265625 66.160156 130.328125 66.382812 130.328125 66.652344 C 130.328125 66.925781 130.25 67.175781 130.09375 67.402344 C 129.9375 67.632812 129.710938 67.816406 129.421875 67.949219 C 129.140625 68.074219 128.8125 68.136719 128.4375 68.136719 C 127.832031 68.136719 127.367188 68.011719 127.046875 67.761719 C 126.734375 67.503906 126.535156 67.128906 126.453125 66.636719 Z M 126.453125 66.636719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 132.851562 67.324219 L 132.960938 68.011719 C 132.730469 68.0625 132.53125 68.089844 132.367188 68.089844 C 132.074219 68.089844 131.851562 68.042969 131.695312 67.949219 C 131.539062 67.855469 131.421875 67.738281 131.351562 67.589844 C 131.289062 67.445312 131.257812 67.136719 131.257812 66.667969 L 131.257812 63.980469 L 130.679688 63.980469 L 130.679688 63.355469 L 131.257812 63.355469 L 131.257812 62.199219 L 132.054688 61.730469 L 132.054688 63.355469 L 132.851562 63.355469 L 132.851562 63.980469 L 132.054688 63.980469 L 132.054688 66.699219 C 132.054688 66.929688 132.0625 67.074219 132.085938 67.136719 C 132.117188 67.199219 132.164062 67.253906 132.226562 67.292969 C 132.289062 67.335938 132.375 67.355469 132.492188 67.355469 C 132.585938 67.355469 132.703125 67.347656 132.851562 67.324219 Z M 132.851562 67.324219 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 133.519531 68.027344 L 133.519531 63.355469 L 134.238281 63.355469 L 134.238281 64.074219 C 134.414062 63.742188 134.582031 63.523438 134.738281 63.417969 C 134.894531 63.316406 135.066406 63.261719 135.253906 63.261719 C 135.511719 63.261719 135.785156 63.347656 136.066406 63.511719 L 135.785156 64.246094 C 135.597656 64.132812 135.402344 64.074219 135.207031 64.074219 C 135.039062 64.074219 134.882812 64.128906 134.738281 64.230469 C 134.601562 64.335938 134.503906 64.480469 134.441406 64.667969 C 134.355469 64.949219 134.316406 65.257812 134.316406 65.589844 L 134.316406 68.027344 Z M 133.519531 68.027344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 139.503906 68.027344 L 139.503906 67.339844 C 139.136719 67.871094 138.644531 68.136719 138.019531 68.136719 C 137.746094 68.136719 137.492188 68.082031 137.253906 67.980469 C 137.011719 67.867188 136.832031 67.730469 136.707031 67.574219 C 136.589844 67.417969 136.511719 67.226562 136.472656 66.996094 C 136.441406 66.839844 136.425781 66.589844 136.425781 66.246094 L 136.425781 63.355469 L 137.207031 63.355469 L 137.207031 65.949219 C 137.207031 66.367188 137.226562 66.644531 137.269531 66.777344 C 137.308594 66.988281 137.410156 67.152344 137.566406 67.277344 C 137.730469 67.394531 137.933594 67.449219 138.175781 67.449219 C 138.414062 67.449219 138.636719 67.394531 138.847656 67.277344 C 139.054688 67.152344 139.199219 66.988281 139.285156 66.777344 C 139.367188 66.570312 139.410156 66.261719 139.410156 65.855469 L 139.410156 63.355469 L 140.207031 63.355469 L 140.207031 68.027344 Z M 139.503906 68.027344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 144.335938 66.324219 L 145.117188 66.417969 C 145.03125 66.960938 144.8125 67.382812 144.460938 67.683594 C 144.105469 67.988281 143.671875 68.136719 143.164062 68.136719 C 142.527344 68.136719 142.015625 67.929688 141.632812 67.511719 C 141.246094 67.097656 141.054688 66.496094 141.054688 65.714844 C 141.054688 65.207031 141.136719 64.761719 141.304688 64.386719 C 141.46875 64.011719 141.71875 63.730469 142.054688 63.542969 C 142.398438 63.355469 142.773438 63.261719 143.179688 63.261719 C 143.679688 63.261719 144.089844 63.394531 144.414062 63.652344 C 144.734375 63.902344 144.945312 64.261719 145.039062 64.730469 L 144.273438 64.855469 C 144.199219 64.542969 144.070312 64.308594 143.882812 64.152344 C 143.695312 63.988281 143.46875 63.902344 143.210938 63.902344 C 142.804688 63.902344 142.476562 64.050781 142.226562 64.339844 C 141.984375 64.621094 141.867188 65.070312 141.867188 65.683594 C 141.867188 66.320312 141.984375 66.777344 142.226562 67.058594 C 142.464844 67.339844 142.777344 67.480469 143.164062 67.480469 C 143.476562 67.480469 143.734375 67.386719 143.945312 67.199219 C 144.152344 67.011719 144.28125 66.722656 144.335938 66.324219 Z M 144.335938 66.324219 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 147.378906 67.324219 L 147.488281 68.011719 C 147.257812 68.0625 147.058594 68.089844 146.894531 68.089844 C 146.601562 68.089844 146.378906 68.042969 146.222656 67.949219 C 146.066406 67.855469 145.949219 67.738281 145.878906 67.589844 C 145.816406 67.445312 145.785156 67.136719 145.785156 66.667969 L 145.785156 63.980469 L 145.207031 63.980469 L 145.207031 63.355469 L 145.785156 63.355469 L 145.785156 62.199219 L 146.582031 61.730469 L 146.582031 63.355469 L 147.378906 63.355469 L 147.378906 63.980469 L 146.582031 63.980469 L 146.582031 66.699219 C 146.582031 66.929688 146.589844 67.074219 146.613281 67.136719 C 146.644531 67.199219 146.691406 67.253906 146.753906 67.292969 C 146.816406 67.335938 146.902344 67.355469 147.019531 67.355469 C 147.113281 67.355469 147.230469 67.347656 147.378906 67.324219 Z M 147.378906 67.324219 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 148.058594 62.496094 L 148.058594 61.589844 L 148.855469 61.589844 L 148.855469 62.496094 Z M 148.058594 68.027344 L 148.058594 63.355469 L 148.855469 63.355469 L 148.855469 68.027344 Z M 148.058594 68.027344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 149.703125 65.699219 C 149.703125 64.835938 149.941406 64.195312 150.421875 63.777344 C 150.828125 63.433594 151.316406 63.261719 151.890625 63.261719 C 152.535156 63.261719 153.0625 63.472656 153.46875 63.886719 C 153.875 64.304688 154.078125 64.882812 154.078125 65.621094 C 154.078125 66.226562 153.984375 66.699219 153.796875 67.042969 C 153.617188 67.386719 153.359375 67.660156 153.015625 67.855469 C 152.671875 68.042969 152.296875 68.136719 151.890625 68.136719 C 151.234375 68.136719 150.703125 67.929688 150.296875 67.511719 C 149.898438 67.085938 149.703125 66.480469 149.703125 65.699219 Z M 150.515625 65.699219 C 150.515625 66.292969 150.644531 66.742188 150.90625 67.042969 C 151.164062 67.335938 151.492188 67.480469 151.890625 67.480469 C 152.285156 67.480469 152.613281 67.335938 152.875 67.042969 C 153.132812 66.742188 153.265625 66.285156 153.265625 65.667969 C 153.265625 65.097656 153.132812 64.660156 152.875 64.355469 C 152.613281 64.054688 152.285156 63.902344 151.890625 63.902344 C 151.492188 63.902344 151.164062 64.054688 150.90625 64.355469 C 150.644531 64.648438 150.515625 65.097656 150.515625 65.699219 Z M 150.515625 65.699219 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 154.847656 68.027344 L 154.847656 63.355469 L 155.566406 63.355469 L 155.566406 64.027344 C 155.898438 63.519531 156.394531 63.261719 157.050781 63.261719 C 157.332031 63.261719 157.585938 63.316406 157.816406 63.417969 C 158.054688 63.511719 158.230469 63.644531 158.347656 63.808594 C 158.460938 63.964844 158.542969 64.160156 158.597656 64.386719 C 158.628906 64.535156 158.644531 64.789062 158.644531 65.152344 L 158.644531 68.027344 L 157.847656 68.027344 L 157.847656 65.183594 C 157.847656 64.863281 157.816406 64.621094 157.753906 64.464844 C 157.691406 64.308594 157.582031 64.183594 157.425781 64.089844 C 157.269531 63.988281 157.085938 63.933594 156.878906 63.933594 C 156.542969 63.933594 156.253906 64.042969 156.003906 64.261719 C 155.761719 64.472656 155.644531 64.878906 155.644531 65.480469 L 155.644531 68.027344 Z M 154.847656 68.027344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 159.382812 66.636719 L 160.164062 66.511719 C 160.203125 66.824219 160.324219 67.066406 160.523438 67.230469 C 160.730469 67.398438 161.011719 67.480469 161.367188 67.480469 C 161.730469 67.480469 162 67.410156 162.179688 67.261719 C 162.355469 67.117188 162.445312 66.945312 162.445312 66.746094 C 162.445312 66.558594 162.367188 66.417969 162.210938 66.324219 C 162.09375 66.253906 161.824219 66.160156 161.398438 66.042969 C 160.8125 65.898438 160.40625 65.773438 160.179688 65.667969 C 159.960938 65.566406 159.792969 65.417969 159.679688 65.230469 C 159.5625 65.042969 159.507812 64.835938 159.507812 64.605469 C 159.507812 64.398438 159.554688 64.207031 159.648438 64.027344 C 159.742188 63.851562 159.871094 63.699219 160.039062 63.574219 C 160.164062 63.492188 160.328125 63.417969 160.539062 63.355469 C 160.757812 63.292969 160.984375 63.261719 161.226562 63.261719 C 161.589844 63.261719 161.90625 63.316406 162.179688 63.417969 C 162.460938 63.523438 162.667969 63.664062 162.804688 63.839844 C 162.9375 64.019531 163.03125 64.257812 163.085938 64.558594 L 162.304688 64.667969 C 162.273438 64.429688 162.167969 64.242188 161.992188 64.105469 C 161.824219 63.972656 161.589844 63.902344 161.289062 63.902344 C 160.921875 63.902344 160.664062 63.964844 160.507812 64.089844 C 160.351562 64.207031 160.273438 64.347656 160.273438 64.511719 C 160.273438 64.617188 160.304688 64.707031 160.367188 64.777344 C 160.429688 64.871094 160.53125 64.945312 160.679688 64.996094 C 160.75 65.027344 160.980469 65.097656 161.367188 65.199219 C 161.929688 65.347656 162.320312 65.464844 162.539062 65.558594 C 162.765625 65.652344 162.945312 65.792969 163.070312 65.980469 C 163.195312 66.160156 163.257812 66.382812 163.257812 66.652344 C 163.257812 66.925781 163.179688 67.175781 163.023438 67.402344 C 162.867188 67.632812 162.640625 67.816406 162.351562 67.949219 C 162.070312 68.074219 161.742188 68.136719 161.367188 68.136719 C 160.761719 68.136719 160.296875 68.011719 159.976562 67.761719 C 159.664062 67.503906 159.464844 67.128906 159.382812 66.636719 Z M 159.382812 66.636719 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 18.09375 84.542969 L 18.09375 90.621094 L 27.253906 90.621094 L 30.21875 87.660156 L 27.175781 84.617188 Z M 18.09375 84.542969 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 50.304688 87.980469 L 42.234375 90.574219 L 42.234375 85.386719 Z M 50.304688 87.980469 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 42.671875 87.78125 L 30.074219 87.78125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 2.671875 89.53125 L 0.1875 83.09375 L 1.109375 83.09375 L 2.78125 87.765625 C 2.914062 88.140625 3.023438 88.496094 3.109375 88.828125 C 3.210938 88.476562 3.332031 88.121094 3.46875 87.765625 L 5.203125 83.09375 L 6.078125 83.09375 L 3.546875 89.53125 Z M 2.671875 89.53125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 6.519531 86.976562 L 7.082031 86.976562 L 7.082031 91.273438 L 6.519531 91.273438 Z M 6.519531 86.976562 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 7.980469 91.273438 L 7.980469 86.976562 L 8.574219 86.976562 L 10.824219 90.351562 L 10.824219 86.976562 L 11.371094 86.976562 L 11.371094 91.273438 L 10.792969 91.273438 L 8.527344 87.898438 L 8.527344 91.273438 Z M 7.980469 91.273438 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 13.851562 91.273438 L 13.320312 91.273438 L 13.320312 87.914062 C 13.195312 88.039062 13.027344 88.164062 12.820312 88.289062 C 12.621094 88.40625 12.4375 88.492188 12.273438 88.554688 L 12.273438 88.039062 C 12.5625 87.90625 12.820312 87.738281 13.039062 87.539062 C 13.265625 87.34375 13.421875 87.148438 13.507812 86.960938 L 13.851562 86.960938 Z M 13.851562 91.273438 "/>
<g clip-path="url(#clip3)" clip-rule="nonzero">
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 51.585938 72.203125 L 123.789062 72.203125 L 123.789062 104.125 L 51.585938 104.125 Z M 51.585938 72.203125 "/>
</g>
<g clip-path="url(#clip4)" clip-rule="nonzero">
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 51.585938 72.203125 L 123.789062 72.203125 L 123.789062 104.125 L 51.585938 104.125 Z M 51.585938 72.203125 "/>
</g>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 61.503906 100.777344 L 61.503906 94.339844 L 62.378906 94.339844 L 65.753906 99.386719 L 65.753906 94.339844 L 66.582031 94.339844 L 66.582031 100.777344 L 65.707031 100.777344 L 62.316406 95.714844 L 62.316406 100.777344 Z M 61.503906 100.777344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 67.796875 100.777344 L 67.796875 94.339844 L 70.234375 94.339844 C 70.660156 94.339844 70.988281 94.363281 71.21875 94.402344 C 71.53125 94.457031 71.789062 94.554688 72 94.699219 C 72.21875 94.847656 72.390625 95.054688 72.515625 95.324219 C 72.648438 95.585938 72.71875 95.878906 72.71875 96.199219 C 72.71875 96.753906 72.539062 97.214844 72.1875 97.589844 C 71.84375 97.964844 71.21875 98.152344 70.3125 98.152344 L 68.65625 98.152344 L 68.65625 100.777344 Z M 68.65625 97.402344 L 70.328125 97.402344 C 70.867188 97.402344 71.253906 97.300781 71.484375 97.089844 C 71.722656 96.882812 71.84375 96.597656 71.84375 96.230469 C 71.84375 95.960938 71.773438 95.730469 71.640625 95.542969 C 71.503906 95.347656 71.320312 95.214844 71.09375 95.152344 C 70.957031 95.113281 70.691406 95.089844 70.296875 95.089844 L 68.65625 95.089844 Z M 68.65625 97.402344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 73.773438 94.339844 L 74.617188 94.339844 L 74.617188 100.777344 L 73.773438 100.777344 Z M 73.773438 94.339844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 78.601562 94.339844 L 79.445312 94.339844 L 79.445312 100.777344 L 78.601562 100.777344 Z M 78.601562 94.339844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 80.765625 100.777344 L 80.765625 96.105469 L 81.484375 96.105469 L 81.484375 96.777344 C 81.816406 96.269531 82.3125 96.011719 82.96875 96.011719 C 83.25 96.011719 83.503906 96.066406 83.734375 96.167969 C 83.972656 96.261719 84.148438 96.394531 84.265625 96.558594 C 84.378906 96.714844 84.460938 96.910156 84.515625 97.136719 C 84.546875 97.285156 84.5625 97.539062 84.5625 97.902344 L 84.5625 100.777344 L 83.765625 100.777344 L 83.765625 97.933594 C 83.765625 97.613281 83.734375 97.371094 83.671875 97.214844 C 83.609375 97.058594 83.5 96.933594 83.34375 96.839844 C 83.1875 96.738281 83.003906 96.683594 82.796875 96.683594 C 82.460938 96.683594 82.171875 96.792969 81.921875 97.011719 C 81.679688 97.222656 81.5625 97.628906 81.5625 98.230469 L 81.5625 100.777344 Z M 80.765625 100.777344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 87.347656 100.074219 L 87.457031 100.761719 C 87.226562 100.8125 87.027344 100.839844 86.863281 100.839844 C 86.570312 100.839844 86.347656 100.792969 86.191406 100.699219 C 86.035156 100.605469 85.917969 100.488281 85.847656 100.339844 C 85.785156 100.195312 85.753906 99.886719 85.753906 99.417969 L 85.753906 96.730469 L 85.175781 96.730469 L 85.175781 96.105469 L 85.753906 96.105469 L 85.753906 94.949219 L 86.550781 94.480469 L 86.550781 96.105469 L 87.347656 96.105469 L 87.347656 96.730469 L 86.550781 96.730469 L 86.550781 99.449219 C 86.550781 99.679688 86.558594 99.824219 86.582031 99.886719 C 86.613281 99.949219 86.660156 100.003906 86.722656 100.042969 C 86.785156 100.085938 86.871094 100.105469 86.988281 100.105469 C 87.082031 100.105469 87.199219 100.097656 87.347656 100.074219 Z M 87.347656 100.074219 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 91.21875 99.277344 L 92.046875 99.371094 C 91.910156 99.851562 91.664062 100.226562 91.3125 100.496094 C 90.96875 100.757812 90.523438 100.886719 89.984375 100.886719 C 89.304688 100.886719 88.765625 100.679688 88.359375 100.261719 C 87.960938 99.835938 87.765625 99.242188 87.765625 98.480469 C 87.765625 97.699219 87.96875 97.097656 88.375 96.667969 C 88.78125 96.230469 89.304688 96.011719 89.953125 96.011719 C 90.578125 96.011719 91.082031 96.226562 91.46875 96.652344 C 91.863281 97.070312 92.0625 97.664062 92.0625 98.433594 C 92.0625 98.488281 92.0625 98.558594 92.0625 98.652344 L 88.578125 98.652344 C 88.609375 99.164062 88.753906 99.554688 89.015625 99.824219 C 89.273438 100.097656 89.601562 100.230469 90 100.230469 C 90.289062 100.230469 90.535156 100.160156 90.734375 100.011719 C 90.941406 99.855469 91.101562 99.613281 91.21875 99.277344 Z M 88.625 97.996094 L 91.234375 97.996094 C 91.203125 97.601562 91.101562 97.304688 90.9375 97.105469 C 90.6875 96.804688 90.359375 96.652344 89.953125 96.652344 C 89.585938 96.652344 89.28125 96.777344 89.03125 97.027344 C 88.789062 97.269531 88.65625 97.589844 88.625 97.996094 Z M 88.625 97.996094 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 92.863281 100.777344 L 92.863281 96.105469 L 93.582031 96.105469 L 93.582031 96.824219 C 93.757812 96.492188 93.925781 96.273438 94.082031 96.167969 C 94.238281 96.066406 94.410156 96.011719 94.597656 96.011719 C 94.855469 96.011719 95.128906 96.097656 95.410156 96.261719 L 95.128906 96.996094 C 94.941406 96.882812 94.746094 96.824219 94.550781 96.824219 C 94.382812 96.824219 94.226562 96.878906 94.082031 96.980469 C 93.945312 97.085938 93.847656 97.230469 93.785156 97.417969 C 93.699219 97.699219 93.660156 98.007812 93.660156 98.339844 L 93.660156 100.777344 Z M 92.863281 100.777344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 95.972656 100.777344 L 95.972656 96.730469 L 95.269531 96.730469 L 95.269531 96.105469 L 95.972656 96.105469 L 95.972656 95.621094 C 95.972656 95.300781 95.996094 95.066406 96.050781 94.917969 C 96.132812 94.710938 96.269531 94.542969 96.457031 94.417969 C 96.652344 94.292969 96.925781 94.230469 97.269531 94.230469 C 97.488281 94.230469 97.730469 94.257812 98.003906 94.308594 L 97.878906 94.996094 C 97.722656 94.964844 97.570312 94.949219 97.425781 94.949219 C 97.183594 94.949219 97.011719 95.003906 96.910156 95.105469 C 96.804688 95.210938 96.753906 95.402344 96.753906 95.683594 L 96.753906 96.105469 L 97.675781 96.105469 L 97.675781 96.730469 L 96.753906 96.730469 L 96.753906 100.777344 Z M 95.972656 100.777344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 101.25 100.199219 C 100.957031 100.449219 100.675781 100.628906 100.40625 100.730469 C 100.132812 100.832031 99.84375 100.886719 99.53125 100.886719 C 99.019531 100.886719 98.625 100.761719 98.34375 100.511719 C 98.070312 100.261719 97.9375 99.941406 97.9375 99.542969 C 97.9375 99.316406 97.988281 99.105469 98.09375 98.917969 C 98.195312 98.730469 98.332031 98.582031 98.5 98.464844 C 98.664062 98.351562 98.851562 98.261719 99.0625 98.199219 C 99.21875 98.167969 99.453125 98.132812 99.765625 98.089844 C 100.410156 98.019531 100.882812 97.925781 101.1875 97.808594 C 101.1875 97.707031 101.1875 97.636719 101.1875 97.605469 C 101.1875 97.285156 101.113281 97.058594 100.96875 96.933594 C 100.757812 96.746094 100.457031 96.652344 100.0625 96.652344 C 99.6875 96.652344 99.410156 96.722656 99.234375 96.855469 C 99.054688 96.980469 98.925781 97.210938 98.84375 97.542969 L 98.078125 97.449219 C 98.140625 97.117188 98.25 96.851562 98.40625 96.652344 C 98.570312 96.445312 98.804688 96.289062 99.109375 96.183594 C 99.421875 96.070312 99.773438 96.011719 100.171875 96.011719 C 100.578125 96.011719 100.898438 96.058594 101.140625 96.152344 C 101.390625 96.246094 101.570312 96.367188 101.6875 96.511719 C 101.8125 96.648438 101.894531 96.824219 101.9375 97.042969 C 101.96875 97.179688 101.984375 97.417969 101.984375 97.761719 L 101.984375 98.824219 C 101.984375 99.554688 102 100.019531 102.03125 100.214844 C 102.0625 100.414062 102.128906 100.601562 102.234375 100.777344 L 101.40625 100.777344 C 101.320312 100.613281 101.269531 100.417969 101.25 100.199219 Z M 101.1875 98.433594 C 100.894531 98.550781 100.460938 98.648438 99.890625 98.730469 C 99.566406 98.785156 99.335938 98.839844 99.203125 98.902344 C 99.066406 98.957031 98.960938 99.039062 98.890625 99.152344 C 98.816406 99.269531 98.78125 99.394531 98.78125 99.527344 C 98.78125 99.738281 98.859375 99.914062 99.015625 100.058594 C 99.171875 100.195312 99.40625 100.261719 99.71875 100.261719 C 100.019531 100.261719 100.289062 100.195312 100.53125 100.058594 C 100.769531 99.925781 100.945312 99.742188 101.0625 99.511719 C 101.144531 99.335938 101.1875 99.074219 101.1875 98.730469 Z M 101.1875 98.433594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 106.097656 99.074219 L 106.878906 99.167969 C 106.792969 99.710938 106.574219 100.132812 106.222656 100.433594 C 105.867188 100.738281 105.433594 100.886719 104.925781 100.886719 C 104.289062 100.886719 103.777344 100.679688 103.394531 100.261719 C 103.007812 99.847656 102.816406 99.246094 102.816406 98.464844 C 102.816406 97.957031 102.898438 97.511719 103.066406 97.136719 C 103.230469 96.761719 103.480469 96.480469 103.816406 96.292969 C 104.160156 96.105469 104.535156 96.011719 104.941406 96.011719 C 105.441406 96.011719 105.851562 96.144531 106.175781 96.402344 C 106.496094 96.652344 106.707031 97.011719 106.800781 97.480469 L 106.035156 97.605469 C 105.960938 97.292969 105.832031 97.058594 105.644531 96.902344 C 105.457031 96.738281 105.230469 96.652344 104.972656 96.652344 C 104.566406 96.652344 104.238281 96.800781 103.988281 97.089844 C 103.746094 97.371094 103.628906 97.820312 103.628906 98.433594 C 103.628906 99.070312 103.746094 99.527344 103.988281 99.808594 C 104.226562 100.089844 104.539062 100.230469 104.925781 100.230469 C 105.238281 100.230469 105.496094 100.136719 105.707031 99.949219 C 105.914062 99.761719 106.042969 99.472656 106.097656 99.074219 Z M 106.097656 99.074219 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 110.589844 99.277344 L 111.417969 99.371094 C 111.28125 99.851562 111.035156 100.226562 110.683594 100.496094 C 110.339844 100.757812 109.894531 100.886719 109.355469 100.886719 C 108.675781 100.886719 108.136719 100.679688 107.730469 100.261719 C 107.332031 99.835938 107.136719 99.242188 107.136719 98.480469 C 107.136719 97.699219 107.339844 97.097656 107.746094 96.667969 C 108.152344 96.230469 108.675781 96.011719 109.324219 96.011719 C 109.949219 96.011719 110.453125 96.226562 110.839844 96.652344 C 111.234375 97.070312 111.433594 97.664062 111.433594 98.433594 C 111.433594 98.488281 111.433594 98.558594 111.433594 98.652344 L 107.949219 98.652344 C 107.980469 99.164062 108.125 99.554688 108.386719 99.824219 C 108.644531 100.097656 108.972656 100.230469 109.371094 100.230469 C 109.660156 100.230469 109.90625 100.160156 110.105469 100.011719 C 110.3125 99.855469 110.472656 99.613281 110.589844 99.277344 Z M 107.996094 97.996094 L 110.605469 97.996094 C 110.574219 97.601562 110.472656 97.304688 110.308594 97.105469 C 110.058594 96.804688 109.730469 96.652344 109.324219 96.652344 C 108.957031 96.652344 108.652344 96.777344 108.402344 97.027344 C 108.160156 97.269531 108.027344 97.589844 107.996094 97.996094 Z M 107.996094 97.996094 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 130.433594 95.925781 L 156.574219 95.925781 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 124.394531 95.832031 L 128.429688 97.128906 L 132.46875 98.429688 L 132.46875 93.238281 L 128.429688 94.535156 Z M 124.394531 95.832031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 141.445312 89.003906 L 188.109375 89.003906 L 188.109375 103.984375 L 141.445312 103.984375 Z M 141.445312 89.003906 "/>
<g clip-path="url(#clip5)" clip-rule="nonzero">
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 141.445312 89.003906 L 188.109375 89.003906 L 188.109375 103.984375 L 141.445312 103.984375 Z M 141.445312 89.003906 "/>
</g>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 148.824219 98.8125 L 148.824219 92.375 L 153.167969 92.375 L 153.167969 93.125 L 149.683594 93.125 L 149.683594 95.125 L 152.699219 95.125 L 152.699219 95.890625 L 149.683594 95.890625 L 149.683594 98.8125 Z M 148.824219 98.8125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 157.070312 98.8125 L 157.070312 98.125 C 156.703125 98.65625 156.210938 98.921875 155.585938 98.921875 C 155.3125 98.921875 155.058594 98.867188 154.820312 98.765625 C 154.578125 98.652344 154.398438 98.515625 154.273438 98.359375 C 154.15625 98.203125 154.078125 98.011719 154.039062 97.78125 C 154.007812 97.625 153.992188 97.375 153.992188 97.03125 L 153.992188 94.140625 L 154.773438 94.140625 L 154.773438 96.734375 C 154.773438 97.152344 154.792969 97.429688 154.835938 97.5625 C 154.875 97.773438 154.976562 97.9375 155.132812 98.0625 C 155.296875 98.179688 155.5 98.234375 155.742188 98.234375 C 155.980469 98.234375 156.203125 98.179688 156.414062 98.0625 C 156.621094 97.9375 156.765625 97.773438 156.851562 97.5625 C 156.933594 97.355469 156.976562 97.046875 156.976562 96.640625 L 156.976562 94.140625 L 157.773438 94.140625 L 157.773438 98.8125 Z M 157.070312 98.8125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 158.855469 98.8125 L 158.855469 94.140625 L 159.574219 94.140625 L 159.574219 94.8125 C 159.90625 94.304688 160.402344 94.046875 161.058594 94.046875 C 161.339844 94.046875 161.59375 94.101562 161.824219 94.203125 C 162.0625 94.296875 162.238281 94.429688 162.355469 94.59375 C 162.46875 94.75 162.550781 94.945312 162.605469 95.171875 C 162.636719 95.320312 162.652344 95.574219 162.652344 95.9375 L 162.652344 98.8125 L 161.855469 98.8125 L 161.855469 95.96875 C 161.855469 95.648438 161.824219 95.40625 161.761719 95.25 C 161.699219 95.09375 161.589844 94.96875 161.433594 94.875 C 161.277344 94.773438 161.09375 94.71875 160.886719 94.71875 C 160.550781 94.71875 160.261719 94.828125 160.011719 95.046875 C 159.769531 95.257812 159.652344 95.664062 159.652344 96.265625 L 159.652344 98.8125 Z M 158.855469 98.8125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 166.75 97.109375 L 167.53125 97.203125 C 167.445312 97.746094 167.226562 98.167969 166.875 98.46875 C 166.519531 98.773438 166.085938 98.921875 165.578125 98.921875 C 164.941406 98.921875 164.429688 98.714844 164.046875 98.296875 C 163.660156 97.882812 163.46875 97.28125 163.46875 96.5 C 163.46875 95.992188 163.550781 95.546875 163.71875 95.171875 C 163.882812 94.796875 164.132812 94.515625 164.46875 94.328125 C 164.8125 94.140625 165.1875 94.046875 165.59375 94.046875 C 166.09375 94.046875 166.503906 94.179688 166.828125 94.4375 C 167.148438 94.6875 167.359375 95.046875 167.453125 95.515625 L 166.6875 95.640625 C 166.613281 95.328125 166.484375 95.09375 166.296875 94.9375 C 166.109375 94.773438 165.882812 94.6875 165.625 94.6875 C 165.21875 94.6875 164.890625 94.835938 164.640625 95.125 C 164.398438 95.40625 164.28125 95.855469 164.28125 96.46875 C 164.28125 97.105469 164.398438 97.5625 164.640625 97.84375 C 164.878906 98.125 165.191406 98.265625 165.578125 98.265625 C 165.890625 98.265625 166.148438 98.171875 166.359375 97.984375 C 166.566406 97.796875 166.695312 97.507812 166.75 97.109375 Z M 166.75 97.109375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 169.789062 98.109375 L 169.898438 98.796875 C 169.667969 98.847656 169.46875 98.875 169.304688 98.875 C 169.011719 98.875 168.789062 98.828125 168.632812 98.734375 C 168.476562 98.640625 168.359375 98.523438 168.289062 98.375 C 168.226562 98.230469 168.195312 97.921875 168.195312 97.453125 L 168.195312 94.765625 L 167.617188 94.765625 L 167.617188 94.140625 L 168.195312 94.140625 L 168.195312 92.984375 L 168.992188 92.515625 L 168.992188 94.140625 L 169.789062 94.140625 L 169.789062 94.765625 L 168.992188 94.765625 L 168.992188 97.484375 C 168.992188 97.714844 169 97.859375 169.023438 97.921875 C 169.054688 97.984375 169.101562 98.039062 169.164062 98.078125 C 169.226562 98.121094 169.3125 98.140625 169.429688 98.140625 C 169.523438 98.140625 169.640625 98.132812 169.789062 98.109375 Z M 169.789062 98.109375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 170.472656 93.28125 L 170.472656 92.375 L 171.269531 92.375 L 171.269531 93.28125 Z M 170.472656 98.8125 L 170.472656 94.140625 L 171.269531 94.140625 L 171.269531 98.8125 Z M 170.472656 98.8125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 172.113281 96.484375 C 172.113281 95.621094 172.351562 94.980469 172.832031 94.5625 C 173.238281 94.21875 173.726562 94.046875 174.300781 94.046875 C 174.945312 94.046875 175.472656 94.257812 175.878906 94.671875 C 176.285156 95.089844 176.488281 95.667969 176.488281 96.40625 C 176.488281 97.011719 176.394531 97.484375 176.207031 97.828125 C 176.027344 98.171875 175.769531 98.445312 175.425781 98.640625 C 175.082031 98.828125 174.707031 98.921875 174.300781 98.921875 C 173.644531 98.921875 173.113281 98.714844 172.707031 98.296875 C 172.308594 97.871094 172.113281 97.265625 172.113281 96.484375 Z M 172.925781 96.484375 C 172.925781 97.078125 173.054688 97.527344 173.316406 97.828125 C 173.574219 98.121094 173.902344 98.265625 174.300781 98.265625 C 174.695312 98.265625 175.023438 98.121094 175.285156 97.828125 C 175.542969 97.527344 175.675781 97.070312 175.675781 96.453125 C 175.675781 95.882812 175.542969 95.445312 175.285156 95.140625 C 175.023438 94.839844 174.695312 94.6875 174.300781 94.6875 C 173.902344 94.6875 173.574219 94.839844 173.316406 95.140625 C 173.054688 95.433594 172.925781 95.882812 172.925781 96.484375 Z M 172.925781 96.484375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 177.257812 98.8125 L 177.257812 94.140625 L 177.976562 94.140625 L 177.976562 94.8125 C 178.308594 94.304688 178.804688 94.046875 179.460938 94.046875 C 179.742188 94.046875 179.996094 94.101562 180.226562 94.203125 C 180.464844 94.296875 180.640625 94.429688 180.757812 94.59375 C 180.871094 94.75 180.953125 94.945312 181.007812 95.171875 C 181.039062 95.320312 181.054688 95.574219 181.054688 95.9375 L 181.054688 98.8125 L 180.257812 98.8125 L 180.257812 95.96875 C 180.257812 95.648438 180.226562 95.40625 180.164062 95.25 C 180.101562 95.09375 179.992188 94.96875 179.835938 94.875 C 179.679688 94.773438 179.496094 94.71875 179.289062 94.71875 C 178.953125 94.71875 178.664062 94.828125 178.414062 95.046875 C 178.171875 95.257812 178.054688 95.664062 178.054688 96.265625 L 178.054688 98.8125 Z M 177.257812 98.8125 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 57.574219 83.953125 L 116.628906 83.953125 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 75.0625 83.929688 L 79.722656 77.734375 L 88.933594 77.734375 L 88.933594 90.117188 L 79.722656 90.117188 Z M 75.0625 83.929688 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.207682;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 73.49844 84.019531 L 67.662718 87.390625 L 61.826997 90.757812 L 61.826997 77.28125 L 67.662718 80.648438 Z M 73.49844 84.019531 " transform="matrix(0.987319,0,0,1,0,0)"/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 93.390625 77.644531 L 113.589844 77.644531 L 113.589844 90.066406 L 93.390625 90.066406 Z M 93.390625 77.644531 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 95.191406 86.902344 L 95.191406 80.464844 L 97.410156 80.464844 C 97.917969 80.464844 98.304688 80.496094 98.566406 80.558594 C 98.929688 80.644531 99.242188 80.792969 99.503906 81.011719 C 99.847656 81.304688 100.101562 81.675781 100.269531 82.121094 C 100.433594 82.558594 100.519531 83.070312 100.519531 83.652344 C 100.519531 84.144531 100.460938 84.574219 100.347656 84.949219 C 100.230469 85.324219 100.085938 85.636719 99.910156 85.886719 C 99.730469 86.136719 99.535156 86.335938 99.316406 86.480469 C 99.105469 86.617188 98.851562 86.722656 98.550781 86.792969 C 98.257812 86.867188 97.914062 86.902344 97.519531 86.902344 Z M 96.050781 86.136719 L 97.425781 86.136719 C 97.851562 86.136719 98.183594 86.101562 98.425781 86.027344 C 98.664062 85.945312 98.855469 85.832031 99.003906 85.683594 C 99.199219 85.488281 99.355469 85.214844 99.472656 84.871094 C 99.585938 84.527344 99.644531 84.117188 99.644531 83.636719 C 99.644531 82.960938 99.535156 82.445312 99.316406 82.089844 C 99.097656 81.726562 98.824219 81.480469 98.503906 81.355469 C 98.273438 81.261719 97.910156 81.214844 97.410156 81.214844 L 96.050781 81.214844 Z M 96.050781 86.136719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 101.203125 84.839844 L 102 84.761719 C 102.039062 85.085938 102.128906 85.351562 102.265625 85.558594 C 102.410156 85.769531 102.628906 85.933594 102.921875 86.058594 C 103.210938 86.183594 103.539062 86.246094 103.90625 86.246094 C 104.226562 86.246094 104.515625 86.199219 104.765625 86.105469 C 105.015625 86.011719 105.203125 85.882812 105.328125 85.714844 C 105.453125 85.539062 105.515625 85.351562 105.515625 85.152344 C 105.515625 84.957031 105.453125 84.785156 105.328125 84.636719 C 105.210938 84.480469 105.019531 84.351562 104.75 84.246094 C 104.582031 84.175781 104.203125 84.070312 103.609375 83.933594 C 103.015625 83.789062 102.597656 83.652344 102.359375 83.527344 C 102.054688 83.371094 101.828125 83.175781 101.671875 82.933594 C 101.523438 82.695312 101.453125 82.425781 101.453125 82.121094 C 101.453125 81.800781 101.539062 81.496094 101.71875 81.214844 C 101.90625 80.933594 102.175781 80.722656 102.53125 80.574219 C 102.882812 80.429688 103.28125 80.355469 103.71875 80.355469 C 104.195312 80.355469 104.617188 80.433594 104.984375 80.589844 C 105.347656 80.738281 105.625 80.960938 105.8125 81.261719 C 106.007812 81.566406 106.117188 81.902344 106.140625 82.277344 L 105.3125 82.339844 C 105.269531 81.933594 105.125 81.628906 104.875 81.417969 C 104.625 81.210938 104.25 81.105469 103.75 81.105469 C 103.238281 81.105469 102.863281 81.199219 102.625 81.386719 C 102.382812 81.574219 102.265625 81.804688 102.265625 82.074219 C 102.265625 82.304688 102.347656 82.492188 102.515625 82.636719 C 102.679688 82.792969 103.109375 82.949219 103.796875 83.105469 C 104.492188 83.261719 104.972656 83.398438 105.234375 83.511719 C 105.609375 83.679688 105.882812 83.898438 106.0625 84.167969 C 106.238281 84.429688 106.328125 84.738281 106.328125 85.089844 C 106.328125 85.425781 106.226562 85.746094 106.03125 86.058594 C 105.832031 86.363281 105.550781 86.597656 105.1875 86.761719 C 104.820312 86.925781 104.410156 87.011719 103.953125 87.011719 C 103.367188 87.011719 102.878906 86.925781 102.484375 86.761719 C 102.085938 86.585938 101.773438 86.332031 101.546875 85.996094 C 101.328125 85.652344 101.210938 85.269531 101.203125 84.839844 Z M 101.203125 84.839844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 107.300781 86.902344 L 107.300781 80.464844 L 109.738281 80.464844 C 110.164062 80.464844 110.492188 80.488281 110.722656 80.527344 C 111.035156 80.582031 111.292969 80.679688 111.503906 80.824219 C 111.722656 80.972656 111.894531 81.179688 112.019531 81.449219 C 112.152344 81.710938 112.222656 82.003906 112.222656 82.324219 C 112.222656 82.878906 112.042969 83.339844 111.691406 83.714844 C 111.347656 84.089844 110.722656 84.277344 109.816406 84.277344 L 108.160156 84.277344 L 108.160156 86.902344 Z M 108.160156 83.527344 L 109.832031 83.527344 C 110.371094 83.527344 110.757812 83.425781 110.988281 83.214844 C 111.226562 83.007812 111.347656 82.722656 111.347656 82.355469 C 111.347656 82.085938 111.277344 81.855469 111.144531 81.667969 C 111.007812 81.472656 110.824219 81.339844 110.597656 81.277344 C 110.460938 81.238281 110.195312 81.214844 109.800781 81.214844 L 108.160156 81.214844 Z M 108.160156 83.527344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 118.542969 83.828125 C 118.542969 84.679688 117.855469 85.367188 117.003906 85.367188 C 116.15625 85.367188 115.464844 84.679688 115.464844 83.828125 C 115.464844 82.976562 116.15625 82.289062 117.003906 82.289062 C 117.855469 82.289062 118.542969 82.976562 118.542969 83.828125 Z M 118.542969 83.828125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 58.632812 83.945312 C 58.632812 84.792969 57.941406 85.484375 57.089844 85.484375 C 56.242188 85.484375 55.550781 84.792969 55.550781 83.945312 C 55.550781 83.09375 56.242188 82.402344 57.089844 82.402344 C 57.941406 82.402344 58.632812 83.09375 58.632812 83.945312 Z M 58.632812 83.945312 "/>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 79 KiB

BIN
static/images/biocas2016/hwconfig.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 674 KiB

432
static/images/biocas2016/uC_PS.svg Normal file
View File

@ -0,0 +1,432 @@
<?xml version="1.0" encoding="UTF-8"?>
<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" width="333.651367pt" height="246.360718pt" viewBox="0 0 333.651367 246.360718" version="1.1">
<defs>
<g>
<symbol overflow="visible" id="glyph0-0">
<path style="stroke:none;" d="M 1.40625 0 L 1.40625 -7.03125 L 7.03125 -7.03125 L 7.03125 0 Z M 1.578125 -0.171875 L 6.859375 -0.171875 L 6.859375 -6.859375 L 1.578125 -6.859375 Z M 1.578125 -0.171875 "/>
</symbol>
<symbol overflow="visible" id="glyph0-1">
<path style="stroke:none;" d="M 0.875 0 L 0.875 -8.046875 L 3.90625 -8.046875 C 4.4375 -8.046875 4.84375 -8.019531 5.125 -7.96875 C 5.519531 -7.90625 5.851562 -7.78125 6.125 -7.59375 C 6.394531 -7.414062 6.609375 -7.160156 6.765625 -6.828125 C 6.929688 -6.492188 7.015625 -6.125 7.015625 -5.71875 C 7.015625 -5.039062 6.796875 -4.460938 6.359375 -3.984375 C 5.921875 -3.515625 5.132812 -3.28125 4 -3.28125 L 1.9375 -3.28125 L 1.9375 0 Z M 1.9375 -4.21875 L 4.015625 -4.21875 C 4.703125 -4.21875 5.191406 -4.347656 5.484375 -4.609375 C 5.773438 -4.867188 5.921875 -5.226562 5.921875 -5.6875 C 5.921875 -6.03125 5.832031 -6.320312 5.65625 -6.5625 C 5.488281 -6.800781 5.265625 -6.957031 4.984375 -7.03125 C 4.804688 -7.082031 4.476562 -7.109375 4 -7.109375 L 1.9375 -7.109375 Z M 1.9375 -4.21875 "/>
</symbol>
<symbol overflow="visible" id="glyph0-2">
<path style="stroke:none;" d="M 0.375 -2.921875 C 0.375 -3.992188 0.675781 -4.789062 1.28125 -5.3125 C 1.78125 -5.75 2.390625 -5.96875 3.109375 -5.96875 C 3.910156 -5.96875 4.566406 -5.703125 5.078125 -5.171875 C 5.585938 -4.648438 5.84375 -3.925781 5.84375 -3 C 5.84375 -2.25 5.726562 -1.65625 5.5 -1.21875 C 5.269531 -0.789062 4.941406 -0.457031 4.515625 -0.21875 C 4.085938 0.0078125 3.617188 0.125 3.109375 0.125 C 2.296875 0.125 1.632812 -0.132812 1.125 -0.65625 C 0.625 -1.175781 0.375 -1.929688 0.375 -2.921875 Z M 1.390625 -2.921875 C 1.390625 -2.171875 1.550781 -1.609375 1.875 -1.234375 C 2.207031 -0.867188 2.617188 -0.6875 3.109375 -0.6875 C 3.597656 -0.6875 4.003906 -0.867188 4.328125 -1.234375 C 4.660156 -1.609375 4.828125 -2.179688 4.828125 -2.953125 C 4.828125 -3.671875 4.660156 -4.210938 4.328125 -4.578125 C 4.003906 -4.953125 3.597656 -5.140625 3.109375 -5.140625 C 2.617188 -5.140625 2.207031 -4.953125 1.875 -4.578125 C 1.550781 -4.210938 1.390625 -3.660156 1.390625 -2.921875 Z M 1.390625 -2.921875 "/>
</symbol>
<symbol overflow="visible" id="glyph0-3">
<path style="stroke:none;" d="M 1.8125 0 L 0.03125 -5.828125 L 1.0625 -5.828125 L 1.984375 -2.46875 L 2.328125 -1.21875 C 2.335938 -1.28125 2.4375 -1.679688 2.625 -2.421875 L 3.5625 -5.828125 L 4.578125 -5.828125 L 5.453125 -2.453125 L 5.734375 -1.328125 L 6.078125 -2.46875 L 7.078125 -5.828125 L 8.03125 -5.828125 L 6.21875 0 L 5.1875 0 L 4.25 -3.5 L 4.03125 -4.484375 L 2.84375 0 Z M 1.8125 0 "/>
</symbol>
<symbol overflow="visible" id="glyph0-4">
<path style="stroke:none;" d="M 4.734375 -1.875 L 5.75 -1.75 C 5.59375 -1.15625 5.296875 -0.691406 4.859375 -0.359375 C 4.421875 -0.0351562 3.863281 0.125 3.1875 0.125 C 2.332031 0.125 1.65625 -0.132812 1.15625 -0.65625 C 0.65625 -1.175781 0.40625 -1.914062 0.40625 -2.875 C 0.40625 -3.851562 0.65625 -4.613281 1.15625 -5.15625 C 1.664062 -5.695312 2.328125 -5.96875 3.140625 -5.96875 C 3.921875 -5.96875 4.554688 -5.703125 5.046875 -5.171875 C 5.546875 -4.640625 5.796875 -3.890625 5.796875 -2.921875 C 5.796875 -2.867188 5.789062 -2.785156 5.78125 -2.671875 L 1.4375 -2.671875 C 1.46875 -2.023438 1.644531 -1.53125 1.96875 -1.1875 C 2.300781 -0.851562 2.710938 -0.6875 3.203125 -0.6875 C 3.554688 -0.6875 3.863281 -0.78125 4.125 -0.96875 C 4.382812 -1.15625 4.585938 -1.457031 4.734375 -1.875 Z M 1.484375 -3.484375 L 4.75 -3.484375 C 4.707031 -3.972656 4.582031 -4.335938 4.375 -4.578125 C 4.0625 -4.960938 3.648438 -5.15625 3.140625 -5.15625 C 2.691406 -5.15625 2.3125 -5 2 -4.6875 C 1.6875 -4.382812 1.515625 -3.984375 1.484375 -3.484375 Z M 1.484375 -3.484375 "/>
</symbol>
<symbol overflow="visible" id="glyph0-5">
<path style="stroke:none;" d="M 0.734375 0 L 0.734375 -5.828125 L 1.625 -5.828125 L 1.625 -4.953125 C 1.851562 -5.359375 2.0625 -5.628906 2.25 -5.765625 C 2.4375 -5.898438 2.648438 -5.96875 2.890625 -5.96875 C 3.222656 -5.96875 3.5625 -5.859375 3.90625 -5.640625 L 3.5625 -4.734375 C 3.320312 -4.867188 3.078125 -4.9375 2.828125 -4.9375 C 2.617188 -4.9375 2.425781 -4.867188 2.25 -4.734375 C 2.082031 -4.609375 1.960938 -4.429688 1.890625 -4.203125 C 1.773438 -3.859375 1.71875 -3.472656 1.71875 -3.046875 L 1.71875 0 Z M 0.734375 0 "/>
</symbol>
<symbol overflow="visible" id="glyph0-6">
<path style="stroke:none;" d=""/>
</symbol>
<symbol overflow="visible" id="glyph0-7">
<path style="stroke:none;" d="M 0.875 0 L 0.875 -8.046875 L 3.640625 -8.046875 C 4.265625 -8.046875 4.742188 -8.007812 5.078125 -7.9375 C 5.535156 -7.832031 5.925781 -7.640625 6.25 -7.359375 C 6.675781 -7.003906 6.992188 -6.546875 7.203125 -5.984375 C 7.421875 -5.421875 7.53125 -4.785156 7.53125 -4.078125 C 7.53125 -3.460938 7.457031 -2.914062 7.3125 -2.4375 C 7.164062 -1.96875 6.976562 -1.578125 6.75 -1.265625 C 6.53125 -0.960938 6.285156 -0.722656 6.015625 -0.546875 C 5.753906 -0.367188 5.4375 -0.234375 5.0625 -0.140625 C 4.6875 -0.046875 4.257812 0 3.78125 0 Z M 1.9375 -0.953125 L 3.65625 -0.953125 C 4.1875 -0.953125 4.601562 -1 4.90625 -1.09375 C 5.207031 -1.195312 5.445312 -1.335938 5.625 -1.515625 C 5.875 -1.765625 6.066406 -2.101562 6.203125 -2.53125 C 6.347656 -2.957031 6.421875 -3.476562 6.421875 -4.09375 C 6.421875 -4.925781 6.28125 -5.566406 6 -6.015625 C 5.726562 -6.472656 5.394531 -6.78125 5 -6.9375 C 4.71875 -7.050781 4.257812 -7.109375 3.625 -7.109375 L 1.9375 -7.109375 Z M 1.9375 -0.953125 "/>
</symbol>
<symbol overflow="visible" id="glyph0-8">
<path style="stroke:none;" d="M 0.75 -6.921875 L 0.75 -8.046875 L 1.734375 -8.046875 L 1.734375 -6.921875 Z M 0.75 0 L 0.75 -5.828125 L 1.734375 -5.828125 L 1.734375 0 Z M 0.75 0 "/>
</symbol>
<symbol overflow="visible" id="glyph0-9">
<path style="stroke:none;" d="M 0.34375 -1.734375 L 1.328125 -1.890625 C 1.378906 -1.503906 1.53125 -1.207031 1.78125 -1 C 2.03125 -0.789062 2.378906 -0.6875 2.828125 -0.6875 C 3.285156 -0.6875 3.625 -0.773438 3.84375 -0.953125 C 4.0625 -1.140625 4.171875 -1.359375 4.171875 -1.609375 C 4.171875 -1.828125 4.078125 -2.003906 3.890625 -2.140625 C 3.753906 -2.222656 3.414062 -2.332031 2.875 -2.46875 C 2.144531 -2.65625 1.640625 -2.8125 1.359375 -2.9375 C 1.078125 -3.070312 0.863281 -3.257812 0.71875 -3.5 C 0.582031 -3.738281 0.515625 -4 0.515625 -4.28125 C 0.515625 -4.539062 0.570312 -4.78125 0.6875 -5 C 0.8125 -5.226562 0.972656 -5.414062 1.171875 -5.5625 C 1.328125 -5.675781 1.535156 -5.769531 1.796875 -5.84375 C 2.066406 -5.925781 2.351562 -5.96875 2.65625 -5.96875 C 3.113281 -5.96875 3.515625 -5.898438 3.859375 -5.765625 C 4.210938 -5.628906 4.46875 -5.445312 4.625 -5.21875 C 4.789062 -5 4.90625 -4.703125 4.96875 -4.328125 L 4 -4.203125 C 3.957031 -4.492188 3.832031 -4.722656 3.625 -4.890625 C 3.414062 -5.066406 3.117188 -5.15625 2.734375 -5.15625 C 2.273438 -5.15625 1.945312 -5.078125 1.75 -4.921875 C 1.5625 -4.773438 1.46875 -4.601562 1.46875 -4.40625 C 1.46875 -4.269531 1.507812 -4.148438 1.59375 -4.046875 C 1.664062 -3.941406 1.789062 -3.859375 1.96875 -3.796875 C 2.0625 -3.753906 2.351562 -3.664062 2.84375 -3.53125 C 3.539062 -3.34375 4.023438 -3.191406 4.296875 -3.078125 C 4.578125 -2.960938 4.796875 -2.789062 4.953125 -2.5625 C 5.109375 -2.332031 5.1875 -2.050781 5.1875 -1.71875 C 5.1875 -1.382812 5.085938 -1.070312 4.890625 -0.78125 C 4.703125 -0.488281 4.425781 -0.265625 4.0625 -0.109375 C 3.707031 0.046875 3.300781 0.125 2.84375 0.125 C 2.082031 0.125 1.503906 -0.03125 1.109375 -0.34375 C 0.710938 -0.65625 0.457031 -1.117188 0.34375 -1.734375 Z M 0.34375 -1.734375 "/>
</symbol>
<symbol overflow="visible" id="glyph0-10">
<path style="stroke:none;" d="M 0.734375 2.234375 L 0.734375 -5.828125 L 1.640625 -5.828125 L 1.640625 -5.078125 C 1.859375 -5.367188 2.097656 -5.585938 2.359375 -5.734375 C 2.628906 -5.890625 2.953125 -5.96875 3.328125 -5.96875 C 3.828125 -5.96875 4.265625 -5.835938 4.640625 -5.578125 C 5.023438 -5.328125 5.316406 -4.96875 5.515625 -4.5 C 5.710938 -4.03125 5.8125 -3.515625 5.8125 -2.953125 C 5.8125 -2.359375 5.703125 -1.820312 5.484375 -1.34375 C 5.265625 -0.863281 4.953125 -0.5 4.546875 -0.25 C 4.140625 0 3.710938 0.125 3.265625 0.125 C 2.929688 0.125 2.632812 0.0546875 2.375 -0.078125 C 2.113281 -0.210938 1.898438 -0.390625 1.734375 -0.609375 L 1.734375 2.234375 Z M 1.640625 -2.890625 C 1.640625 -2.140625 1.789062 -1.582031 2.09375 -1.21875 C 2.394531 -0.863281 2.765625 -0.6875 3.203125 -0.6875 C 3.640625 -0.6875 4.015625 -0.867188 4.328125 -1.234375 C 4.640625 -1.609375 4.796875 -2.1875 4.796875 -2.96875 C 4.796875 -3.707031 4.640625 -4.257812 4.328125 -4.625 C 4.023438 -5 3.660156 -5.1875 3.234375 -5.1875 C 2.816406 -5.1875 2.445312 -4.988281 2.125 -4.59375 C 1.800781 -4.207031 1.640625 -3.640625 1.640625 -2.890625 Z M 1.640625 -2.890625 "/>
</symbol>
<symbol overflow="visible" id="glyph0-11">
<path style="stroke:none;" d="M 4.546875 -0.71875 C 4.179688 -0.40625 3.828125 -0.1875 3.484375 -0.0625 C 3.148438 0.0625 2.789062 0.125 2.40625 0.125 C 1.757812 0.125 1.265625 -0.03125 0.921875 -0.34375 C 0.578125 -0.65625 0.40625 -1.050781 0.40625 -1.53125 C 0.40625 -1.820312 0.46875 -2.082031 0.59375 -2.3125 C 0.726562 -2.550781 0.898438 -2.742188 1.109375 -2.890625 C 1.316406 -3.035156 1.554688 -3.144531 1.828125 -3.21875 C 2.015625 -3.269531 2.304688 -3.316406 2.703125 -3.359375 C 3.503906 -3.453125 4.09375 -3.566406 4.46875 -3.703125 C 4.46875 -3.835938 4.46875 -3.921875 4.46875 -3.953125 C 4.46875 -4.359375 4.375 -4.644531 4.1875 -4.8125 C 3.9375 -5.03125 3.5625 -5.140625 3.0625 -5.140625 C 2.601562 -5.140625 2.257812 -5.054688 2.03125 -4.890625 C 1.8125 -4.734375 1.648438 -4.445312 1.546875 -4.03125 L 0.578125 -4.171875 C 0.660156 -4.585938 0.800781 -4.921875 1 -5.171875 C 1.207031 -5.421875 1.5 -5.613281 1.875 -5.75 C 2.257812 -5.894531 2.703125 -5.96875 3.203125 -5.96875 C 3.703125 -5.96875 4.109375 -5.90625 4.421875 -5.78125 C 4.734375 -5.664062 4.960938 -5.519531 5.109375 -5.34375 C 5.253906 -5.164062 5.359375 -4.941406 5.421875 -4.671875 C 5.453125 -4.503906 5.46875 -4.203125 5.46875 -3.765625 L 5.46875 -2.4375 C 5.46875 -1.519531 5.488281 -0.9375 5.53125 -0.6875 C 5.570312 -0.445312 5.65625 -0.21875 5.78125 0 L 4.75 0 C 4.644531 -0.207031 4.578125 -0.445312 4.546875 -0.71875 Z M 4.46875 -2.921875 C 4.101562 -2.773438 3.5625 -2.648438 2.84375 -2.546875 C 2.4375 -2.492188 2.148438 -2.429688 1.984375 -2.359375 C 1.816406 -2.285156 1.6875 -2.175781 1.59375 -2.03125 C 1.507812 -1.894531 1.46875 -1.738281 1.46875 -1.5625 C 1.46875 -1.300781 1.566406 -1.082031 1.765625 -0.90625 C 1.960938 -0.726562 2.253906 -0.640625 2.640625 -0.640625 C 3.015625 -0.640625 3.347656 -0.722656 3.640625 -0.890625 C 3.941406 -1.054688 4.164062 -1.285156 4.3125 -1.578125 C 4.414062 -1.796875 4.46875 -2.125 4.46875 -2.5625 Z M 4.46875 -2.921875 "/>
</symbol>
<symbol overflow="visible" id="glyph0-12">
<path style="stroke:none;" d="M 2.90625 -0.890625 L 3.046875 -0.015625 C 2.765625 0.046875 2.515625 0.078125 2.296875 0.078125 C 1.941406 0.078125 1.664062 0.0195312 1.46875 -0.09375 C 1.269531 -0.207031 1.128906 -0.351562 1.046875 -0.53125 C 0.960938 -0.71875 0.921875 -1.109375 0.921875 -1.703125 L 0.921875 -5.0625 L 0.203125 -5.0625 L 0.203125 -5.828125 L 0.921875 -5.828125 L 0.921875 -7.28125 L 1.90625 -7.875 L 1.90625 -5.828125 L 2.90625 -5.828125 L 2.90625 -5.0625 L 1.90625 -5.0625 L 1.90625 -1.65625 C 1.90625 -1.375 1.921875 -1.191406 1.953125 -1.109375 C 1.992188 -1.023438 2.050781 -0.957031 2.125 -0.90625 C 2.207031 -0.863281 2.320312 -0.84375 2.46875 -0.84375 C 2.570312 -0.84375 2.71875 -0.859375 2.90625 -0.890625 Z M 2.90625 -0.890625 "/>
</symbol>
<symbol overflow="visible" id="glyph0-13">
<path style="stroke:none;" d="M 0.734375 0 L 0.734375 -5.828125 L 1.625 -5.828125 L 1.625 -5 C 2.0625 -5.644531 2.679688 -5.96875 3.484375 -5.96875 C 3.835938 -5.96875 4.160156 -5.90625 4.453125 -5.78125 C 4.753906 -5.65625 4.976562 -5.488281 5.125 -5.28125 C 5.269531 -5.070312 5.367188 -4.828125 5.421875 -4.546875 C 5.460938 -4.367188 5.484375 -4.050781 5.484375 -3.59375 L 5.484375 0 L 4.5 0 L 4.5 -3.546875 C 4.5 -3.953125 4.457031 -4.253906 4.375 -4.453125 C 4.300781 -4.648438 4.164062 -4.804688 3.96875 -4.921875 C 3.769531 -5.046875 3.539062 -5.109375 3.28125 -5.109375 C 2.851562 -5.109375 2.488281 -4.972656 2.1875 -4.703125 C 1.882812 -4.441406 1.734375 -3.9375 1.734375 -3.1875 L 1.734375 0 Z M 0.734375 0 "/>
</symbol>
<symbol overflow="visible" id="glyph0-14">
<path style="stroke:none;" d="M 0.765625 2.234375 L 0.765625 -8.046875 L 2.9375 -8.046875 L 2.9375 -7.234375 L 1.75 -7.234375 L 1.75 1.421875 L 2.9375 1.421875 L 2.9375 2.234375 Z M 0.765625 2.234375 "/>
</symbol>
<symbol overflow="visible" id="glyph0-15">
<path style="stroke:none;" d="M -0.015625 0 L 3.078125 -8.046875 L 4.21875 -8.046875 L 7.515625 0 L 6.3125 0 L 5.359375 -2.4375 L 2 -2.4375 L 1.109375 0 Z M 2.3125 -3.3125 L 5.03125 -3.3125 L 4.203125 -5.53125 C 3.941406 -6.207031 3.75 -6.765625 3.625 -7.203125 C 3.519531 -6.691406 3.375 -6.179688 3.1875 -5.671875 Z M 2.3125 -3.3125 "/>
</symbol>
<symbol overflow="visible" id="glyph0-16">
<path style="stroke:none;" d="M 2.390625 2.234375 L 0.21875 2.234375 L 0.21875 1.421875 L 1.40625 1.421875 L 1.40625 -7.234375 L 0.21875 -7.234375 L 0.21875 -8.046875 L 2.390625 -8.046875 Z M 2.390625 2.234375 "/>
</symbol>
<symbol overflow="visible" id="glyph1-0">
<path style="stroke:none;" d="M 1.21875 0 L 1.21875 -6.09375 L 6.09375 -6.09375 L 6.09375 0 Z M 1.375 -0.15625 L 5.9375 -0.15625 L 5.9375 -5.9375 L 1.375 -5.9375 Z M 1.375 -0.15625 "/>
</symbol>
<symbol overflow="visible" id="glyph1-1">
<path style="stroke:none;" d="M 0.40625 -3.4375 C 0.40625 -4.269531 0.488281 -4.9375 0.65625 -5.4375 C 0.832031 -5.9375 1.085938 -6.320312 1.421875 -6.59375 C 1.753906 -6.875 2.175781 -7.015625 2.6875 -7.015625 C 3.050781 -7.015625 3.375 -6.9375 3.65625 -6.78125 C 3.945312 -6.632812 4.179688 -6.414062 4.359375 -6.125 C 4.546875 -5.84375 4.691406 -5.5 4.796875 -5.09375 C 4.898438 -4.6875 4.953125 -4.132812 4.953125 -3.4375 C 4.953125 -2.625 4.867188 -1.960938 4.703125 -1.453125 C 4.535156 -0.953125 4.285156 -0.5625 3.953125 -0.28125 C 3.617188 -0.0078125 3.195312 0.125 2.6875 0.125 C 2.007812 0.125 1.476562 -0.117188 1.09375 -0.609375 C 0.632812 -1.179688 0.40625 -2.125 0.40625 -3.4375 Z M 1.28125 -3.4375 C 1.28125 -2.289062 1.414062 -1.523438 1.6875 -1.140625 C 1.957031 -0.765625 2.289062 -0.578125 2.6875 -0.578125 C 3.070312 -0.578125 3.398438 -0.769531 3.671875 -1.15625 C 3.941406 -1.539062 4.078125 -2.300781 4.078125 -3.4375 C 4.078125 -4.59375 3.941406 -5.359375 3.671875 -5.734375 C 3.398438 -6.109375 3.066406 -6.296875 2.671875 -6.296875 C 2.273438 -6.296875 1.960938 -6.128906 1.734375 -5.796875 C 1.429688 -5.367188 1.28125 -4.582031 1.28125 -3.4375 Z M 1.28125 -3.4375 "/>
</symbol>
<symbol overflow="visible" id="glyph1-2">
<path style="stroke:none;" d="M 3.625 0 L 2.78125 0 L 2.78125 -5.453125 C 2.570312 -5.265625 2.300781 -5.070312 1.96875 -4.875 C 1.632812 -4.675781 1.332031 -4.523438 1.0625 -4.421875 L 1.0625 -5.25 C 1.539062 -5.476562 1.957031 -5.753906 2.3125 -6.078125 C 2.675781 -6.398438 2.929688 -6.710938 3.078125 -7.015625 L 3.625 -7.015625 Z M 3.625 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-3">
<path style="stroke:none;" d="M 4.90625 -0.828125 L 4.90625 0 L 0.296875 0 C 0.285156 -0.207031 0.316406 -0.40625 0.390625 -0.59375 C 0.515625 -0.90625 0.703125 -1.210938 0.953125 -1.515625 C 1.210938 -1.828125 1.585938 -2.179688 2.078125 -2.578125 C 2.835938 -3.203125 3.347656 -3.695312 3.609375 -4.0625 C 3.878906 -4.425781 4.015625 -4.769531 4.015625 -5.09375 C 4.015625 -5.425781 3.894531 -5.707031 3.65625 -5.9375 C 3.414062 -6.175781 3.097656 -6.296875 2.703125 -6.296875 C 2.285156 -6.296875 1.953125 -6.171875 1.703125 -5.921875 C 1.460938 -5.679688 1.34375 -5.34375 1.34375 -4.90625 L 0.453125 -4.984375 C 0.515625 -5.640625 0.742188 -6.140625 1.140625 -6.484375 C 1.535156 -6.835938 2.0625 -7.015625 2.71875 -7.015625 C 3.394531 -7.015625 3.925781 -6.828125 4.3125 -6.453125 C 4.707031 -6.078125 4.90625 -5.613281 4.90625 -5.0625 C 4.90625 -4.789062 4.847656 -4.519531 4.734375 -4.25 C 4.617188 -3.976562 4.425781 -3.691406 4.15625 -3.390625 C 3.894531 -3.097656 3.457031 -2.691406 2.84375 -2.171875 C 2.320312 -1.734375 1.988281 -1.4375 1.84375 -1.28125 C 1.695312 -1.132812 1.578125 -0.984375 1.484375 -0.828125 Z M 4.90625 -0.828125 "/>
</symbol>
<symbol overflow="visible" id="glyph1-4">
<path style="stroke:none;" d="M 0.40625 -1.84375 L 1.265625 -1.953125 C 1.359375 -1.472656 1.523438 -1.125 1.765625 -0.90625 C 2.003906 -0.6875 2.289062 -0.578125 2.625 -0.578125 C 3.03125 -0.578125 3.375 -0.71875 3.65625 -1 C 3.9375 -1.28125 4.078125 -1.628906 4.078125 -2.046875 C 4.078125 -2.429688 3.945312 -2.753906 3.6875 -3.015625 C 3.425781 -3.273438 3.097656 -3.40625 2.703125 -3.40625 C 2.546875 -3.40625 2.34375 -3.367188 2.09375 -3.296875 L 2.1875 -4.0625 C 2.25 -4.050781 2.296875 -4.046875 2.328125 -4.046875 C 2.691406 -4.046875 3.019531 -4.140625 3.3125 -4.328125 C 3.601562 -4.523438 3.75 -4.820312 3.75 -5.21875 C 3.75 -5.53125 3.644531 -5.785156 3.4375 -5.984375 C 3.226562 -6.191406 2.953125 -6.296875 2.609375 -6.296875 C 2.273438 -6.296875 2 -6.191406 1.78125 -5.984375 C 1.5625 -5.773438 1.421875 -5.460938 1.359375 -5.046875 L 0.5 -5.203125 C 0.601562 -5.773438 0.835938 -6.21875 1.203125 -6.53125 C 1.578125 -6.851562 2.039062 -7.015625 2.59375 -7.015625 C 2.976562 -7.015625 3.328125 -6.929688 3.640625 -6.765625 C 3.960938 -6.597656 4.207031 -6.375 4.375 -6.09375 C 4.550781 -5.8125 4.640625 -5.507812 4.640625 -5.1875 C 4.640625 -4.882812 4.554688 -4.609375 4.390625 -4.359375 C 4.234375 -4.117188 3.992188 -3.925781 3.671875 -3.78125 C 4.085938 -3.6875 4.410156 -3.488281 4.640625 -3.1875 C 4.867188 -2.882812 4.984375 -2.507812 4.984375 -2.0625 C 4.984375 -1.445312 4.757812 -0.925781 4.3125 -0.5 C 3.863281 -0.0820312 3.300781 0.125 2.625 0.125 C 2.007812 0.125 1.5 -0.0546875 1.09375 -0.421875 C 0.695312 -0.785156 0.46875 -1.257812 0.40625 -1.84375 Z M 0.40625 -1.84375 "/>
</symbol>
<symbol overflow="visible" id="glyph1-5">
<path style="stroke:none;" d="M 3.15625 0 L 3.15625 -1.671875 L 0.125 -1.671875 L 0.125 -2.453125 L 3.3125 -6.984375 L 4.015625 -6.984375 L 4.015625 -2.453125 L 4.953125 -2.453125 L 4.953125 -1.671875 L 4.015625 -1.671875 L 4.015625 0 Z M 3.15625 -2.453125 L 3.15625 -5.609375 L 0.96875 -2.453125 Z M 3.15625 -2.453125 "/>
</symbol>
<symbol overflow="visible" id="glyph1-6">
<path style="stroke:none;" d="M 0.40625 -1.828125 L 1.296875 -1.90625 C 1.367188 -1.46875 1.523438 -1.132812 1.765625 -0.90625 C 2.015625 -0.6875 2.304688 -0.578125 2.640625 -0.578125 C 3.054688 -0.578125 3.40625 -0.734375 3.6875 -1.046875 C 3.976562 -1.359375 4.125 -1.773438 4.125 -2.296875 C 4.125 -2.773438 3.984375 -3.15625 3.703125 -3.4375 C 3.429688 -3.726562 3.070312 -3.875 2.625 -3.875 C 2.351562 -3.875 2.101562 -3.8125 1.875 -3.6875 C 1.65625 -3.5625 1.484375 -3.394531 1.359375 -3.1875 L 0.5625 -3.296875 L 1.234375 -6.890625 L 4.703125 -6.890625 L 4.703125 -6.0625 L 1.921875 -6.0625 L 1.546875 -4.1875 C 1.960938 -4.476562 2.398438 -4.625 2.859375 -4.625 C 3.472656 -4.625 3.988281 -4.410156 4.40625 -3.984375 C 4.820312 -3.566406 5.03125 -3.023438 5.03125 -2.359375 C 5.03125 -1.734375 4.847656 -1.191406 4.484375 -0.734375 C 4.035156 -0.160156 3.421875 0.125 2.640625 0.125 C 2.003906 0.125 1.484375 -0.0507812 1.078125 -0.40625 C 0.679688 -0.769531 0.457031 -1.242188 0.40625 -1.828125 Z M 0.40625 -1.828125 "/>
</symbol>
<symbol overflow="visible" id="glyph1-7">
<path style="stroke:none;" d="M 4.84375 -5.265625 L 4 -5.203125 C 3.925781 -5.535156 3.816406 -5.78125 3.671875 -5.9375 C 3.441406 -6.175781 3.15625 -6.296875 2.8125 -6.296875 C 2.539062 -6.296875 2.300781 -6.222656 2.09375 -6.078125 C 1.820312 -5.878906 1.609375 -5.585938 1.453125 -5.203125 C 1.304688 -4.828125 1.226562 -4.289062 1.21875 -3.59375 C 1.425781 -3.914062 1.675781 -4.148438 1.96875 -4.296875 C 2.269531 -4.453125 2.582031 -4.53125 2.90625 -4.53125 C 3.476562 -4.53125 3.960938 -4.316406 4.359375 -3.890625 C 4.765625 -3.472656 4.96875 -2.929688 4.96875 -2.265625 C 4.96875 -1.828125 4.875 -1.421875 4.6875 -1.046875 C 4.5 -0.671875 4.238281 -0.378906 3.90625 -0.171875 C 3.582031 0.0234375 3.210938 0.125 2.796875 0.125 C 2.078125 0.125 1.488281 -0.132812 1.03125 -0.65625 C 0.582031 -1.1875 0.359375 -2.054688 0.359375 -3.265625 C 0.359375 -4.617188 0.609375 -5.597656 1.109375 -6.203125 C 1.546875 -6.742188 2.132812 -7.015625 2.875 -7.015625 C 3.414062 -7.015625 3.863281 -6.859375 4.21875 -6.546875 C 4.570312 -6.234375 4.78125 -5.804688 4.84375 -5.265625 Z M 1.359375 -2.265625 C 1.359375 -1.960938 1.421875 -1.675781 1.546875 -1.40625 C 1.671875 -1.144531 1.84375 -0.941406 2.0625 -0.796875 C 2.289062 -0.648438 2.53125 -0.578125 2.78125 -0.578125 C 3.132812 -0.578125 3.441406 -0.722656 3.703125 -1.015625 C 3.960938 -1.316406 4.09375 -1.71875 4.09375 -2.21875 C 4.09375 -2.695312 3.960938 -3.070312 3.703125 -3.34375 C 3.453125 -3.625 3.132812 -3.765625 2.75 -3.765625 C 2.351562 -3.765625 2.019531 -3.625 1.75 -3.34375 C 1.488281 -3.070312 1.359375 -2.710938 1.359375 -2.265625 Z M 1.359375 -2.265625 "/>
</symbol>
<symbol overflow="visible" id="glyph1-8">
<path style="stroke:none;" d="M 0.46875 -6.0625 L 0.46875 -6.890625 L 4.984375 -6.890625 L 4.984375 -6.21875 C 4.535156 -5.75 4.09375 -5.117188 3.65625 -4.328125 C 3.21875 -3.546875 2.878906 -2.742188 2.640625 -1.921875 C 2.472656 -1.335938 2.363281 -0.695312 2.3125 0 L 1.4375 0 C 1.445312 -0.550781 1.554688 -1.210938 1.765625 -1.984375 C 1.972656 -2.765625 2.269531 -3.515625 2.65625 -4.234375 C 3.039062 -4.960938 3.445312 -5.570312 3.875 -6.0625 Z M 0.46875 -6.0625 "/>
</symbol>
<symbol overflow="visible" id="glyph1-9">
<path style="stroke:none;" d="M 1.96875 0 L 0.125 -6.984375 L 1.0625 -6.984375 L 2.125 -2.40625 C 2.238281 -1.925781 2.335938 -1.445312 2.421875 -0.96875 C 2.597656 -1.71875 2.703125 -2.148438 2.734375 -2.265625 L 4.0625 -6.984375 L 5.1875 -6.984375 L 6.171875 -3.453125 C 6.429688 -2.578125 6.613281 -1.75 6.71875 -0.96875 C 6.8125 -1.414062 6.925781 -1.925781 7.0625 -2.5 L 8.171875 -6.984375 L 9.09375 -6.984375 L 7.171875 0 L 6.28125 0 L 4.8125 -5.3125 C 4.6875 -5.757812 4.613281 -6.035156 4.59375 -6.140625 C 4.519531 -5.816406 4.453125 -5.539062 4.390625 -5.3125 L 2.90625 0 Z M 1.96875 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-10">
<path style="stroke:none;" d="M 0.640625 0 L 0.640625 -5.0625 L 1.40625 -5.0625 L 1.40625 -4.296875 C 1.601562 -4.648438 1.785156 -4.882812 1.953125 -5 C 2.117188 -5.113281 2.300781 -5.171875 2.5 -5.171875 C 2.789062 -5.171875 3.082031 -5.078125 3.375 -4.890625 L 3.078125 -4.09375 C 2.867188 -4.21875 2.660156 -4.28125 2.453125 -4.28125 C 2.265625 -4.28125 2.097656 -4.222656 1.953125 -4.109375 C 1.804688 -4.003906 1.703125 -3.847656 1.640625 -3.640625 C 1.535156 -3.335938 1.484375 -3.003906 1.484375 -2.640625 L 1.484375 0 Z M 0.640625 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-11">
<path style="stroke:none;" d="M 0.640625 -6 L 0.640625 -6.984375 L 1.5 -6.984375 L 1.5 -6 Z M 0.640625 0 L 0.640625 -5.0625 L 1.5 -5.0625 L 1.5 0 Z M 0.640625 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-12">
<path style="stroke:none;" d="M 2.515625 -0.765625 L 2.640625 -0.015625 C 2.398438 0.0351562 2.179688 0.0625 1.984375 0.0625 C 1.679688 0.0625 1.441406 0.015625 1.265625 -0.078125 C 1.097656 -0.179688 0.976562 -0.3125 0.90625 -0.46875 C 0.832031 -0.625 0.796875 -0.960938 0.796875 -1.484375 L 0.796875 -4.390625 L 0.171875 -4.390625 L 0.171875 -5.0625 L 0.796875 -5.0625 L 0.796875 -6.3125 L 1.65625 -6.828125 L 1.65625 -5.0625 L 2.515625 -5.0625 L 2.515625 -4.390625 L 1.65625 -4.390625 L 1.65625 -1.4375 C 1.65625 -1.1875 1.671875 -1.023438 1.703125 -0.953125 C 1.734375 -0.890625 1.78125 -0.835938 1.84375 -0.796875 C 1.914062 -0.753906 2.015625 -0.734375 2.140625 -0.734375 C 2.234375 -0.734375 2.359375 -0.742188 2.515625 -0.765625 Z M 2.515625 -0.765625 "/>
</symbol>
<symbol overflow="visible" id="glyph1-13">
<path style="stroke:none;" d="M 4.109375 -1.625 L 4.984375 -1.515625 C 4.847656 -1.003906 4.585938 -0.601562 4.203125 -0.3125 C 3.828125 -0.03125 3.347656 0.109375 2.765625 0.109375 C 2.023438 0.109375 1.4375 -0.113281 1 -0.5625 C 0.570312 -1.019531 0.359375 -1.660156 0.359375 -2.484375 C 0.359375 -3.335938 0.578125 -4 1.015625 -4.46875 C 1.453125 -4.9375 2.019531 -5.171875 2.71875 -5.171875 C 3.394531 -5.171875 3.945312 -4.941406 4.375 -4.484375 C 4.800781 -4.023438 5.015625 -3.375 5.015625 -2.53125 C 5.015625 -2.488281 5.015625 -2.414062 5.015625 -2.3125 L 1.25 -2.3125 C 1.28125 -1.75 1.4375 -1.320312 1.71875 -1.03125 C 2 -0.738281 2.347656 -0.59375 2.765625 -0.59375 C 3.078125 -0.59375 3.34375 -0.671875 3.5625 -0.828125 C 3.789062 -0.992188 3.972656 -1.257812 4.109375 -1.625 Z M 1.296875 -3.015625 L 4.109375 -3.015625 C 4.078125 -3.441406 3.972656 -3.757812 3.796875 -3.96875 C 3.515625 -4.300781 3.160156 -4.46875 2.734375 -4.46875 C 2.335938 -4.46875 2.003906 -4.332031 1.734375 -4.0625 C 1.460938 -3.800781 1.316406 -3.453125 1.296875 -3.015625 Z M 1.296875 -3.015625 "/>
</symbol>
<symbol overflow="visible" id="glyph1-14">
<path style="stroke:none;" d="M 0.765625 0 L 0.765625 -6.984375 L 3.859375 -6.984375 C 4.484375 -6.984375 4.957031 -6.921875 5.28125 -6.796875 C 5.601562 -6.671875 5.859375 -6.445312 6.046875 -6.125 C 6.242188 -5.8125 6.34375 -5.460938 6.34375 -5.078125 C 6.34375 -4.578125 6.179688 -4.15625 5.859375 -3.8125 C 5.546875 -3.476562 5.050781 -3.265625 4.375 -3.171875 C 4.625 -3.054688 4.8125 -2.941406 4.9375 -2.828125 C 5.207031 -2.578125 5.460938 -2.269531 5.703125 -1.90625 L 6.921875 0 L 5.75 0 L 4.828125 -1.453125 C 4.554688 -1.867188 4.332031 -2.1875 4.15625 -2.40625 C 3.988281 -2.632812 3.832031 -2.789062 3.6875 -2.875 C 3.550781 -2.96875 3.414062 -3.03125 3.28125 -3.0625 C 3.175781 -3.082031 3.003906 -3.09375 2.765625 -3.09375 L 1.6875 -3.09375 L 1.6875 0 Z M 1.6875 -3.90625 L 3.671875 -3.90625 C 4.097656 -3.90625 4.425781 -3.945312 4.65625 -4.03125 C 4.894531 -4.113281 5.078125 -4.25 5.203125 -4.4375 C 5.328125 -4.632812 5.390625 -4.847656 5.390625 -5.078125 C 5.390625 -5.398438 5.269531 -5.664062 5.03125 -5.875 C 4.789062 -6.09375 4.414062 -6.203125 3.90625 -6.203125 L 1.6875 -6.203125 Z M 1.6875 -3.90625 "/>
</symbol>
<symbol overflow="visible" id="glyph1-15">
<path style="stroke:none;" d="M 3.9375 -0.625 C 3.625 -0.351562 3.316406 -0.160156 3.015625 -0.046875 C 2.722656 0.0546875 2.410156 0.109375 2.078125 0.109375 C 1.523438 0.109375 1.097656 -0.0234375 0.796875 -0.296875 C 0.503906 -0.566406 0.359375 -0.910156 0.359375 -1.328125 C 0.359375 -1.578125 0.410156 -1.800781 0.515625 -2 C 0.628906 -2.207031 0.773438 -2.375 0.953125 -2.5 C 1.140625 -2.625 1.347656 -2.71875 1.578125 -2.78125 C 1.742188 -2.832031 2 -2.875 2.34375 -2.90625 C 3.03125 -2.988281 3.539062 -3.085938 3.875 -3.203125 C 3.875 -3.328125 3.875 -3.40625 3.875 -3.4375 C 3.875 -3.78125 3.789062 -4.023438 3.625 -4.171875 C 3.40625 -4.359375 3.082031 -4.453125 2.65625 -4.453125 C 2.25 -4.453125 1.945312 -4.378906 1.75 -4.234375 C 1.5625 -4.097656 1.425781 -3.851562 1.34375 -3.5 L 0.5 -3.609375 C 0.570312 -3.972656 0.695312 -4.265625 0.875 -4.484375 C 1.050781 -4.703125 1.300781 -4.867188 1.625 -4.984375 C 1.957031 -5.109375 2.34375 -5.171875 2.78125 -5.171875 C 3.207031 -5.171875 3.554688 -5.117188 3.828125 -5.015625 C 4.097656 -4.910156 4.296875 -4.78125 4.421875 -4.625 C 4.554688 -4.476562 4.644531 -4.285156 4.6875 -4.046875 C 4.71875 -3.898438 4.734375 -3.640625 4.734375 -3.265625 L 4.734375 -2.125 C 4.734375 -1.320312 4.75 -0.816406 4.78125 -0.609375 C 4.820312 -0.398438 4.898438 -0.195312 5.015625 0 L 4.109375 0 C 4.023438 -0.175781 3.96875 -0.382812 3.9375 -0.625 Z M 3.875 -2.53125 C 3.5625 -2.40625 3.09375 -2.300781 2.46875 -2.21875 C 2.113281 -2.164062 1.863281 -2.109375 1.71875 -2.046875 C 1.570312 -1.984375 1.457031 -1.890625 1.375 -1.765625 C 1.300781 -1.640625 1.265625 -1.503906 1.265625 -1.359375 C 1.265625 -1.128906 1.347656 -0.9375 1.515625 -0.78125 C 1.691406 -0.632812 1.945312 -0.5625 2.28125 -0.5625 C 2.613281 -0.5625 2.90625 -0.628906 3.15625 -0.765625 C 3.414062 -0.910156 3.609375 -1.109375 3.734375 -1.359375 C 3.828125 -1.554688 3.875 -1.84375 3.875 -2.21875 Z M 3.875 -2.53125 "/>
</symbol>
<symbol overflow="visible" id="glyph1-16">
<path style="stroke:none;" d="M 3.921875 0 L 3.921875 -0.640625 C 3.597656 -0.140625 3.128906 0.109375 2.515625 0.109375 C 2.109375 0.109375 1.734375 0 1.390625 -0.21875 C 1.054688 -0.4375 0.796875 -0.742188 0.609375 -1.140625 C 0.421875 -1.546875 0.328125 -2.003906 0.328125 -2.515625 C 0.328125 -3.023438 0.410156 -3.484375 0.578125 -3.890625 C 0.753906 -4.304688 1.007812 -4.625 1.34375 -4.84375 C 1.675781 -5.0625 2.050781 -5.171875 2.46875 -5.171875 C 2.769531 -5.171875 3.039062 -5.101562 3.28125 -4.96875 C 3.519531 -4.84375 3.710938 -4.675781 3.859375 -4.46875 L 3.859375 -6.984375 L 4.71875 -6.984375 L 4.71875 0 Z M 1.21875 -2.515625 C 1.21875 -1.867188 1.351562 -1.382812 1.625 -1.0625 C 1.894531 -0.75 2.21875 -0.59375 2.59375 -0.59375 C 2.96875 -0.59375 3.285156 -0.742188 3.546875 -1.046875 C 3.804688 -1.359375 3.9375 -1.828125 3.9375 -2.453125 C 3.9375 -3.140625 3.800781 -3.644531 3.53125 -3.96875 C 3.269531 -4.289062 2.941406 -4.453125 2.546875 -4.453125 C 2.171875 -4.453125 1.851562 -4.296875 1.59375 -3.984375 C 1.34375 -3.679688 1.21875 -3.191406 1.21875 -2.515625 Z M 1.21875 -2.515625 "/>
</symbol>
<symbol overflow="visible" id="glyph1-17">
<path style="stroke:none;" d="M 5.734375 -2.453125 L 6.65625 -2.21875 C 6.457031 -1.457031 6.109375 -0.875 5.609375 -0.46875 C 5.109375 -0.0703125 4.492188 0.125 3.765625 0.125 C 3.015625 0.125 2.398438 -0.0234375 1.921875 -0.328125 C 1.453125 -0.640625 1.09375 -1.085938 0.84375 -1.671875 C 0.601562 -2.253906 0.484375 -2.878906 0.484375 -3.546875 C 0.484375 -4.265625 0.617188 -4.894531 0.890625 -5.4375 C 1.171875 -5.976562 1.566406 -6.390625 2.078125 -6.671875 C 2.597656 -6.953125 3.164062 -7.09375 3.78125 -7.09375 C 4.476562 -7.09375 5.0625 -6.914062 5.53125 -6.5625 C 6.007812 -6.207031 6.34375 -5.707031 6.53125 -5.0625 L 5.625 -4.84375 C 5.46875 -5.351562 5.234375 -5.722656 4.921875 -5.953125 C 4.609375 -6.191406 4.222656 -6.3125 3.765625 -6.3125 C 3.222656 -6.3125 2.769531 -6.179688 2.40625 -5.921875 C 2.050781 -5.660156 1.800781 -5.3125 1.65625 -4.875 C 1.507812 -4.445312 1.4375 -4.003906 1.4375 -3.546875 C 1.4375 -2.953125 1.519531 -2.429688 1.6875 -1.984375 C 1.863281 -1.546875 2.132812 -1.21875 2.5 -1 C 2.863281 -0.78125 3.257812 -0.671875 3.6875 -0.671875 C 4.207031 -0.671875 4.644531 -0.816406 5 -1.109375 C 5.363281 -1.410156 5.609375 -1.859375 5.734375 -2.453125 Z M 5.734375 -2.453125 "/>
</symbol>
<symbol overflow="visible" id="glyph1-18">
<path style="stroke:none;" d="M 0.328125 -2.53125 C 0.328125 -3.46875 0.585938 -4.160156 1.109375 -4.609375 C 1.535156 -4.984375 2.0625 -5.171875 2.6875 -5.171875 C 3.382812 -5.171875 3.953125 -4.941406 4.390625 -4.484375 C 4.835938 -4.023438 5.0625 -3.394531 5.0625 -2.59375 C 5.0625 -1.945312 4.960938 -1.4375 4.765625 -1.0625 C 4.566406 -0.6875 4.28125 -0.394531 3.90625 -0.1875 C 3.539062 0.0078125 3.132812 0.109375 2.6875 0.109375 C 1.988281 0.109375 1.421875 -0.113281 0.984375 -0.5625 C 0.546875 -1.019531 0.328125 -1.675781 0.328125 -2.53125 Z M 1.203125 -2.53125 C 1.203125 -1.882812 1.34375 -1.398438 1.625 -1.078125 C 1.90625 -0.753906 2.257812 -0.59375 2.6875 -0.59375 C 3.113281 -0.59375 3.46875 -0.753906 3.75 -1.078125 C 4.039062 -1.398438 4.1875 -1.894531 4.1875 -2.5625 C 4.1875 -3.1875 4.039062 -3.65625 3.75 -3.96875 C 3.46875 -4.289062 3.113281 -4.453125 2.6875 -4.453125 C 2.257812 -4.453125 1.90625 -4.289062 1.625 -3.96875 C 1.34375 -3.65625 1.203125 -3.175781 1.203125 -2.53125 Z M 1.203125 -2.53125 "/>
</symbol>
<symbol overflow="visible" id="glyph1-19">
<path style="stroke:none;" d="M 0.640625 0 L 0.640625 -5.0625 L 1.40625 -5.0625 L 1.40625 -4.34375 C 1.5625 -4.59375 1.769531 -4.789062 2.03125 -4.9375 C 2.300781 -5.09375 2.601562 -5.171875 2.9375 -5.171875 C 3.3125 -5.171875 3.617188 -5.09375 3.859375 -4.9375 C 4.097656 -4.78125 4.269531 -4.5625 4.375 -4.28125 C 4.769531 -4.875 5.289062 -5.171875 5.9375 -5.171875 C 6.4375 -5.171875 6.820312 -5.03125 7.09375 -4.75 C 7.363281 -4.476562 7.5 -4.050781 7.5 -3.46875 L 7.5 0 L 6.640625 0 L 6.640625 -3.1875 C 6.640625 -3.53125 6.609375 -3.773438 6.546875 -3.921875 C 6.492188 -4.078125 6.394531 -4.195312 6.25 -4.28125 C 6.101562 -4.375 5.929688 -4.421875 5.734375 -4.421875 C 5.378906 -4.421875 5.082031 -4.300781 4.84375 -4.0625 C 4.613281 -3.832031 4.5 -3.457031 4.5 -2.9375 L 4.5 0 L 3.640625 0 L 3.640625 -3.28125 C 3.640625 -3.664062 3.570312 -3.953125 3.4375 -4.140625 C 3.300781 -4.328125 3.070312 -4.421875 2.75 -4.421875 C 2.507812 -4.421875 2.285156 -4.359375 2.078125 -4.234375 C 1.878906 -4.109375 1.734375 -3.921875 1.640625 -3.671875 C 1.546875 -3.429688 1.5 -3.082031 1.5 -2.625 L 1.5 0 Z M 0.640625 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-20">
<path style="stroke:none;" d="M 0.640625 1.9375 L 0.640625 -5.0625 L 1.421875 -5.0625 L 1.421875 -4.40625 C 1.609375 -4.65625 1.816406 -4.84375 2.046875 -4.96875 C 2.273438 -5.101562 2.554688 -5.171875 2.890625 -5.171875 C 3.316406 -5.171875 3.695312 -5.054688 4.03125 -4.828125 C 4.363281 -4.609375 4.613281 -4.296875 4.78125 -3.890625 C 4.945312 -3.492188 5.03125 -3.050781 5.03125 -2.5625 C 5.03125 -2.050781 4.9375 -1.585938 4.75 -1.171875 C 4.5625 -0.753906 4.289062 -0.4375 3.9375 -0.21875 C 3.582031 0 3.210938 0.109375 2.828125 0.109375 C 2.546875 0.109375 2.289062 0.0507812 2.0625 -0.0625 C 1.832031 -0.1875 1.644531 -0.34375 1.5 -0.53125 L 1.5 1.9375 Z M 1.421875 -2.5 C 1.421875 -1.851562 1.550781 -1.375 1.8125 -1.0625 C 2.070312 -0.75 2.390625 -0.59375 2.765625 -0.59375 C 3.148438 -0.59375 3.476562 -0.753906 3.75 -1.078125 C 4.019531 -1.398438 4.15625 -1.898438 4.15625 -2.578125 C 4.15625 -3.210938 4.019531 -3.691406 3.75 -4.015625 C 3.488281 -4.335938 3.175781 -4.5 2.8125 -4.5 C 2.445312 -4.5 2.125 -4.328125 1.84375 -3.984375 C 1.5625 -3.640625 1.421875 -3.144531 1.421875 -2.5 Z M 1.421875 -2.5 "/>
</symbol>
<symbol overflow="visible" id="glyph1-21">
<path style="stroke:none;" d="M 0.71875 0 L 0.71875 -6.984375 L 2.109375 -6.984375 L 3.765625 -2.03125 C 3.921875 -1.570312 4.03125 -1.226562 4.09375 -1 C 4.175781 -1.257812 4.300781 -1.632812 4.46875 -2.125 L 6.140625 -6.984375 L 7.390625 -6.984375 L 7.390625 0 L 6.5 0 L 6.5 -5.84375 L 4.46875 0 L 3.625 0 L 1.609375 -5.9375 L 1.609375 0 Z M 0.71875 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-22">
<path style="stroke:none;" d="M 3.953125 0 L 3.953125 -0.75 C 3.554688 -0.175781 3.023438 0.109375 2.359375 0.109375 C 2.054688 0.109375 1.773438 0.0507812 1.515625 -0.0625 C 1.253906 -0.175781 1.0625 -0.316406 0.9375 -0.484375 C 0.8125 -0.660156 0.722656 -0.875 0.671875 -1.125 C 0.640625 -1.289062 0.625 -1.554688 0.625 -1.921875 L 0.625 -5.0625 L 1.484375 -5.0625 L 1.484375 -2.25 C 1.484375 -1.800781 1.5 -1.5 1.53125 -1.34375 C 1.582031 -1.125 1.695312 -0.945312 1.875 -0.8125 C 2.050781 -0.6875 2.265625 -0.625 2.515625 -0.625 C 2.773438 -0.625 3.015625 -0.6875 3.234375 -0.8125 C 3.460938 -0.945312 3.625 -1.128906 3.71875 -1.359375 C 3.8125 -1.585938 3.859375 -1.914062 3.859375 -2.34375 L 3.859375 -5.0625 L 4.71875 -5.0625 L 4.71875 0 Z M 3.953125 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-23">
<path style="stroke:none;" d="M 0.625 0 L 0.625 -6.984375 L 1.484375 -6.984375 L 1.484375 0 Z M 0.625 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-24">
<path style="stroke:none;" d="M 0.609375 1.953125 L 0.515625 1.140625 C 0.703125 1.191406 0.863281 1.21875 1 1.21875 C 1.1875 1.21875 1.335938 1.1875 1.453125 1.125 C 1.566406 1.0625 1.660156 0.972656 1.734375 0.859375 C 1.785156 0.773438 1.875 0.5625 2 0.21875 C 2.007812 0.164062 2.035156 0.0976562 2.078125 0.015625 L 0.15625 -5.0625 L 1.078125 -5.0625 L 2.140625 -2.125 C 2.273438 -1.757812 2.394531 -1.367188 2.5 -0.953125 C 2.59375 -1.347656 2.710938 -1.734375 2.859375 -2.109375 L 3.9375 -5.0625 L 4.796875 -5.0625 L 2.859375 0.078125 C 2.660156 0.640625 2.503906 1.023438 2.390625 1.234375 C 2.234375 1.515625 2.054688 1.71875 1.859375 1.84375 C 1.660156 1.976562 1.425781 2.046875 1.15625 2.046875 C 0.988281 2.046875 0.804688 2.015625 0.609375 1.953125 Z M 0.609375 1.953125 "/>
</symbol>
<symbol overflow="visible" id="glyph1-25">
<path style="stroke:none;" d="M -0.015625 0 L 2.671875 -6.984375 L 3.65625 -6.984375 L 6.515625 0 L 5.46875 0 L 4.65625 -2.109375 L 1.734375 -2.109375 L 0.96875 0 Z M 2 -2.859375 L 4.359375 -2.859375 L 3.640625 -4.796875 C 3.410156 -5.378906 3.242188 -5.863281 3.140625 -6.25 C 3.054688 -5.800781 2.929688 -5.351562 2.765625 -4.90625 Z M 2 -2.859375 "/>
</symbol>
<symbol overflow="visible" id="glyph1-26">
<path style="stroke:none;" d="M 0 0.125 L 2.015625 -7.09375 L 2.703125 -7.09375 L 0.6875 0.125 Z M 0 0.125 "/>
</symbol>
<symbol overflow="visible" id="glyph1-27">
<path style="stroke:none;" d="M 0.4375 -2.25 L 1.3125 -2.3125 C 1.351562 -1.96875 1.445312 -1.679688 1.59375 -1.453125 C 1.75 -1.234375 1.984375 -1.050781 2.296875 -0.90625 C 2.617188 -0.769531 2.976562 -0.703125 3.375 -0.703125 C 3.726562 -0.703125 4.035156 -0.753906 4.296875 -0.859375 C 4.566406 -0.972656 4.769531 -1.117188 4.90625 -1.296875 C 5.039062 -1.484375 5.109375 -1.679688 5.109375 -1.890625 C 5.109375 -2.109375 5.039062 -2.300781 4.90625 -2.46875 C 4.78125 -2.632812 4.570312 -2.769531 4.28125 -2.875 C 4.09375 -2.945312 3.675781 -3.0625 3.03125 -3.21875 C 2.394531 -3.375 1.945312 -3.519531 1.6875 -3.65625 C 1.351562 -3.832031 1.101562 -4.046875 0.9375 -4.296875 C 0.78125 -4.554688 0.703125 -4.847656 0.703125 -5.171875 C 0.703125 -5.523438 0.800781 -5.851562 1 -6.15625 C 1.195312 -6.46875 1.488281 -6.703125 1.875 -6.859375 C 2.257812 -7.015625 2.6875 -7.09375 3.15625 -7.09375 C 3.675781 -7.09375 4.132812 -7.007812 4.53125 -6.84375 C 4.925781 -6.675781 5.226562 -6.429688 5.4375 -6.109375 C 5.65625 -5.785156 5.769531 -5.421875 5.78125 -5.015625 L 4.90625 -4.953125 C 4.851562 -5.390625 4.6875 -5.71875 4.40625 -5.9375 C 4.132812 -6.164062 3.734375 -6.28125 3.203125 -6.28125 C 2.640625 -6.28125 2.226562 -6.175781 1.96875 -5.96875 C 1.71875 -5.769531 1.59375 -5.523438 1.59375 -5.234375 C 1.59375 -4.984375 1.679688 -4.78125 1.859375 -4.625 C 2.046875 -4.457031 2.515625 -4.285156 3.265625 -4.109375 C 4.015625 -3.941406 4.523438 -3.796875 4.796875 -3.671875 C 5.203125 -3.484375 5.503906 -3.242188 5.703125 -2.953125 C 5.898438 -2.671875 6 -2.34375 6 -1.96875 C 6 -1.59375 5.890625 -1.238281 5.671875 -0.90625 C 5.460938 -0.582031 5.15625 -0.328125 4.75 -0.140625 C 4.351562 0.0351562 3.90625 0.125 3.40625 0.125 C 2.78125 0.125 2.253906 0.03125 1.828125 -0.15625 C 1.398438 -0.34375 1.0625 -0.617188 0.8125 -0.984375 C 0.570312 -1.359375 0.445312 -1.78125 0.4375 -2.25 Z M 0.4375 -2.25 "/>
</symbol>
<symbol overflow="visible" id="glyph1-28">
<path style="stroke:none;" d="M 1.4375 0 L 0.640625 0 L 0.640625 -6.984375 L 1.5 -6.984375 L 1.5 -4.484375 C 1.851562 -4.941406 2.3125 -5.171875 2.875 -5.171875 C 3.1875 -5.171875 3.484375 -5.109375 3.765625 -4.984375 C 4.046875 -4.859375 4.273438 -4.679688 4.453125 -4.453125 C 4.628906 -4.222656 4.765625 -3.945312 4.859375 -3.625 C 4.960938 -3.3125 5.015625 -2.972656 5.015625 -2.609375 C 5.015625 -1.734375 4.800781 -1.0625 4.375 -0.59375 C 3.945312 -0.125 3.4375 0.109375 2.84375 0.109375 C 2.238281 0.109375 1.769531 -0.140625 1.4375 -0.640625 Z M 1.421875 -2.5625 C 1.421875 -1.957031 1.503906 -1.519531 1.671875 -1.25 C 1.941406 -0.8125 2.304688 -0.59375 2.765625 -0.59375 C 3.140625 -0.59375 3.460938 -0.753906 3.734375 -1.078125 C 4.003906 -1.398438 4.140625 -1.882812 4.140625 -2.53125 C 4.140625 -3.1875 4.007812 -3.671875 3.75 -3.984375 C 3.488281 -4.304688 3.171875 -4.46875 2.796875 -4.46875 C 2.429688 -4.46875 2.109375 -4.300781 1.828125 -3.96875 C 1.554688 -3.644531 1.421875 -3.175781 1.421875 -2.5625 Z M 1.421875 -2.5625 "/>
</symbol>
<symbol overflow="visible" id="glyph1-29">
<path style="stroke:none;" d="M 0.640625 0 L 0.640625 -6.984375 L 1.5 -6.984375 L 1.5 -4.46875 C 1.894531 -4.9375 2.398438 -5.171875 3.015625 -5.171875 C 3.390625 -5.171875 3.710938 -5.097656 3.984375 -4.953125 C 4.265625 -4.804688 4.460938 -4.601562 4.578125 -4.34375 C 4.703125 -4.082031 4.765625 -3.703125 4.765625 -3.203125 L 4.765625 0 L 3.90625 0 L 3.90625 -3.203125 C 3.90625 -3.628906 3.8125 -3.941406 3.625 -4.140625 C 3.4375 -4.335938 3.175781 -4.4375 2.84375 -4.4375 C 2.582031 -4.4375 2.335938 -4.367188 2.109375 -4.234375 C 1.890625 -4.097656 1.734375 -3.914062 1.640625 -3.6875 C 1.546875 -3.46875 1.5 -3.160156 1.5 -2.765625 L 1.5 0 Z M 0.640625 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-30">
<path style="stroke:none;" d="M 0.84375 0 L 0.84375 -4.390625 L 0.09375 -4.390625 L 0.09375 -5.0625 L 0.84375 -5.0625 L 0.84375 -5.59375 C 0.84375 -5.9375 0.875 -6.1875 0.9375 -6.34375 C 1.019531 -6.570312 1.164062 -6.753906 1.375 -6.890625 C 1.582031 -7.023438 1.875 -7.09375 2.25 -7.09375 C 2.488281 -7.09375 2.753906 -7.066406 3.046875 -7.015625 L 2.921875 -6.265625 C 2.742188 -6.296875 2.570312 -6.3125 2.40625 -6.3125 C 2.144531 -6.3125 1.960938 -6.253906 1.859375 -6.140625 C 1.753906 -6.035156 1.703125 -5.828125 1.703125 -5.515625 L 1.703125 -5.0625 L 2.6875 -5.0625 L 2.6875 -4.390625 L 1.703125 -4.390625 L 1.703125 0 Z M 0.84375 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-31">
<path style="stroke:none;" d=""/>
</symbol>
<symbol overflow="visible" id="glyph1-32">
<path style="stroke:none;" d="M 0.890625 0 L 0.890625 -0.96875 L 1.859375 -0.96875 L 1.859375 0 Z M 0.890625 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-33">
<path style="stroke:none;" d="M 0.71875 0 L 0.71875 -6.984375 L 1.640625 -6.984375 L 1.640625 -0.828125 L 5.078125 -0.828125 L 5.078125 0 Z M 0.71875 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-34">
<path style="stroke:none;" d="M 0.484375 0.421875 L 1.3125 0.546875 C 1.351562 0.796875 1.453125 0.984375 1.609375 1.109375 C 1.816406 1.265625 2.109375 1.34375 2.484375 1.34375 C 2.878906 1.34375 3.179688 1.257812 3.390625 1.09375 C 3.609375 0.9375 3.757812 0.71875 3.84375 0.4375 C 3.882812 0.257812 3.90625 -0.101562 3.90625 -0.65625 C 3.53125 -0.21875 3.0625 0 2.5 0 C 1.800781 0 1.257812 -0.25 0.875 -0.75 C 0.5 -1.25 0.3125 -1.851562 0.3125 -2.5625 C 0.3125 -3.039062 0.398438 -3.484375 0.578125 -3.890625 C 0.753906 -4.296875 1.003906 -4.609375 1.328125 -4.828125 C 1.660156 -5.054688 2.050781 -5.171875 2.5 -5.171875 C 3.101562 -5.171875 3.597656 -4.929688 3.984375 -4.453125 L 3.984375 -5.0625 L 4.765625 -5.0625 L 4.765625 -0.6875 C 4.765625 0.101562 4.6875 0.660156 4.53125 0.984375 C 4.375 1.316406 4.117188 1.578125 3.765625 1.765625 C 3.421875 1.953125 2.992188 2.046875 2.484375 2.046875 C 1.878906 2.046875 1.390625 1.910156 1.015625 1.640625 C 0.648438 1.367188 0.472656 0.960938 0.484375 0.421875 Z M 1.1875 -2.625 C 1.1875 -1.957031 1.316406 -1.46875 1.578125 -1.15625 C 1.847656 -0.851562 2.179688 -0.703125 2.578125 -0.703125 C 2.972656 -0.703125 3.300781 -0.851562 3.5625 -1.15625 C 3.832031 -1.46875 3.96875 -1.945312 3.96875 -2.59375 C 3.96875 -3.207031 3.828125 -3.671875 3.546875 -3.984375 C 3.273438 -4.296875 2.945312 -4.453125 2.5625 -4.453125 C 2.1875 -4.453125 1.863281 -4.296875 1.59375 -3.984375 C 1.320312 -3.679688 1.1875 -3.226562 1.1875 -2.625 Z M 1.1875 -2.625 "/>
</symbol>
<symbol overflow="visible" id="glyph1-35">
<path style="stroke:none;" d="M 3.9375 -1.859375 L 4.78125 -1.75 C 4.6875 -1.164062 4.453125 -0.707031 4.078125 -0.375 C 3.703125 -0.0507812 3.238281 0.109375 2.6875 0.109375 C 1.988281 0.109375 1.425781 -0.113281 1 -0.5625 C 0.582031 -1.019531 0.375 -1.671875 0.375 -2.515625 C 0.375 -3.054688 0.460938 -3.53125 0.640625 -3.9375 C 0.828125 -4.351562 1.101562 -4.660156 1.46875 -4.859375 C 1.84375 -5.066406 2.25 -5.171875 2.6875 -5.171875 C 3.238281 -5.171875 3.6875 -5.03125 4.03125 -4.75 C 4.382812 -4.476562 4.609375 -4.085938 4.703125 -3.578125 L 3.875 -3.4375 C 3.789062 -3.78125 3.644531 -4.035156 3.4375 -4.203125 C 3.238281 -4.378906 3 -4.46875 2.71875 -4.46875 C 2.289062 -4.46875 1.941406 -4.3125 1.671875 -4 C 1.398438 -3.6875 1.265625 -3.195312 1.265625 -2.53125 C 1.265625 -1.851562 1.394531 -1.359375 1.65625 -1.046875 C 1.914062 -0.742188 2.253906 -0.59375 2.671875 -0.59375 C 3.003906 -0.59375 3.28125 -0.691406 3.5 -0.890625 C 3.726562 -1.097656 3.875 -1.421875 3.9375 -1.859375 Z M 3.9375 -1.859375 "/>
</symbol>
<symbol overflow="visible" id="glyph1-36">
<path style="stroke:none;" d="M 0.046875 0 L 2.75 -3.640625 L 0.359375 -6.984375 L 1.46875 -6.984375 L 2.734375 -5.1875 C 2.992188 -4.8125 3.179688 -4.523438 3.296875 -4.328125 C 3.441406 -4.585938 3.625 -4.851562 3.84375 -5.125 L 5.25 -6.984375 L 6.25 -6.984375 L 3.796875 -3.6875 L 6.4375 0 L 5.296875 0 L 3.546875 -2.484375 C 3.441406 -2.628906 3.335938 -2.785156 3.234375 -2.953125 C 3.078125 -2.703125 2.96875 -2.53125 2.90625 -2.4375 L 1.15625 0 Z M 0.046875 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-37">
<path style="stroke:none;" d="M 0.46875 -3.40625 C 0.46875 -4.5625 0.78125 -5.46875 1.40625 -6.125 C 2.03125 -6.78125 2.832031 -7.109375 3.8125 -7.109375 C 4.457031 -7.109375 5.035156 -6.953125 5.546875 -6.640625 C 6.066406 -6.328125 6.460938 -5.894531 6.734375 -5.34375 C 7.003906 -4.800781 7.140625 -4.179688 7.140625 -3.484375 C 7.140625 -2.773438 6.992188 -2.140625 6.703125 -1.578125 C 6.421875 -1.023438 6.019531 -0.601562 5.5 -0.3125 C 4.976562 -0.0195312 4.414062 0.125 3.8125 0.125 C 3.15625 0.125 2.566406 -0.03125 2.046875 -0.34375 C 1.523438 -0.664062 1.128906 -1.101562 0.859375 -1.65625 C 0.597656 -2.207031 0.46875 -2.789062 0.46875 -3.40625 Z M 1.421875 -3.390625 C 1.421875 -2.546875 1.644531 -1.878906 2.09375 -1.390625 C 2.550781 -0.910156 3.117188 -0.671875 3.796875 -0.671875 C 4.492188 -0.671875 5.066406 -0.914062 5.515625 -1.40625 C 5.960938 -1.894531 6.1875 -2.585938 6.1875 -3.484375 C 6.1875 -4.054688 6.09375 -4.550781 5.90625 -4.96875 C 5.71875 -5.394531 5.4375 -5.722656 5.0625 -5.953125 C 4.695312 -6.191406 4.28125 -6.3125 3.8125 -6.3125 C 3.164062 -6.3125 2.601562 -6.082031 2.125 -5.625 C 1.65625 -5.175781 1.421875 -4.429688 1.421875 -3.390625 Z M 1.421875 -3.390625 "/>
</symbol>
<symbol overflow="visible" id="glyph1-38">
<path style="stroke:none;" d="M 0.75 0 L 0.75 -6.984375 L 1.6875 -6.984375 L 5.359375 -1.5 L 5.359375 -6.984375 L 6.234375 -6.984375 L 6.234375 0 L 5.296875 0 L 1.625 -5.484375 L 1.625 0 Z M 0.75 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-39">
<path style="stroke:none;" d="M 0.75 0 L 0.75 -6.984375 L 3.15625 -6.984375 C 3.695312 -6.984375 4.113281 -6.945312 4.40625 -6.875 C 4.800781 -6.78125 5.140625 -6.613281 5.421875 -6.375 C 5.785156 -6.0625 6.054688 -5.660156 6.234375 -5.171875 C 6.421875 -4.691406 6.515625 -4.144531 6.515625 -3.53125 C 6.515625 -3 6.453125 -2.523438 6.328125 -2.109375 C 6.210938 -1.703125 6.054688 -1.363281 5.859375 -1.09375 C 5.660156 -0.832031 5.445312 -0.625 5.21875 -0.46875 C 4.988281 -0.3125 4.710938 -0.191406 4.390625 -0.109375 C 4.066406 -0.0351562 3.691406 0 3.265625 0 Z M 1.671875 -0.828125 L 3.171875 -0.828125 C 3.628906 -0.828125 3.988281 -0.867188 4.25 -0.953125 C 4.507812 -1.035156 4.71875 -1.15625 4.875 -1.3125 C 5.09375 -1.53125 5.257812 -1.820312 5.375 -2.1875 C 5.5 -2.5625 5.5625 -3.015625 5.5625 -3.546875 C 5.5625 -4.273438 5.441406 -4.832031 5.203125 -5.21875 C 4.960938 -5.613281 4.675781 -5.878906 4.34375 -6.015625 C 4.09375 -6.109375 3.691406 -6.15625 3.140625 -6.15625 L 1.671875 -6.15625 Z M 1.671875 -0.828125 "/>
</symbol>
<symbol overflow="visible" id="glyph1-40">
<path style="stroke:none;" d="M 2.046875 0 L 0.125 -5.0625 L 1.03125 -5.0625 L 2.109375 -2.03125 C 2.234375 -1.695312 2.34375 -1.359375 2.4375 -1.015625 C 2.507812 -1.273438 2.613281 -1.59375 2.75 -1.96875 L 3.875 -5.0625 L 4.765625 -5.0625 L 2.84375 0 Z M 2.046875 0 "/>
</symbol>
<symbol overflow="visible" id="glyph1-41">
<path style="stroke:none;" d="M 0.640625 0 L 0.640625 -5.0625 L 1.40625 -5.0625 L 1.40625 -4.34375 C 1.78125 -4.894531 2.316406 -5.171875 3.015625 -5.171875 C 3.328125 -5.171875 3.609375 -5.113281 3.859375 -5 C 4.117188 -4.894531 4.3125 -4.753906 4.4375 -4.578125 C 4.5625 -4.398438 4.648438 -4.1875 4.703125 -3.9375 C 4.734375 -3.78125 4.75 -3.503906 4.75 -3.109375 L 4.75 0 L 3.890625 0 L 3.890625 -3.078125 C 3.890625 -3.421875 3.851562 -3.679688 3.78125 -3.859375 C 3.71875 -4.035156 3.601562 -4.171875 3.4375 -4.265625 C 3.269531 -4.367188 3.070312 -4.421875 2.84375 -4.421875 C 2.476562 -4.421875 2.160156 -4.304688 1.890625 -4.078125 C 1.628906 -3.847656 1.5 -3.410156 1.5 -2.765625 L 1.5 0 Z M 0.640625 0 "/>
</symbol>
<symbol overflow="visible" id="glyph2-0">
<path style="stroke:none;" d="M 1.40625 0 L 1.40625 -7.03125 L 7.03125 -7.03125 L 7.03125 0 Z M 1.578125 -0.171875 L 6.859375 -0.171875 L 6.859375 -6.859375 L 1.578125 -6.859375 Z M 1.578125 -0.171875 "/>
</symbol>
<symbol overflow="visible" id="glyph2-1">
<path style="stroke:none;" d="M 5.59375 -5.828125 L 5.59375 0 L 4.703125 0 L 4.703125 -0.6875 C 4.515625 -0.394531 4.328125 -0.195312 4.140625 -0.09375 C 3.878906 0.0625 3.582031 0.140625 3.25 0.140625 C 2.945312 0.140625 2.675781 0.078125 2.4375 -0.046875 C 2.257812 -0.140625 2.066406 -0.320312 1.859375 -0.59375 L 1.859375 2.234375 L 0.875 2.234375 L 0.875 -5.828125 L 1.859375 -5.828125 L 1.859375 -3.359375 C 1.859375 -2.460938 1.90625 -1.878906 2 -1.609375 C 2.09375 -1.347656 2.242188 -1.140625 2.453125 -0.984375 C 2.671875 -0.835938 2.921875 -0.765625 3.203125 -0.765625 C 3.492188 -0.765625 3.753906 -0.84375 3.984375 -1 C 4.210938 -1.15625 4.375 -1.359375 4.46875 -1.609375 C 4.570312 -1.867188 4.625 -2.445312 4.625 -3.34375 L 4.625 -5.828125 Z M 5.59375 -5.828125 "/>
</symbol>
</g>
<clipPath id="clip1">
<path d="M 136 236 L 233 236 L 233 246.359375 L 136 246.359375 Z M 136 236 "/>
</clipPath>
<clipPath id="clip2">
<path d="M 239 236 L 250 236 L 250 246.359375 L 239 246.359375 Z M 239 236 "/>
</clipPath>
<clipPath id="clip3">
<path d="M 66 215 L 333.652344 215 L 333.652344 217 L 66 217 Z M 66 215 "/>
</clipPath>
<clipPath id="clip4">
<path d="M 233 238 L 239 238 L 239 246.359375 L 233 246.359375 Z M 233 238 "/>
</clipPath>
</defs>
<g id="surface1">
<g clip-path="url(#clip1)" clip-rule="nonzero">
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph0-1" x="136.02637" y="244.125"/>
<use xlink:href="#glyph0-2" x="143.51887" y="244.125"/>
<use xlink:href="#glyph0-3" x="149.77387" y="244.125"/>
<use xlink:href="#glyph0-4" x="157.89637" y="244.125"/>
<use xlink:href="#glyph0-5" x="164.15137" y="244.125"/>
<use xlink:href="#glyph0-6" x="167.89762" y="244.125"/>
<use xlink:href="#glyph0-7" x="171.01387" y="244.125"/>
<use xlink:href="#glyph0-8" x="179.13637" y="244.125"/>
<use xlink:href="#glyph0-9" x="181.63387" y="244.125"/>
<use xlink:href="#glyph0-9" x="187.25887" y="244.125"/>
<use xlink:href="#glyph0-8" x="192.88387" y="244.125"/>
<use xlink:href="#glyph0-10" x="195.38137" y="244.125"/>
<use xlink:href="#glyph0-11" x="201.63637" y="244.125"/>
<use xlink:href="#glyph0-12" x="207.89137" y="244.125"/>
<use xlink:href="#glyph0-8" x="211.00762" y="244.125"/>
<use xlink:href="#glyph0-2" x="213.50512" y="244.125"/>
<use xlink:href="#glyph0-13" x="219.76012" y="244.125"/>
<use xlink:href="#glyph0-6" x="226.01512" y="244.125"/>
<use xlink:href="#glyph0-14" x="229.13137" y="244.125"/>
</g>
</g>
<g clip-path="url(#clip2)" clip-rule="nonzero">
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph0-15" x="239.38012" y="244.125"/>
<use xlink:href="#glyph0-16" x="246.87262" y="244.125"/>
</g>
</g>
<g clip-path="url(#clip3)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 215.625 L 333.277344 215.625 "/>
</g>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 215.625 L 67.027344 212.960938 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 102.527344 215.625 L 102.527344 212.960938 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 138.027344 215.625 L 138.027344 212.960938 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 173.527344 215.625 L 173.527344 212.960938 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 209.027344 215.625 L 209.027344 212.960938 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 244.527344 215.625 L 244.527344 212.960938 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 280.027344 215.625 L 280.027344 212.960938 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 315.527344 215.625 L 315.527344 212.960938 "/>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-1" x="63.651372" y="229.375008"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-2" x="96.148122" y="229.375008"/>
<use xlink:href="#glyph1-1" x="101.569122" y="229.375008"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-3" x="131.647872" y="229.375008"/>
<use xlink:href="#glyph1-1" x="137.068872" y="229.375008"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-4" x="167.147622" y="229.375008"/>
<use xlink:href="#glyph1-1" x="172.568622" y="229.375008"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-5" x="202.65137" y="229.375008"/>
<use xlink:href="#glyph1-1" x="208.07237" y="229.375008"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-6" x="238.151119" y="229.375008"/>
<use xlink:href="#glyph1-1" x="243.572119" y="229.375008"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-7" x="273.64112" y="229.375008"/>
<use xlink:href="#glyph1-1" x="279.062119" y="229.375008"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-8" x="309.14087" y="229.375008"/>
<use xlink:href="#glyph1-1" x="314.56187" y="229.375008"/>
</g>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 215.625 L 67.027344 0.375 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 199.066406 L 69.6875 199.066406 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 182.507812 L 69.6875 182.507812 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 165.953125 L 69.6875 165.953125 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 149.394531 L 69.6875 149.394531 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 132.835938 L 69.6875 132.835938 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 116.277344 L 69.6875 116.277344 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 99.722656 L 69.6875 99.722656 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 83.164062 L 69.6875 83.164062 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 66.605469 L 69.6875 66.605469 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 50.046875 L 69.6875 50.046875 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 33.492188 L 69.6875 33.492188 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 16.933594 L 69.6875 16.933594 "/>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-9" x="36.776368" y="202.442304"/>
<use xlink:href="#glyph1-10" x="45.970618" y="202.442304"/>
<use xlink:href="#glyph1-11" x="49.217368" y="202.442304"/>
<use xlink:href="#glyph1-12" x="51.381868" y="202.442304"/>
<use xlink:href="#glyph1-13" x="54.082618" y="202.442304"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-14" x="37.526368" y="185.88461"/>
<use xlink:href="#glyph1-13" x="44.565868" y="185.88461"/>
<use xlink:href="#glyph1-15" x="49.986868" y="185.88461"/>
<use xlink:href="#glyph1-16" x="55.407868" y="185.88461"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-17" x="18.026368" y="169.326917"/>
<use xlink:href="#glyph1-18" x="25.065868" y="169.326917"/>
<use xlink:href="#glyph1-19" x="30.486868" y="169.326917"/>
<use xlink:href="#glyph1-20" x="38.608618" y="169.326917"/>
<use xlink:href="#glyph1-15" x="44.029618" y="169.326917"/>
<use xlink:href="#glyph1-10" x="49.450618" y="169.326917"/>
<use xlink:href="#glyph1-13" x="52.697368" y="169.326917"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-21" x="24.026372" y="152.769223"/>
<use xlink:href="#glyph1-22" x="32.148122" y="152.769223"/>
<use xlink:href="#glyph1-23" x="37.569122" y="152.769223"/>
<use xlink:href="#glyph1-12" x="39.733622" y="152.769223"/>
<use xlink:href="#glyph1-11" x="42.434372" y="152.769223"/>
<use xlink:href="#glyph1-20" x="44.598872" y="152.769223"/>
<use xlink:href="#glyph1-23" x="50.019872" y="152.769223"/>
<use xlink:href="#glyph1-24" x="52.184372" y="152.769223"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-25" x="21.776374" y="136.211548"/>
<use xlink:href="#glyph1-16" x="28.269874" y="136.211548"/>
<use xlink:href="#glyph1-16" x="33.690874" y="136.211548"/>
<use xlink:href="#glyph1-26" x="39.111874" y="136.211548"/>
<use xlink:href="#glyph1-27" x="41.812624" y="136.211548"/>
<use xlink:href="#glyph1-22" x="48.306124" y="136.211548"/>
<use xlink:href="#glyph1-28" x="53.727124" y="136.211548"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-27" x="10.526376" y="119.653855"/>
<use xlink:href="#glyph1-29" x="17.019876" y="119.653855"/>
<use xlink:href="#glyph1-11" x="22.440876" y="119.653855"/>
<use xlink:href="#glyph1-30" x="24.605376" y="119.653855"/>
<use xlink:href="#glyph1-12" x="27.306126" y="119.653855"/>
<use xlink:href="#glyph1-31" x="30.006876" y="119.653855"/>
<use xlink:href="#glyph1-25" x="32.707626" y="119.653855"/>
<use xlink:href="#glyph1-10" x="39.201126" y="119.653855"/>
<use xlink:href="#glyph1-11" x="42.447876" y="119.653855"/>
<use xlink:href="#glyph1-12" x="44.612376" y="119.653855"/>
<use xlink:href="#glyph1-29" x="47.313126" y="119.653855"/>
<use xlink:href="#glyph1-32" x="52.734126" y="119.653855"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-27" x="8.276378" y="103.096161"/>
<use xlink:href="#glyph1-29" x="14.769878" y="103.096161"/>
<use xlink:href="#glyph1-11" x="20.190878" y="103.096161"/>
<use xlink:href="#glyph1-30" x="22.355378" y="103.096161"/>
<use xlink:href="#glyph1-12" x="25.056128" y="103.096161"/>
<use xlink:href="#glyph1-31" x="27.756878" y="103.096161"/>
<use xlink:href="#glyph1-33" x="30.457628" y="103.096161"/>
<use xlink:href="#glyph1-18" x="35.878628" y="103.096161"/>
<use xlink:href="#glyph1-34" x="41.299628" y="103.096161"/>
<use xlink:href="#glyph1-11" x="46.720628" y="103.096161"/>
<use xlink:href="#glyph1-35" x="48.885128" y="103.096161"/>
<use xlink:href="#glyph1-32" x="53.760128" y="103.096161"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-36" x="9.776376" y="86.538467"/>
<use xlink:href="#glyph1-37" x="16.269876" y="86.538467"/>
<use xlink:href="#glyph1-14" x="23.845626" y="86.538467"/>
<use xlink:href="#glyph1-26" x="30.885126" y="86.538467"/>
<use xlink:href="#glyph1-36" x="33.585876" y="86.538467"/>
<use xlink:href="#glyph1-38" x="40.079376" y="86.538467"/>
<use xlink:href="#glyph1-37" x="47.118876" y="86.538467"/>
<use xlink:href="#glyph1-14" x="54.694626" y="86.538467"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-25" x="23.276373" y="69.980773"/>
<use xlink:href="#glyph1-38" x="29.769873" y="69.980773"/>
<use xlink:href="#glyph1-39" x="36.809373" y="69.980773"/>
<use xlink:href="#glyph1-26" x="43.848873" y="69.980773"/>
<use xlink:href="#glyph1-37" x="46.549623" y="69.980773"/>
<use xlink:href="#glyph1-14" x="54.125373" y="69.980773"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-21" x="-0.723623" y="53.42308"/>
<use xlink:href="#glyph1-18" x="7.398127" y="53.42308"/>
<use xlink:href="#glyph1-40" x="12.819127" y="53.42308"/>
<use xlink:href="#glyph1-13" x="17.694127" y="53.42308"/>
<use xlink:href="#glyph1-31" x="23.115127" y="53.42308"/>
<use xlink:href="#glyph1-17" x="25.815877" y="53.42308"/>
<use xlink:href="#glyph1-18" x="32.855377" y="53.42308"/>
<use xlink:href="#glyph1-41" x="38.276377" y="53.42308"/>
<use xlink:href="#glyph1-30" x="43.697377" y="53.42308"/>
<use xlink:href="#glyph1-11" x="46.398127" y="53.42308"/>
<use xlink:href="#glyph1-34" x="48.562627" y="53.42308"/>
<use xlink:href="#glyph1-32" x="53.983627" y="53.42308"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-21" x="36.776379" y="36.865386"/>
<use xlink:href="#glyph1-18" x="44.898129" y="36.865386"/>
<use xlink:href="#glyph1-40" x="50.319129" y="36.865386"/>
<use xlink:href="#glyph1-13" x="55.194129" y="36.865386"/>
</g>
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph1-27" x="35.27638" y="20.307712"/>
<use xlink:href="#glyph1-23" x="41.76988" y="20.307712"/>
<use xlink:href="#glyph1-13" x="43.93438" y="20.307712"/>
<use xlink:href="#glyph1-13" x="49.35538" y="20.307712"/>
<use xlink:href="#glyph1-20" x="54.77638" y="20.307712"/>
</g>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(20.783997%,16.470337%,52.548218%);fill-opacity:1;" d="M 67.027344 192.445312 L 280.195312 192.445312 L 280.195312 205.691406 L 67.027344 205.691406 Z M 67.027344 192.445312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(20.783997%,16.470337%,52.548218%);fill-opacity:1;" d="M 67.027344 175.886719 L 222.898438 175.886719 L 222.898438 189.132812 L 67.027344 189.132812 Z M 67.027344 175.886719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(20.783997%,16.470337%,52.548218%);fill-opacity:1;" d="M 67.027344 159.328125 L 249.675781 159.328125 L 249.675781 172.574219 L 67.027344 172.574219 Z M 67.027344 159.328125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(20.783997%,16.470337%,52.548218%);fill-opacity:1;" d="M 67.027344 142.769531 L 309.847656 142.769531 L 309.847656 156.015625 L 67.027344 156.015625 Z M 67.027344 142.769531 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(20.783997%,16.470337%,52.548218%);fill-opacity:1;" d="M 67.027344 126.214844 L 266.074219 126.214844 L 266.074219 139.460938 L 67.027344 139.460938 Z M 67.027344 126.214844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(20.783997%,16.470337%,52.548218%);fill-opacity:1;" d="M 67.027344 109.65625 L 254.253906 109.65625 L 254.253906 122.902344 L 67.027344 122.902344 Z M 67.027344 109.65625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(20.783997%,16.470337%,52.548218%);fill-opacity:1;" d="M 67.027344 93.097656 L 251.910156 93.097656 L 251.910156 106.34375 L 67.027344 106.34375 Z M 67.027344 93.097656 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(20.783997%,16.470337%,52.548218%);fill-opacity:1;" d="M 67.027344 76.539062 L 250.101562 76.539062 L 250.101562 89.785156 L 67.027344 89.785156 Z M 67.027344 76.539062 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(20.783997%,16.470337%,52.548218%);fill-opacity:1;" d="M 67.027344 59.984375 L 228.375 59.984375 L 228.375 73.230469 L 67.027344 73.230469 Z M 67.027344 59.984375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(20.783997%,16.470337%,52.548218%);fill-opacity:1;" d="M 67.027344 43.425781 L 213.25 43.425781 L 213.25 56.671875 L 67.027344 56.671875 Z M 67.027344 43.425781 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(20.783997%,16.470337%,52.548218%);fill-opacity:1;" d="M 67.027344 26.867188 L 217.867188 26.867188 L 217.867188 40.113281 L 67.027344 40.113281 Z M 67.027344 26.867188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(20.783997%,16.470337%,52.548218%);fill-opacity:1;" d="M 67.027344 10.308594 L 165.714844 10.308594 L 165.714844 23.554688 L 67.027344 23.554688 Z M 67.027344 10.308594 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 192.445312 L 280.195312 192.445312 L 280.195312 205.691406 L 67.027344 205.691406 Z M 67.027344 192.445312 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 175.886719 L 222.898438 175.886719 L 222.898438 189.132812 L 67.027344 189.132812 Z M 67.027344 175.886719 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 159.328125 L 249.675781 159.328125 L 249.675781 172.574219 L 67.027344 172.574219 Z M 67.027344 159.328125 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 142.769531 L 309.847656 142.769531 L 309.847656 156.015625 L 67.027344 156.015625 Z M 67.027344 142.769531 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 126.214844 L 266.074219 126.214844 L 266.074219 139.460938 L 67.027344 139.460938 Z M 67.027344 126.214844 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 109.65625 L 254.253906 109.65625 L 254.253906 122.902344 L 67.027344 122.902344 Z M 67.027344 109.65625 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 93.097656 L 251.910156 93.097656 L 251.910156 106.34375 L 67.027344 106.34375 Z M 67.027344 93.097656 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 76.539062 L 250.101562 76.539062 L 250.101562 89.785156 L 67.027344 89.785156 Z M 67.027344 76.539062 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 59.984375 L 228.375 59.984375 L 228.375 73.230469 L 67.027344 73.230469 Z M 67.027344 59.984375 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 43.425781 L 213.25 43.425781 L 213.25 56.671875 L 67.027344 56.671875 Z M 67.027344 43.425781 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 26.867188 L 217.867188 26.867188 L 217.867188 40.113281 L 67.027344 40.113281 Z M 67.027344 26.867188 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 10.308594 L 165.714844 10.308594 L 165.714844 23.554688 L 67.027344 23.554688 Z M 67.027344 10.308594 "/>
<path style="fill:none;stroke-width:0.75;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(14.901733%,14.901733%,14.901733%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.027344 215.625 L 67.027344 0.375 "/>
<g clip-path="url(#clip4)" clip-rule="nonzero">
<g style="fill:rgb(14.901733%,14.901733%,14.901733%);fill-opacity:1;">
<use xlink:href="#glyph2-1" x="232.67469" y="244.118984"/>
</g>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 70 KiB

BIN
static/images/biocas2017/BGR.pdf Normal file
View File

Binary file not shown.

BIN
static/images/biocas2017/BODE.pdf Normal file
View File

Binary file not shown.

BIN
static/images/biocas2017/D2D.pdf Normal file
View File

Binary file not shown.

BIN
static/images/biocas2017/ENGINI.pdf Normal file
View File

Binary file not shown.

BIN
static/images/biocas2017/PSRR.pdf Normal file
View File

Binary file not shown.

BIN
static/images/biocas2017/REG.pdf Normal file
View File

Binary file not shown.

BIN
static/images/biocas2017/SDM.pdf Normal file
View File

Binary file not shown.

BIN
static/images/biocas2017/SPEC.pdf Normal file
View File

Binary file not shown.

BIN
static/images/biocas2017/SYS.pdf Normal file
View File

Binary file not shown.

BIN
static/images/biocas2017/refc.pdf Normal file
View File

Binary file not shown.

205
static/images/biocas2018/concept.svg Normal file
View File

@ -0,0 +1,205 @@
<?xml version="1.0" encoding="UTF-8"?>
<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" width="161.197113pt" height="79.35527pt" viewBox="0 0 161.197113 79.35527" version="1.1">
<defs>
<clipPath id="clip1">
<path d="M 51 76 L 54 76 L 54 79.355469 L 51 79.355469 Z M 51 76 "/>
</clipPath>
<clipPath id="clip2">
<path d="M 55 76 L 58 76 L 58 79.355469 L 55 79.355469 Z M 55 76 "/>
</clipPath>
<clipPath id="clip3">
<path d="M 59 76 L 62 76 L 62 79.355469 L 59 79.355469 Z M 59 76 "/>
</clipPath>
<clipPath id="clip4">
<path d="M 63 76 L 66 76 L 66 79.355469 L 63 79.355469 Z M 63 76 "/>
</clipPath>
<clipPath id="clip5">
<path d="M 158 25 L 161.195312 25 L 161.195312 30 L 158 30 Z M 158 25 "/>
</clipPath>
</defs>
<g id="surface1">
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 85.628906 8.730469 L 95.691406 8.730469 L 95.691406 24.800781 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 108.78125 64.015625 L 116.011719 64.015625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 119.523438 64.0625 L 113.960938 61.46875 L 113.960938 66.660156 L 116.742188 65.359375 Z M 119.523438 64.0625 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 38.8125 34.132812 L 78.609375 34.132812 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 23.160156 76.984375 L 14.929688 76.984375 " transform="matrix(0,1,1,0,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 75.921875 22.828125 L 78.097656 22.828125 L 78.097656 24.5625 L 75.921875 24.5625 Z M 75.921875 22.828125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 77.023438 24.558594 L 77.855469 23.480469 L 78.6875 22.40625 L 75.355469 22.40625 L 76.191406 23.480469 Z M 77.023438 24.558594 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 23.160156 83.09375 L 14.929688 83.09375 " transform="matrix(0,1,1,0,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 82.035156 22.828125 L 84.210938 22.828125 L 84.210938 24.5625 L 82.035156 24.5625 Z M 82.035156 22.828125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 83.132812 24.558594 L 83.964844 23.480469 L 84.796875 22.40625 L 81.464844 22.40625 L 82.300781 23.480469 Z M 83.132812 24.558594 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.199999;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 71.875 -9.332031 C 71.589844 -4.800781 75.027344 -0.902344 79.558594 -0.617188 C 84.089844 -0.332031 88 -3.773438 88.28125 -8.300781 C 88.570312 -12.828125 85.128906 -16.730469 80.597656 -17.015625 C 76.0625 -17.300781 72.160156 -13.859375 71.875 -9.332031 " transform="matrix(1,0,0,-1,0,0)"/>
<path style="fill:none;stroke-width:0.4;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 73.367188 -8.933594 C 73.640625 -8.933594 73.863281 -8.5625 74.105469 -8.820312 C 74.191406 -8.925781 74.441406 -9.152344 74.585938 -8.941406 C 74.722656 -8.84375 74.730469 -8.578125 74.984375 -8.585938 C 75.25 -8.769531 75.160156 -9.117188 75.476562 -9.25 C 75.789062 -8.960938 75.652344 -8.53125 75.980469 -8.261719 C 76.320312 -8.703125 76.160156 -9.257812 76.484375 -9.703125 C 76.789062 -9.191406 76.703125 -8.589844 76.855469 -8.046875 C 76.914062 -7.941406 76.859375 -7.664062 77.027344 -7.640625 C 77.34375 -8.605469 77.1875 -9.625 77.515625 -10.582031 C 77.800781 -9.53125 77.742188 -8.441406 77.878906 -7.375 C 77.9375 -7.085938 77.875 -6.675781 78.046875 -6.449219 C 78.371094 -8.332031 78.226562 -10.238281 78.539062 -12.121094 C 78.777344 -10.96875 78.714844 -9.757812 78.800781 -8.582031 C 78.890625 -7.238281 78.84375 -5.875 79.0625 -4.542969 C 79.320312 -6.679688 79.265625 -8.835938 79.378906 -10.980469 C 79.445312 -12.085938 79.398438 -13.226562 79.578125 -14.304688 C 79.832031 -11.523438 79.78125 -8.730469 79.90625 -5.941406 C 79.960938 -5.070312 79.914062 -4.179688 80.070312 -3.324219 C 80.324219 -5.929688 80.28125 -8.550781 80.414062 -11.160156 C 80.476562 -11.882812 80.410156 -12.746094 80.59375 -13.382812 C 80.886719 -10.675781 80.761719 -7.949219 81.074219 -5.242188 C 81.195312 -5.304688 81.144531 -5.648438 81.183594 -5.800781 C 81.363281 -7.746094 81.296875 -9.699219 81.589844 -11.636719 C 81.796875 -11.011719 81.738281 -10.285156 81.820312 -9.625 C 81.921875 -8.671875 81.863281 -7.695312 82.113281 -6.757812 C 82.429688 -7.945312 82.28125 -9.175781 82.605469 -10.363281 C 82.804688 -10.167969 82.730469 -9.792969 82.808594 -9.539062 C 82.933594 -8.953125 82.855469 -8.320312 83.136719 -7.757812 C 83.457031 -8.347656 83.292969 -9.027344 83.632812 -9.613281 C 83.90625 -9.332031 83.839844 -8.929688 83.988281 -8.605469 C 83.988281 -8.515625 84.132812 -8.171875 84.253906 -8.410156 C 84.433594 -8.664062 84.367188 -9.011719 84.675781 -9.214844 C 84.96875 -9.066406 84.847656 -8.695312 85.203125 -8.601562 C 85.453125 -8.691406 85.414062 -9.023438 85.746094 -9.007812 C 85.933594 -8.921875 86.101562 -8.609375 86.382812 -8.792969 C 86.488281 -8.847656 86.597656 -8.945312 86.761719 -8.921875 " transform="matrix(1,0,0,-1,0,0)"/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 84.433594 38.597656 L 124.230469 38.597656 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 83.527344 29.71875 L 123.328125 29.71875 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.199999;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 71.726562 33.617188 C 71.441406 38.144531 74.878906 42.046875 79.410156 42.332031 C 83.941406 42.617188 87.847656 39.175781 88.132812 34.648438 C 88.421875 30.121094 84.980469 26.21875 80.449219 25.933594 C 75.914062 25.648438 72.011719 29.089844 71.726562 33.617188 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:round;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 76.253906 37.808594 L 83.605469 30.457031 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:round;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 83.605469 37.808594 L 76.253906 30.457031 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.807491;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 67.629654 34.671206 L 49.363393 45.216595 L 49.364027 34.670229 L 49.36467 24.127843 L 58.497158 29.397535 Z M 67.629654 34.671206 " transform="matrix(1,0.00208608,-0.00216222,0.981529,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 51.132812 31.945312 L 51.726562 31.945312 L 51.726562 35.820312 L 53.851562 35.820312 L 53.851562 36.320312 L 51.132812 36.320312 Z M 51.132812 31.945312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 54.472656 31.945312 L 55.269531 31.945312 L 57.207031 35.601562 L 57.207031 31.945312 L 57.785156 31.945312 L 57.785156 36.320312 L 56.988281 36.320312 L 55.035156 32.664062 L 55.035156 36.320312 L 54.472656 36.320312 Z M 54.472656 31.945312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 60.414062 32.523438 L 59.617188 34.710938 L 61.226562 34.710938 Z M 60.085938 31.945312 L 60.757812 31.945312 L 62.429688 36.320312 L 61.804688 36.320312 L 61.414062 35.195312 L 59.429688 35.195312 L 59.039062 36.320312 L 58.414062 36.320312 Z M 60.085938 31.945312 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 114.886719 34.132812 L 121.265625 42.445312 L 134.164062 42.445312 L 134.164062 25.820312 L 121.265625 25.820312 Z M 114.886719 34.132812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 121.253906 32.519531 L 120.457031 34.707031 L 122.066406 34.707031 Z M 120.925781 31.941406 L 121.597656 31.941406 L 123.269531 36.316406 L 122.644531 36.316406 L 122.253906 35.191406 L 120.269531 35.191406 L 119.878906 36.316406 L 119.253906 36.316406 Z M 120.925781 31.941406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 124.496094 32.425781 L 124.496094 35.832031 L 125.199219 35.832031 C 125.800781 35.832031 126.246094 35.699219 126.527344 35.425781 C 126.808594 35.144531 126.949219 34.714844 126.949219 34.128906 C 126.949219 33.535156 126.808594 33.105469 126.527344 32.832031 C 126.246094 32.5625 125.800781 32.425781 125.199219 32.425781 Z M 123.902344 31.941406 L 125.121094 31.941406 C 125.964844 31.941406 126.582031 32.121094 126.980469 32.472656 C 127.375 32.828125 127.574219 33.378906 127.574219 34.128906 C 127.574219 34.878906 127.375 35.433594 126.980469 35.785156 C 126.582031 36.140625 125.964844 36.316406 125.121094 36.316406 L 123.902344 36.316406 Z M 123.902344 31.941406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 131.785156 32.285156 L 131.785156 32.910156 C 131.585938 32.722656 131.371094 32.582031 131.144531 32.488281 C 130.925781 32.394531 130.691406 32.347656 130.441406 32.347656 C 129.941406 32.347656 129.554688 32.503906 129.285156 32.816406 C 129.023438 33.121094 128.894531 33.558594 128.894531 34.128906 C 128.894531 34.714844 129.023438 35.15625 129.285156 35.457031 C 129.554688 35.761719 129.941406 35.910156 130.441406 35.910156 C 130.691406 35.910156 130.925781 35.871094 131.144531 35.785156 C 131.371094 35.691406 131.585938 35.550781 131.785156 35.363281 L 131.785156 35.972656 C 131.574219 36.121094 131.355469 36.230469 131.128906 36.300781 C 130.898438 36.363281 130.652344 36.394531 130.394531 36.394531 C 129.738281 36.394531 129.214844 36.199219 128.832031 35.800781 C 128.457031 35.394531 128.269531 34.839844 128.269531 34.128906 C 128.269531 33.433594 128.457031 32.878906 128.832031 32.472656 C 129.214844 32.066406 129.738281 31.863281 130.394531 31.863281 C 130.652344 31.863281 130.898438 31.902344 131.128906 31.972656 C 131.367188 32.035156 131.585938 32.140625 131.785156 32.285156 Z M 131.785156 32.285156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 10.8125 55.582031 L 10.183594 56.519531 L 9.554688 57.453125 L 12.074219 57.453125 L 11.445312 56.519531 Z M 10.8125 55.582031 "/>
<path style="fill:none;stroke-width:0.783069;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 27.90625 71.785156 C 21.40625 71.785156 15.003906 60.507812 10.753906 60.507812 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 10.8125 71.96875 L 10.8125 57.042969 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 28.09375 71.90625 L 9.875 71.90625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 29.351562 71.90625 L 28.414062 71.273438 L 27.480469 70.644531 L 27.480469 73.167969 L 28.414062 72.535156 Z M 29.351562 71.90625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 3.621094 60.101562 C 3.621094 60.675781 3.421875 61.117188 3.027344 61.429688 C 2.628906 61.742188 2.066406 61.898438 1.339844 61.898438 L 0.667969 61.898438 L 0.667969 64.148438 L -0.00390625 64.148438 L -0.00390625 58.429688 L 1.480469 58.429688 C 2.90625 58.429688 3.621094 58.988281 3.621094 60.101562 Z M 0.667969 61.335938 L 1.261719 61.335938 C 1.855469 61.335938 2.28125 61.242188 2.542969 61.054688 C 2.800781 60.859375 2.933594 60.550781 2.933594 60.132812 C 2.933594 59.757812 2.808594 59.476562 2.558594 59.289062 C 2.316406 59.101562 1.933594 59.007812 1.402344 59.007812 L 0.667969 59.007812 Z M 0.667969 61.335938 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 4.511719 62.183594 L 4.933594 62.183594 L 4.933594 65.746094 L 4.511719 65.746094 Z M 4.511719 62.183594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 8.761719 65.746094 L 8.292969 65.746094 L 6.339844 62.746094 L 6.308594 62.746094 C 6.339844 63.101562 6.355469 63.425781 6.355469 63.714844 L 6.355469 65.746094 L 5.964844 65.746094 L 5.964844 62.183594 L 6.433594 62.183594 L 8.386719 65.152344 L 8.402344 65.152344 C 8.402344 65.113281 8.394531 64.972656 8.386719 64.730469 C 8.375 64.492188 8.371094 64.324219 8.371094 64.230469 L 8.371094 62.183594 L 8.761719 62.183594 Z M 8.761719 65.746094 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 31.820312 74.195312 C 30.734375 74.195312 30.195312 73.425781 30.195312 71.882812 C 30.195312 71.269531 30.398438 70.546875 30.804688 69.710938 L 31.570312 69.710938 C 31.195312 70.546875 31.007812 71.273438 31.007812 71.898438 C 31.007812 73.023438 31.296875 73.585938 31.882812 73.585938 C 32.414062 73.585938 32.679688 72.890625 32.679688 71.492188 L 33.335938 71.492188 C 33.335938 72.890625 33.601562 73.585938 34.132812 73.585938 C 34.703125 73.585938 34.992188 73.023438 34.992188 71.898438 C 34.992188 71.273438 34.808594 70.546875 34.445312 69.710938 L 35.210938 69.710938 C 35.617188 70.546875 35.820312 71.269531 35.820312 71.882812 C 35.820312 73.425781 35.277344 74.195312 34.195312 74.195312 C 33.484375 74.195312 33.089844 73.804688 33.007812 73.023438 C 32.902344 73.804688 32.507812 74.195312 31.820312 74.195312 Z M 31.820312 74.195312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(30.587769%,60.391235%,2.352905%);fill-opacity:1;" d="M 126.324219 53.605469 L 125.527344 55.792969 L 127.136719 55.792969 Z M 125.996094 53.027344 L 126.667969 53.027344 L 128.339844 57.402344 L 127.714844 57.402344 L 127.324219 56.277344 L 125.339844 56.277344 L 124.949219 57.402344 L 124.324219 57.402344 Z M 125.996094 53.027344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(30.587769%,60.391235%,2.352905%);fill-opacity:1;" d="M 128.574219 58.183594 L 129.214844 58.183594 L 129.214844 55.949219 L 128.511719 56.089844 L 128.511719 55.730469 L 129.214844 55.589844 L 129.605469 55.589844 L 129.605469 58.183594 L 130.246094 58.183594 L 130.246094 58.511719 L 128.574219 58.511719 Z M 128.574219 58.183594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(30.587769%,60.391235%,2.352905%);fill-opacity:1;" d="M 132.230469 52.855469 C 131.96875 53.304688 131.777344 53.746094 131.652344 54.183594 C 131.527344 54.621094 131.464844 55.066406 131.464844 55.511719 C 131.464844 55.972656 131.527344 56.425781 131.652344 56.871094 C 131.777344 57.308594 131.96875 57.75 132.230469 58.199219 L 131.761719 58.199219 C 131.46875 57.738281 131.25 57.289062 131.105469 56.839844 C 130.957031 56.394531 130.886719 55.949219 130.886719 55.511719 C 130.886719 55.085938 130.957031 54.652344 131.105469 54.214844 C 131.25 53.769531 131.46875 53.316406 131.761719 52.855469 Z M 132.230469 52.855469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(30.587769%,60.391235%,2.352905%);fill-opacity:1;" d="M 133.632812 53.183594 L 133.632812 54.121094 L 134.742188 54.121094 L 134.742188 54.542969 L 133.632812 54.542969 L 133.632812 56.324219 C 133.632812 56.585938 133.667969 56.757812 133.742188 56.839844 C 133.8125 56.914062 133.964844 56.949219 134.195312 56.949219 L 134.742188 56.949219 L 134.742188 57.402344 L 134.195312 57.402344 C 133.777344 57.402344 133.492188 57.324219 133.335938 57.167969 C 133.179688 57.011719 133.101562 56.730469 133.101562 56.324219 L 133.101562 54.542969 L 132.695312 54.542969 L 132.695312 54.121094 L 133.101562 54.121094 L 133.101562 53.183594 Z M 133.632812 53.183594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(30.587769%,60.391235%,2.352905%);fill-opacity:1;" d="M 135.203125 52.855469 L 135.671875 52.855469 C 135.960938 53.316406 136.179688 53.769531 136.328125 54.214844 C 136.472656 54.652344 136.546875 55.085938 136.546875 55.511719 C 136.546875 55.949219 136.472656 56.394531 136.328125 56.839844 C 136.179688 57.289062 135.960938 57.738281 135.671875 58.199219 L 135.203125 58.199219 C 135.460938 57.75 135.65625 57.308594 135.78125 56.871094 C 135.90625 56.425781 135.96875 55.972656 135.96875 55.511719 C 135.96875 55.066406 135.90625 54.621094 135.78125 54.183594 C 135.65625 53.746094 135.460938 53.304688 135.203125 52.855469 Z M 135.203125 52.855469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(80.783081%,36.077881%,0%);fill-opacity:1;" d="M 126.324219 59.449219 L 125.527344 61.636719 L 127.136719 61.636719 Z M 125.996094 58.871094 L 126.667969 58.871094 L 128.339844 63.246094 L 127.714844 63.246094 L 127.324219 62.121094 L 125.339844 62.121094 L 124.949219 63.246094 L 124.324219 63.246094 Z M 125.996094 58.871094 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(80.783081%,36.077881%,0%);fill-opacity:1;" d="M 128.839844 64.03125 L 130.214844 64.03125 L 130.214844 64.359375 L 128.371094 64.359375 L 128.371094 64.03125 C 128.515625 63.875 128.71875 63.667969 128.980469 63.40625 C 129.238281 63.148438 129.402344 62.976562 129.464844 62.890625 C 129.589844 62.757812 129.675781 62.640625 129.730469 62.546875 C 129.78125 62.445312 129.808594 62.34375 129.808594 62.25 C 129.808594 62.09375 129.75 61.96875 129.636719 61.875 C 129.53125 61.773438 129.390625 61.71875 129.214844 61.71875 C 129.089844 61.71875 128.957031 61.742188 128.824219 61.78125 C 128.6875 61.824219 128.542969 61.890625 128.386719 61.984375 L 128.386719 61.578125 C 128.542969 61.515625 128.6875 61.46875 128.824219 61.4375 C 128.96875 61.40625 129.097656 61.390625 129.214844 61.390625 C 129.515625 61.390625 129.753906 61.46875 129.933594 61.625 C 130.109375 61.773438 130.199219 61.96875 130.199219 62.21875 C 130.199219 62.34375 130.175781 62.460938 130.136719 62.5625 C 130.09375 62.667969 130.011719 62.792969 129.886719 62.9375 C 129.855469 62.980469 129.75 63.09375 129.574219 63.28125 C 129.40625 63.460938 129.160156 63.710938 128.839844 64.03125 Z M 128.839844 64.03125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(80.783081%,36.077881%,0%);fill-opacity:1;" d="M 132.230469 58.699219 C 131.96875 59.148438 131.777344 59.589844 131.652344 60.027344 C 131.527344 60.464844 131.464844 60.910156 131.464844 61.355469 C 131.464844 61.816406 131.527344 62.269531 131.652344 62.714844 C 131.777344 63.152344 131.96875 63.59375 132.230469 64.042969 L 131.761719 64.042969 C 131.46875 63.582031 131.25 63.132812 131.105469 62.683594 C 130.957031 62.238281 130.886719 61.792969 130.886719 61.355469 C 130.886719 60.929688 130.957031 60.496094 131.105469 60.058594 C 131.25 59.613281 131.46875 59.160156 131.761719 58.699219 Z M 132.230469 58.699219 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(80.783081%,36.077881%,0%);fill-opacity:1;" d="M 133.632812 59.027344 L 133.632812 59.964844 L 134.742188 59.964844 L 134.742188 60.386719 L 133.632812 60.386719 L 133.632812 62.167969 C 133.632812 62.429688 133.667969 62.601562 133.742188 62.683594 C 133.8125 62.757812 133.964844 62.792969 134.195312 62.792969 L 134.742188 62.792969 L 134.742188 63.246094 L 134.195312 63.246094 C 133.777344 63.246094 133.492188 63.167969 133.335938 63.011719 C 133.179688 62.855469 133.101562 62.574219 133.101562 62.167969 L 133.101562 60.386719 L 132.695312 60.386719 L 132.695312 59.964844 L 133.101562 59.964844 L 133.101562 59.027344 Z M 133.632812 59.027344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(80.783081%,36.077881%,0%);fill-opacity:1;" d="M 135.203125 58.699219 L 135.671875 58.699219 C 135.960938 59.160156 136.179688 59.613281 136.328125 60.058594 C 136.472656 60.496094 136.546875 60.929688 136.546875 61.355469 C 136.546875 61.792969 136.472656 62.238281 136.328125 62.683594 C 136.179688 63.132812 135.960938 63.582031 135.671875 64.042969 L 135.203125 64.042969 C 135.460938 63.59375 135.65625 63.152344 135.78125 62.714844 C 135.90625 62.269531 135.96875 61.816406 135.96875 61.355469 C 135.96875 60.910156 135.90625 60.464844 135.78125 60.027344 C 135.65625 59.589844 135.460938 59.148438 135.203125 58.699219 Z M 135.203125 58.699219 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(12.548828%,29.019165%,52.940369%);fill-opacity:1;" d="M 126.324219 65.292969 L 125.527344 67.480469 L 127.136719 67.480469 Z M 125.996094 64.714844 L 126.667969 64.714844 L 128.339844 69.089844 L 127.714844 69.089844 L 127.324219 67.964844 L 125.339844 67.964844 L 124.949219 69.089844 L 124.324219 69.089844 Z M 125.996094 64.714844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(12.548828%,29.019165%,52.940369%);fill-opacity:1;" d="M 129.699219 68.625 C 129.886719 68.667969 130.03125 68.757812 130.136719 68.890625 C 130.238281 69.015625 130.292969 69.171875 130.292969 69.359375 C 130.292969 69.640625 130.191406 69.867188 129.996094 70.03125 C 129.796875 70.1875 129.515625 70.265625 129.152344 70.265625 C 129.035156 70.265625 128.910156 70.25 128.777344 70.21875 C 128.652344 70.199219 128.519531 70.164062 128.386719 70.109375 L 128.386719 69.734375 C 128.488281 69.796875 128.605469 69.84375 128.730469 69.875 C 128.863281 69.90625 129.003906 69.921875 129.152344 69.921875 C 129.390625 69.921875 129.574219 69.875 129.699219 69.78125 C 129.832031 69.6875 129.902344 69.546875 129.902344 69.359375 C 129.902344 69.183594 129.839844 69.046875 129.714844 68.953125 C 129.597656 68.859375 129.4375 68.8125 129.230469 68.8125 L 128.886719 68.8125 L 128.886719 68.484375 L 129.246094 68.484375 C 129.433594 68.484375 129.578125 68.449219 129.683594 68.375 C 129.785156 68.292969 129.839844 68.179688 129.839844 68.03125 C 129.839844 67.886719 129.785156 67.773438 129.683594 67.6875 C 129.578125 67.605469 129.425781 67.5625 129.230469 67.5625 C 129.113281 67.5625 128.996094 67.578125 128.871094 67.609375 C 128.746094 67.632812 128.609375 67.664062 128.464844 67.703125 L 128.464844 67.359375 C 128.621094 67.320312 128.761719 67.289062 128.886719 67.265625 C 129.019531 67.246094 129.144531 67.234375 129.261719 67.234375 C 129.5625 67.234375 129.796875 67.304688 129.964844 67.4375 C 130.140625 67.574219 130.230469 67.757812 130.230469 67.984375 C 130.230469 68.152344 130.183594 68.292969 130.089844 68.40625 C 129.996094 68.511719 129.863281 68.585938 129.699219 68.625 Z M 129.699219 68.625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(12.548828%,29.019165%,52.940369%);fill-opacity:1;" d="M 132.230469 64.542969 C 131.96875 64.992188 131.777344 65.433594 131.652344 65.871094 C 131.527344 66.308594 131.464844 66.753906 131.464844 67.199219 C 131.464844 67.660156 131.527344 68.113281 131.652344 68.558594 C 131.777344 68.996094 131.96875 69.4375 132.230469 69.886719 L 131.761719 69.886719 C 131.46875 69.425781 131.25 68.976562 131.105469 68.527344 C 130.957031 68.082031 130.886719 67.636719 130.886719 67.199219 C 130.886719 66.773438 130.957031 66.339844 131.105469 65.902344 C 131.25 65.457031 131.46875 65.003906 131.761719 64.542969 Z M 132.230469 64.542969 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(12.548828%,29.019165%,52.940369%);fill-opacity:1;" d="M 133.632812 64.871094 L 133.632812 65.808594 L 134.742188 65.808594 L 134.742188 66.230469 L 133.632812 66.230469 L 133.632812 68.011719 C 133.632812 68.273438 133.667969 68.445312 133.742188 68.527344 C 133.8125 68.601562 133.964844 68.636719 134.195312 68.636719 L 134.742188 68.636719 L 134.742188 69.089844 L 134.195312 69.089844 C 133.777344 69.089844 133.492188 69.011719 133.335938 68.855469 C 133.179688 68.699219 133.101562 68.417969 133.101562 68.011719 L 133.101562 66.230469 L 132.695312 66.230469 L 132.695312 65.808594 L 133.101562 65.808594 L 133.101562 64.871094 Z M 133.632812 64.871094 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(12.548828%,29.019165%,52.940369%);fill-opacity:1;" d="M 135.203125 64.542969 L 135.671875 64.542969 C 135.960938 65.003906 136.179688 65.457031 136.328125 65.902344 C 136.472656 66.339844 136.546875 66.773438 136.546875 67.199219 C 136.546875 67.636719 136.472656 68.082031 136.328125 68.527344 C 136.179688 68.976562 135.960938 69.425781 135.671875 69.886719 L 135.203125 69.886719 C 135.460938 69.4375 135.65625 68.996094 135.78125 68.558594 C 135.90625 68.113281 135.96875 67.660156 135.96875 67.199219 C 135.96875 66.753906 135.90625 66.308594 135.78125 65.871094 C 135.65625 65.433594 135.460938 64.992188 135.203125 64.542969 Z M 135.203125 64.542969 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(36.077881%,20.783997%,39.99939%);fill-opacity:1;" d="M 126.324219 71.136719 L 125.527344 73.324219 L 127.136719 73.324219 Z M 125.996094 70.558594 L 126.667969 70.558594 L 128.339844 74.933594 L 127.714844 74.933594 L 127.324219 73.808594 L 125.339844 73.808594 L 124.949219 74.933594 L 124.324219 74.933594 Z M 125.996094 70.558594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(36.077881%,20.783997%,39.99939%);fill-opacity:1;" d="M 129.589844 73.46875 L 128.589844 75.03125 L 129.589844 75.03125 Z M 129.480469 73.125 L 129.980469 73.125 L 129.980469 75.03125 L 130.402344 75.03125 L 130.402344 75.359375 L 129.980469 75.359375 L 129.980469 76.046875 L 129.589844 76.046875 L 129.589844 75.359375 L 128.277344 75.359375 L 128.277344 74.984375 Z M 129.480469 73.125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(36.077881%,20.783997%,39.99939%);fill-opacity:1;" d="M 132.230469 70.386719 C 131.96875 70.835938 131.777344 71.277344 131.652344 71.714844 C 131.527344 72.152344 131.464844 72.597656 131.464844 73.042969 C 131.464844 73.503906 131.527344 73.957031 131.652344 74.402344 C 131.777344 74.839844 131.96875 75.28125 132.230469 75.730469 L 131.761719 75.730469 C 131.46875 75.269531 131.25 74.820312 131.105469 74.371094 C 130.957031 73.925781 130.886719 73.480469 130.886719 73.042969 C 130.886719 72.617188 130.957031 72.183594 131.105469 71.746094 C 131.25 71.300781 131.46875 70.847656 131.761719 70.386719 Z M 132.230469 70.386719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(36.077881%,20.783997%,39.99939%);fill-opacity:1;" d="M 133.632812 70.714844 L 133.632812 71.652344 L 134.742188 71.652344 L 134.742188 72.074219 L 133.632812 72.074219 L 133.632812 73.855469 C 133.632812 74.117188 133.667969 74.289062 133.742188 74.371094 C 133.8125 74.445312 133.964844 74.480469 134.195312 74.480469 L 134.742188 74.480469 L 134.742188 74.933594 L 134.195312 74.933594 C 133.777344 74.933594 133.492188 74.855469 133.335938 74.699219 C 133.179688 74.542969 133.101562 74.261719 133.101562 73.855469 L 133.101562 72.074219 L 132.695312 72.074219 L 132.695312 71.652344 L 133.101562 71.652344 L 133.101562 70.714844 Z M 133.632812 70.714844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(36.077881%,20.783997%,39.99939%);fill-opacity:1;" d="M 135.203125 70.386719 L 135.671875 70.386719 C 135.960938 70.847656 136.179688 71.300781 136.328125 71.746094 C 136.472656 72.183594 136.546875 72.617188 136.546875 73.042969 C 136.546875 73.480469 136.472656 73.925781 136.328125 74.371094 C 136.179688 74.820312 135.960938 75.269531 135.671875 75.730469 L 135.203125 75.730469 C 135.460938 75.28125 135.65625 74.839844 135.78125 74.402344 C 135.90625 73.957031 135.96875 73.503906 135.96875 73.042969 C 135.96875 72.597656 135.90625 72.152344 135.78125 71.714844 C 135.65625 71.277344 135.460938 70.835938 135.203125 70.386719 Z M 135.203125 70.386719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(30.587769%,60.391235%,2.352905%);fill-opacity:1;" d="M 146.492188 53.867188 C 146.199219 53.910156 145.960938 54.019531 145.773438 54.195312 C 145.523438 54.414062 145.398438 54.71875 145.398438 55.101562 C 145.398438 55.488281 145.523438 55.796875 145.773438 56.023438 C 145.960938 56.191406 146.199219 56.296875 146.492188 56.335938 Z M 147.085938 56.335938 C 147.375 56.296875 147.621094 56.191406 147.820312 56.023438 C 148.070312 55.796875 148.195312 55.488281 148.195312 55.101562 C 148.195312 54.71875 148.070312 54.414062 147.820312 54.195312 C 147.621094 54.019531 147.375 53.910156 147.085938 53.867188 Z M 146.492188 56.820312 C 146.023438 56.78125 145.632812 56.628906 145.320312 56.367188 C 144.953125 56.054688 144.773438 55.632812 144.773438 55.101562 C 144.773438 54.570312 144.953125 54.148438 145.320312 53.835938 C 145.621094 53.578125 146.011719 53.425781 146.492188 53.382812 L 146.492188 52.914062 L 147.085938 52.914062 L 147.085938 53.382812 C 147.5625 53.425781 147.953125 53.578125 148.257812 53.835938 C 148.632812 54.148438 148.820312 54.570312 148.820312 55.101562 C 148.820312 55.632812 148.632812 56.054688 148.257812 56.367188 C 147.953125 56.628906 147.5625 56.785156 147.085938 56.835938 L 147.085938 57.289062 L 146.492188 57.289062 Z M 146.492188 56.820312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(30.587769%,60.391235%,2.352905%);fill-opacity:1;" d="M 149.300781 58.070312 L 149.941406 58.070312 L 149.941406 55.835938 L 149.238281 55.976562 L 149.238281 55.617188 L 149.941406 55.476562 L 150.332031 55.476562 L 150.332031 58.070312 L 150.972656 58.070312 L 150.972656 58.398438 L 149.300781 58.398438 Z M 149.300781 58.070312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(30.587769%,60.391235%,2.352905%);fill-opacity:1;" d="M 152.957031 52.742188 C 152.695312 53.191406 152.503906 53.632812 152.378906 54.070312 C 152.253906 54.507812 152.191406 54.953125 152.191406 55.398438 C 152.191406 55.859375 152.253906 56.3125 152.378906 56.757812 C 152.503906 57.195312 152.695312 57.636719 152.957031 58.085938 L 152.488281 58.085938 C 152.195312 57.625 151.976562 57.175781 151.832031 56.726562 C 151.683594 56.28125 151.613281 55.835938 151.613281 55.398438 C 151.613281 54.972656 151.683594 54.539062 151.832031 54.101562 C 151.976562 53.65625 152.195312 53.203125 152.488281 52.742188 Z M 152.957031 52.742188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(30.587769%,60.391235%,2.352905%);fill-opacity:1;" d="M 154.359375 53.070312 L 154.359375 54.007812 L 155.46875 54.007812 L 155.46875 54.429688 L 154.359375 54.429688 L 154.359375 56.210938 C 154.359375 56.472656 154.394531 56.644531 154.46875 56.726562 C 154.539062 56.800781 154.691406 56.835938 154.921875 56.835938 L 155.46875 56.835938 L 155.46875 57.289062 L 154.921875 57.289062 C 154.503906 57.289062 154.21875 57.210938 154.0625 57.054688 C 153.90625 56.898438 153.828125 56.617188 153.828125 56.210938 L 153.828125 54.429688 L 153.421875 54.429688 L 153.421875 54.007812 L 153.828125 54.007812 L 153.828125 53.070312 Z M 154.359375 53.070312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(30.587769%,60.391235%,2.352905%);fill-opacity:1;" d="M 155.929688 52.742188 L 156.398438 52.742188 C 156.6875 53.203125 156.90625 53.65625 157.054688 54.101562 C 157.199219 54.539062 157.273438 54.972656 157.273438 55.398438 C 157.273438 55.835938 157.199219 56.28125 157.054688 56.726562 C 156.90625 57.175781 156.6875 57.625 156.398438 58.085938 L 155.929688 58.085938 C 156.1875 57.636719 156.382812 57.195312 156.507812 56.757812 C 156.632812 56.3125 156.695312 55.859375 156.695312 55.398438 C 156.695312 54.953125 156.632812 54.507812 156.507812 54.070312 C 156.382812 53.632812 156.1875 53.191406 155.929688 52.742188 Z M 155.929688 52.742188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(80.783081%,36.077881%,0%);fill-opacity:1;" d="M 146.492188 59.710938 C 146.199219 59.753906 145.960938 59.863281 145.773438 60.039062 C 145.523438 60.257812 145.398438 60.5625 145.398438 60.945312 C 145.398438 61.332031 145.523438 61.640625 145.773438 61.867188 C 145.960938 62.035156 146.199219 62.140625 146.492188 62.179688 Z M 147.085938 62.179688 C 147.375 62.140625 147.621094 62.035156 147.820312 61.867188 C 148.070312 61.640625 148.195312 61.332031 148.195312 60.945312 C 148.195312 60.5625 148.070312 60.257812 147.820312 60.039062 C 147.621094 59.863281 147.375 59.753906 147.085938 59.710938 Z M 146.492188 62.664062 C 146.023438 62.625 145.632812 62.472656 145.320312 62.210938 C 144.953125 61.898438 144.773438 61.476562 144.773438 60.945312 C 144.773438 60.414062 144.953125 59.992188 145.320312 59.679688 C 145.621094 59.421875 146.011719 59.269531 146.492188 59.226562 L 146.492188 58.757812 L 147.085938 58.757812 L 147.085938 59.226562 C 147.5625 59.269531 147.953125 59.421875 148.257812 59.679688 C 148.632812 59.992188 148.820312 60.414062 148.820312 60.945312 C 148.820312 61.476562 148.632812 61.898438 148.257812 62.210938 C 147.953125 62.472656 147.5625 62.628906 147.085938 62.679688 L 147.085938 63.132812 L 146.492188 63.132812 Z M 146.492188 62.664062 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(80.783081%,36.077881%,0%);fill-opacity:1;" d="M 149.566406 63.914062 L 150.941406 63.914062 L 150.941406 64.242188 L 149.097656 64.242188 L 149.097656 63.914062 C 149.242188 63.757812 149.445312 63.550781 149.707031 63.289062 C 149.964844 63.03125 150.128906 62.859375 150.191406 62.773438 C 150.316406 62.640625 150.402344 62.523438 150.457031 62.429688 C 150.507812 62.328125 150.535156 62.226562 150.535156 62.132812 C 150.535156 61.976562 150.476562 61.851562 150.363281 61.757812 C 150.257812 61.65625 150.117188 61.601562 149.941406 61.601562 C 149.816406 61.601562 149.683594 61.625 149.550781 61.664062 C 149.414062 61.707031 149.269531 61.773438 149.113281 61.867188 L 149.113281 61.460938 C 149.269531 61.398438 149.414062 61.351562 149.550781 61.320312 C 149.695312 61.289062 149.824219 61.273438 149.941406 61.273438 C 150.242188 61.273438 150.480469 61.351562 150.660156 61.507812 C 150.835938 61.65625 150.925781 61.851562 150.925781 62.101562 C 150.925781 62.226562 150.902344 62.34375 150.863281 62.445312 C 150.820312 62.550781 150.738281 62.675781 150.613281 62.820312 C 150.582031 62.863281 150.476562 62.976562 150.300781 63.164062 C 150.132812 63.34375 149.886719 63.59375 149.566406 63.914062 Z M 149.566406 63.914062 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(80.783081%,36.077881%,0%);fill-opacity:1;" d="M 152.957031 58.585938 C 152.695312 59.035156 152.503906 59.476562 152.378906 59.914062 C 152.253906 60.351562 152.191406 60.796875 152.191406 61.242188 C 152.191406 61.703125 152.253906 62.15625 152.378906 62.601562 C 152.503906 63.039062 152.695312 63.480469 152.957031 63.929688 L 152.488281 63.929688 C 152.195312 63.46875 151.976562 63.019531 151.832031 62.570312 C 151.683594 62.125 151.613281 61.679688 151.613281 61.242188 C 151.613281 60.816406 151.683594 60.382812 151.832031 59.945312 C 151.976562 59.5 152.195312 59.046875 152.488281 58.585938 Z M 152.957031 58.585938 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(80.783081%,36.077881%,0%);fill-opacity:1;" d="M 154.359375 58.914062 L 154.359375 59.851562 L 155.46875 59.851562 L 155.46875 60.273438 L 154.359375 60.273438 L 154.359375 62.054688 C 154.359375 62.316406 154.394531 62.488281 154.46875 62.570312 C 154.539062 62.644531 154.691406 62.679688 154.921875 62.679688 L 155.46875 62.679688 L 155.46875 63.132812 L 154.921875 63.132812 C 154.503906 63.132812 154.21875 63.054688 154.0625 62.898438 C 153.90625 62.742188 153.828125 62.460938 153.828125 62.054688 L 153.828125 60.273438 L 153.421875 60.273438 L 153.421875 59.851562 L 153.828125 59.851562 L 153.828125 58.914062 Z M 154.359375 58.914062 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(80.783081%,36.077881%,0%);fill-opacity:1;" d="M 155.929688 58.585938 L 156.398438 58.585938 C 156.6875 59.046875 156.90625 59.5 157.054688 59.945312 C 157.199219 60.382812 157.273438 60.816406 157.273438 61.242188 C 157.273438 61.679688 157.199219 62.125 157.054688 62.570312 C 156.90625 63.019531 156.6875 63.46875 156.398438 63.929688 L 155.929688 63.929688 C 156.1875 63.480469 156.382812 63.039062 156.507812 62.601562 C 156.632812 62.15625 156.695312 61.703125 156.695312 61.242188 C 156.695312 60.796875 156.632812 60.351562 156.507812 59.914062 C 156.382812 59.476562 156.1875 59.035156 155.929688 58.585938 Z M 155.929688 58.585938 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(12.548828%,29.019165%,52.940369%);fill-opacity:1;" d="M 146.492188 65.554688 C 146.199219 65.597656 145.960938 65.707031 145.773438 65.882812 C 145.523438 66.101562 145.398438 66.40625 145.398438 66.789062 C 145.398438 67.175781 145.523438 67.484375 145.773438 67.710938 C 145.960938 67.878906 146.199219 67.984375 146.492188 68.023438 Z M 147.085938 68.023438 C 147.375 67.984375 147.621094 67.878906 147.820312 67.710938 C 148.070312 67.484375 148.195312 67.175781 148.195312 66.789062 C 148.195312 66.40625 148.070312 66.101562 147.820312 65.882812 C 147.621094 65.707031 147.375 65.597656 147.085938 65.554688 Z M 146.492188 68.507812 C 146.023438 68.46875 145.632812 68.316406 145.320312 68.054688 C 144.953125 67.742188 144.773438 67.320312 144.773438 66.789062 C 144.773438 66.257812 144.953125 65.835938 145.320312 65.523438 C 145.621094 65.265625 146.011719 65.113281 146.492188 65.070312 L 146.492188 64.601562 L 147.085938 64.601562 L 147.085938 65.070312 C 147.5625 65.113281 147.953125 65.265625 148.257812 65.523438 C 148.632812 65.835938 148.820312 66.257812 148.820312 66.789062 C 148.820312 67.320312 148.632812 67.742188 148.257812 68.054688 C 147.953125 68.316406 147.5625 68.472656 147.085938 68.523438 L 147.085938 68.976562 L 146.492188 68.976562 Z M 146.492188 68.507812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(12.548828%,29.019165%,52.940369%);fill-opacity:1;" d="M 150.425781 68.507812 C 150.613281 68.550781 150.757812 68.640625 150.863281 68.773438 C 150.964844 68.898438 151.019531 69.054688 151.019531 69.242188 C 151.019531 69.523438 150.917969 69.75 150.722656 69.914062 C 150.523438 70.070312 150.242188 70.148438 149.878906 70.148438 C 149.761719 70.148438 149.636719 70.132812 149.503906 70.101562 C 149.378906 70.082031 149.246094 70.046875 149.113281 69.992188 L 149.113281 69.617188 C 149.214844 69.679688 149.332031 69.726562 149.457031 69.757812 C 149.589844 69.789062 149.730469 69.804688 149.878906 69.804688 C 150.117188 69.804688 150.300781 69.757812 150.425781 69.664062 C 150.558594 69.570312 150.628906 69.429688 150.628906 69.242188 C 150.628906 69.066406 150.566406 68.929688 150.441406 68.835938 C 150.324219 68.742188 150.164062 68.695312 149.957031 68.695312 L 149.613281 68.695312 L 149.613281 68.367188 L 149.972656 68.367188 C 150.160156 68.367188 150.304688 68.332031 150.410156 68.257812 C 150.511719 68.175781 150.566406 68.0625 150.566406 67.914062 C 150.566406 67.769531 150.511719 67.65625 150.410156 67.570312 C 150.304688 67.488281 150.152344 67.445312 149.957031 67.445312 C 149.839844 67.445312 149.722656 67.460938 149.597656 67.492188 C 149.472656 67.515625 149.335938 67.546875 149.191406 67.585938 L 149.191406 67.242188 C 149.347656 67.203125 149.488281 67.171875 149.613281 67.148438 C 149.746094 67.128906 149.871094 67.117188 149.988281 67.117188 C 150.289062 67.117188 150.523438 67.1875 150.691406 67.320312 C 150.867188 67.457031 150.957031 67.640625 150.957031 67.867188 C 150.957031 68.035156 150.910156 68.175781 150.816406 68.289062 C 150.722656 68.394531 150.589844 68.46875 150.425781 68.507812 Z M 150.425781 68.507812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(12.548828%,29.019165%,52.940369%);fill-opacity:1;" d="M 152.957031 64.429688 C 152.695312 64.878906 152.503906 65.320312 152.378906 65.757812 C 152.253906 66.195312 152.191406 66.640625 152.191406 67.085938 C 152.191406 67.546875 152.253906 68 152.378906 68.445312 C 152.503906 68.882812 152.695312 69.324219 152.957031 69.773438 L 152.488281 69.773438 C 152.195312 69.3125 151.976562 68.863281 151.832031 68.414062 C 151.683594 67.96875 151.613281 67.523438 151.613281 67.085938 C 151.613281 66.660156 151.683594 66.226562 151.832031 65.789062 C 151.976562 65.34375 152.195312 64.890625 152.488281 64.429688 Z M 152.957031 64.429688 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(12.548828%,29.019165%,52.940369%);fill-opacity:1;" d="M 154.359375 64.757812 L 154.359375 65.695312 L 155.46875 65.695312 L 155.46875 66.117188 L 154.359375 66.117188 L 154.359375 67.898438 C 154.359375 68.160156 154.394531 68.332031 154.46875 68.414062 C 154.539062 68.488281 154.691406 68.523438 154.921875 68.523438 L 155.46875 68.523438 L 155.46875 68.976562 L 154.921875 68.976562 C 154.503906 68.976562 154.21875 68.898438 154.0625 68.742188 C 153.90625 68.585938 153.828125 68.304688 153.828125 67.898438 L 153.828125 66.117188 L 153.421875 66.117188 L 153.421875 65.695312 L 153.828125 65.695312 L 153.828125 64.757812 Z M 154.359375 64.757812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(12.548828%,29.019165%,52.940369%);fill-opacity:1;" d="M 155.929688 64.429688 L 156.398438 64.429688 C 156.6875 64.890625 156.90625 65.34375 157.054688 65.789062 C 157.199219 66.226562 157.273438 66.660156 157.273438 67.085938 C 157.273438 67.523438 157.199219 67.96875 157.054688 68.414062 C 156.90625 68.863281 156.6875 69.3125 156.398438 69.773438 L 155.929688 69.773438 C 156.1875 69.324219 156.382812 68.882812 156.507812 68.445312 C 156.632812 68 156.695312 67.546875 156.695312 67.085938 C 156.695312 66.640625 156.632812 66.195312 156.507812 65.757812 C 156.382812 65.320312 156.1875 64.878906 155.929688 64.429688 Z M 155.929688 64.429688 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(36.077881%,20.783997%,39.99939%);fill-opacity:1;" d="M 146.492188 71.398438 C 146.199219 71.441406 145.960938 71.550781 145.773438 71.726562 C 145.523438 71.945312 145.398438 72.25 145.398438 72.632812 C 145.398438 73.019531 145.523438 73.328125 145.773438 73.554688 C 145.960938 73.722656 146.199219 73.828125 146.492188 73.867188 Z M 147.085938 73.867188 C 147.375 73.828125 147.621094 73.722656 147.820312 73.554688 C 148.070312 73.328125 148.195312 73.019531 148.195312 72.632812 C 148.195312 72.25 148.070312 71.945312 147.820312 71.726562 C 147.621094 71.550781 147.375 71.441406 147.085938 71.398438 Z M 146.492188 74.351562 C 146.023438 74.3125 145.632812 74.160156 145.320312 73.898438 C 144.953125 73.585938 144.773438 73.164062 144.773438 72.632812 C 144.773438 72.101562 144.953125 71.679688 145.320312 71.367188 C 145.621094 71.109375 146.011719 70.957031 146.492188 70.914062 L 146.492188 70.445312 L 147.085938 70.445312 L 147.085938 70.914062 C 147.5625 70.957031 147.953125 71.109375 148.257812 71.367188 C 148.632812 71.679688 148.820312 72.101562 148.820312 72.632812 C 148.820312 73.164062 148.632812 73.585938 148.257812 73.898438 C 147.953125 74.160156 147.5625 74.316406 147.085938 74.367188 L 147.085938 74.820312 L 146.492188 74.820312 Z M 146.492188 74.351562 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(36.077881%,20.783997%,39.99939%);fill-opacity:1;" d="M 150.316406 73.355469 L 149.316406 74.917969 L 150.316406 74.917969 Z M 150.207031 73.011719 L 150.707031 73.011719 L 150.707031 74.917969 L 151.128906 74.917969 L 151.128906 75.246094 L 150.707031 75.246094 L 150.707031 75.933594 L 150.316406 75.933594 L 150.316406 75.246094 L 149.003906 75.246094 L 149.003906 74.871094 Z M 150.207031 73.011719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(36.077881%,20.783997%,39.99939%);fill-opacity:1;" d="M 152.957031 70.273438 C 152.695312 70.722656 152.503906 71.164062 152.378906 71.601562 C 152.253906 72.039062 152.191406 72.484375 152.191406 72.929688 C 152.191406 73.390625 152.253906 73.84375 152.378906 74.289062 C 152.503906 74.726562 152.695312 75.167969 152.957031 75.617188 L 152.488281 75.617188 C 152.195312 75.15625 151.976562 74.707031 151.832031 74.257812 C 151.683594 73.8125 151.613281 73.367188 151.613281 72.929688 C 151.613281 72.503906 151.683594 72.070312 151.832031 71.632812 C 151.976562 71.1875 152.195312 70.734375 152.488281 70.273438 Z M 152.957031 70.273438 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(36.077881%,20.783997%,39.99939%);fill-opacity:1;" d="M 154.359375 70.601562 L 154.359375 71.539062 L 155.46875 71.539062 L 155.46875 71.960938 L 154.359375 71.960938 L 154.359375 73.742188 C 154.359375 74.003906 154.394531 74.175781 154.46875 74.257812 C 154.539062 74.332031 154.691406 74.367188 154.921875 74.367188 L 155.46875 74.367188 L 155.46875 74.820312 L 154.921875 74.820312 C 154.503906 74.820312 154.21875 74.742188 154.0625 74.585938 C 153.90625 74.429688 153.828125 74.148438 153.828125 73.742188 L 153.828125 71.960938 L 153.421875 71.960938 L 153.421875 71.539062 L 153.828125 71.539062 L 153.828125 70.601562 Z M 154.359375 70.601562 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(36.077881%,20.783997%,39.99939%);fill-opacity:1;" d="M 155.929688 70.273438 L 156.398438 70.273438 C 156.6875 70.734375 156.90625 71.1875 157.054688 71.632812 C 157.199219 72.070312 157.273438 72.503906 157.273438 72.929688 C 157.273438 73.367188 157.199219 73.8125 157.054688 74.257812 C 156.90625 74.707031 156.6875 75.15625 156.398438 75.617188 L 155.929688 75.617188 C 156.1875 75.167969 156.382812 74.726562 156.507812 74.289062 C 156.632812 73.84375 156.695312 73.390625 156.695312 72.929688 C 156.695312 72.484375 156.632812 72.039062 156.507812 71.601562 C 156.382812 71.164062 156.1875 70.722656 155.929688 70.273438 Z M 155.929688 70.273438 "/>
<path style="fill:none;stroke-width:0.565685;stroke-linecap:round;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 37.019531 103.8125 L 39.617188 101.214844 " transform="matrix(1,-1,1,1,0,0)"/>
<path style="fill:none;stroke-width:0.565685;stroke-linecap:round;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 39.617188 103.8125 L 37.019531 101.214844 " transform="matrix(1,-1,1,1,0,0)"/>
<path style="fill:none;stroke-width:0.783069;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(30.587769%,60.391235%,2.352905%);stroke-opacity:1;stroke-miterlimit:4;" d="M 48.417969 71.910156 L 48.730469 71.910156 C 50.714844 71.910156 51.046875 62.175781 51.046875 60.5625 C 51.046875 58.929688 52.574219 58.976562 52.597656 60.5625 C 52.621094 62.144531 53.273438 71.882812 55.507812 71.882812 L 63.167969 71.882812 "/>
<path style="fill:none;stroke-width:0.783069;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(80.783081%,36.077881%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 50.03125 71.910156 L 52.113281 71.910156 C 54.097656 71.910156 54.429688 62.175781 54.429688 60.5625 C 54.429688 58.929688 55.953125 58.976562 55.976562 60.5625 C 56 62.144531 56.65625 71.882812 58.890625 71.882812 L 64.546875 71.882812 "/>
<path style="fill:none;stroke-width:0.783069;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(12.548828%,29.019165%,52.940369%);stroke-opacity:1;stroke-miterlimit:4;" d="M 53.394531 71.910156 L 55.476562 71.910156 C 57.460938 71.910156 57.792969 62.175781 57.792969 60.5625 C 57.792969 58.929688 59.316406 58.976562 59.339844 60.5625 C 59.363281 62.144531 60.019531 71.882812 62.253906 71.882812 L 65.761719 71.882812 "/>
<path style="fill:none;stroke-width:0.783069;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(36.077881%,20.783997%,39.99939%);stroke-opacity:1;stroke-miterlimit:4;" d="M 66.792969 71.910156 L 65.066406 71.910156 C 63.078125 71.910156 62.75 62.175781 62.75 60.5625 C 62.75 58.929688 61.222656 58.976562 61.199219 60.5625 C 61.175781 62.144531 60.519531 71.882812 58.285156 71.882812 L 50.128906 71.882812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 48.457031 55.582031 L 47.828125 56.519531 L 47.199219 57.453125 L 49.71875 57.453125 L 49.089844 56.519531 Z M 48.457031 55.582031 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 48.457031 71.96875 L 48.457031 57.042969 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 65.738281 71.90625 L 47.519531 71.90625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 66.996094 71.90625 L 66.054688 71.273438 L 65.125 70.644531 L 65.125 73.167969 L 66.054688 72.535156 Z M 66.996094 71.90625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(30.587769%,60.391235%,2.352905%);fill-opacity:1;" d="M 51.199219 73.632812 L 51.199219 74.085938 L 50.683594 74.085938 C 50.484375 74.085938 50.347656 74.128906 50.277344 74.210938 C 50.203125 74.285156 50.167969 74.421875 50.167969 74.617188 L 50.167969 74.914062 L 51.042969 74.914062 L 51.042969 75.335938 L 50.167969 75.335938 L 50.167969 78.195312 L 49.621094 78.195312 L 49.621094 75.335938 L 49.105469 75.335938 L 49.105469 74.914062 L 49.621094 74.914062 L 49.621094 74.679688 C 49.621094 74.316406 49.703125 74.050781 49.871094 73.882812 C 50.035156 73.71875 50.308594 73.632812 50.683594 73.632812 Z M 51.199219 73.632812 "/>
<g clip-path="url(#clip1)" clip-rule="nonzero">
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(30.587769%,60.391235%,2.352905%);fill-opacity:1;" d="M 51.417969 78.976562 L 52.058594 78.976562 L 52.058594 76.742188 L 51.355469 76.882812 L 51.355469 76.523438 L 52.058594 76.382812 L 52.449219 76.382812 L 52.449219 78.976562 L 53.089844 78.976562 L 53.089844 79.304688 L 51.417969 79.304688 Z M 51.417969 78.976562 "/>
</g>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 51.808594 73.085938 L 51.808594 70.859375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(80.783081%,36.077881%,0%);fill-opacity:1;" d="M 55.429688 73.632812 L 55.429688 74.085938 L 54.914062 74.085938 C 54.714844 74.085938 54.578125 74.128906 54.507812 74.210938 C 54.433594 74.285156 54.398438 74.421875 54.398438 74.617188 L 54.398438 74.914062 L 55.273438 74.914062 L 55.273438 75.335938 L 54.398438 75.335938 L 54.398438 78.195312 L 53.851562 78.195312 L 53.851562 75.335938 L 53.335938 75.335938 L 53.335938 74.914062 L 53.851562 74.914062 L 53.851562 74.679688 C 53.851562 74.316406 53.933594 74.050781 54.101562 73.882812 C 54.265625 73.71875 54.539062 73.632812 54.914062 73.632812 Z M 55.429688 73.632812 "/>
<g clip-path="url(#clip2)" clip-rule="nonzero">
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(80.783081%,36.077881%,0%);fill-opacity:1;" d="M 55.914062 78.976562 L 57.289062 78.976562 L 57.289062 79.304688 L 55.445312 79.304688 L 55.445312 78.976562 C 55.589844 78.820312 55.792969 78.613281 56.054688 78.351562 C 56.3125 78.09375 56.476562 77.921875 56.539062 77.835938 C 56.664062 77.703125 56.75 77.585938 56.804688 77.492188 C 56.855469 77.390625 56.882812 77.289062 56.882812 77.195312 C 56.882812 77.039062 56.824219 76.914062 56.710938 76.820312 C 56.605469 76.71875 56.464844 76.664062 56.289062 76.664062 C 56.164062 76.664062 56.03125 76.6875 55.898438 76.726562 C 55.761719 76.769531 55.617188 76.835938 55.460938 76.929688 L 55.460938 76.523438 C 55.617188 76.460938 55.761719 76.414062 55.898438 76.382812 C 56.042969 76.351562 56.171875 76.335938 56.289062 76.335938 C 56.589844 76.335938 56.828125 76.414062 57.007812 76.570312 C 57.183594 76.71875 57.273438 76.914062 57.273438 77.164062 C 57.273438 77.289062 57.25 77.40625 57.210938 77.507812 C 57.167969 77.613281 57.085938 77.738281 56.960938 77.882812 C 56.929688 77.925781 56.824219 78.039062 56.648438 78.226562 C 56.480469 78.40625 56.234375 78.65625 55.914062 78.976562 Z M 55.914062 78.976562 "/>
</g>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 55.140625 73.085938 L 55.140625 70.859375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(12.548828%,29.019165%,52.940369%);fill-opacity:1;" d="M 59.613281 73.632812 L 59.613281 74.085938 L 59.097656 74.085938 C 58.898438 74.085938 58.761719 74.128906 58.691406 74.210938 C 58.617188 74.285156 58.582031 74.421875 58.582031 74.617188 L 58.582031 74.914062 L 59.457031 74.914062 L 59.457031 75.335938 L 58.582031 75.335938 L 58.582031 78.195312 L 58.035156 78.195312 L 58.035156 75.335938 L 57.519531 75.335938 L 57.519531 74.914062 L 58.035156 74.914062 L 58.035156 74.679688 C 58.035156 74.316406 58.117188 74.050781 58.285156 73.882812 C 58.449219 73.71875 58.722656 73.632812 59.097656 73.632812 Z M 59.613281 73.632812 "/>
<g clip-path="url(#clip3)" clip-rule="nonzero">
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(12.548828%,29.019165%,52.940369%);fill-opacity:1;" d="M 60.953125 77.726562 C 61.140625 77.769531 61.285156 77.859375 61.390625 77.992188 C 61.492188 78.117188 61.546875 78.273438 61.546875 78.460938 C 61.546875 78.742188 61.445312 78.96875 61.25 79.132812 C 61.050781 79.289062 60.769531 79.367188 60.40625 79.367188 C 60.289062 79.367188 60.164062 79.351562 60.03125 79.320312 C 59.90625 79.300781 59.773438 79.265625 59.640625 79.210938 L 59.640625 78.835938 C 59.742188 78.898438 59.859375 78.945312 59.984375 78.976562 C 60.117188 79.007812 60.257812 79.023438 60.40625 79.023438 C 60.644531 79.023438 60.828125 78.976562 60.953125 78.882812 C 61.085938 78.789062 61.15625 78.648438 61.15625 78.460938 C 61.15625 78.285156 61.09375 78.148438 60.96875 78.054688 C 60.851562 77.960938 60.691406 77.914062 60.484375 77.914062 L 60.140625 77.914062 L 60.140625 77.585938 L 60.5 77.585938 C 60.6875 77.585938 60.832031 77.550781 60.9375 77.476562 C 61.039062 77.394531 61.09375 77.28125 61.09375 77.132812 C 61.09375 76.988281 61.039062 76.875 60.9375 76.789062 C 60.832031 76.707031 60.679688 76.664062 60.484375 76.664062 C 60.367188 76.664062 60.25 76.679688 60.125 76.710938 C 60 76.734375 59.863281 76.765625 59.71875 76.804688 L 59.71875 76.460938 C 59.875 76.421875 60.015625 76.390625 60.140625 76.367188 C 60.273438 76.347656 60.398438 76.335938 60.515625 76.335938 C 60.816406 76.335938 61.050781 76.40625 61.21875 76.539062 C 61.394531 76.675781 61.484375 76.859375 61.484375 77.085938 C 61.484375 77.253906 61.4375 77.394531 61.34375 77.507812 C 61.25 77.613281 61.117188 77.6875 60.953125 77.726562 Z M 60.953125 77.726562 "/>
</g>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 58.425781 73.085938 L 58.425781 70.859375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(36.077881%,20.783997%,39.99939%);fill-opacity:1;" d="M 63.785156 73.632812 L 63.785156 74.085938 L 63.269531 74.085938 C 63.070312 74.085938 62.933594 74.128906 62.863281 74.210938 C 62.789062 74.285156 62.753906 74.421875 62.753906 74.617188 L 62.753906 74.914062 L 63.628906 74.914062 L 63.628906 75.335938 L 62.753906 75.335938 L 62.753906 78.195312 L 62.207031 78.195312 L 62.207031 75.335938 L 61.691406 75.335938 L 61.691406 74.914062 L 62.207031 74.914062 L 62.207031 74.679688 C 62.207031 74.316406 62.289062 74.050781 62.457031 73.882812 C 62.621094 73.71875 62.894531 73.632812 63.269531 73.632812 Z M 63.785156 73.632812 "/>
<g clip-path="url(#clip4)" clip-rule="nonzero">
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(36.077881%,20.783997%,39.99939%);fill-opacity:1;" d="M 65.015625 76.726562 L 64.015625 78.289062 L 65.015625 78.289062 Z M 64.90625 76.382812 L 65.40625 76.382812 L 65.40625 78.289062 L 65.828125 78.289062 L 65.828125 78.617188 L 65.40625 78.617188 L 65.40625 79.304688 L 65.015625 79.304688 L 65.015625 78.617188 L 63.703125 78.617188 L 63.703125 78.242188 Z M 64.90625 76.382812 "/>
</g>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 62.007812 73.085938 L 62.007812 70.859375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 69.183594 74.285156 C 68.097656 74.285156 67.558594 73.515625 67.558594 71.972656 C 67.558594 71.359375 67.761719 70.636719 68.167969 69.800781 L 68.933594 69.800781 C 68.558594 70.636719 68.371094 71.363281 68.371094 71.988281 C 68.371094 73.113281 68.660156 73.675781 69.246094 73.675781 C 69.777344 73.675781 70.042969 72.980469 70.042969 71.582031 L 70.699219 71.582031 C 70.699219 72.980469 70.964844 73.675781 71.496094 73.675781 C 72.066406 73.675781 72.355469 73.113281 72.355469 71.988281 C 72.355469 71.363281 72.171875 70.636719 71.808594 69.800781 L 72.574219 69.800781 C 72.980469 70.636719 73.183594 71.359375 73.183594 71.972656 C 73.183594 73.515625 72.640625 74.285156 71.558594 74.285156 C 70.847656 74.285156 70.453125 73.894531 70.371094 73.113281 C 70.265625 73.894531 69.871094 74.285156 69.183594 74.285156 Z M 69.183594 74.285156 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.6;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 36.679688 64.386719 C 36.539062 66.601562 38.222656 68.507812 40.4375 68.648438 C 42.652344 68.789062 44.566406 67.105469 44.703125 64.890625 C 44.84375 62.675781 43.160156 60.769531 40.945312 60.628906 C 38.726562 60.492188 36.816406 62.171875 36.679688 64.386719 "/>
<path style="fill:none;stroke-width:0.6;stroke-linecap:round;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 38.855469 66.476562 L 42.527344 62.800781 "/>
<path style="fill:none;stroke-width:0.6;stroke-linecap:round;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 42.527344 66.476562 L 38.855469 62.800781 "/>
<path style="fill:none;stroke-width:0.6;stroke-linecap:round;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 40.691406 67.238281 L 40.691406 62.042969 "/>
<path style="fill:none;stroke-width:0.6;stroke-linecap:round;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 43.289062 64.640625 L 38.09375 64.640625 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:round;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 77.671875 65.617188 L 81.914062 61.378906 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:round;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 81.914062 65.617188 L 77.671875 61.378906 "/>
<path style="fill:none;stroke-width:2.25;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 39.050781 26.28125 L 39.050781 42.132812 "/>
<path style="fill:none;stroke-width:0.708661;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 33.042969 27.066406 L 37.074219 28.746094 "/>
<path style="fill:none;stroke-width:0.708661;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 33.042969 29.414062 L 37.074219 31.089844 "/>
<path style="fill:none;stroke-width:0.708661;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 33.042969 31.757812 L 37.074219 33.4375 "/>
<path style="fill:none;stroke-width:0.708661;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 33.042969 34.101562 L 37.074219 35.78125 "/>
<path style="fill:none;stroke-width:0.708661;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 33.042969 36.449219 L 37.074219 38.125 "/>
<path style="fill:none;stroke-width:0.708661;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 33.042969 38.792969 L 37.074219 40.472656 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 23.792969 43.53125 L 26.105469 43.53125 L 26.105469 43.9375 L 24.292969 43.9375 L 24.292969 45.015625 L 26.027344 45.015625 L 26.027344 45.4375 L 24.292969 45.4375 L 24.292969 46.75 L 26.152344 46.75 L 26.152344 47.171875 L 23.792969 47.171875 Z M 23.792969 43.53125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 26.941406 43.375 L 27.394531 43.375 L 27.394531 47.171875 L 26.941406 47.171875 Z M 26.941406 43.375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 30.671875 45.6875 L 30.671875 45.90625 L 28.609375 45.90625 C 28.628906 46.21875 28.722656 46.460938 28.890625 46.625 C 29.054688 46.78125 29.285156 46.859375 29.578125 46.859375 C 29.753906 46.859375 29.921875 46.839844 30.078125 46.796875 C 30.242188 46.757812 30.40625 46.695312 30.5625 46.609375 L 30.5625 47.03125 C 30.40625 47.105469 30.238281 47.15625 30.0625 47.1875 C 29.894531 47.226562 29.722656 47.25 29.546875 47.25 C 29.117188 47.25 28.773438 47.125 28.515625 46.875 C 28.265625 46.617188 28.140625 46.265625 28.140625 45.828125 C 28.140625 45.382812 28.257812 45.027344 28.5 44.765625 C 28.738281 44.507812 29.0625 44.375 29.46875 44.375 C 29.84375 44.375 30.132812 44.496094 30.34375 44.734375 C 30.5625 44.964844 30.671875 45.28125 30.671875 45.6875 Z M 30.21875 45.5625 C 30.21875 45.3125 30.148438 45.117188 30.015625 44.96875 C 29.878906 44.824219 29.703125 44.75 29.484375 44.75 C 29.234375 44.75 29.03125 44.824219 28.875 44.96875 C 28.726562 45.105469 28.644531 45.304688 28.625 45.5625 Z M 30.21875 45.5625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 33.371094 44.546875 L 33.371094 44.96875 C 33.246094 44.898438 33.113281 44.84375 32.980469 44.8125 C 32.855469 44.773438 32.730469 44.75 32.605469 44.75 C 32.3125 44.75 32.082031 44.84375 31.917969 45.03125 C 31.761719 45.21875 31.683594 45.480469 31.683594 45.8125 C 31.683594 46.148438 31.761719 46.40625 31.917969 46.59375 C 32.082031 46.773438 32.3125 46.859375 32.605469 46.859375 C 32.730469 46.859375 32.855469 46.84375 32.980469 46.8125 C 33.113281 46.773438 33.246094 46.71875 33.371094 46.65625 L 33.371094 47.0625 C 33.246094 47.125 33.113281 47.171875 32.980469 47.203125 C 32.84375 47.234375 32.703125 47.25 32.558594 47.25 C 32.140625 47.25 31.8125 47.121094 31.574219 46.859375 C 31.332031 46.601562 31.214844 46.25 31.214844 45.8125 C 31.214844 45.367188 31.332031 45.015625 31.574219 44.765625 C 31.824219 44.507812 32.160156 44.375 32.589844 44.375 C 32.722656 44.375 32.855469 44.390625 32.980469 44.421875 C 33.113281 44.445312 33.246094 44.484375 33.371094 44.546875 Z M 33.371094 44.546875 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 34.609375 43.65625 L 34.609375 44.4375 L 35.53125 44.4375 L 35.53125 44.78125 L 34.609375 44.78125 L 34.609375 46.265625 C 34.609375 46.496094 34.632812 46.640625 34.6875 46.703125 C 34.75 46.765625 34.875 46.796875 35.0625 46.796875 L 35.53125 46.796875 L 35.53125 47.171875 L 35.0625 47.171875 C 34.71875 47.171875 34.476562 47.109375 34.34375 46.984375 C 34.21875 46.851562 34.15625 46.609375 34.15625 46.265625 L 34.15625 44.78125 L 33.828125 44.78125 L 33.828125 44.4375 L 34.15625 44.4375 L 34.15625 43.65625 Z M 34.609375 43.65625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 37.714844 44.859375 C 37.660156 44.828125 37.605469 44.808594 37.542969 44.796875 C 37.480469 44.777344 37.410156 44.765625 37.339844 44.765625 C 37.089844 44.765625 36.894531 44.851562 36.761719 45.015625 C 36.625 45.183594 36.558594 45.421875 36.558594 45.734375 L 36.558594 47.171875 L 36.105469 47.171875 L 36.105469 44.4375 L 36.558594 44.4375 L 36.558594 44.859375 C 36.652344 44.695312 36.769531 44.574219 36.917969 44.5 C 37.074219 44.417969 37.261719 44.375 37.480469 44.375 C 37.511719 44.375 37.542969 44.382812 37.574219 44.390625 C 37.613281 44.390625 37.65625 44.390625 37.699219 44.390625 Z M 37.714844 44.859375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 39.136719 44.75 C 38.894531 44.75 38.703125 44.84375 38.558594 45.03125 C 38.421875 45.21875 38.355469 45.480469 38.355469 45.8125 C 38.355469 46.136719 38.421875 46.390625 38.558594 46.578125 C 38.703125 46.765625 38.894531 46.859375 39.136719 46.859375 C 39.375 46.859375 39.5625 46.765625 39.699219 46.578125 C 39.84375 46.390625 39.917969 46.136719 39.917969 45.8125 C 39.917969 45.492188 39.84375 45.234375 39.699219 45.046875 C 39.5625 44.851562 39.375 44.75 39.136719 44.75 Z M 39.136719 44.375 C 39.519531 44.375 39.824219 44.507812 40.042969 44.765625 C 40.269531 45.015625 40.386719 45.367188 40.386719 45.8125 C 40.386719 46.261719 40.269531 46.617188 40.042969 46.875 C 39.824219 47.125 39.519531 47.25 39.136719 47.25 C 38.738281 47.25 38.433594 47.125 38.214844 46.875 C 37.996094 46.617188 37.886719 46.261719 37.886719 45.8125 C 37.886719 45.367188 37.996094 45.015625 38.214844 44.765625 C 38.433594 44.507812 38.738281 44.375 39.136719 44.375 Z M 39.136719 44.375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 42.925781 44.859375 L 42.925781 43.375 L 43.378906 43.375 L 43.378906 47.171875 L 42.925781 47.171875 L 42.925781 46.765625 C 42.832031 46.921875 42.710938 47.042969 42.566406 47.125 C 42.429688 47.207031 42.257812 47.25 42.050781 47.25 C 41.726562 47.25 41.460938 47.121094 41.253906 46.859375 C 41.042969 46.589844 40.941406 46.242188 40.941406 45.8125 C 40.941406 45.375 41.042969 45.027344 41.253906 44.765625 C 41.460938 44.507812 41.726562 44.375 42.050781 44.375 C 42.257812 44.375 42.429688 44.417969 42.566406 44.5 C 42.710938 44.574219 42.832031 44.695312 42.925781 44.859375 Z M 41.394531 45.8125 C 41.394531 46.136719 41.460938 46.390625 41.597656 46.578125 C 41.730469 46.765625 41.917969 46.859375 42.160156 46.859375 C 42.398438 46.859375 42.585938 46.765625 42.722656 46.578125 C 42.855469 46.390625 42.925781 46.136719 42.925781 45.8125 C 42.925781 45.480469 42.855469 45.21875 42.722656 45.03125 C 42.585938 44.84375 42.398438 44.75 42.160156 44.75 C 41.917969 44.75 41.730469 44.84375 41.597656 45.03125 C 41.460938 45.21875 41.394531 45.480469 41.394531 45.8125 Z M 41.394531 45.8125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 46.648438 45.6875 L 46.648438 45.90625 L 44.585938 45.90625 C 44.605469 46.21875 44.699219 46.460938 44.867188 46.625 C 45.03125 46.78125 45.261719 46.859375 45.554688 46.859375 C 45.730469 46.859375 45.898438 46.839844 46.054688 46.796875 C 46.21875 46.757812 46.382812 46.695312 46.539062 46.609375 L 46.539062 47.03125 C 46.382812 47.105469 46.214844 47.15625 46.039062 47.1875 C 45.871094 47.226562 45.699219 47.25 45.523438 47.25 C 45.09375 47.25 44.75 47.125 44.492188 46.875 C 44.242188 46.617188 44.117188 46.265625 44.117188 45.828125 C 44.117188 45.382812 44.234375 45.027344 44.476562 44.765625 C 44.714844 44.507812 45.039062 44.375 45.445312 44.375 C 45.820312 44.375 46.109375 44.496094 46.320312 44.734375 C 46.539062 44.964844 46.648438 45.28125 46.648438 45.6875 Z M 46.195312 45.5625 C 46.195312 45.3125 46.125 45.117188 45.992188 44.96875 C 45.855469 44.824219 45.679688 44.75 45.460938 44.75 C 45.210938 44.75 45.007812 44.824219 44.851562 44.96875 C 44.703125 45.105469 44.621094 45.304688 44.601562 45.5625 Z M 46.195312 45.5625 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 92.667969 41.109375 L 111.402344 41.054688 L 111.402344 27.113281 L 92.667969 27.167969 Z M 92.667969 41.109375 "/>
<path style="fill:none;stroke-width:0.6;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(53.33252%,54.116821%,52.156067%);stroke-opacity:1;stroke-miterlimit:4;" d="M 95.699219 38.53125 L 95.699219 29.78125 "/>
<path style="fill:none;stroke-width:0.6;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(53.33252%,54.116821%,52.156067%);stroke-opacity:1;stroke-miterlimit:4;" d="M 104.289062 38.65625 L 94.851562 38.65625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(53.33252%,54.116821%,52.156067%);fill-opacity:1;" d="M 95.699219 28.582031 L 95.128906 29.429688 L 94.5625 30.277344 L 96.84375 30.277344 L 96.273438 29.429688 Z M 95.699219 28.582031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(53.33252%,54.116821%,52.156067%);fill-opacity:1;" d="M 105.425781 38.65625 L 103.730469 37.515625 L 103.730469 39.800781 L 104.578125 39.226562 Z M 105.425781 38.65625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 100.453125 34.097656 L 101.25 34.097656 L 101.25 31.316406 L 100.375 31.503906 L 100.375 31.050781 L 101.25 30.878906 L 101.75 30.878906 L 101.75 34.097656 L 102.546875 34.097656 L 102.546875 34.519531 L 100.453125 34.519531 Z M 100.453125 34.097656 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 104.277344 30.878906 L 104.699219 30.878906 L 103.433594 34.988281 L 103.011719 34.988281 Z M 104.277344 30.878906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 106.921875 31.863281 L 106.921875 32.285156 C 106.796875 32.222656 106.660156 32.175781 106.515625 32.144531 C 106.378906 32.113281 106.238281 32.097656 106.09375 32.097656 C 105.875 32.097656 105.707031 32.136719 105.59375 32.207031 C 105.476562 32.269531 105.421875 32.371094 105.421875 32.503906 C 105.421875 32.609375 105.460938 32.691406 105.546875 32.753906 C 105.628906 32.808594 105.789062 32.863281 106.03125 32.925781 L 106.1875 32.957031 C 106.5 33.019531 106.722656 33.113281 106.859375 33.238281 C 106.992188 33.363281 107.0625 33.542969 107.0625 33.769531 C 107.0625 34.019531 106.960938 34.222656 106.765625 34.378906 C 106.566406 34.523438 106.289062 34.597656 105.9375 34.597656 C 105.789062 34.597656 105.632812 34.582031 105.46875 34.550781 C 105.3125 34.519531 105.144531 34.480469 104.96875 34.425781 L 104.96875 33.957031 C 105.132812 34.042969 105.296875 34.105469 105.453125 34.144531 C 105.617188 34.1875 105.78125 34.207031 105.9375 34.207031 C 106.15625 34.207031 106.320312 34.175781 106.4375 34.113281 C 106.550781 34.042969 106.609375 33.9375 106.609375 33.800781 C 106.609375 33.675781 106.566406 33.582031 106.484375 33.519531 C 106.398438 33.457031 106.21875 33.394531 105.9375 33.332031 L 105.78125 33.300781 C 105.5 33.238281 105.296875 33.152344 105.171875 33.035156 C 105.054688 32.910156 105 32.738281 105 32.519531 C 105 32.269531 105.085938 32.078125 105.265625 31.941406 C 105.453125 31.796875 105.710938 31.722656 106.046875 31.722656 C 106.210938 31.722656 106.367188 31.734375 106.515625 31.753906 C 106.660156 31.777344 106.796875 31.8125 106.921875 31.863281 Z M 106.921875 31.863281 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 88.523438 60.515625 L 89.320312 60.515625 L 89.320312 62.90625 L 92.179688 62.90625 L 92.179688 60.515625 L 92.976562 60.515625 L 92.976562 66.34375 L 92.179688 66.34375 L 92.179688 63.5625 L 89.320312 63.5625 L 89.320312 66.34375 L 88.523438 66.34375 Z M 88.523438 60.515625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 96.242188 60.265625 C 95.886719 60.871094 95.625 61.464844 95.460938 62.046875 C 95.292969 62.632812 95.210938 63.226562 95.210938 63.828125 C 95.210938 64.433594 95.292969 65.03125 95.460938 65.625 C 95.636719 66.210938 95.898438 66.800781 96.242188 67.40625 L 95.617188 67.40625 C 95.21875 66.789062 94.921875 66.1875 94.726562 65.59375 C 94.539062 65 94.445312 64.414062 94.445312 63.828125 C 94.445312 63.246094 94.539062 62.664062 94.726562 62.078125 C 94.921875 61.484375 95.21875 60.882812 95.617188 60.265625 Z M 96.242188 60.265625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 99.039062 66.453125 C 97.953125 66.453125 97.414062 65.683594 97.414062 64.140625 C 97.414062 63.527344 97.617188 62.804688 98.023438 61.96875 L 98.789062 61.96875 C 98.414062 62.804688 98.226562 63.53125 98.226562 64.15625 C 98.226562 65.28125 98.515625 65.84375 99.101562 65.84375 C 99.632812 65.84375 99.898438 65.148438 99.898438 63.75 L 100.554688 63.75 C 100.554688 65.148438 100.820312 65.84375 101.351562 65.84375 C 101.921875 65.84375 102.210938 65.28125 102.210938 64.15625 C 102.210938 63.53125 102.027344 62.804688 101.664062 61.96875 L 102.429688 61.96875 C 102.835938 62.804688 103.039062 63.527344 103.039062 64.140625 C 103.039062 65.683594 102.496094 66.453125 101.414062 66.453125 C 100.703125 66.453125 100.308594 66.0625 100.226562 65.28125 C 100.121094 66.0625 99.726562 66.453125 99.039062 66.453125 Z M 99.039062 66.453125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 104.210938 60.265625 L 104.835938 60.265625 C 105.230469 60.882812 105.523438 61.484375 105.710938 62.078125 C 105.90625 62.664062 106.007812 63.246094 106.007812 63.828125 C 106.007812 64.414062 105.90625 65 105.710938 65.59375 C 105.523438 66.1875 105.230469 66.789062 104.835938 67.40625 L 104.210938 67.40625 C 104.554688 66.800781 104.808594 66.210938 104.976562 65.625 C 105.152344 65.03125 105.242188 64.433594 105.242188 63.828125 C 105.242188 63.226562 105.152344 62.632812 104.976562 62.046875 C 104.808594 61.464844 104.554688 60.871094 104.210938 60.265625 Z M 104.210938 60.265625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 44.289062 5.394531 L 44.289062 9.925781 L 45.242188 9.925781 C 46.042969 9.925781 46.632812 9.746094 47.007812 9.378906 C 47.382812 9.015625 47.570312 8.441406 47.570312 7.660156 C 47.570312 6.878906 47.382812 6.308594 47.007812 5.941406 C 46.632812 5.578125 46.042969 5.394531 45.242188 5.394531 Z M 43.492188 4.753906 L 45.117188 4.753906 C 46.25 4.753906 47.078125 4.988281 47.601562 5.457031 C 48.132812 5.925781 48.398438 6.660156 48.398438 7.660156 C 48.398438 8.660156 48.132812 9.402344 47.601562 9.878906 C 47.070312 10.347656 46.242188 10.582031 45.117188 10.582031 L 43.492188 10.582031 Z M 43.492188 4.753906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 50.445312 5.394531 L 50.445312 9.925781 L 51.398438 9.925781 C 52.199219 9.925781 52.789062 9.746094 53.164062 9.378906 C 53.539062 9.015625 53.726562 8.441406 53.726562 7.660156 C 53.726562 6.878906 53.539062 6.308594 53.164062 5.941406 C 52.789062 5.578125 52.199219 5.394531 51.398438 5.394531 Z M 49.648438 4.753906 L 51.273438 4.753906 C 52.40625 4.753906 53.234375 4.988281 53.757812 5.457031 C 54.289062 5.925781 54.554688 6.660156 54.554688 7.660156 C 54.554688 8.660156 54.289062 9.402344 53.757812 9.878906 C 53.226562 10.347656 52.398438 10.582031 51.273438 10.582031 L 49.648438 10.582031 Z M 49.648438 4.753906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 55.289062 4.753906 L 56.085938 4.753906 L 57.320312 9.675781 L 58.539062 4.753906 L 59.429688 4.753906 L 60.648438 9.675781 L 61.867188 4.753906 L 62.679688 4.753906 L 61.210938 10.582031 L 60.210938 10.582031 L 58.992188 5.519531 L 57.742188 10.582031 L 56.757812 10.582031 Z M 55.289062 4.753906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 67.210938 4.941406 L 67.210938 5.707031 C 66.90625 5.5625 66.621094 5.457031 66.351562 5.394531 C 66.089844 5.324219 65.839844 5.285156 65.601562 5.285156 C 65.164062 5.285156 64.828125 5.371094 64.601562 5.535156 C 64.371094 5.703125 64.257812 5.9375 64.257812 6.238281 C 64.257812 6.5 64.328125 6.699219 64.476562 6.832031 C 64.632812 6.957031 64.929688 7.0625 65.367188 7.144531 L 65.835938 7.238281 C 66.429688 7.355469 66.867188 7.550781 67.148438 7.832031 C 67.429688 8.113281 67.570312 8.496094 67.570312 8.972656 C 67.570312 9.535156 67.375 9.964844 66.992188 10.253906 C 66.617188 10.546875 66.0625 10.691406 65.335938 10.691406 C 65.054688 10.691406 64.757812 10.660156 64.445312 10.597656 C 64.132812 10.535156 63.808594 10.441406 63.476562 10.316406 L 63.476562 9.503906 C 63.796875 9.691406 64.109375 9.832031 64.414062 9.925781 C 64.726562 10.011719 65.03125 10.050781 65.335938 10.050781 C 65.78125 10.050781 66.125 9.964844 66.367188 9.785156 C 66.617188 9.609375 66.742188 9.359375 66.742188 9.035156 C 66.742188 8.746094 66.652344 8.519531 66.476562 8.363281 C 66.296875 8.199219 66.011719 8.074219 65.617188 7.988281 L 65.132812 7.894531 C 64.539062 7.78125 64.109375 7.597656 63.851562 7.347656 C 63.589844 7.097656 63.460938 6.75 63.460938 6.300781 C 63.460938 5.792969 63.640625 5.390625 64.007812 5.097656 C 64.371094 4.796875 64.871094 4.644531 65.507812 4.644531 C 65.777344 4.644531 66.054688 4.671875 66.335938 4.722656 C 66.625 4.765625 66.917969 4.839844 67.210938 4.941406 Z M 67.210938 4.941406 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 94.628906 31.007812 L 102.429688 39.507812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 95.734375 26.246094 L 96.566406 25.167969 L 97.398438 24.09375 L 94.066406 24.09375 L 94.898438 25.167969 Z M 95.734375 26.246094 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 99.03125 21.265625 C 99.132812 21.296875 99.234375 21.375 99.328125 21.5 C 99.429688 21.617188 99.535156 21.773438 99.640625 21.96875 L 100.140625 22.96875 L 99.609375 22.96875 L 99.140625 22.03125 C 99.023438 21.792969 98.910156 21.632812 98.796875 21.546875 C 98.679688 21.464844 98.523438 21.421875 98.328125 21.421875 L 97.796875 21.421875 L 97.796875 22.96875 L 97.296875 22.96875 L 97.296875 19.328125 L 98.421875 19.328125 C 98.835938 19.328125 99.144531 19.417969 99.34375 19.59375 C 99.550781 19.761719 99.65625 20.023438 99.65625 20.375 C 99.65625 20.605469 99.601562 20.796875 99.5 20.953125 C 99.394531 21.101562 99.238281 21.203125 99.03125 21.265625 Z M 97.796875 19.734375 L 97.796875 21.015625 L 98.421875 21.015625 C 98.648438 21.015625 98.828125 20.964844 98.953125 20.859375 C 99.078125 20.746094 99.140625 20.585938 99.140625 20.375 C 99.140625 20.15625 99.078125 19.996094 98.953125 19.890625 C 98.828125 19.789062 98.648438 19.734375 98.421875 19.734375 Z M 97.796875 19.734375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 102.960938 19.4375 L 102.960938 19.921875 C 102.773438 19.839844 102.59375 19.777344 102.429688 19.734375 C 102.261719 19.683594 102.105469 19.65625 101.960938 19.65625 C 101.6875 19.65625 101.480469 19.710938 101.335938 19.8125 C 101.1875 19.917969 101.117188 20.070312 101.117188 20.265625 C 101.117188 20.421875 101.164062 20.542969 101.257812 20.625 C 101.351562 20.710938 101.53125 20.777344 101.804688 20.828125 L 102.101562 20.890625 C 102.476562 20.953125 102.746094 21.074219 102.914062 21.25 C 103.089844 21.429688 103.179688 21.667969 103.179688 21.96875 C 103.179688 22.324219 103.058594 22.59375 102.820312 22.78125 C 102.589844 22.960938 102.246094 23.046875 101.789062 23.046875 C 101.609375 23.046875 101.421875 23.023438 101.226562 22.984375 C 101.039062 22.945312 100.839844 22.886719 100.632812 22.8125 L 100.632812 22.296875 C 100.828125 22.414062 101.023438 22.5 101.210938 22.5625 C 101.40625 22.617188 101.601562 22.640625 101.789062 22.640625 C 102.070312 22.640625 102.28125 22.589844 102.429688 22.484375 C 102.585938 22.371094 102.664062 22.210938 102.664062 22 C 102.664062 21.824219 102.605469 21.683594 102.492188 21.578125 C 102.386719 21.476562 102.210938 21.402344 101.960938 21.359375 L 101.664062 21.296875 C 101.296875 21.226562 101.03125 21.109375 100.867188 20.953125 C 100.699219 20.796875 100.617188 20.578125 100.617188 20.296875 C 100.617188 19.976562 100.730469 19.71875 100.960938 19.53125 C 101.1875 19.34375 101.5 19.25 101.898438 19.25 C 102.0625 19.25 102.234375 19.265625 102.414062 19.296875 C 102.589844 19.328125 102.773438 19.375 102.960938 19.4375 Z M 102.960938 19.4375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 103.445312 19.328125 L 106.523438 19.328125 L 106.523438 19.734375 L 105.242188 19.734375 L 105.242188 22.96875 L 104.742188 22.96875 L 104.742188 19.734375 L 103.445312 19.734375 Z M 103.445312 19.328125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 96.894531 42.628906 L 97.394531 42.628906 L 97.394531 44.113281 L 99.191406 44.113281 L 99.191406 42.628906 L 99.675781 42.628906 L 99.675781 46.269531 L 99.191406 46.269531 L 99.191406 44.535156 L 97.394531 44.535156 L 97.394531 46.269531 L 96.894531 46.269531 Z M 96.894531 42.628906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 101.71875 42.472656 C 101.5 42.847656 101.335938 43.21875 101.234375 43.582031 C 101.128906 43.949219 101.078125 44.324219 101.078125 44.707031 C 101.078125 45.082031 101.128906 45.453125 101.234375 45.816406 C 101.335938 46.183594 101.5 46.550781 101.71875 46.925781 L 101.328125 46.925781 C 101.085938 46.539062 100.90625 46.167969 100.78125 45.800781 C 100.664062 45.4375 100.609375 45.074219 100.609375 44.707031 C 100.609375 44.34375 100.664062 43.980469 100.78125 43.613281 C 100.90625 43.238281 101.085938 42.859375 101.328125 42.472656 Z M 101.71875 42.472656 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 103.46875 46.347656 C 102.789062 46.347656 102.453125 45.863281 102.453125 44.894531 C 102.453125 44.511719 102.578125 44.058594 102.828125 43.535156 L 103.3125 43.535156 C 103.082031 44.058594 102.96875 44.511719 102.96875 44.894531 C 102.96875 45.605469 103.148438 45.957031 103.515625 45.957031 C 103.835938 45.957031 104 45.519531 104 44.644531 L 104.421875 44.644531 C 104.421875 45.519531 104.585938 45.957031 104.921875 45.957031 C 105.273438 45.957031 105.453125 45.605469 105.453125 44.894531 C 105.453125 44.511719 105.335938 44.058594 105.109375 43.535156 L 105.59375 43.535156 C 105.84375 44.058594 105.96875 44.511719 105.96875 44.894531 C 105.96875 45.863281 105.628906 46.347656 104.953125 46.347656 C 104.515625 46.347656 104.269531 46.105469 104.21875 45.613281 C 104.144531 46.105469 103.894531 46.347656 103.46875 46.347656 Z M 103.46875 46.347656 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 106.710938 42.472656 L 107.101562 42.472656 C 107.339844 42.859375 107.515625 43.238281 107.632812 43.613281 C 107.757812 43.980469 107.820312 44.34375 107.820312 44.707031 C 107.820312 45.074219 107.757812 45.4375 107.632812 45.800781 C 107.515625 46.167969 107.339844 46.539062 107.101562 46.925781 L 106.710938 46.925781 C 106.917969 46.550781 107.074219 46.183594 107.179688 45.816406 C 107.292969 45.453125 107.351562 45.082031 107.351562 44.707031 C 107.351562 44.324219 107.292969 43.949219 107.179688 43.582031 C 107.074219 43.21875 106.917969 42.847656 106.710938 42.472656 Z M 106.710938 42.472656 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 6.269531 19.558594 L 6.269531 20.074219 C 6.101562 19.917969 5.925781 19.804688 5.738281 19.730469 C 5.550781 19.648438 5.351562 19.605469 5.144531 19.605469 C 4.726562 19.605469 4.402344 19.738281 4.175781 19.996094 C 3.957031 20.246094 3.847656 20.617188 3.847656 21.105469 C 3.847656 21.585938 3.957031 21.957031 4.175781 22.214844 C 4.402344 22.464844 4.726562 22.589844 5.144531 22.589844 C 5.351562 22.589844 5.550781 22.554688 5.738281 22.480469 C 5.925781 22.398438 6.101562 22.277344 6.269531 22.121094 L 6.269531 22.636719 C 6.101562 22.753906 5.917969 22.839844 5.722656 22.902344 C 5.535156 22.964844 5.332031 22.996094 5.113281 22.996094 C 4.558594 22.996094 4.121094 22.832031 3.800781 22.496094 C 3.488281 22.152344 3.332031 21.691406 3.332031 21.105469 C 3.332031 20.511719 3.488281 20.050781 3.800781 19.714844 C 4.121094 19.371094 4.558594 19.199219 5.113281 19.199219 C 5.332031 19.199219 5.535156 19.230469 5.722656 19.292969 C 5.917969 19.355469 6.101562 19.445312 6.269531 19.558594 Z M 6.269531 19.558594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 8.515625 19.605469 C 8.160156 19.605469 7.875 19.742188 7.65625 20.011719 C 7.445312 20.273438 7.34375 20.636719 7.34375 21.105469 C 7.34375 21.566406 7.445312 21.929688 7.65625 22.199219 C 7.875 22.460938 8.160156 22.589844 8.515625 22.589844 C 8.867188 22.589844 9.148438 22.460938 9.359375 22.199219 C 9.578125 21.929688 9.6875 21.566406 9.6875 21.105469 C 9.6875 20.636719 9.578125 20.273438 9.359375 20.011719 C 9.148438 19.742188 8.867188 19.605469 8.515625 19.605469 Z M 8.515625 19.199219 C 9.023438 19.199219 9.429688 19.371094 9.734375 19.714844 C 10.046875 20.058594 10.203125 20.523438 10.203125 21.105469 C 10.203125 21.679688 10.046875 22.136719 9.734375 22.480469 C 9.429688 22.824219 9.023438 22.996094 8.515625 22.996094 C 8.003906 22.996094 7.59375 22.824219 7.28125 22.480469 C 6.976562 22.136719 6.828125 21.679688 6.828125 21.105469 C 6.828125 20.523438 6.976562 20.058594 7.28125 19.714844 C 7.59375 19.371094 8.003906 19.199219 8.515625 19.199219 Z M 8.515625 19.199219 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 12.703125 21.214844 C 12.804688 21.246094 12.90625 21.324219 13 21.449219 C 13.101562 21.566406 13.207031 21.722656 13.3125 21.917969 L 13.8125 22.917969 L 13.28125 22.917969 L 12.8125 21.980469 C 12.695312 21.742188 12.582031 21.582031 12.46875 21.496094 C 12.351562 21.414062 12.195312 21.371094 12 21.371094 L 11.46875 21.371094 L 11.46875 22.917969 L 10.96875 22.917969 L 10.96875 19.277344 L 12.09375 19.277344 C 12.507812 19.277344 12.816406 19.367188 13.015625 19.542969 C 13.222656 19.710938 13.328125 19.972656 13.328125 20.324219 C 13.328125 20.554688 13.273438 20.746094 13.171875 20.902344 C 13.066406 21.050781 12.910156 21.152344 12.703125 21.214844 Z M 11.46875 19.683594 L 11.46875 20.964844 L 12.09375 20.964844 C 12.320312 20.964844 12.5 20.914062 12.625 20.808594 C 12.75 20.695312 12.8125 20.535156 12.8125 20.324219 C 12.8125 20.105469 12.75 19.945312 12.625 19.839844 C 12.5 19.738281 12.320312 19.683594 12.09375 19.683594 Z M 11.46875 19.683594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 13.582031 19.277344 L 16.660156 19.277344 L 16.660156 19.683594 L 15.378906 19.683594 L 15.378906 22.917969 L 14.878906 22.917969 L 14.878906 19.683594 L 13.582031 19.683594 Z M 13.582031 19.277344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 17.140625 19.277344 L 17.640625 19.277344 L 17.640625 22.917969 L 17.140625 22.917969 Z M 17.140625 19.277344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 21.347656 19.558594 L 21.347656 20.074219 C 21.179688 19.917969 21.003906 19.804688 20.816406 19.730469 C 20.628906 19.648438 20.429688 19.605469 20.222656 19.605469 C 19.804688 19.605469 19.480469 19.738281 19.253906 19.996094 C 19.035156 20.246094 18.925781 20.617188 18.925781 21.105469 C 18.925781 21.585938 19.035156 21.957031 19.253906 22.214844 C 19.480469 22.464844 19.804688 22.589844 20.222656 22.589844 C 20.429688 22.589844 20.628906 22.554688 20.816406 22.480469 C 21.003906 22.398438 21.179688 22.277344 21.347656 22.121094 L 21.347656 22.636719 C 21.179688 22.753906 20.996094 22.839844 20.800781 22.902344 C 20.613281 22.964844 20.410156 22.996094 20.191406 22.996094 C 19.636719 22.996094 19.199219 22.832031 18.878906 22.496094 C 18.566406 22.152344 18.410156 21.691406 18.410156 21.105469 C 18.410156 20.511719 18.566406 20.050781 18.878906 19.714844 C 19.199219 19.371094 19.636719 19.199219 20.191406 19.199219 C 20.410156 19.199219 20.613281 19.230469 20.800781 19.292969 C 20.996094 19.355469 21.179688 19.445312 21.347656 19.558594 Z M 21.347656 19.558594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 23.328125 19.761719 L 22.671875 21.574219 L 24 21.574219 Z M 23.0625 19.277344 L 23.609375 19.277344 L 25 22.917969 L 24.484375 22.917969 L 24.15625 21.980469 L 22.515625 21.980469 L 22.1875 22.917969 L 21.671875 22.917969 Z M 23.0625 19.277344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 25.527344 19.277344 L 26.027344 19.277344 L 26.027344 22.496094 L 27.808594 22.496094 L 27.808594 22.917969 L 25.527344 22.917969 Z M 25.527344 19.277344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 1.449219 25.03125 L 1.949219 25.03125 L 1.949219 28.25 L 3.730469 28.25 L 3.730469 28.671875 L 1.449219 28.671875 Z M 1.449219 25.03125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 4.230469 25.03125 L 6.324219 25.03125 L 6.324219 25.4375 L 4.730469 25.4375 L 4.730469 26.515625 L 6.167969 26.515625 L 6.167969 26.9375 L 4.730469 26.9375 L 4.730469 28.671875 L 4.230469 28.671875 Z M 4.230469 25.03125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 7.613281 25.4375 L 7.613281 26.796875 L 8.238281 26.796875 C 8.464844 26.796875 8.644531 26.742188 8.769531 26.625 C 8.894531 26.5 8.957031 26.328125 8.957031 26.109375 C 8.957031 25.890625 8.894531 25.726562 8.769531 25.609375 C 8.644531 25.496094 8.464844 25.4375 8.238281 25.4375 Z M 7.113281 25.03125 L 8.238281 25.03125 C 8.644531 25.03125 8.949219 25.125 9.160156 25.3125 C 9.367188 25.492188 9.472656 25.757812 9.472656 26.109375 C 9.472656 26.476562 9.367188 26.75 9.160156 26.9375 C 8.949219 27.117188 8.644531 27.203125 8.238281 27.203125 L 7.613281 27.203125 L 7.613281 28.671875 L 7.113281 28.671875 Z M 7.113281 25.03125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 13.910156 25.140625 L 13.910156 25.625 C 13.722656 25.542969 13.542969 25.480469 13.378906 25.4375 C 13.210938 25.386719 13.054688 25.359375 12.910156 25.359375 C 12.636719 25.359375 12.429688 25.414062 12.285156 25.515625 C 12.136719 25.621094 12.066406 25.773438 12.066406 25.96875 C 12.066406 26.125 12.113281 26.246094 12.207031 26.328125 C 12.300781 26.414062 12.480469 26.480469 12.753906 26.53125 L 13.050781 26.59375 C 13.425781 26.65625 13.695312 26.777344 13.863281 26.953125 C 14.039062 27.132812 14.128906 27.371094 14.128906 27.671875 C 14.128906 28.027344 14.007812 28.296875 13.769531 28.484375 C 13.539062 28.664062 13.195312 28.75 12.738281 28.75 C 12.558594 28.75 12.371094 28.726562 12.175781 28.6875 C 11.988281 28.648438 11.789062 28.589844 11.582031 28.515625 L 11.582031 28 C 11.777344 28.117188 11.972656 28.203125 12.160156 28.265625 C 12.355469 28.320312 12.550781 28.34375 12.738281 28.34375 C 13.019531 28.34375 13.230469 28.292969 13.378906 28.1875 C 13.535156 28.074219 13.613281 27.914062 13.613281 27.703125 C 13.613281 27.527344 13.554688 27.386719 13.441406 27.28125 C 13.335938 27.179688 13.160156 27.105469 12.910156 27.0625 L 12.613281 27 C 12.246094 26.929688 11.980469 26.8125 11.816406 26.65625 C 11.648438 26.5 11.566406 26.28125 11.566406 26 C 11.566406 25.679688 11.679688 25.421875 11.910156 25.234375 C 12.136719 25.046875 12.449219 24.953125 12.847656 24.953125 C 13.011719 24.953125 13.183594 24.96875 13.363281 25 C 13.539062 25.03125 13.722656 25.078125 13.910156 25.140625 Z M 13.910156 25.140625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 14.894531 25.03125 L 15.394531 25.03125 L 15.394531 28.671875 L 14.894531 28.671875 Z M 14.894531 25.03125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 18.855469 28.15625 L 18.855469 27.171875 L 18.058594 27.171875 L 18.058594 26.765625 L 19.355469 26.765625 L 19.355469 28.328125 C 19.15625 28.464844 18.941406 28.570312 18.714844 28.640625 C 18.484375 28.710938 18.238281 28.75 17.980469 28.75 C 17.417969 28.75 16.972656 28.585938 16.652344 28.25 C 16.328125 27.917969 16.167969 27.453125 16.167969 26.859375 C 16.167969 26.257812 16.328125 25.789062 16.652344 25.453125 C 16.972656 25.121094 17.417969 24.953125 17.980469 24.953125 C 18.21875 24.953125 18.441406 24.984375 18.652344 25.046875 C 18.871094 25.109375 19.074219 25.199219 19.261719 25.3125 L 19.261719 25.828125 C 19.074219 25.671875 18.875 25.558594 18.667969 25.484375 C 18.46875 25.402344 18.253906 25.359375 18.027344 25.359375 C 17.578125 25.359375 17.238281 25.484375 17.011719 25.734375 C 16.792969 25.984375 16.683594 26.359375 16.683594 26.859375 C 16.683594 27.351562 16.792969 27.71875 17.011719 27.96875 C 17.238281 28.21875 17.578125 28.34375 18.027344 28.34375 C 18.203125 28.34375 18.359375 28.328125 18.496094 28.296875 C 18.628906 28.265625 18.75 28.21875 18.855469 28.15625 Z M 18.855469 28.15625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 20.246094 25.03125 L 20.917969 25.03125 L 22.527344 28.078125 L 22.527344 25.03125 L 23.011719 25.03125 L 23.011719 28.671875 L 22.339844 28.671875 L 20.730469 25.625 L 20.730469 28.671875 L 20.246094 28.671875 Z M 20.246094 25.03125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 25.207031 25.515625 L 24.550781 27.328125 L 25.878906 27.328125 Z M 24.941406 25.03125 L 25.488281 25.03125 L 26.878906 28.671875 L 26.363281 28.671875 L 26.035156 27.734375 L 24.394531 27.734375 L 24.066406 28.671875 L 23.550781 28.671875 Z M 24.941406 25.03125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 27.40625 25.03125 L 27.90625 25.03125 L 27.90625 28.25 L 29.6875 28.25 L 29.6875 28.671875 L 27.40625 28.671875 Z M 27.40625 25.03125 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 13.238281 34.207031 L 26.945312 34.207031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 30.460938 34.253906 L 27.675781 32.957031 L 24.894531 31.660156 L 24.894531 36.851562 L 27.675781 35.550781 Z M 30.460938 34.253906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 137.394531 25.902344 L 137.394531 28.730469 L 137.988281 28.730469 C 138.488281 28.730469 138.851562 28.617188 139.082031 28.386719 C 139.320312 28.160156 139.441406 27.800781 139.441406 27.308594 C 139.441406 26.820312 139.320312 26.464844 139.082031 26.246094 C 138.851562 26.019531 138.488281 25.902344 137.988281 25.902344 Z M 136.894531 25.496094 L 137.910156 25.496094 C 138.617188 25.496094 139.136719 25.644531 139.472656 25.933594 C 139.804688 26.226562 139.972656 26.683594 139.972656 27.308594 C 139.972656 27.933594 139.804688 28.398438 139.472656 28.699219 C 139.136719 28.992188 138.617188 29.136719 137.910156 29.136719 L 136.894531 29.136719 Z M 136.894531 25.496094 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 140.742188 25.496094 L 143.054688 25.496094 L 143.054688 25.902344 L 141.242188 25.902344 L 141.242188 26.980469 L 142.976562 26.980469 L 142.976562 27.402344 L 141.242188 27.402344 L 141.242188 28.714844 L 143.101562 28.714844 L 143.101562 29.136719 L 140.742188 29.136719 Z M 140.742188 25.496094 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 146.640625 25.777344 L 146.640625 26.292969 C 146.472656 26.136719 146.296875 26.023438 146.109375 25.949219 C 145.921875 25.867188 145.722656 25.824219 145.515625 25.824219 C 145.097656 25.824219 144.773438 25.957031 144.546875 26.214844 C 144.328125 26.464844 144.21875 26.835938 144.21875 27.324219 C 144.21875 27.804688 144.328125 28.175781 144.546875 28.433594 C 144.773438 28.683594 145.097656 28.808594 145.515625 28.808594 C 145.722656 28.808594 145.921875 28.773438 146.109375 28.699219 C 146.296875 28.617188 146.472656 28.496094 146.640625 28.339844 L 146.640625 28.855469 C 146.472656 28.972656 146.289062 29.058594 146.09375 29.121094 C 145.90625 29.183594 145.703125 29.214844 145.484375 29.214844 C 144.929688 29.214844 144.492188 29.050781 144.171875 28.714844 C 143.859375 28.371094 143.703125 27.910156 143.703125 27.324219 C 143.703125 26.730469 143.859375 26.269531 144.171875 25.933594 C 144.492188 25.589844 144.929688 25.417969 145.484375 25.417969 C 145.703125 25.417969 145.90625 25.449219 146.09375 25.511719 C 146.289062 25.574219 146.472656 25.664062 146.640625 25.777344 Z M 146.640625 25.777344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 148.886719 25.824219 C 148.53125 25.824219 148.246094 25.960938 148.027344 26.230469 C 147.816406 26.492188 147.714844 26.855469 147.714844 27.324219 C 147.714844 27.785156 147.816406 28.148438 148.027344 28.417969 C 148.246094 28.679688 148.53125 28.808594 148.886719 28.808594 C 149.238281 28.808594 149.519531 28.679688 149.730469 28.417969 C 149.949219 28.148438 150.058594 27.785156 150.058594 27.324219 C 150.058594 26.855469 149.949219 26.492188 149.730469 26.230469 C 149.519531 25.960938 149.238281 25.824219 148.886719 25.824219 Z M 148.886719 25.417969 C 149.394531 25.417969 149.800781 25.589844 150.105469 25.933594 C 150.417969 26.277344 150.574219 26.742188 150.574219 27.324219 C 150.574219 27.898438 150.417969 28.355469 150.105469 28.699219 C 149.800781 29.042969 149.394531 29.214844 148.886719 29.214844 C 148.375 29.214844 147.964844 29.042969 147.652344 28.699219 C 147.347656 28.355469 147.199219 27.898438 147.199219 27.324219 C 147.199219 26.742188 147.347656 26.277344 147.652344 25.933594 C 147.964844 25.589844 148.375 25.417969 148.886719 25.417969 Z M 148.886719 25.417969 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 151.839844 25.902344 L 151.839844 28.730469 L 152.433594 28.730469 C 152.933594 28.730469 153.296875 28.617188 153.527344 28.386719 C 153.765625 28.160156 153.886719 27.800781 153.886719 27.308594 C 153.886719 26.820312 153.765625 26.464844 153.527344 26.246094 C 153.296875 26.019531 152.933594 25.902344 152.433594 25.902344 Z M 151.339844 25.496094 L 152.355469 25.496094 C 153.0625 25.496094 153.582031 25.644531 153.917969 25.933594 C 154.25 26.226562 154.417969 26.683594 154.417969 27.308594 C 154.417969 27.933594 154.25 28.398438 153.917969 28.699219 C 153.582031 28.992188 153.0625 29.136719 152.355469 29.136719 L 151.339844 29.136719 Z M 151.339844 25.496094 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 155.1875 25.496094 L 157.5 25.496094 L 157.5 25.902344 L 155.6875 25.902344 L 155.6875 26.980469 L 157.421875 26.980469 L 157.421875 27.402344 L 155.6875 27.402344 L 155.6875 28.714844 L 157.546875 28.714844 L 157.546875 29.136719 L 155.1875 29.136719 Z M 155.1875 25.496094 "/>
<g clip-path="url(#clip5)" clip-rule="nonzero">
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 160.085938 27.433594 C 160.1875 27.464844 160.289062 27.542969 160.382812 27.667969 C 160.484375 27.785156 160.589844 27.941406 160.695312 28.136719 L 161.195312 29.136719 L 160.664062 29.136719 L 160.195312 28.199219 C 160.078125 27.960938 159.964844 27.800781 159.851562 27.714844 C 159.734375 27.632812 159.578125 27.589844 159.382812 27.589844 L 158.851562 27.589844 L 158.851562 29.136719 L 158.351562 29.136719 L 158.351562 25.496094 L 159.476562 25.496094 C 159.890625 25.496094 160.199219 25.585938 160.398438 25.761719 C 160.605469 25.929688 160.710938 26.191406 160.710938 26.542969 C 160.710938 26.773438 160.65625 26.964844 160.554688 27.121094 C 160.449219 27.269531 160.292969 27.371094 160.085938 27.433594 Z M 158.851562 25.902344 L 158.851562 27.183594 L 159.476562 27.183594 C 159.703125 27.183594 159.882812 27.132812 160.007812 27.027344 C 160.132812 26.914062 160.195312 26.753906 160.195312 26.542969 C 160.195312 26.324219 160.132812 26.164062 160.007812 26.058594 C 159.882812 25.957031 159.703125 25.902344 159.476562 25.902344 Z M 158.851562 25.902344 "/>
</g>
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 136.671875 34.15625 L 150.378906 34.15625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 153.894531 34.203125 L 151.109375 32.90625 L 148.328125 31.609375 L 148.328125 36.800781 L 151.109375 35.5 Z M 153.894531 34.203125 "/>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 99 KiB

218
static/images/biocas2018/core.svg Normal file
View File

@ -0,0 +1,218 @@
<?xml version="1.0" encoding="UTF-8"?>
<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" width="185.669113pt" height="102.56218pt" viewBox="0 0 185.669113 102.56218" version="1.1">
<defs>
<clipPath id="clip1">
<path d="M 29 82 L 52 82 L 52 102.5625 L 29 102.5625 Z M 29 82 "/>
</clipPath>
<clipPath id="clip2">
<path d="M 162 47 L 185.667969 47 L 185.667969 73 L 162 73 Z M 162 47 "/>
</clipPath>
<clipPath id="clip3">
<path d="M 162 29 L 185.667969 29 L 185.667969 55 L 162 55 Z M 162 29 "/>
</clipPath>
<clipPath id="clip4">
<path d="M 163 49 L 185.667969 49 L 185.667969 74 L 163 74 Z M 163 49 "/>
</clipPath>
<clipPath id="clip5">
<path d="M 163 28 L 185.667969 28 L 185.667969 53 L 163 53 Z M 163 28 "/>
</clipPath>
<clipPath id="clip6">
<path d="M 166 51 L 185.667969 51 L 185.667969 76 L 166 76 Z M 166 51 "/>
</clipPath>
<clipPath id="clip7">
<path d="M 166 26 L 185.667969 26 L 185.667969 51 L 166 51 Z M 166 26 "/>
</clipPath>
<clipPath id="clip8">
<path d="M 169 51 L 185.667969 51 L 185.667969 76 L 169 76 Z M 169 51 "/>
</clipPath>
<clipPath id="clip9">
<path d="M 169 26 L 185.667969 26 L 185.667969 51 L 169 51 Z M 169 26 "/>
</clipPath>
<clipPath id="clip10">
<path d="M 172 49 L 185.667969 49 L 185.667969 74 L 172 74 Z M 172 49 "/>
</clipPath>
<clipPath id="clip11">
<path d="M 172 28 L 185.667969 28 L 185.667969 53 L 172 53 Z M 172 28 "/>
</clipPath>
<clipPath id="clip12">
<path d="M 168 38 L 185.667969 38 L 185.667969 64 L 168 64 Z M 168 38 "/>
</clipPath>
<clipPath id="clip13">
<path d="M 126 98 L 129 98 L 129 102.5625 L 126 102.5625 Z M 126 98 "/>
</clipPath>
<clipPath id="clip14">
<path d="M 167 30 L 185.667969 30 L 185.667969 45 L 167 45 Z M 167 30 "/>
</clipPath>
<clipPath id="clip15">
<path d="M 167 57 L 185.667969 57 L 185.667969 72 L 167 72 Z M 167 57 "/>
</clipPath>
<clipPath id="clip16">
<path d="M 181 26 L 185.667969 26 L 185.667969 34 L 181 34 Z M 181 26 "/>
</clipPath>
</defs>
<g id="surface1">
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 20.386719 16.257812 L 84.921875 16.257812 C 86.03125 16.257812 86.921875 17.148438 86.921875 18.257812 L 86.921875 91.84375 C 86.921875 92.953125 86.03125 93.84375 84.921875 93.84375 L 20.386719 93.84375 C 19.277344 93.84375 18.386719 92.953125 18.386719 91.84375 L 18.386719 18.257812 C 18.386719 17.148438 19.277344 16.257812 20.386719 16.257812 Z M 20.386719 16.257812 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 6.699219 38.550781 L 85.566406 38.550781 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 80.679688 37.453125 L 82.410156 37.453125 L 82.410156 39.632812 L 80.679688 39.632812 Z M 80.679688 37.453125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 82.410156 38.554688 L 80.253906 40.21875 L 80.253906 36.886719 L 81.332031 37.722656 Z M 82.410156 38.554688 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 45.277344 37.453125 L 47.007812 37.453125 L 47.007812 39.632812 L 45.277344 39.632812 Z M 45.277344 37.453125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 47.003906 38.554688 L 45.929688 39.386719 L 44.851562 40.21875 L 44.851562 36.886719 L 45.929688 37.722656 Z M 47.003906 38.554688 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 86.011719 32.230469 L 88.1875 32.230469 L 88.1875 33.964844 L 86.011719 33.964844 Z M 86.011719 32.230469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 87.109375 33.960938 L 87.945312 32.882812 L 88.777344 31.804688 L 85.445312 31.804688 Z M 87.109375 33.960938 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.947984;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 91.496973 38.554688 C 91.496973 40.929688 89.573848 42.855469 87.205121 42.855469 C 84.836394 42.855469 82.917177 40.929688 82.917177 38.554688 C 82.917177 36.179688 84.836394 34.25 87.205121 34.25 C 89.573848 34.25 91.496973 36.179688 91.496973 38.554688 Z M 91.496973 38.554688 " transform="matrix(0.99935,0,0,1,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 87.644531 35.597656 L 87.644531 38.050781 L 90.097656 38.050781 L 90.097656 38.785156 L 87.644531 38.785156 L 87.644531 41.238281 L 86.910156 41.238281 L 86.910156 38.785156 L 84.457031 38.785156 L 84.457031 38.050781 L 86.910156 38.050781 L 86.910156 35.597656 Z M 87.644531 35.597656 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.80026;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 47.292412 50.929688 L 74.235679 50.835938 L 74.235679 26.175781 L 47.292412 26.273438 Z M 47.292412 50.929688 " transform="matrix(0.999351,0,0,1,0,0)"/>
<path style="fill:none;stroke-width:0.80026;stroke-linecap:butt;stroke-linejoin:bevel;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 70.960116 38.554688 L 50.567975 38.554688 " transform="matrix(0.999351,0,0,1,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 54.992188 31.808594 L 58.835938 31.808594 L 58.835938 32.542969 L 55.789062 36.089844 L 58.835938 36.089844 L 58.835938 36.730469 L 54.882812 36.730469 L 54.882812 35.996094 L 57.914062 32.449219 L 54.992188 32.449219 Z M 54.992188 31.808594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 61.484375 31.183594 L 63.0625 31.183594 L 63.0625 31.667969 L 61.484375 31.667969 Z M 61.484375 31.183594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 64.082031 32.574219 L 65.050781 32.574219 L 65.050781 29.246094 L 63.988281 29.449219 L 63.988281 28.917969 L 65.035156 28.699219 L 65.628906 28.699219 L 65.628906 32.574219 L 66.597656 32.574219 L 66.597656 33.074219 L 64.082031 33.074219 Z M 64.082031 32.574219 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 50.734375 47.074219 L 52.1875 47.074219 L 52.1875 42.074219 L 50.609375 42.386719 L 50.609375 41.574219 L 52.1875 41.261719 L 53.078125 41.261719 L 53.078125 47.074219 L 54.515625 47.074219 L 54.515625 47.824219 L 50.734375 47.824219 Z M 50.734375 47.074219 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 55.882812 44.996094 L 58.257812 44.996094 L 58.257812 45.714844 L 55.882812 45.714844 Z M 55.882812 44.996094 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 59.246094 42.902344 L 63.089844 42.902344 L 63.089844 43.636719 L 60.042969 47.183594 L 63.089844 47.183594 L 63.089844 47.824219 L 59.136719 47.824219 L 59.136719 47.089844 L 62.167969 43.542969 L 59.246094 43.542969 Z M 59.246094 42.902344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 65.738281 42.273438 L 67.316406 42.273438 L 67.316406 42.757812 L 65.738281 42.757812 Z M 65.738281 42.273438 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 68.339844 43.664062 L 69.308594 43.664062 L 69.308594 40.335938 L 68.246094 40.539062 L 68.246094 40.007812 L 69.292969 39.789062 L 69.886719 39.789062 L 69.886719 43.664062 L 70.855469 43.664062 L 70.855469 44.164062 L 68.339844 44.164062 Z M 68.339844 43.664062 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.806038;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 41.04153 39.079604 L 34.654968 42.765192 L 28.268415 46.454746 L 28.268092 39.078994 L 28.267777 31.707208 Z M 41.04153 39.079604 " transform="matrix(1,0.0020936,-0.00216223,0.985069,0,0)"/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.806038;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 71.78073 16.018581 L 65.394167 19.704169 L 59.01152 23.393714 L 59.011197 16.017962 L 59.010883 8.646176 L 65.393853 12.332382 Z M 71.78073 16.018581 " transform="matrix(1,0.0020936,-0.00216223,0.985069,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(64.312744%,0%,0%);fill-opacity:1;" d="M 33.0625 35.183594 L 33.0625 35.855469 L 32.28125 35.855469 C 31.988281 35.855469 31.785156 35.917969 31.671875 36.042969 C 31.566406 36.160156 31.515625 36.367188 31.515625 36.667969 L 31.515625 37.105469 L 32.84375 37.105469 L 32.84375 37.730469 L 31.515625 37.730469 L 31.515625 42.027344 L 30.703125 42.027344 L 30.703125 37.730469 L 29.921875 37.730469 L 29.921875 37.105469 L 30.703125 37.105469 L 30.703125 36.761719 C 30.703125 36.210938 30.828125 35.808594 31.078125 35.558594 C 31.335938 35.308594 31.742188 35.183594 32.296875 35.183594 Z M 33.0625 35.183594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(64.312744%,0%,0%);fill-opacity:1;" d="M 60.898438 12.890625 L 61.523438 12.890625 L 61.523438 16.03125 L 63.398438 14.375 L 64.210938 14.375 L 62.179688 16.171875 L 64.289062 18.203125 L 63.476562 18.203125 L 61.523438 16.328125 L 61.523438 18.203125 L 60.898438 18.203125 Z M 60.898438 12.890625 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 101.785156 71.195312 L 20.085938 71.195312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 22.960938 70.117188 L 24.691406 70.117188 L 24.691406 72.292969 L 22.960938 72.292969 Z M 22.960938 70.117188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 22.960938 71.191406 L 25.117188 69.527344 L 25.117188 72.859375 L 24.039062 72.027344 Z M 22.960938 71.191406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 59.777344 70.117188 L 61.507812 70.117188 L 61.507812 72.292969 L 59.777344 72.292969 Z M 59.777344 70.117188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 59.78125 71.191406 L 60.855469 70.359375 L 61.933594 69.527344 L 61.933594 72.859375 L 60.855469 72.027344 Z M 59.78125 71.191406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 17.183594 75.785156 L 19.359375 75.785156 L 19.359375 77.515625 L 17.183594 77.515625 Z M 17.183594 75.785156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 18.261719 75.785156 L 17.425781 76.863281 L 16.59375 77.941406 L 19.925781 77.941406 Z M 18.261719 75.785156 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.947984;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M -13.942656 -71.191406 C -13.942656 -68.816406 -15.865782 -66.890625 -18.234509 -66.890625 C -20.603236 -66.890625 -22.522452 -68.816406 -22.522452 -71.191406 C -22.522452 -73.570312 -20.603236 -75.496094 -18.234509 -75.496094 C -15.865782 -75.496094 -13.942656 -73.570312 -13.942656 -71.191406 Z M -13.942656 -71.191406 " transform="matrix(-0.99935,0,0,-1,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 17.726562 74.148438 L 17.726562 71.695312 L 15.273438 71.695312 L 15.273438 70.960938 L 17.726562 70.960938 L 17.726562 68.507812 L 18.460938 68.507812 L 18.460938 70.960938 L 20.914062 70.960938 L 20.914062 71.695312 L 18.460938 71.695312 L 18.460938 74.148438 Z M 17.726562 74.148438 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.80026;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 32.775177 83.664062 L 59.718445 83.570312 L 59.718445 58.910156 L 32.775177 59.007812 Z M 32.775177 83.664062 " transform="matrix(0.999351,0,0,1,0,0)"/>
<path style="fill:none;stroke-width:0.80026;stroke-linecap:butt;stroke-linejoin:bevel;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 56.442881 71.289062 L 36.050741 71.289062 " transform="matrix(0.999351,0,0,1,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 40.484375 64.542969 L 44.328125 64.542969 L 44.328125 65.277344 L 41.28125 68.824219 L 44.328125 68.824219 L 44.328125 69.464844 L 40.375 69.464844 L 40.375 68.730469 L 43.40625 65.183594 L 40.484375 65.183594 Z M 40.484375 64.542969 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 46.972656 63.917969 L 48.550781 63.917969 L 48.550781 64.402344 L 46.972656 64.402344 Z M 46.972656 63.917969 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 49.574219 65.308594 L 50.542969 65.308594 L 50.542969 61.980469 L 49.480469 62.183594 L 49.480469 61.652344 L 50.527344 61.433594 L 51.121094 61.433594 L 51.121094 65.308594 L 52.089844 65.308594 L 52.089844 65.808594 L 49.574219 65.808594 Z M 49.574219 65.308594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 36.222656 79.808594 L 37.675781 79.808594 L 37.675781 74.808594 L 36.097656 75.121094 L 36.097656 74.308594 L 37.675781 73.996094 L 38.566406 73.996094 L 38.566406 79.808594 L 40.003906 79.808594 L 40.003906 80.558594 L 36.222656 80.558594 Z M 36.222656 79.808594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 41.371094 77.730469 L 43.746094 77.730469 L 43.746094 78.449219 L 41.371094 78.449219 Z M 41.371094 77.730469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 44.738281 75.636719 L 48.582031 75.636719 L 48.582031 76.371094 L 45.535156 79.917969 L 48.582031 79.917969 L 48.582031 80.558594 L 44.628906 80.558594 L 44.628906 79.824219 L 47.660156 76.277344 L 44.738281 76.277344 Z M 44.738281 75.636719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 51.230469 75.007812 L 52.808594 75.007812 L 52.808594 75.492188 L 51.230469 75.492188 Z M 51.230469 75.007812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 53.832031 76.398438 L 54.800781 76.398438 L 54.800781 73.070312 L 53.738281 73.273438 L 53.738281 72.742188 L 54.785156 72.523438 L 55.378906 72.523438 L 55.378906 76.398438 L 56.347656 76.398438 L 56.347656 76.898438 L 53.832031 76.898438 Z M 53.832031 76.398438 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.806038;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M -65.031236 72.269899 L -71.417798 75.955487 L -77.804352 79.64504 L -77.800768 72.26928 L -77.801083 64.897494 L -71.418113 68.5837 Z M -65.031236 72.269899 " transform="matrix(-1,0.0020936,0.00216223,0.985069,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 34.082031 94.167969 L 40.476562 97.789062 L 46.867188 101.40625 L 46.851562 94.140625 L 46.835938 86.878906 L 40.460938 90.523438 Z M 34.082031 94.167969 "/>
<g clip-path="url(#clip1)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.806038;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M -33.875177 95.667298 L -40.26173 99.356852 L -46.644386 103.042431 L -46.644709 95.66668 L -46.645024 88.294893 L -40.262053 91.9811 Z M -33.875177 95.667298 " transform="matrix(-1,0.0020936,0.00216223,0.985069,0,0)"/>
</g>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(64.312744%,0%,0%);fill-opacity:1;" d="M 76.246094 67.660156 L 76.246094 68.332031 L 75.464844 68.332031 C 75.171875 68.332031 74.96875 68.394531 74.855469 68.519531 C 74.75 68.636719 74.699219 68.84375 74.699219 69.144531 L 74.699219 69.582031 L 76.027344 69.582031 L 76.027344 70.207031 L 74.699219 70.207031 L 74.699219 74.503906 L 73.886719 74.503906 L 73.886719 70.207031 L 73.105469 70.207031 L 73.105469 69.582031 L 73.886719 69.582031 L 73.886719 69.238281 C 73.886719 68.6875 74.011719 68.285156 74.261719 68.035156 C 74.519531 67.785156 74.925781 67.660156 75.480469 67.660156 Z M 76.246094 67.660156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(64.312744%,0%,0%);fill-opacity:1;" d="M 41.617188 91.101562 L 42.242188 91.101562 L 42.242188 94.242188 L 44.117188 92.585938 L 44.929688 92.585938 L 42.898438 94.382812 L 45.007812 96.414062 L 44.195312 96.414062 L 42.242188 94.539062 L 42.242188 96.414062 L 41.617188 96.414062 Z M 41.617188 91.101562 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 12.527344 35.609375 L 12.527344 41.507812 L 3.492188 41.507812 L 0.570312 38.632812 L 3.570312 35.683594 Z M 12.527344 35.609375 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 93.132812 74.070312 L 93.132812 68.171875 L 102.167969 68.171875 L 105.089844 71.046875 L 102.089844 73.996094 Z M 93.132812 74.070312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 86.726562 72.425781 C 86.011719 72.425781 85.433594 71.847656 85.433594 71.132812 C 85.433594 70.421875 86.011719 69.84375 86.726562 69.84375 C 87.4375 69.84375 88.015625 70.421875 88.015625 71.132812 C 88.015625 71.847656 87.4375 72.425781 86.726562 72.425781 Z M 86.726562 72.425781 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 18.359375 39.816406 C 17.644531 39.816406 17.070312 39.238281 17.070312 38.527344 C 17.070312 37.8125 17.644531 37.234375 18.359375 37.234375 C 19.070312 37.234375 19.648438 37.8125 19.648438 38.527344 C 19.648438 39.238281 19.070312 39.816406 18.359375 39.816406 Z M 18.359375 39.816406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(64.312744%,0%,0%);fill-opacity:1;" d="M 98.097656 58.078125 C 97.449219 58.078125 96.933594 58.320312 96.550781 58.796875 C 96.175781 59.277344 95.988281 59.929688 95.988281 60.75 C 95.988281 61.585938 96.175781 62.242188 96.550781 62.71875 C 96.933594 63.199219 97.449219 63.4375 98.097656 63.4375 C 98.742188 63.4375 99.253906 63.199219 99.628906 62.71875 C 100.003906 62.242188 100.191406 61.585938 100.191406 60.75 C 100.191406 59.929688 100.003906 59.277344 99.628906 58.796875 C 99.253906 58.320312 98.742188 58.078125 98.097656 58.078125 Z M 99.347656 63.90625 L 100.503906 65.1875 L 99.441406 65.1875 L 98.472656 64.140625 C 98.367188 64.148438 98.289062 64.15625 98.238281 64.15625 C 98.183594 64.15625 98.136719 64.15625 98.097656 64.15625 C 97.167969 64.15625 96.429688 63.851562 95.878906 63.234375 C 95.324219 62.621094 95.050781 61.792969 95.050781 60.75 C 95.050781 59.71875 95.324219 58.898438 95.878906 58.28125 C 96.429688 57.65625 97.167969 57.34375 98.097656 57.34375 C 99.011719 57.34375 99.746094 57.65625 100.300781 58.28125 C 100.851562 58.898438 101.128906 59.71875 101.128906 60.75 C 101.128906 61.523438 100.972656 62.179688 100.660156 62.71875 C 100.355469 63.261719 99.917969 63.65625 99.347656 63.90625 Z M 99.347656 63.90625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(64.312744%,0%,0%);fill-opacity:1;" d="M 7.355469 24.988281 L 8.230469 24.988281 L 8.230469 31.550781 L 7.355469 31.550781 Z M 7.355469 24.988281 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.806562;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M -45.310608 18.940852 L -51.701066 22.631226 L -58.091533 26.317629 L -58.091859 18.940222 L -58.08828 11.562807 L -51.701393 15.253819 Z M -45.310608 18.940852 " transform="matrix(0.00209088,-1,0.983789,0.00216223,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 15.585938 54.320312 L 17.429688 54.320312 L 17.429688 54.882812 L 15.585938 54.882812 Z M 15.585938 54.320312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 18.59375 55.945312 L 19.71875 55.945312 L 19.71875 52.054688 L 18.484375 52.289062 L 18.484375 51.664062 L 19.703125 51.414062 L 20.40625 51.414062 L 20.40625 55.945312 L 21.53125 55.945312 L 21.53125 56.523438 L 18.59375 56.523438 Z M 18.59375 55.945312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 3.390625 5.808594 C 2.523438 5.808594 1.921875 5.910156 1.578125 6.105469 C 1.242188 6.304688 1.078125 6.644531 1.078125 7.121094 C 1.078125 7.507812 1.203125 7.816406 1.453125 8.042969 C 1.710938 8.261719 2.054688 8.371094 2.484375 8.371094 C 3.085938 8.371094 3.566406 8.164062 3.921875 7.746094 C 4.285156 7.320312 4.46875 6.753906 4.46875 6.042969 L 4.46875 5.808594 Z M 5.546875 5.355469 L 5.546875 9.105469 L 4.46875 9.105469 L 4.46875 8.105469 C 4.21875 8.503906 3.910156 8.800781 3.546875 8.996094 C 3.179688 9.183594 2.734375 9.277344 2.203125 9.277344 C 1.523438 9.277344 0.988281 9.089844 0.59375 8.714844 C 0.195312 8.332031 0 7.824219 0 7.199219 C 0 6.460938 0.242188 5.902344 0.734375 5.527344 C 1.234375 5.152344 1.972656 4.964844 2.953125 4.964844 L 4.46875 4.964844 L 4.46875 4.855469 C 4.46875 4.355469 4.300781 3.972656 3.96875 3.699219 C 3.644531 3.429688 3.191406 3.292969 2.609375 3.292969 C 2.234375 3.292969 1.863281 3.339844 1.5 3.433594 C 1.144531 3.527344 0.804688 3.664062 0.484375 3.839844 L 0.484375 2.839844 C 0.878906 2.683594 1.257812 2.570312 1.625 2.496094 C 2 2.425781 2.363281 2.386719 2.71875 2.386719 C 3.664062 2.386719 4.375 2.632812 4.84375 3.121094 C 5.3125 3.613281 5.546875 4.355469 5.546875 5.355469 Z M 5.546875 5.355469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 7.609375 -0.00390625 L 8.546875 -0.00390625 C 9.128906 0.925781 9.566406 1.832031 9.859375 2.714844 C 10.148438 3.589844 10.296875 4.464844 10.296875 5.339844 C 10.296875 6.214844 10.148438 7.097656 9.859375 7.980469 C 9.566406 8.867188 9.128906 9.765625 8.546875 10.683594 L 7.609375 10.683594 C 8.117188 9.785156 8.503906 8.898438 8.765625 8.011719 C 9.023438 7.128906 9.15625 6.238281 9.15625 5.339844 C 9.15625 4.433594 9.023438 3.542969 8.765625 2.667969 C 8.503906 1.785156 8.117188 0.894531 7.609375 -0.00390625 Z M 7.609375 -0.00390625 "/>
<g clip-path="url(#clip2)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 173.816406 59.054688 L 175.488281 60.722656 M 175.488281 59.054688 L 173.816406 60.722656 "/>
</g>
<g clip-path="url(#clip3)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 173.816406 41.285156 L 175.488281 42.957031 M 175.488281 41.285156 L 173.816406 42.957031 "/>
</g>
<path style="fill:none;stroke-width:0.4;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 180.414062 51.214844 L 180.386719 49.582031 L 180.320312 48.164062 L 180.195312 46.570312 L 180.019531 44.972656 L 179.792969 43.386719 L 179.535156 41.925781 L 179.222656 40.421875 L 178.851562 38.878906 L 178.429688 37.351562 L 177.945312 35.792969 L 177.480469 34.4375 L 176.90625 32.929688 L 176.28125 31.429688 L 175.632812 30.007812 L 175.003906 28.734375 L 174.210938 27.246094 L 173.5 26.003906 L 172.628906 24.589844 L 171.816406 23.359375 L 170.882812 22.042969 L 169.957031 20.816406 L 168.949219 19.566406 L 167.988281 18.449219 L 166.914062 17.273438 L 165.761719 16.09375 L 164.726562 15.097656 L 163.574219 14.054688 L 162.351562 13.019531 L 161.121094 12.042969 L 159.90625 11.136719 L 158.519531 10.171875 L 157.25 9.347656 L 155.867188 8.511719 L 154.589844 7.792969 L 153.167969 7.050781 L 151.8125 6.394531 L 150.371094 5.753906 L 148.945312 5.171875 L 147.433594 4.609375 L 145.960938 4.117188 L 144.4375 3.660156 L 142.914062 3.253906 L 141.503906 2.925781 L 139.878906 2.601562 L 138.414062 2.355469 L 136.847656 2.144531 L 135.339844 1.988281 L 133.664062 1.867188 L 132.207031 1.808594 L 130.554688 1.796875 M 130.652344 100.632812 L 132.105469 100.621094 L 133.757812 100.554688 L 135.261719 100.449219 L 136.902344 100.277344 L 138.308594 100.085938 L 139.90625 99.820312 L 141.441406 99.515625 L 142.960938 99.160156 L 144.46875 98.761719 L 145.898438 98.332031 L 147.433594 97.816406 L 148.878906 97.28125 L 150.382812 96.671875 L 151.722656 96.074219 L 153.183594 95.367188 L 154.5625 94.648438 L 155.914062 93.886719 L 157.300781 93.050781 L 158.550781 92.234375 L 159.804688 91.363281 L 161.160156 90.359375 L 162.355469 89.40625 L 163.546875 88.398438 L 164.722656 87.332031 L 165.777344 86.320312 L 166.863281 85.207031 L 167.910156 84.070312 L 168.988281 82.816406 L 169.902344 81.683594 L 170.917969 80.339844 L 171.792969 79.101562 L 172.621094 77.847656 L 173.46875 76.472656 L 174.277344 75.066406 L 174.96875 73.765625 L 175.660156 72.359375 L 176.292969 70.96875 L 176.933594 69.4375 L 177.441406 68.097656 L 177.976562 66.539062 L 178.433594 65.058594 L 178.839844 63.582031 L 179.203125 62.089844 L 179.523438 60.558594 L 179.808594 58.921875 L 180.023438 57.417969 L 180.191406 55.925781 L 180.316406 54.324219 L 180.390625 52.722656 L 180.414062 51.214844 "/>
<g clip-path="url(#clip4)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 175.308594 61 L 176.976562 62.671875 M 176.976562 61 L 175.308594 62.671875 "/>
</g>
<g clip-path="url(#clip5)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 175.308594 39.339844 L 176.976562 41.007812 M 176.976562 39.339844 L 175.308594 41.007812 "/>
</g>
<g clip-path="url(#clip6)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 177.851562 62.335938 L 179.519531 64.003906 M 179.519531 62.335938 L 177.851562 64.003906 "/>
</g>
<g clip-path="url(#clip7)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 177.851562 38.003906 L 179.519531 39.675781 M 179.519531 38.003906 L 177.851562 39.675781 "/>
</g>
<g clip-path="url(#clip8)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 180.890625 62.335938 L 182.5625 64.003906 M 182.5625 62.335938 L 180.890625 64.003906 "/>
</g>
<g clip-path="url(#clip9)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 180.890625 38.003906 L 182.5625 39.675781 M 182.5625 38.003906 L 180.890625 39.675781 "/>
</g>
<g clip-path="url(#clip10)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 183.433594 61 L 185.101562 62.671875 M 185.101562 61 L 183.433594 62.671875 "/>
</g>
<g clip-path="url(#clip11)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 183.433594 39.339844 L 185.101562 41.007812 M 185.101562 39.339844 L 183.433594 41.007812 "/>
</g>
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.242188 51.214844 L 180.605469 51.214844 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 155.699219 51.214844 L 155.699219 52.359375 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 180.414062 51.214844 L 180.414062 52.359375 "/>
<g clip-path="url(#clip12)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 181.042969 51.003906 C 181.042969 51.464844 180.667969 51.839844 180.207031 51.839844 C 179.746094 51.839844 179.371094 51.464844 179.371094 51.003906 C 179.371094 50.542969 179.746094 50.171875 180.207031 50.171875 C 180.667969 50.171875 181.042969 50.542969 181.042969 51.003906 Z M 181.042969 51.003906 "/>
</g>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 135.929688 51.214844 L 135.929688 51.785156 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 140.871094 51.214844 L 140.871094 51.785156 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 145.816406 51.214844 L 145.816406 51.785156 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 150.757812 51.214844 L 150.757812 51.785156 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 160.644531 51.214844 L 160.644531 51.785156 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 165.585938 51.214844 L 165.585938 51.785156 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 170.527344 51.214844 L 170.527344 51.785156 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 175.472656 51.214844 L 175.472656 51.785156 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 100.632812 L 130.988281 1.796875 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 100.632812 L 129.84375 100.632812 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 75.921875 L 129.84375 75.921875 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 51.214844 L 129.84375 51.214844 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 26.503906 L 129.84375 26.503906 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 1.792969 L 129.84375 1.792969 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 95.691406 L 130.414062 95.691406 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 90.75 L 130.414062 90.75 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 85.808594 L 130.414062 85.808594 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 80.867188 L 130.414062 80.867188 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 70.980469 L 130.414062 70.980469 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 66.039062 L 130.414062 66.039062 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 61.097656 L 130.414062 61.097656 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 56.15625 L 130.414062 56.15625 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 46.273438 L 130.414062 46.273438 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 41.328125 L 130.414062 41.328125 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 36.386719 L 130.414062 36.386719 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 31.445312 L 130.414062 31.445312 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 21.5625 L 130.414062 21.5625 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 16.621094 L 130.414062 16.621094 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 11.679688 L 130.414062 11.679688 "/>
<path style="fill:none;stroke-width:1.2;stroke-linecap:square;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 130.988281 6.738281 L 130.414062 6.738281 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 125.84375 3.207031 L 126.640625 3.207031 L 126.640625 0.425781 L 125.765625 0.613281 L 125.765625 0.160156 L 126.640625 -0.0117188 L 127.140625 -0.0117188 L 127.140625 3.207031 L 127.9375 3.207031 L 127.9375 3.628906 L 125.84375 3.628906 Z M 125.84375 3.207031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 121.484375 24.988281 C 121.222656 24.988281 121.03125 25.113281 120.90625 25.363281 C 120.78125 25.613281 120.71875 25.996094 120.71875 26.503906 C 120.71875 27.003906 120.78125 27.378906 120.90625 27.628906 C 121.03125 27.878906 121.222656 28.003906 121.484375 28.003906 C 121.734375 28.003906 121.921875 27.878906 122.046875 27.628906 C 122.179688 27.378906 122.25 27.003906 122.25 26.503906 C 122.25 25.996094 122.179688 25.613281 122.046875 25.363281 C 121.921875 25.113281 121.734375 24.988281 121.484375 24.988281 Z M 121.484375 24.597656 C 121.890625 24.597656 122.195312 24.765625 122.40625 25.097656 C 122.625 25.421875 122.734375 25.890625 122.734375 26.503906 C 122.734375 27.109375 122.625 27.578125 122.40625 27.910156 C 122.195312 28.234375 121.890625 28.394531 121.484375 28.394531 C 121.078125 28.394531 120.765625 28.234375 120.546875 27.910156 C 120.328125 27.578125 120.21875 27.109375 120.21875 26.503906 C 120.21875 25.890625 120.328125 25.421875 120.546875 25.097656 C 120.765625 24.765625 121.078125 24.597656 121.484375 24.597656 Z M 121.484375 24.597656 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 123.589844 27.691406 L 124.105469 27.691406 L 124.105469 28.316406 L 123.589844 28.316406 Z M 123.589844 27.691406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 125.191406 24.675781 L 127.113281 24.675781 L 127.113281 25.082031 L 125.628906 25.082031 L 125.628906 25.972656 C 125.699219 25.953125 125.773438 25.9375 125.847656 25.925781 C 125.917969 25.917969 125.992188 25.910156 126.066406 25.910156 C 126.472656 25.910156 126.792969 26.027344 127.035156 26.253906 C 127.273438 26.472656 127.394531 26.769531 127.394531 27.144531 C 127.394531 27.542969 127.269531 27.847656 127.019531 28.066406 C 126.777344 28.285156 126.433594 28.394531 125.988281 28.394531 C 125.832031 28.394531 125.675781 28.378906 125.519531 28.347656 C 125.363281 28.324219 125.199219 28.292969 125.035156 28.238281 L 125.035156 27.738281 C 125.179688 27.8125 125.332031 27.871094 125.488281 27.910156 C 125.644531 27.953125 125.804688 27.972656 125.972656 27.972656 C 126.261719 27.972656 126.488281 27.902344 126.644531 27.753906 C 126.808594 27.609375 126.894531 27.40625 126.894531 27.144531 C 126.894531 26.894531 126.808594 26.699219 126.644531 26.550781 C 126.488281 26.394531 126.261719 26.316406 125.972656 26.316406 C 125.847656 26.316406 125.714844 26.332031 125.582031 26.363281 C 125.457031 26.394531 125.324219 26.441406 125.191406 26.503906 Z M 125.191406 24.675781 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 153.160156 54.664062 C 152.898438 54.664062 152.707031 54.789062 152.582031 55.039062 C 152.457031 55.289062 152.394531 55.671875 152.394531 56.179688 C 152.394531 56.679688 152.457031 57.054688 152.582031 57.304688 C 152.707031 57.554688 152.898438 57.679688 153.160156 57.679688 C 153.410156 57.679688 153.597656 57.554688 153.722656 57.304688 C 153.855469 57.054688 153.925781 56.679688 153.925781 56.179688 C 153.925781 55.671875 153.855469 55.289062 153.722656 55.039062 C 153.597656 54.789062 153.410156 54.664062 153.160156 54.664062 Z M 153.160156 54.273438 C 153.566406 54.273438 153.871094 54.441406 154.082031 54.773438 C 154.300781 55.097656 154.410156 55.566406 154.410156 56.179688 C 154.410156 56.785156 154.300781 57.253906 154.082031 57.585938 C 153.871094 57.910156 153.566406 58.070312 153.160156 58.070312 C 152.753906 58.070312 152.441406 57.910156 152.222656 57.585938 C 152.003906 57.253906 151.894531 56.785156 151.894531 56.179688 C 151.894531 55.566406 152.003906 55.097656 152.222656 54.773438 C 152.441406 54.441406 152.753906 54.273438 153.160156 54.273438 Z M 153.160156 54.273438 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 155.265625 57.367188 L 155.78125 57.367188 L 155.78125 57.992188 L 155.265625 57.992188 Z M 155.265625 57.367188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 156.867188 54.351562 L 158.789062 54.351562 L 158.789062 54.757812 L 157.304688 54.757812 L 157.304688 55.648438 C 157.375 55.628906 157.449219 55.613281 157.523438 55.601562 C 157.59375 55.59375 157.667969 55.585938 157.742188 55.585938 C 158.148438 55.585938 158.46875 55.703125 158.710938 55.929688 C 158.949219 56.148438 159.070312 56.445312 159.070312 56.820312 C 159.070312 57.21875 158.945312 57.523438 158.695312 57.742188 C 158.453125 57.960938 158.109375 58.070312 157.664062 58.070312 C 157.507812 58.070312 157.351562 58.054688 157.195312 58.023438 C 157.039062 58 156.875 57.96875 156.710938 57.914062 L 156.710938 57.414062 C 156.855469 57.488281 157.007812 57.546875 157.164062 57.585938 C 157.320312 57.628906 157.480469 57.648438 157.648438 57.648438 C 157.9375 57.648438 158.164062 57.578125 158.320312 57.429688 C 158.484375 57.285156 158.570312 57.082031 158.570312 56.820312 C 158.570312 56.570312 158.484375 56.375 158.320312 56.226562 C 158.164062 56.070312 157.9375 55.992188 157.648438 55.992188 C 157.523438 55.992188 157.390625 56.007812 157.257812 56.039062 C 157.132812 56.070312 157 56.117188 156.867188 56.179688 Z M 156.867188 54.351562 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 124.296875 101 L 125.609375 101 L 125.609375 101.390625 L 124.296875 101.390625 Z M 124.296875 101 "/>
<g clip-path="url(#clip13)" clip-rule="nonzero">
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 126.472656 102.140625 L 127.269531 102.140625 L 127.269531 99.359375 L 126.394531 99.546875 L 126.394531 99.09375 L 127.269531 98.921875 L 127.769531 98.921875 L 127.769531 102.140625 L 128.566406 102.140625 L 128.566406 102.5625 L 126.472656 102.5625 Z M 126.472656 102.140625 "/>
</g>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 119.550781 76.167969 L 120.863281 76.167969 L 120.863281 76.558594 L 119.550781 76.558594 Z M 119.550781 76.167969 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 122.695312 74.402344 C 122.433594 74.402344 122.242188 74.527344 122.117188 74.777344 C 121.992188 75.027344 121.929688 75.410156 121.929688 75.917969 C 121.929688 76.417969 121.992188 76.792969 122.117188 77.042969 C 122.242188 77.292969 122.433594 77.417969 122.695312 77.417969 C 122.945312 77.417969 123.132812 77.292969 123.257812 77.042969 C 123.390625 76.792969 123.460938 76.417969 123.460938 75.917969 C 123.460938 75.410156 123.390625 75.027344 123.257812 74.777344 C 123.132812 74.527344 122.945312 74.402344 122.695312 74.402344 Z M 122.695312 74.011719 C 123.101562 74.011719 123.40625 74.179688 123.617188 74.511719 C 123.835938 74.835938 123.945312 75.304688 123.945312 75.917969 C 123.945312 76.523438 123.835938 76.992188 123.617188 77.324219 C 123.40625 77.648438 123.101562 77.808594 122.695312 77.808594 C 122.289062 77.808594 121.976562 77.648438 121.757812 77.324219 C 121.539062 76.992188 121.429688 76.523438 121.429688 75.917969 C 121.429688 75.304688 121.539062 74.835938 121.757812 74.511719 C 121.976562 74.179688 122.289062 74.011719 122.695312 74.011719 Z M 122.695312 74.011719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 124.800781 77.105469 L 125.316406 77.105469 L 125.316406 77.730469 L 124.800781 77.730469 Z M 124.800781 77.105469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 126.402344 74.089844 L 128.324219 74.089844 L 128.324219 74.496094 L 126.839844 74.496094 L 126.839844 75.386719 C 126.910156 75.367188 126.984375 75.351562 127.058594 75.339844 C 127.128906 75.332031 127.203125 75.324219 127.277344 75.324219 C 127.683594 75.324219 128.003906 75.441406 128.246094 75.667969 C 128.484375 75.886719 128.605469 76.183594 128.605469 76.558594 C 128.605469 76.957031 128.480469 77.261719 128.230469 77.480469 C 127.988281 77.699219 127.644531 77.808594 127.199219 77.808594 C 127.042969 77.808594 126.886719 77.792969 126.730469 77.761719 C 126.574219 77.738281 126.410156 77.707031 126.246094 77.652344 L 126.246094 77.152344 C 126.390625 77.226562 126.542969 77.285156 126.699219 77.324219 C 126.855469 77.367188 127.015625 77.386719 127.183594 77.386719 C 127.472656 77.386719 127.699219 77.316406 127.855469 77.167969 C 128.019531 77.023438 128.105469 76.820312 128.105469 76.558594 C 128.105469 76.308594 128.019531 76.113281 127.855469 75.964844 C 127.699219 75.808594 127.472656 75.730469 127.183594 75.730469 C 127.058594 75.730469 126.925781 75.746094 126.792969 75.777344 C 126.667969 75.808594 126.535156 75.855469 126.402344 75.917969 Z M 126.402344 74.089844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 179.578125 56.824219 L 180.375 56.824219 L 180.375 54.042969 L 179.5 54.230469 L 179.5 53.777344 L 180.375 53.605469 L 180.875 53.605469 L 180.875 56.824219 L 181.671875 56.824219 L 181.671875 57.246094 L 179.578125 57.246094 Z M 179.578125 56.824219 "/>
<g clip-path="url(#clip14)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(93.72406%,16.078186%,16.078186%);stroke-opacity:1;stroke-miterlimit:4;" d="M 172.269531 40.105469 C 174.519531 36.210938 179.238281 34.492188 183.464844 36.03125 "/>
</g>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(93.72406%,16.078186%,16.078186%);fill-opacity:1;" d="M 184.835938 36.660156 L 183.785156 36.957031 L 182.734375 37.257812 L 183.230469 36.019531 L 183.726562 34.777344 Z M 184.835938 36.660156 "/>
<g clip-path="url(#clip15)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(93.72406%,16.078186%,16.078186%);stroke-opacity:1;stroke-miterlimit:4;" d="M 172.265625 -62.121094 C 174.515625 -66.015625 179.234375 -67.734375 183.460938 -66.195312 " transform="matrix(1,0,0,-1,0,0)"/>
</g>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(93.72406%,16.078186%,16.078186%);fill-opacity:1;" d="M 184.902344 65.5 L 183.773438 65.175781 L 182.648438 64.855469 L 183.710938 67.519531 L 184.308594 66.507812 Z M 184.902344 65.5 "/>
<g clip-path="url(#clip16)" clip-rule="nonzero">
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(93.72406%,16.078186%,16.078186%);fill-opacity:1;" d="M 181.230469 26.605469 L 182.042969 26.605469 L 182.042969 30.652344 L 184.464844 28.527344 L 185.496094 28.527344 L 182.886719 30.824219 L 185.605469 33.449219 L 184.542969 33.449219 L 182.042969 31.042969 L 182.042969 33.449219 L 181.230469 33.449219 Z M 181.230469 26.605469 "/>
</g>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(93.72406%,16.078186%,16.078186%);stroke-opacity:1;stroke-miterlimit:4;" d="M 178.882812 27.851562 L 178.882812 32.035156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(93.72406%,16.078186%,16.078186%);fill-opacity:1;" d="M 178.863281 33.152344 L 179.515625 32.3125 L 180.164062 31.472656 L 177.566406 31.472656 Z M 178.863281 33.152344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 112.738281 5.835938 C 112.738281 5.046875 112.570312 4.425781 112.238281 3.976562 C 111.914062 3.53125 111.472656 3.304688 110.910156 3.304688 C 110.335938 3.304688 109.882812 3.53125 109.550781 3.976562 C 109.226562 4.425781 109.066406 5.046875 109.066406 5.835938 C 109.066406 6.628906 109.226562 7.253906 109.550781 7.710938 C 109.882812 8.160156 110.335938 8.382812 110.910156 8.382812 C 111.472656 8.382812 111.914062 8.160156 112.238281 7.710938 C 112.570312 7.253906 112.738281 6.628906 112.738281 5.835938 Z M 109.066406 3.554688 C 109.292969 3.160156 109.582031 2.867188 109.925781 2.679688 C 110.269531 2.492188 110.679688 2.398438 111.160156 2.398438 C 111.960938 2.398438 112.613281 2.71875 113.113281 3.351562 C 113.613281 3.976562 113.863281 4.804688 113.863281 5.835938 C 113.863281 6.867188 113.613281 7.703125 113.113281 8.335938 C 112.613281 8.972656 111.960938 9.289062 111.160156 9.289062 C 110.679688 9.289062 110.269531 9.195312 109.925781 9.007812 C 109.582031 8.8125 109.292969 8.519531 109.066406 8.132812 L 109.066406 9.117188 L 107.988281 9.117188 L 107.988281 -0.0078125 L 109.066406 -0.0078125 Z M 109.066406 3.554688 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 115.480469 0.0078125 L 116.417969 0.0078125 C 117 0.9375 117.4375 1.84375 117.730469 2.726562 C 118.019531 3.601562 118.167969 4.476562 118.167969 5.351562 C 118.167969 6.226562 118.019531 7.109375 117.730469 7.992188 C 117.4375 8.878906 117 9.777344 116.417969 10.695312 L 115.480469 10.695312 C 115.988281 9.796875 116.375 8.910156 116.636719 8.023438 C 116.894531 7.140625 117.027344 6.25 117.027344 5.351562 C 117.027344 4.445312 116.894531 3.554688 116.636719 2.679688 C 116.375 1.796875 115.988281 0.90625 115.480469 0.0078125 Z M 115.480469 0.0078125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 166.957031 39.949219 L 166.957031 41.308594 L 167.582031 41.308594 C 167.808594 41.308594 167.988281 41.253906 168.113281 41.136719 C 168.238281 41.011719 168.300781 40.839844 168.300781 40.621094 C 168.300781 40.402344 168.238281 40.238281 168.113281 40.121094 C 167.988281 40.007812 167.808594 39.949219 167.582031 39.949219 Z M 166.457031 39.542969 L 167.582031 39.542969 C 167.988281 39.542969 168.292969 39.636719 168.503906 39.824219 C 168.710938 40.003906 168.816406 40.269531 168.816406 40.621094 C 168.816406 40.988281 168.710938 41.261719 168.503906 41.449219 C 168.292969 41.628906 167.988281 41.714844 167.582031 41.714844 L 166.957031 41.714844 L 166.957031 43.183594 L 166.457031 43.183594 Z M 166.457031 39.542969 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 170.167969 42.195312 C 169.949219 42.195312 169.777344 42.28125 169.652344 42.445312 C 169.527344 42.601562 169.464844 42.816406 169.464844 43.085938 C 169.464844 43.367188 169.527344 43.585938 169.652344 43.742188 C 169.777344 43.898438 169.949219 43.976562 170.167969 43.976562 C 170.375 43.976562 170.542969 43.898438 170.667969 43.742188 C 170.792969 43.585938 170.855469 43.367188 170.855469 43.085938 C 170.855469 42.816406 170.792969 42.601562 170.667969 42.445312 C 170.542969 42.28125 170.375 42.195312 170.167969 42.195312 Z M 170.574219 44.132812 L 170.964844 44.570312 L 170.605469 44.570312 L 170.292969 44.210938 C 170.25 44.21875 170.21875 44.226562 170.199219 44.226562 C 170.1875 44.226562 170.175781 44.226562 170.167969 44.226562 C 169.855469 44.226562 169.605469 44.125 169.417969 43.914062 C 169.238281 43.707031 169.152344 43.429688 169.152344 43.085938 C 169.152344 42.742188 169.238281 42.46875 169.417969 42.257812 C 169.605469 42.050781 169.855469 41.945312 170.167969 41.945312 C 170.46875 41.945312 170.707031 42.050781 170.886719 42.257812 C 171.074219 42.46875 171.167969 42.742188 171.167969 43.085938 C 171.167969 43.347656 171.113281 43.566406 171.011719 43.742188 C 170.917969 43.921875 170.769531 44.050781 170.574219 44.132812 Z M 170.574219 44.132812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 167.824219 56.640625 L 167.824219 58 L 168.449219 58 C 168.675781 58 168.855469 57.945312 168.980469 57.828125 C 169.105469 57.703125 169.167969 57.53125 169.167969 57.3125 C 169.167969 57.09375 169.105469 56.929688 168.980469 56.8125 C 168.855469 56.699219 168.675781 56.640625 168.449219 56.640625 Z M 167.324219 56.234375 L 168.449219 56.234375 C 168.855469 56.234375 169.160156 56.328125 169.371094 56.515625 C 169.578125 56.695312 169.683594 56.960938 169.683594 57.3125 C 169.683594 57.679688 169.578125 57.953125 169.371094 58.140625 C 169.160156 58.320312 168.855469 58.40625 168.449219 58.40625 L 167.824219 58.40625 L 167.824219 59.875 L 167.324219 59.875 Z M 167.324219 56.234375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 170.140625 58.683594 L 170.4375 58.683594 L 170.4375 60.871094 L 170.140625 60.871094 Z M 170.140625 58.683594 "/>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 51 KiB

311
static/images/biocas2018/ddws-core.svg Normal file
View File

@ -0,0 +1,311 @@
<?xml version="1.0" encoding="UTF-8"?>
<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" width="262.62735pt" height="122.658775pt" viewBox="0 0 262.62735 122.658775" version="1.1">
<defs>
<clipPath id="clip1">
<path d="M 178 100 L 250 100 L 250 122.660156 L 178 122.660156 Z M 178 100 "/>
</clipPath>
<clipPath id="clip2">
<path d="M 180 83 L 227 83 L 227 122.660156 L 180 122.660156 Z M 180 83 "/>
</clipPath>
<clipPath id="clip3">
<path d="M 244 97 L 262.628906 97 L 262.628906 113 L 244 113 Z M 244 97 "/>
</clipPath>
<clipPath id="clip4">
<path d="M 217 87 L 254 87 L 254 122.660156 L 217 122.660156 Z M 217 87 "/>
</clipPath>
<clipPath id="clip5">
<path d="M 56 89 L 97 89 L 97 122.660156 L 56 122.660156 Z M 56 89 "/>
</clipPath>
<clipPath id="clip6">
<path d="M 13 0 L 56 0 L 56 122.660156 L 13 122.660156 Z M 13 0 "/>
</clipPath>
</defs>
<g id="surface1">
<g clip-path="url(#clip1)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 244.722656 104.984375 L 244.722656 117.925781 C 244.722656 117.925781 244.21875 119.425781 243.222656 119.425781 L 184.90625 119.425781 C 183.914062 119.425781 183.40625 118.6875 183.40625 117.925781 L 183.40625 104.875 "/>
</g>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 170.601562 104.945312 L 252.648438 104.945312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 189.476562 103.984375 L 190.992188 103.984375 L 190.992188 105.882812 L 189.476562 105.882812 Z M 189.476562 103.984375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 190.992188 104.945312 L 190.046875 105.671875 L 189.105469 106.402344 L 189.105469 103.488281 L 190.046875 104.214844 Z M 190.992188 104.945312 "/>
<path style=" stroke:none;fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 191.390625 115.054688 L 215.378906 114.976562 L 215.378906 94.847656 L 191.390625 94.921875 Z M 191.390625 115.054688 "/>
<g clip-path="url(#clip2)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 191.390625 115.054688 L 215.378906 114.976562 L 215.378906 94.847656 L 191.390625 94.921875 Z M 191.390625 115.054688 "/>
</g>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:bevel;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 212.300781 104.136719 L 194.46875 104.136719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 196.355469 101.871094 L 199.121094 101.871094 L 199.121094 102.542969 L 195.417969 102.542969 L 195.417969 101.871094 C 195.707031 101.570312 196.113281 101.160156 196.636719 100.632812 C 197.15625 100.105469 197.480469 99.769531 197.605469 99.621094 C 197.863281 99.339844 198.042969 99.101562 198.136719 98.902344 C 198.238281 98.707031 198.292969 98.507812 198.292969 98.324219 C 198.292969 98.007812 198.183594 97.757812 197.964844 97.558594 C 197.746094 97.363281 197.464844 97.257812 197.121094 97.257812 C 196.871094 97.257812 196.605469 97.308594 196.324219 97.402344 C 196.050781 97.488281 195.761719 97.617188 195.449219 97.792969 L 195.449219 96.996094 C 195.769531 96.863281 196.066406 96.757812 196.339844 96.699219 C 196.621094 96.632812 196.875 96.605469 197.105469 96.605469 C 197.707031 96.605469 198.1875 96.757812 198.542969 97.058594 C 198.90625 97.363281 199.089844 97.757812 199.089844 98.257812 C 199.089844 98.503906 199.042969 98.730469 198.949219 98.949219 C 198.855469 99.167969 198.691406 99.425781 198.464844 99.714844 C 198.390625 99.789062 198.175781 100.007812 197.824219 100.371094 C 197.480469 100.726562 196.988281 101.226562 196.355469 101.871094 Z M 196.355469 101.871094 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 200.355469 98.167969 L 203.777344 98.167969 L 203.777344 98.824219 L 201.074219 101.964844 L 203.777344 101.964844 L 203.777344 102.542969 L 200.261719 102.542969 L 200.261719 101.882812 L 202.964844 98.746094 L 200.355469 98.746094 Z M 200.355469 98.167969 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 204.511719 100.027344 L 206.621094 100.027344 L 206.621094 100.667969 L 204.511719 100.667969 Z M 204.511719 100.027344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 208.011719 101.871094 L 209.292969 101.871094 L 209.292969 97.433594 L 207.886719 97.714844 L 207.886719 96.996094 L 209.292969 96.714844 L 210.074219 96.714844 L 210.074219 101.871094 L 211.371094 101.871094 L 211.371094 102.542969 L 208.011719 102.542969 Z M 208.011719 101.871094 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 194.914062 106.164062 C 194.558594 106.769531 194.296875 107.363281 194.132812 107.945312 C 193.964844 108.53125 193.882812 109.125 193.882812 109.726562 C 193.882812 110.332031 193.964844 110.925781 194.132812 111.523438 C 194.308594 112.109375 194.570312 112.699219 194.914062 113.300781 L 194.289062 113.300781 C 193.890625 112.6875 193.59375 112.085938 193.398438 111.492188 C 193.210938 110.898438 193.117188 110.3125 193.117188 109.726562 C 193.117188 109.144531 193.210938 108.5625 193.398438 107.976562 C 193.59375 107.382812 193.890625 106.78125 194.289062 106.164062 Z M 194.914062 106.164062 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 195.992188 107.867188 L 199.414062 107.867188 L 199.414062 108.523438 L 196.710938 111.664062 L 199.414062 111.664062 L 199.414062 112.242188 L 195.898438 112.242188 L 195.898438 111.585938 L 198.601562 108.445312 L 195.992188 108.445312 Z M 195.992188 107.867188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 200.148438 109.726562 L 202.257812 109.726562 L 202.257812 110.367188 L 200.148438 110.367188 Z M 200.148438 109.726562 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 203.648438 111.570312 L 204.929688 111.570312 L 204.929688 107.132812 L 203.523438 107.414062 L 203.523438 106.695312 L 204.929688 106.414062 L 205.710938 106.414062 L 205.710938 111.570312 L 207.007812 111.570312 L 207.007812 112.242188 L 203.648438 112.242188 Z M 203.648438 111.570312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 208.382812 106.164062 L 209.007812 106.164062 C 209.402344 106.78125 209.695312 107.382812 209.882812 107.976562 C 210.078125 108.5625 210.179688 109.144531 210.179688 109.726562 C 210.179688 110.3125 210.078125 110.898438 209.882812 111.492188 C 209.695312 112.085938 209.402344 112.6875 209.007812 113.300781 L 208.382812 113.300781 C 208.726562 112.699219 208.980469 112.109375 209.148438 111.523438 C 209.324219 110.925781 209.414062 110.332031 209.414062 109.726562 C 209.414062 109.125 209.324219 108.53125 209.148438 107.945312 C 208.980469 107.363281 208.726562 106.769531 208.382812 106.164062 Z M 208.382812 106.164062 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 211.820312 108.621094 L 213.554688 108.621094 L 213.554688 109.042969 L 211.226562 109.042969 L 211.226562 108.621094 C 211.414062 108.433594 211.667969 108.175781 211.992188 107.855469 C 212.3125 107.523438 212.515625 107.308594 212.601562 107.214844 C 212.765625 107.039062 212.882812 106.882812 212.945312 106.757812 C 213.007812 106.632812 213.039062 106.519531 213.039062 106.402344 C 213.039062 106.207031 212.96875 106.050781 212.835938 105.933594 C 212.699219 105.808594 212.523438 105.746094 212.304688 105.746094 C 212.148438 105.746094 211.980469 105.773438 211.804688 105.824219 C 211.636719 105.878906 211.453125 105.960938 211.257812 106.074219 L 211.257812 105.574219 C 211.453125 105.492188 211.636719 105.425781 211.804688 105.382812 C 211.980469 105.34375 212.140625 105.324219 212.289062 105.324219 C 212.664062 105.324219 212.960938 105.425781 213.179688 105.621094 C 213.40625 105.808594 213.523438 106.058594 213.523438 106.371094 C 213.523438 106.519531 213.496094 106.660156 213.445312 106.792969 C 213.390625 106.925781 213.289062 107.089844 213.132812 107.277344 C 213.089844 107.320312 212.960938 107.457031 212.742188 107.683594 C 212.53125 107.914062 212.226562 108.226562 211.820312 108.621094 Z M 211.820312 108.621094 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 177.914062 103.964844 L 179.429688 103.964844 L 179.429688 105.867188 L 177.914062 105.867188 Z M 177.914062 103.964844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 179.425781 104.925781 L 178.484375 105.660156 L 177.542969 106.382812 L 177.542969 103.46875 L 178.484375 104.203125 Z M 179.425781 104.925781 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 182.5 108.988281 L 184.402344 108.988281 L 184.402344 110.503906 L 182.5 110.503906 Z M 182.5 108.988281 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 183.460938 108.988281 L 184.1875 109.933594 L 184.917969 110.875 L 182.003906 110.875 L 182.730469 109.933594 Z M 183.460938 108.988281 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.947676;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M -179.679688 -104.902344 C -179.679688 -102.820312 -181.359375 -101.136719 -183.429688 -101.136719 C -185.5 -101.136719 -187.179688 -102.820312 -187.179688 -104.902344 C -187.179688 -106.980469 -185.5 -108.664062 -183.429688 -108.664062 C -181.359375 -108.664062 -179.679688 -106.980469 -179.679688 -104.902344 Z M -179.679688 -104.902344 " transform="matrix(-1,0,0,-1,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 182.933594 107.570312 L 182.933594 105.398438 L 180.761719 105.398438 L 180.761719 104.726562 L 182.933594 104.726562 L 182.933594 102.550781 L 183.589844 102.550781 L 183.589844 104.726562 L 185.777344 104.726562 L 185.777344 105.398438 L 183.589844 105.398438 L 183.589844 107.570312 Z M 182.933594 107.570312 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 164.6875 107.570312 L 164.6875 102.40625 L 172.589844 102.40625 L 175.148438 104.925781 L 172.523438 107.503906 Z M 164.6875 107.570312 "/>
<path style=" stroke:none;fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 248.761719 107.65625 L 248.761719 102.5 L 256.667969 102.5 L 259.226562 105.011719 L 256.601562 107.65625 Z M 248.761719 107.65625 "/>
<g clip-path="url(#clip3)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 248.761719 107.65625 L 248.761719 102.5 L 256.667969 102.5 L 259.226562 105.011719 L 256.601562 107.65625 Z M 248.761719 107.65625 "/>
</g>
<path style=" stroke:none;fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 229.289062 111.269531 L 242.289062 111.21875 L 242.289062 98.472656 L 229.289062 98.519531 Z M 229.289062 111.269531 "/>
<g clip-path="url(#clip4)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 229.289062 111.269531 L 242.289062 111.21875 L 242.289062 98.472656 L 229.289062 98.519531 Z M 229.289062 111.269531 "/>
</g>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 230.769531 103.992188 L 234.191406 103.992188 L 234.191406 104.648438 L 231.488281 107.789062 L 234.191406 107.789062 L 234.191406 108.367188 L 230.675781 108.367188 L 230.675781 107.710938 L 233.378906 104.570312 L 230.769531 104.570312 Z M 230.769531 103.992188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 236.441406 103.601562 L 237.753906 103.601562 L 237.753906 103.992188 L 236.441406 103.992188 Z M 236.441406 103.601562 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 238.695312 104.742188 L 239.492188 104.742188 L 239.492188 101.960938 L 238.617188 102.148438 L 238.617188 101.695312 L 239.492188 101.523438 L 239.992188 101.523438 L 239.992188 104.742188 L 240.789062 104.742188 L 240.789062 105.164062 L 238.695312 105.164062 Z M 238.695312 104.742188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 244.761719 103.71875 C 245.386719 103.71875 245.890625 104.226562 245.890625 104.851562 C 245.890625 105.46875 245.386719 105.980469 244.761719 105.980469 C 244.136719 105.980469 243.632812 105.46875 243.632812 104.851562 C 243.632812 104.226562 244.136719 103.71875 244.761719 103.71875 Z M 244.761719 103.71875 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 178.726562 110.273438 L 181.367188 110.273438 L 181.367188 111.070312 L 178.726562 111.070312 Z M 178.726562 110.273438 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 252.917969 94.441406 C 252.34375 94.441406 251.886719 94.65625 251.542969 95.082031 C 251.207031 95.507812 251.042969 96.089844 251.042969 96.832031 C 251.042969 97.5625 251.207031 98.136719 251.542969 98.566406 C 251.886719 98.996094 252.34375 99.207031 252.917969 99.207031 C 253.488281 99.207031 253.941406 98.996094 254.277344 98.566406 C 254.609375 98.136719 254.777344 97.5625 254.777344 96.832031 C 254.777344 96.089844 254.609375 95.507812 254.277344 95.082031 C 253.941406 94.65625 253.488281 94.441406 252.917969 94.441406 Z M 254.027344 99.628906 L 255.058594 100.769531 L 254.105469 100.769531 L 253.246094 99.832031 C 253.160156 99.839844 253.09375 99.84375 253.042969 99.84375 C 253 99.84375 252.957031 99.84375 252.917969 99.84375 C 252.09375 99.84375 251.4375 99.578125 250.949219 99.035156 C 250.457031 98.484375 250.214844 97.75 250.214844 96.832031 C 250.214844 95.90625 250.457031 95.171875 250.949219 94.628906 C 251.4375 94.078125 252.09375 93.800781 252.917969 93.800781 C 253.730469 93.800781 254.378906 94.078125 254.871094 94.628906 C 255.359375 95.171875 255.605469 95.90625 255.605469 96.832031 C 255.605469 97.507812 255.46875 98.089844 255.199219 98.566406 C 254.925781 99.046875 254.535156 99.402344 254.027344 99.628906 Z M 254.027344 99.628906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 167.042969 95.503906 L 167.042969 100.035156 L 167.996094 100.035156 C 168.796875 100.035156 169.386719 99.855469 169.761719 99.488281 C 170.136719 99.125 170.324219 98.550781 170.324219 97.769531 C 170.324219 96.988281 170.136719 96.417969 169.761719 96.050781 C 169.386719 95.6875 168.796875 95.503906 167.996094 95.503906 Z M 166.246094 94.863281 L 167.871094 94.863281 C 169.003906 94.863281 169.832031 95.09375 170.355469 95.566406 C 170.886719 96.035156 171.152344 96.769531 171.152344 97.769531 C 171.152344 98.769531 170.886719 99.507812 170.355469 99.988281 C 169.824219 100.457031 168.996094 100.691406 167.871094 100.691406 L 166.246094 100.691406 Z M 166.246094 94.863281 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.835201;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 247.949633 104.512088 L 243.016974 107.354602 L 238.088581 110.201014 L 238.089514 98.8182 L 243.01744 101.663195 Z M 247.949633 104.512088 " transform="matrix(0.917479,0.00212533,-0.0019838,1,0,0)"/>
<path style="fill:none;stroke-width:0.4;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 219.480469 107.113281 L 220.777344 107.113281 L 220.777344 105.109375 L 220.78125 103.101562 L 222.078125 103.101562 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 169.484375 81.535156 L 169.484375 82.550781 C 169.171875 82.375 168.863281 82.246094 168.5625 82.160156 C 168.257812 82.078125 167.953125 82.035156 167.640625 82.035156 C 166.929688 82.035156 166.382812 82.257812 166 82.707031 C 165.613281 83.144531 165.421875 83.761719 165.421875 84.566406 C 165.421875 85.371094 165.613281 85.996094 166 86.441406 C 166.382812 86.878906 166.929688 87.09375 167.640625 87.09375 C 167.953125 87.09375 168.257812 87.058594 168.5625 86.96875 C 168.863281 86.886719 169.171875 86.761719 169.484375 86.59375 L 169.484375 87.59375 C 169.179688 87.734375 168.867188 87.839844 168.546875 87.910156 C 168.222656 87.980469 167.878906 88.019531 167.515625 88.019531 C 166.523438 88.019531 165.738281 87.714844 165.15625 87.09375 C 164.570312 86.46875 164.28125 85.628906 164.28125 84.566406 C 164.28125 83.503906 164.570312 82.667969 165.15625 82.050781 C 165.75 81.4375 166.5625 81.128906 167.59375 81.128906 C 167.914062 81.128906 168.234375 81.167969 168.546875 81.238281 C 168.867188 81.300781 169.179688 81.402344 169.484375 81.535156 Z M 169.484375 81.535156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 171.203125 78.738281 L 172.140625 78.738281 C 172.722656 79.667969 173.160156 80.574219 173.453125 81.457031 C 173.742188 82.332031 173.890625 83.207031 173.890625 84.082031 C 173.890625 84.957031 173.742188 85.839844 173.453125 86.71875 C 173.160156 87.609375 172.722656 88.507812 172.140625 89.425781 L 171.203125 89.425781 C 171.710938 88.527344 172.097656 87.636719 172.359375 86.753906 C 172.617188 85.871094 172.75 84.980469 172.75 84.082031 C 172.75 83.175781 172.617188 82.285156 172.359375 81.410156 C 172.097656 80.527344 171.710938 79.632812 171.203125 78.738281 Z M 171.203125 78.738281 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 198.125 60.363281 L 179.601562 60.363281 C 179.601562 60.363281 178.101562 59.855469 178.101562 58.863281 L 178.101562 29.296875 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M -35.882812 177.691406 C -35.882812 178.214844 -36.179688 178.703125 -36.664062 178.964844 C -37.148438 179.230469 -37.738281 179.230469 -38.226562 178.964844 C -38.710938 178.703125 -39.007812 178.214844 -39.007812 177.691406 " transform="matrix(0,-1,1,0,0,0)"/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 172.179688 -37.515625 L 197.75 -37.515625 " transform="matrix(1,0,0,-1,0,0)"/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 182.003906 -37.488281 L 182.003906 -51.113281 C 182.003906 -51.113281 182.511719 -52.613281 183.503906 -52.613281 L 231.421875 -52.613281 " transform="matrix(1,0,0,-1,0,0)"/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 170.058594 29.398438 L 217.203125 29.398438 C 217.203125 29.398438 218.703125 29.902344 218.703125 30.898438 L 218.703125 51.113281 "/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.947676;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 223 52.59375 C 223 54.96875 221.082031 56.894531 218.714844 56.894531 C 216.347656 56.894531 214.425781 54.96875 214.425781 52.59375 C 214.425781 50.214844 216.347656 48.289062 218.714844 48.289062 C 221.082031 48.289062 223 50.214844 223 52.59375 Z M 223 52.59375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 219.148438 49.734375 L 219.148438 52.1875 L 221.601562 52.1875 L 221.601562 52.921875 L 219.148438 52.921875 L 219.148438 55.375 L 218.414062 55.375 L 218.414062 52.921875 L 215.960938 52.921875 L 215.960938 52.1875 L 218.414062 52.1875 L 218.414062 49.734375 Z M 219.148438 49.734375 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.920908;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 262.113084 41.820312 L 278.506151 41.761719 L 278.506151 25.433594 L 262.113084 25.492188 Z M 262.113084 41.820312 " transform="matrix(0.754654,0,0,1,0,0)"/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.806373;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 204.2208 37.097213 L 202.694738 37.979363 L 201.168669 38.857606 L 201.168988 35.334168 Z M 204.2208 37.097213 " transform="matrix(0.984252,0.00212533,-0.00212817,1,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 200.769531 28.199219 L 200.769531 30.855469 L 201.175781 30.855469 C 201.644531 30.855469 201.996094 30.746094 202.238281 30.527344 C 202.476562 30.300781 202.597656 29.964844 202.597656 29.527344 C 202.597656 29.089844 202.476562 28.757812 202.238281 28.542969 C 201.996094 28.316406 201.644531 28.199219 201.175781 28.199219 Z M 199.644531 27.339844 L 200.832031 27.339844 C 201.496094 27.339844 201.992188 27.382812 202.316406 27.480469 C 202.648438 27.574219 202.929688 27.738281 203.160156 27.964844 C 203.367188 28.164062 203.519531 28.394531 203.613281 28.652344 C 203.714844 28.902344 203.769531 29.195312 203.769531 29.527344 C 203.769531 29.851562 203.714844 30.144531 203.613281 30.402344 C 203.519531 30.664062 203.367188 30.894531 203.160156 31.089844 C 202.917969 31.320312 202.632812 31.480469 202.300781 31.574219 C 201.976562 31.667969 201.488281 31.714844 200.832031 31.714844 L 199.644531 31.714844 Z M 199.644531 27.339844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 206.953125 39.839844 L 206.332031 38.9375 L 205.707031 38.027344 L 208.199219 38.027344 L 207.578125 38.9375 Z M 206.953125 39.839844 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 202.175781 39.738281 L 203.9375 39.738281 L 203.9375 35.03125 L 206.945312 35.03125 L 206.945312 39.734375 L 208.683594 39.734375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 203.9375 34.914062 L 204.5625 35.820312 L 205.183594 36.730469 L 202.691406 36.730469 L 203.3125 35.820312 Z M 203.9375 34.914062 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 227.546875 50.445312 L 227.546875 54.875 L 234.480469 54.875 L 236.722656 52.71875 L 234.421875 50.503906 Z M 227.546875 50.445312 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 164.199219 35.339844 L 164.199219 39.765625 L 171.132812 39.765625 L 173.378906 37.609375 L 171.078125 35.394531 Z M 164.199219 35.339844 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 164.199219 27.136719 L 164.199219 31.5625 L 171.132812 31.5625 L 173.378906 29.40625 L 171.078125 27.195312 Z M 164.199219 27.136719 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.920908;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 262.113084 64.625 L 278.506151 64.5625 L 278.506151 48.238281 L 262.113084 48.300781 Z M 262.113084 64.625 " transform="matrix(0.754654,0,0,1,0,0)"/>
<path style="fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.806373;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 204.2701 59.89789 L 201.217977 61.662189 L 201.218296 58.138751 Z M 204.2701 59.89789 " transform="matrix(0.984252,0.00212533,-0.00212817,1,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 200.769531 51 L 200.769531 53.65625 L 201.175781 53.65625 C 201.644531 53.65625 201.996094 53.546875 202.238281 53.328125 C 202.476562 53.101562 202.597656 52.761719 202.597656 52.328125 C 202.597656 51.886719 202.476562 51.5625 202.238281 51.339844 C 201.996094 51.117188 201.644531 51 201.175781 51 Z M 199.644531 50.136719 L 200.832031 50.136719 C 201.496094 50.136719 201.992188 50.1875 202.316406 50.28125 C 202.648438 50.375 202.929688 50.539062 203.160156 50.761719 C 203.367188 50.964844 203.519531 51.195312 203.613281 51.453125 C 203.714844 51.703125 203.769531 51.996094 203.769531 52.328125 C 203.769531 52.652344 203.714844 52.945312 203.613281 53.203125 C 203.519531 53.464844 203.367188 53.695312 203.160156 53.886719 C 202.917969 54.121094 202.632812 54.28125 202.300781 54.375 C 201.976562 54.464844 201.488281 54.511719 200.832031 54.511719 L 199.644531 54.511719 Z M 199.644531 50.136719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 206.953125 62.648438 L 206.332031 61.738281 L 205.707031 60.832031 L 208.199219 60.832031 L 207.578125 61.738281 Z M 206.953125 62.648438 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 202.175781 62.539062 L 203.9375 62.539062 L 203.9375 57.835938 L 206.945312 57.835938 L 206.945312 62.53125 L 208.683594 62.53125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 203.9375 57.714844 L 204.5625 58.625 L 205.183594 59.53125 L 202.691406 59.53125 L 203.3125 58.625 Z M 203.9375 57.714844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 182.007812 38.851562 C 181.296875 38.851562 180.71875 38.273438 180.71875 37.558594 C 180.71875 36.84375 181.296875 36.269531 182.007812 36.269531 C 182.722656 36.269531 183.296875 36.84375 183.296875 37.558594 C 183.296875 38.273438 182.722656 38.851562 182.007812 38.851562 Z M 182.007812 38.851562 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 178.066406 30.675781 C 177.355469 30.675781 176.777344 30.09375 176.777344 29.382812 C 176.777344 28.671875 177.355469 28.089844 178.066406 28.089844 C 178.78125 28.089844 179.359375 28.671875 179.359375 29.382812 C 179.359375 30.09375 178.78125 30.675781 178.066406 30.675781 Z M 178.066406 30.675781 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 165.046875 42.675781 L 165.046875 47.769531 L 166.125 47.769531 C 167.03125 47.769531 167.691406 47.566406 168.109375 47.160156 C 168.535156 46.753906 168.75 46.109375 168.75 45.21875 C 168.75 44.339844 168.535156 43.691406 168.109375 43.285156 C 167.691406 42.878906 167.03125 42.675781 166.125 42.675781 Z M 164.171875 41.941406 L 165.984375 41.941406 C 167.253906 41.941406 168.1875 42.207031 168.78125 42.738281 C 169.382812 43.269531 169.6875 44.09375 169.6875 45.21875 C 169.6875 46.34375 169.382812 47.175781 168.78125 47.707031 C 168.1875 48.238281 167.253906 48.503906 165.984375 48.503906 L 164.171875 48.503906 Z M 164.171875 41.941406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 170.910156 45.957031 L 171.503906 45.957031 L 171.503906 50.332031 L 170.910156 50.332031 Z M 170.910156 45.957031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 164.585938 18.042969 L 164.585938 23.132812 L 165.664062 23.132812 C 166.570312 23.132812 167.230469 22.933594 167.648438 22.527344 C 168.074219 22.121094 168.289062 21.476562 168.289062 20.589844 C 168.289062 19.707031 168.074219 19.058594 167.648438 18.652344 C 167.230469 18.246094 166.570312 18.042969 165.664062 18.042969 Z M 163.710938 17.308594 L 165.523438 17.308594 C 166.792969 17.308594 167.726562 17.574219 168.320312 18.105469 C 168.921875 18.632812 169.226562 19.464844 169.226562 20.589844 C 169.226562 21.714844 168.921875 22.542969 168.320312 23.074219 C 167.726562 23.605469 166.792969 23.871094 165.523438 23.871094 L 163.710938 23.871094 Z M 163.710938 17.308594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 172.214844 21.734375 C 171.785156 21.734375 171.449219 21.898438 171.199219 22.214844 C 170.949219 22.53125 170.824219 22.964844 170.824219 23.511719 C 170.824219 24.070312 170.949219 24.507812 171.199219 24.828125 C 171.449219 25.152344 171.785156 25.3125 172.214844 25.3125 C 172.652344 25.3125 172.996094 25.152344 173.246094 24.828125 C 173.496094 24.507812 173.621094 24.070312 173.621094 23.511719 C 173.621094 22.964844 173.496094 22.53125 173.246094 22.214844 C 172.996094 21.898438 172.652344 21.734375 172.214844 21.734375 Z M 173.042969 25.625 L 173.824219 26.484375 L 173.121094 26.484375 L 172.464844 25.78125 C 172.402344 25.78125 172.347656 25.78125 172.308594 25.78125 C 172.277344 25.78125 172.246094 25.78125 172.214844 25.78125 C 171.597656 25.78125 171.109375 25.578125 170.746094 25.171875 C 170.378906 24.757812 170.199219 24.203125 170.199219 23.511719 C 170.199219 22.828125 170.378906 22.28125 170.746094 21.875 C 171.109375 21.460938 171.597656 21.25 172.214844 21.25 C 172.828125 21.25 173.316406 21.460938 173.683594 21.875 C 174.058594 22.28125 174.246094 22.828125 174.246094 23.511719 C 174.246094 24.027344 174.140625 24.464844 173.933594 24.828125 C 173.734375 25.183594 173.4375 25.449219 173.042969 25.625 Z M 173.042969 25.625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 225.171875 41.570312 L 225.171875 46.664062 L 226.25 46.664062 C 227.15625 46.664062 227.816406 46.460938 228.234375 46.050781 C 228.660156 45.648438 228.875 45.003906 228.875 44.117188 C 228.875 43.234375 228.660156 42.585938 228.234375 42.175781 C 227.816406 41.773438 227.15625 41.570312 226.25 41.570312 Z M 224.296875 40.835938 L 226.109375 40.835938 C 227.378906 40.835938 228.3125 41.101562 228.90625 41.632812 C 229.507812 42.164062 229.8125 42.992188 229.8125 44.117188 C 229.8125 45.242188 229.507812 46.070312 228.90625 46.601562 C 228.3125 47.132812 227.378906 47.398438 226.109375 47.398438 L 224.296875 47.398438 Z M 224.296875 40.835938 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 231.628906 45.339844 L 231.628906 46.980469 L 232.363281 46.980469 C 232.644531 46.980469 232.855469 46.914062 233.003906 46.777344 C 233.160156 46.632812 233.238281 46.425781 233.238281 46.167969 C 233.238281 45.910156 233.160156 45.707031 233.003906 45.558594 C 232.855469 45.414062 232.644531 45.339844 232.363281 45.339844 Z M 231.035156 44.855469 L 232.363281 44.855469 C 232.851562 44.855469 233.222656 44.96875 233.472656 45.199219 C 233.722656 45.417969 233.847656 45.742188 233.847656 46.167969 C 233.847656 46.59375 233.722656 46.917969 233.472656 47.132812 C 233.222656 47.355469 232.851562 47.464844 232.363281 47.464844 L 231.628906 47.464844 L 231.628906 49.230469 L 231.035156 49.230469 Z M 231.035156 44.855469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 235.214844 45.339844 L 235.214844 46.980469 L 235.949219 46.980469 C 236.230469 46.980469 236.441406 46.914062 236.589844 46.777344 C 236.746094 46.632812 236.824219 46.425781 236.824219 46.167969 C 236.824219 45.910156 236.746094 45.707031 236.589844 45.558594 C 236.441406 45.414062 236.230469 45.339844 235.949219 45.339844 Z M 234.621094 44.855469 L 235.949219 44.855469 C 236.4375 44.855469 236.808594 44.96875 237.058594 45.199219 C 237.308594 45.417969 237.433594 45.742188 237.433594 46.167969 C 237.433594 46.59375 237.308594 46.917969 237.058594 47.132812 C 236.808594 47.355469 236.4375 47.464844 235.949219 47.464844 L 235.214844 47.464844 L 235.214844 49.230469 L 234.621094 49.230469 Z M 234.621094 44.855469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 168.472656 8.675781 C 168.472656 7.886719 168.304688 7.269531 167.972656 6.820312 C 167.648438 6.375 167.207031 6.148438 166.644531 6.148438 C 166.070312 6.148438 165.617188 6.375 165.285156 6.820312 C 164.960938 7.269531 164.800781 7.886719 164.800781 8.675781 C 164.800781 9.46875 164.960938 10.09375 165.285156 10.550781 C 165.617188 11.003906 166.070312 11.226562 166.644531 11.226562 C 167.207031 11.226562 167.648438 11.003906 167.972656 10.550781 C 168.304688 10.09375 168.472656 9.46875 168.472656 8.675781 Z M 164.800781 6.398438 C 165.027344 6.003906 165.316406 5.710938 165.660156 5.523438 C 166.003906 5.335938 166.414062 5.242188 166.894531 5.242188 C 167.695312 5.242188 168.347656 5.5625 168.847656 6.195312 C 169.347656 6.820312 169.597656 7.648438 169.597656 8.675781 C 169.597656 9.710938 169.347656 10.546875 168.847656 11.175781 C 168.347656 11.816406 167.695312 12.132812 166.894531 12.132812 C 166.414062 12.132812 166.003906 12.039062 165.660156 11.851562 C 165.316406 11.65625 165.027344 11.363281 164.800781 10.976562 L 164.800781 11.960938 L 163.722656 11.960938 L 163.722656 2.835938 L 164.800781 2.835938 Z M 164.800781 6.398438 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 171.214844 2.851562 L 172.152344 2.851562 C 172.734375 3.78125 173.171875 4.6875 173.464844 5.570312 C 173.753906 6.445312 173.902344 7.320312 173.902344 8.195312 C 173.902344 9.070312 173.753906 9.953125 173.464844 10.835938 C 173.171875 11.71875 172.734375 12.621094 172.152344 13.539062 L 171.214844 13.539062 C 171.722656 12.636719 172.109375 11.753906 172.371094 10.867188 C 172.628906 9.984375 172.761719 9.089844 172.761719 8.195312 C 172.761719 7.289062 172.628906 6.398438 172.371094 5.523438 C 172.109375 4.636719 171.722656 3.75 171.214844 2.851562 Z M 171.214844 2.851562 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 191.351562 58.058594 L 189.039062 62.171875 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 191.460938 35.507812 L 189.148438 39.617188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 187.121094 40.257812 L 187.714844 40.257812 L 188.449219 42.246094 L 189.199219 40.257812 L 189.792969 40.257812 L 189.792969 43.183594 L 189.402344 43.183594 L 189.402344 40.621094 L 188.652344 42.621094 L 188.261719 42.621094 L 187.511719 40.621094 L 187.511719 43.183594 L 187.121094 43.183594 Z M 187.121094 40.257812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 192.054688 40.355469 L 192.054688 40.746094 C 191.90625 40.675781 191.765625 40.621094 191.632812 40.589844 C 191.496094 40.550781 191.367188 40.527344 191.242188 40.527344 C 191.03125 40.527344 190.867188 40.570312 190.742188 40.652344 C 190.625 40.738281 190.570312 40.855469 190.570312 41.007812 C 190.570312 41.148438 190.605469 41.246094 190.679688 41.308594 C 190.761719 41.371094 190.914062 41.425781 191.132812 41.464844 L 191.367188 41.507812 C 191.65625 41.574219 191.871094 41.675781 192.007812 41.824219 C 192.152344 41.960938 192.226562 42.144531 192.226562 42.371094 C 192.226562 42.664062 192.132812 42.882812 191.945312 43.027344 C 191.757812 43.175781 191.480469 43.246094 191.117188 43.246094 C 190.980469 43.246094 190.835938 43.230469 190.679688 43.199219 C 190.523438 43.167969 190.359375 43.121094 190.195312 43.058594 L 190.195312 42.652344 C 190.351562 42.738281 190.507812 42.800781 190.664062 42.855469 C 190.820312 42.898438 190.96875 42.917969 191.117188 42.917969 C 191.335938 42.917969 191.507812 42.878906 191.632812 42.792969 C 191.757812 42.699219 191.820312 42.570312 191.820312 42.402344 C 191.820312 42.269531 191.773438 42.160156 191.679688 42.074219 C 191.59375 41.992188 191.453125 41.925781 191.257812 41.882812 L 191.007812 41.839844 C 190.714844 41.789062 190.5 41.699219 190.367188 41.574219 C 190.242188 41.449219 190.179688 41.273438 190.179688 41.042969 C 190.179688 40.785156 190.265625 40.582031 190.445312 40.433594 C 190.632812 40.289062 190.882812 40.214844 191.195312 40.214844 C 191.339844 40.214844 191.480469 40.230469 191.617188 40.257812 C 191.761719 40.285156 191.90625 40.316406 192.054688 40.355469 Z M 192.054688 40.355469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 193.035156 41.792969 L 193.035156 42.855469 L 193.675781 42.855469 C 193.882812 42.855469 194.039062 42.816406 194.144531 42.730469 C 194.246094 42.632812 194.300781 42.503906 194.300781 42.324219 C 194.300781 42.132812 194.246094 42.003906 194.144531 41.917969 C 194.039062 41.835938 193.882812 41.792969 193.675781 41.792969 Z M 193.035156 40.589844 L 193.035156 41.464844 L 193.628906 41.464844 C 193.816406 41.464844 193.957031 41.425781 194.050781 41.355469 C 194.144531 41.285156 194.191406 41.175781 194.191406 41.027344 C 194.191406 40.882812 194.144531 40.773438 194.050781 40.699219 C 193.957031 40.628906 193.816406 40.589844 193.628906 40.589844 Z M 192.644531 40.257812 L 193.660156 40.257812 C 193.960938 40.257812 194.191406 40.324219 194.347656 40.449219 C 194.511719 40.574219 194.597656 40.753906 194.597656 40.980469 C 194.597656 41.167969 194.554688 41.316406 194.472656 41.417969 C 194.386719 41.523438 194.261719 41.585938 194.097656 41.605469 C 194.292969 41.648438 194.445312 41.738281 194.550781 41.871094 C 194.664062 42.007812 194.722656 42.175781 194.722656 42.371094 C 194.722656 42.632812 194.632812 42.835938 194.457031 42.980469 C 194.277344 43.117188 194.023438 43.183594 193.691406 43.183594 L 192.644531 43.183594 Z M 192.644531 40.257812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 186.40625 63.4375 L 187 63.4375 L 187.734375 65.421875 L 188.484375 63.4375 L 189.078125 63.4375 L 189.078125 66.359375 L 188.6875 66.359375 L 188.6875 63.796875 L 187.9375 65.796875 L 187.546875 65.796875 L 186.796875 63.796875 L 186.796875 66.359375 L 186.40625 66.359375 Z M 186.40625 63.4375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 191.34375 63.53125 L 191.34375 63.921875 C 191.195312 63.851562 191.054688 63.796875 190.921875 63.761719 C 190.785156 63.726562 190.65625 63.703125 190.53125 63.703125 C 190.320312 63.703125 190.15625 63.746094 190.03125 63.828125 C 189.914062 63.914062 189.859375 64.03125 189.859375 64.1875 C 189.859375 64.324219 189.894531 64.421875 189.96875 64.484375 C 190.050781 64.546875 190.203125 64.601562 190.421875 64.636719 L 190.65625 64.6875 C 190.945312 64.75 191.160156 64.855469 191.296875 65 C 191.441406 65.132812 191.515625 65.320312 191.515625 65.546875 C 191.515625 65.839844 191.421875 66.058594 191.234375 66.203125 C 191.046875 66.351562 190.769531 66.421875 190.40625 66.421875 C 190.269531 66.421875 190.125 66.40625 189.96875 66.375 C 189.8125 66.339844 189.648438 66.296875 189.484375 66.234375 L 189.484375 65.828125 C 189.640625 65.914062 189.796875 65.980469 189.953125 66.03125 C 190.109375 66.074219 190.257812 66.089844 190.40625 66.089844 C 190.625 66.089844 190.796875 66.050781 190.921875 65.964844 C 191.046875 65.875 191.109375 65.746094 191.109375 65.578125 C 191.109375 65.445312 191.0625 65.335938 190.96875 65.25 C 190.882812 65.167969 190.742188 65.105469 190.546875 65.0625 L 190.296875 65.011719 C 190.003906 64.964844 189.789062 64.875 189.65625 64.75 C 189.53125 64.625 189.46875 64.449219 189.46875 64.214844 C 189.46875 63.960938 189.554688 63.757812 189.734375 63.609375 C 189.921875 63.464844 190.171875 63.386719 190.484375 63.386719 C 190.628906 63.386719 190.769531 63.40625 190.90625 63.4375 C 191.050781 63.460938 191.195312 63.492188 191.34375 63.53125 Z M 191.34375 63.53125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 192.324219 64.964844 L 192.324219 66.03125 L 192.964844 66.03125 C 193.171875 66.03125 193.328125 65.992188 193.433594 65.90625 C 193.535156 65.8125 193.589844 65.675781 193.589844 65.5 C 193.589844 65.3125 193.535156 65.175781 193.433594 65.089844 C 193.328125 65.007812 193.171875 64.964844 192.964844 64.964844 Z M 192.324219 63.761719 L 192.324219 64.636719 L 192.917969 64.636719 C 193.105469 64.636719 193.246094 64.605469 193.339844 64.53125 C 193.433594 64.460938 193.480469 64.351562 193.480469 64.203125 C 193.480469 64.058594 193.433594 63.949219 193.339844 63.875 C 193.246094 63.800781 193.105469 63.761719 192.917969 63.761719 Z M 191.933594 63.4375 L 192.949219 63.4375 C 193.25 63.4375 193.480469 63.5 193.636719 63.625 C 193.800781 63.75 193.886719 63.925781 193.886719 64.15625 C 193.886719 64.339844 193.84375 64.492188 193.761719 64.589844 C 193.675781 64.699219 193.550781 64.757812 193.386719 64.78125 C 193.582031 64.824219 193.734375 64.914062 193.839844 65.046875 C 193.953125 65.183594 194.011719 65.351562 194.011719 65.546875 C 194.011719 65.808594 193.921875 66.007812 193.746094 66.15625 C 193.566406 66.292969 193.3125 66.359375 192.980469 66.359375 L 191.933594 66.359375 Z M 191.933594 63.4375 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.4;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 186.535156 56.152344 L 193.863281 56.125 L 193.863281 48.820312 L 186.535156 48.851562 Z M 186.535156 56.152344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 188.316406 50.453125 L 188.644531 50.453125 L 188.644531 54.453125 L 188.316406 54.453125 Z M 188.316406 50.453125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 191.910156 50.453125 L 192.238281 50.453125 L 192.238281 54.453125 L 191.910156 54.453125 Z M 191.910156 50.453125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 190.21875 53.078125 C 189.921875 53.078125 189.679688 52.835938 189.679688 52.539062 C 189.679688 52.242188 189.921875 52 190.21875 52 C 190.515625 52 190.757812 52.242188 190.757812 52.539062 C 190.757812 52.835938 190.515625 53.078125 190.21875 53.078125 Z M 190.21875 53.078125 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.4;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 186.5 32.992188 L 193.828125 32.96875 L 193.828125 25.664062 L 186.5 25.691406 Z M 186.5 32.992188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 188.28125 27.292969 L 188.609375 27.292969 L 188.609375 31.292969 L 188.28125 31.292969 Z M 188.28125 27.292969 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 191.875 27.292969 L 192.203125 27.292969 L 192.203125 31.292969 L 191.875 31.292969 Z M 191.875 27.292969 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 190.183594 29.921875 C 189.882812 29.921875 189.644531 29.675781 189.644531 29.382812 C 189.644531 29.082031 189.882812 28.839844 190.183594 28.839844 C 190.480469 28.839844 190.722656 29.082031 190.722656 29.382812 C 190.722656 29.675781 190.480469 29.921875 190.183594 29.921875 Z M 190.183594 29.921875 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 12.554688 32.710938 L 26.644531 32.710938 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 22.90625 31.75 L 24.421875 31.75 L 24.421875 33.652344 L 22.90625 33.652344 Z M 22.90625 31.75 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 24.421875 32.710938 L 23.476562 33.4375 L 22.535156 34.164062 L 22.535156 31.253906 L 23.476562 31.980469 Z M 24.421875 32.710938 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 12.652344 58.054688 L 26.746094 58.054688 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 23.007812 57.136719 L 24.523438 57.136719 L 24.523438 59.039062 L 23.007812 59.039062 Z M 23.007812 57.136719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 24.519531 58.101562 L 23.578125 58.832031 L 22.636719 59.558594 L 22.636719 56.648438 Z M 24.519531 58.101562 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 12.554688 108.753906 L 26.644531 108.753906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 22.90625 107.839844 L 24.421875 107.839844 L 24.421875 109.742188 L 22.90625 109.742188 Z M 22.90625 107.839844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 24.421875 108.800781 L 23.476562 109.53125 L 22.535156 110.257812 L 22.535156 107.34375 L 23.476562 108.074219 Z M 24.421875 108.800781 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 12.804688 83.355469 L 26.894531 83.355469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 23.15625 82.441406 L 24.671875 82.441406 L 24.671875 84.339844 L 23.15625 84.339844 Z M 23.15625 82.441406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 24.671875 83.402344 L 23.726562 84.132812 L 22.785156 84.859375 L 22.785156 81.945312 L 23.726562 82.675781 Z M 24.671875 83.402344 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 39.523438 52.0625 L 90.757812 52.0625 C 91.523438 52.0625 92.257812 51.554688 92.257812 50.5625 L 92.257812 26.320312 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 38.3125 26.53125 L 130.328125 26.53125 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 124.917969 24.320312 L 124.917969 28.742188 L 131.855469 28.742188 L 134.097656 26.589844 L 131.796875 24.375 Z M 124.917969 24.320312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 96.089844 25.539062 L 97.605469 25.539062 L 97.605469 27.441406 L 96.089844 27.441406 Z M 96.089844 25.539062 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 97.601562 26.5 L 96.660156 27.226562 L 95.71875 27.957031 L 95.71875 25.042969 L 96.660156 25.769531 Z M 97.601562 26.5 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 100.171875 33.832031 L 117.539062 33.765625 L 117.539062 16.449219 L 100.171875 16.519531 Z M 100.171875 33.832031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 104.738281 23.699219 L 103.144531 28.105469 L 106.347656 28.105469 Z M 102.066406 28.757812 L 104.300781 22.933594 L 105.191406 22.933594 L 107.410156 28.757812 Z M 102.066406 28.757812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 109.296875 28.089844 L 112.15625 28.089844 L 112.15625 28.757812 L 108.390625 28.757812 L 108.390625 28.089844 L 110.265625 25.652344 L 108.390625 23.589844 L 108.390625 22.933594 L 112.078125 22.933594 L 112.078125 23.589844 L 109.296875 23.589844 L 111.171875 25.632812 Z M 109.296875 28.089844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 113.738281 25.058594 L 115.472656 25.058594 L 115.472656 25.480469 L 113.144531 25.480469 L 113.144531 25.058594 C 113.332031 24.871094 113.585938 24.617188 113.910156 24.292969 C 114.230469 23.960938 114.433594 23.746094 114.519531 23.652344 C 114.683594 23.476562 114.800781 23.324219 114.863281 23.199219 C 114.925781 23.074219 114.957031 22.957031 114.957031 22.839844 C 114.957031 22.644531 114.886719 22.488281 114.753906 22.371094 C 114.617188 22.246094 114.441406 22.183594 114.222656 22.183594 C 114.066406 22.183594 113.898438 22.210938 113.722656 22.257812 C 113.554688 22.316406 113.371094 22.398438 113.175781 22.507812 L 113.175781 22.007812 C 113.371094 21.925781 113.554688 21.867188 113.722656 21.824219 C 113.898438 21.785156 114.058594 21.757812 114.207031 21.757812 C 114.582031 21.757812 114.878906 21.863281 115.097656 22.058594 C 115.324219 22.246094 115.441406 22.496094 115.441406 22.808594 C 115.441406 22.957031 115.414062 23.09375 115.363281 23.230469 C 115.308594 23.367188 115.207031 23.527344 115.050781 23.714844 C 115.007812 23.757812 114.878906 23.894531 114.660156 24.121094 C 114.449219 24.351562 114.144531 24.664062 113.738281 25.058594 Z M 113.738281 25.058594 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 97.804688 37.738281 L 115.175781 37.671875 L 115.175781 20.363281 L 97.804688 20.429688 Z M 97.804688 37.738281 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 102.375 27.609375 L 100.78125 32.011719 L 103.984375 32.011719 Z M 99.703125 32.671875 L 101.9375 26.839844 L 102.828125 26.839844 L 105.046875 32.671875 Z M 99.703125 32.671875 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 106.933594 32 L 109.792969 32 L 109.792969 32.671875 L 106.027344 32.671875 L 106.027344 32 L 107.902344 29.5625 L 106.027344 27.5 L 106.027344 26.839844 L 109.714844 26.839844 L 109.714844 27.5 L 106.933594 27.5 L 108.808594 29.546875 Z M 106.933594 32 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 111.375 28.964844 L 113.109375 28.964844 L 113.109375 29.386719 L 110.78125 29.386719 L 110.78125 28.964844 C 110.96875 28.78125 111.222656 28.527344 111.546875 28.203125 C 111.867188 27.871094 112.070312 27.65625 112.15625 27.5625 C 112.320312 27.382812 112.4375 27.234375 112.5 27.109375 C 112.5625 26.984375 112.59375 26.867188 112.59375 26.75 C 112.59375 26.550781 112.523438 26.398438 112.390625 26.28125 C 112.253906 26.15625 112.078125 26.089844 111.859375 26.089844 C 111.703125 26.089844 111.535156 26.121094 111.359375 26.171875 C 111.191406 26.226562 111.007812 26.308594 110.8125 26.421875 L 110.8125 25.921875 C 111.007812 25.839844 111.191406 25.777344 111.359375 25.734375 C 111.535156 25.695312 111.695312 25.671875 111.84375 25.671875 C 112.21875 25.671875 112.515625 25.773438 112.734375 25.964844 C 112.960938 26.15625 113.078125 26.40625 113.078125 26.714844 C 113.078125 26.867188 113.050781 27.007812 113 27.136719 C 112.945312 27.277344 112.84375 27.4375 112.6875 27.625 C 112.644531 27.667969 112.515625 27.800781 112.296875 28.03125 C 112.085938 28.257812 111.78125 28.574219 111.375 28.964844 Z M 111.375 28.964844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 84.917969 51.09375 L 86.433594 51.09375 L 86.433594 52.996094 L 84.917969 52.996094 Z M 84.917969 51.09375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 84.921875 52.058594 L 85.863281 52.785156 L 86.808594 53.511719 L 86.808594 50.601562 L 85.863281 51.328125 Z M 84.921875 52.058594 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.363281 60.570312 L 84.734375 60.503906 L 84.734375 43.195312 L 67.363281 43.261719 Z M 67.363281 60.570312 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 70.339844 57.199219 L 78.910156 57.199219 L 78.910156 54.480469 L 82.367188 54.480469 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 70.359375 47.242188 L 78.929688 47.242188 L 78.929688 49.972656 L 82.390625 49.972656 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 70.390625 54.847656 C 70.792969 56.113281 71.308594 57.355469 71.894531 57.089844 C 72.535156 56.726562 73.007812 55.074219 73.441406 53.585938 C 74.003906 51.640625 74.5 49.367188 75.207031 47.980469 C 75.457031 47.507812 75.742188 47.238281 76.050781 47.347656 C 76.714844 47.71875 77.1875 49.363281 77.621094 50.859375 L 78.308594 53.386719 C 78.527344 54.03125 78.804688 54.675781 79.121094 54.539062 C 79.464844 54.351562 79.722656 53.503906 79.957031 52.738281 C 80.261719 51.734375 80.527344 51.058594 80.910156 50.34375 C 81.046875 50.101562 81.203125 49.960938 81.367188 50.015625 C 81.726562 50.207031 81.980469 51.058594 82.214844 51.820312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 125.609375 31.375 L 125.609375 36.464844 L 126.6875 36.464844 C 127.59375 36.464844 128.253906 36.261719 128.671875 35.859375 C 129.097656 35.453125 129.3125 34.808594 129.3125 33.921875 C 129.3125 33.039062 129.097656 32.386719 128.671875 31.984375 C 128.253906 31.578125 127.59375 31.375 126.6875 31.375 Z M 124.734375 30.636719 L 126.546875 30.636719 C 127.816406 30.636719 128.75 30.90625 129.34375 31.4375 C 129.945312 31.964844 130.25 32.796875 130.25 33.921875 C 130.25 35.046875 129.945312 35.875 129.34375 36.40625 C 128.75 36.9375 127.816406 37.203125 126.546875 37.203125 L 124.734375 37.203125 Z M 124.734375 30.636719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 132.613281 36.453125 L 135.707031 36.453125 L 135.707031 37.203125 L 131.535156 37.203125 L 131.535156 36.453125 C 131.878906 36.109375 132.335938 35.648438 132.910156 35.0625 C 133.492188 34.464844 133.863281 34.089844 134.019531 33.921875 C 134.300781 33.601562 134.492188 33.328125 134.597656 33.109375 C 134.710938 32.882812 134.769531 32.664062 134.769531 32.453125 C 134.769531 32.101562 134.648438 31.8125 134.410156 31.589844 C 134.167969 31.375 133.851562 31.261719 133.457031 31.261719 C 133.175781 31.261719 132.878906 31.320312 132.566406 31.421875 C 132.261719 31.511719 131.933594 31.664062 131.582031 31.859375 L 131.582031 30.953125 C 131.933594 30.820312 132.269531 30.714844 132.582031 30.636719 C 132.894531 30.558594 133.179688 30.511719 133.441406 30.511719 C 134.117188 30.511719 134.660156 30.6875 135.066406 31.03125 C 135.472656 31.375 135.675781 31.828125 135.675781 32.386719 C 135.675781 32.664062 135.621094 32.921875 135.519531 33.171875 C 135.414062 33.414062 135.230469 33.695312 134.972656 34.011719 C 134.898438 34.101562 134.664062 34.339844 134.269531 34.75 C 133.871094 35.15625 133.320312 35.726562 132.613281 36.453125 Z M 132.613281 36.453125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 139.058594 35.066406 C 138.628906 35.066406 138.292969 35.230469 138.042969 35.550781 C 137.792969 35.863281 137.667969 36.296875 137.667969 36.84375 C 137.667969 37.402344 137.792969 37.839844 138.042969 38.160156 C 138.292969 38.484375 138.628906 38.644531 139.058594 38.644531 C 139.496094 38.644531 139.839844 38.484375 140.089844 38.160156 C 140.339844 37.839844 140.464844 37.402344 140.464844 36.84375 C 140.464844 36.296875 140.339844 35.863281 140.089844 35.550781 C 139.839844 35.230469 139.496094 35.066406 139.058594 35.066406 Z M 139.886719 38.957031 L 140.667969 39.816406 L 139.964844 39.816406 L 139.308594 39.113281 C 139.246094 39.113281 139.191406 39.113281 139.152344 39.113281 C 139.121094 39.113281 139.089844 39.113281 139.058594 39.113281 C 138.441406 39.113281 137.953125 38.910156 137.589844 38.503906 C 137.222656 38.089844 137.042969 37.535156 137.042969 36.84375 C 137.042969 36.160156 137.222656 35.613281 137.589844 35.207031 C 137.953125 34.792969 138.441406 34.582031 139.058594 34.582031 C 139.671875 34.582031 140.160156 34.792969 140.527344 35.207031 C 140.902344 35.613281 141.089844 36.160156 141.089844 36.84375 C 141.089844 37.359375 140.984375 37.796875 140.777344 38.160156 C 140.578125 38.511719 140.28125 38.78125 139.886719 38.957031 Z M 139.886719 38.957031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 142.90625 34.660156 L 143.390625 34.660156 L 141.875 39.59375 L 141.375 39.59375 Z M 142.90625 34.660156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 143.976562 34.660156 L 144.570312 34.660156 L 144.570312 39.035156 L 143.976562 39.035156 Z M 143.976562 34.660156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 46.765625 43.285156 L 46.765625 48.378906 L 47.84375 48.378906 C 48.75 48.378906 49.410156 48.175781 49.828125 47.769531 C 50.253906 47.363281 50.46875 46.714844 50.46875 45.832031 C 50.46875 44.949219 50.253906 44.300781 49.828125 43.894531 C 49.410156 43.488281 48.75 43.285156 47.84375 43.285156 Z M 45.890625 42.550781 L 47.703125 42.550781 C 48.972656 42.550781 49.90625 42.816406 50.5 43.34375 C 51.101562 43.878906 51.40625 44.707031 51.40625 45.832031 C 51.40625 46.957031 51.101562 47.785156 50.5 48.316406 C 49.90625 48.84375 48.972656 49.113281 47.703125 49.113281 L 45.890625 49.113281 Z M 45.890625 42.550781 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 53.769531 48.363281 L 56.863281 48.363281 L 56.863281 49.113281 L 52.691406 49.113281 L 52.691406 48.363281 C 53.035156 48.019531 53.492188 47.558594 54.066406 46.96875 C 54.648438 46.378906 55.019531 46 55.175781 45.832031 C 55.457031 45.507812 55.648438 45.238281 55.753906 45.019531 C 55.867188 44.792969 55.925781 44.574219 55.925781 44.363281 C 55.925781 44.007812 55.804688 43.71875 55.566406 43.503906 C 55.324219 43.285156 55.007812 43.175781 54.613281 43.175781 C 54.332031 43.175781 54.035156 43.230469 53.722656 43.332031 C 53.417969 43.425781 53.089844 43.574219 52.738281 43.769531 L 52.738281 42.863281 C 53.089844 42.730469 53.425781 42.625 53.738281 42.550781 C 54.050781 42.464844 54.335938 42.425781 54.597656 42.425781 C 55.273438 42.425781 55.816406 42.59375 56.222656 42.941406 C 56.628906 43.285156 56.832031 43.738281 56.832031 44.300781 C 56.832031 44.574219 56.777344 44.832031 56.675781 45.082031 C 56.570312 45.324219 56.386719 45.605469 56.128906 45.925781 C 56.054688 46.007812 55.820312 46.253906 55.425781 46.660156 C 55.027344 47.066406 54.476562 47.632812 53.769531 48.363281 Z M 53.769531 48.363281 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 59.042969 47.050781 L 59.042969 48.691406 L 59.777344 48.691406 C 60.058594 48.691406 60.269531 48.625 60.417969 48.488281 C 60.574219 48.339844 60.652344 48.136719 60.652344 47.878906 C 60.652344 47.621094 60.574219 47.417969 60.417969 47.269531 C 60.269531 47.125 60.058594 47.050781 59.777344 47.050781 Z M 58.449219 46.566406 L 59.777344 46.566406 C 60.265625 46.566406 60.636719 46.683594 60.886719 46.910156 C 61.136719 47.128906 61.261719 47.453125 61.261719 47.878906 C 61.261719 48.308594 61.136719 48.628906 60.886719 48.84375 C 60.636719 49.066406 60.265625 49.175781 59.777344 49.175781 L 59.042969 49.175781 L 59.042969 50.941406 L 58.449219 50.941406 Z M 58.449219 46.566406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 62.628906 47.050781 L 62.628906 48.691406 L 63.363281 48.691406 C 63.644531 48.691406 63.855469 48.625 64.003906 48.488281 C 64.160156 48.339844 64.238281 48.136719 64.238281 47.878906 C 64.238281 47.621094 64.160156 47.417969 64.003906 47.269531 C 63.855469 47.125 63.644531 47.050781 63.363281 47.050781 Z M 62.035156 46.566406 L 63.363281 46.566406 C 63.851562 46.566406 64.222656 46.683594 64.472656 46.910156 C 64.722656 47.128906 64.847656 47.453125 64.847656 47.878906 C 64.847656 48.308594 64.722656 48.628906 64.472656 48.84375 C 64.222656 49.066406 63.851562 49.175781 63.363281 49.175781 L 62.628906 49.175781 L 62.628906 50.941406 L 62.035156 50.941406 Z M 62.035156 46.566406 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 41.902344 7.753906 L 119.644531 7.753906 C 120.410156 7.753906 121.144531 8.257812 121.144531 9.253906 L 121.144531 26.539062 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 44.0625 6.832031 L 45.578125 6.832031 L 45.578125 8.734375 L 44.0625 8.734375 Z M 44.0625 6.832031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 44.066406 7.792969 L 45.007812 8.519531 L 45.949219 9.25 L 45.949219 6.335938 L 45.007812 7.0625 Z M 44.066406 7.792969 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 44.191406 51.113281 L 45.707031 51.113281 L 45.707031 53.011719 L 44.191406 53.011719 Z M 44.191406 51.113281 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 44.195312 52.074219 L 45.136719 52.800781 L 46.078125 53.53125 L 46.078125 50.617188 L 45.136719 51.34375 Z M 44.195312 52.074219 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 92.289062 27.777344 C 91.578125 27.777344 91 27.199219 91 26.488281 C 91 25.773438 91.578125 25.195312 92.289062 25.195312 C 93 25.195312 93.578125 25.773438 93.578125 26.488281 C 93.578125 27.199219 93 27.777344 92.289062 27.777344 Z M 92.289062 27.777344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 121.148438 27.824219 C 120.4375 27.824219 119.859375 27.246094 119.859375 26.53125 C 119.859375 25.820312 120.4375 25.242188 121.148438 25.242188 C 121.859375 25.242188 122.4375 25.820312 122.4375 26.53125 C 122.4375 27.246094 121.859375 27.824219 121.148438 27.824219 Z M 121.148438 27.824219 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 39.523438 109.554688 L 90.757812 109.554688 C 91.523438 109.554688 92.257812 109.046875 92.257812 108.054688 L 92.257812 83.8125 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 38.3125 84.023438 L 130.328125 84.023438 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 124.917969 81.808594 L 124.917969 86.238281 L 131.855469 86.238281 L 134.097656 84.074219 L 131.796875 81.863281 Z M 124.917969 81.808594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 96.089844 83.03125 L 97.605469 83.03125 L 97.605469 84.933594 L 96.089844 84.933594 Z M 96.089844 83.03125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 97.601562 83.992188 L 95.71875 85.445312 L 95.71875 82.535156 L 96.660156 83.257812 Z M 97.601562 83.992188 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 100.171875 91.320312 L 117.539062 91.257812 L 117.539062 73.945312 L 100.171875 74.011719 Z M 100.171875 91.320312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 104.738281 81.191406 L 103.144531 85.59375 L 106.347656 85.59375 Z M 102.066406 86.253906 L 104.300781 80.425781 L 105.191406 80.425781 L 107.410156 86.253906 Z M 102.066406 86.253906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 109.296875 85.582031 L 112.15625 85.582031 L 112.15625 86.253906 L 108.390625 86.253906 L 108.390625 85.582031 L 110.265625 83.144531 L 108.390625 81.082031 L 108.390625 80.425781 L 112.078125 80.425781 L 112.078125 81.082031 L 109.296875 81.082031 L 111.171875 83.128906 Z M 109.296875 85.582031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 113.738281 82.550781 L 115.472656 82.550781 L 115.472656 82.96875 L 113.144531 82.96875 L 113.144531 82.550781 C 113.332031 82.363281 113.585938 82.109375 113.910156 81.785156 C 114.230469 81.453125 114.433594 81.238281 114.519531 81.144531 C 114.683594 80.964844 114.800781 80.816406 114.863281 80.691406 C 114.925781 80.566406 114.957031 80.449219 114.957031 80.332031 C 114.957031 80.132812 114.886719 79.980469 114.753906 79.863281 C 114.617188 79.738281 114.441406 79.675781 114.222656 79.675781 C 114.066406 79.675781 113.898438 79.703125 113.722656 79.753906 C 113.554688 79.808594 113.371094 79.886719 113.175781 80.003906 L 113.175781 79.503906 C 113.371094 79.421875 113.554688 79.359375 113.722656 79.316406 C 113.898438 79.277344 114.058594 79.253906 114.207031 79.253906 C 114.582031 79.253906 114.878906 79.355469 115.097656 79.550781 C 115.324219 79.738281 115.441406 79.988281 115.441406 80.300781 C 115.441406 80.449219 115.414062 80.589844 115.363281 80.71875 C 115.308594 80.859375 115.207031 81.019531 115.050781 81.207031 C 115.007812 81.25 114.878906 81.382812 114.660156 81.613281 C 114.449219 81.839844 114.144531 82.15625 113.738281 82.550781 Z M 113.738281 82.550781 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 97.804688 95.230469 L 115.175781 95.164062 L 115.175781 77.855469 L 97.804688 77.917969 Z M 97.804688 95.230469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 102.375 85.101562 L 100.78125 89.507812 L 103.984375 89.507812 Z M 99.703125 90.164062 L 101.9375 84.335938 L 102.828125 84.335938 L 105.046875 90.164062 Z M 99.703125 90.164062 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 106.933594 89.492188 L 109.792969 89.492188 L 109.792969 90.164062 L 106.027344 90.164062 L 106.027344 89.492188 L 107.902344 87.050781 L 106.027344 84.992188 L 106.027344 84.335938 L 109.714844 84.335938 L 109.714844 84.992188 L 106.933594 84.992188 L 108.808594 87.039062 Z M 106.933594 89.492188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 111.375 86.457031 L 113.109375 86.457031 L 113.109375 86.878906 L 110.78125 86.878906 L 110.78125 86.457031 C 110.96875 86.269531 111.222656 86.011719 111.546875 85.691406 C 111.867188 85.359375 112.070312 85.144531 112.15625 85.050781 C 112.320312 84.875 112.4375 84.71875 112.5 84.59375 C 112.5625 84.46875 112.59375 84.355469 112.59375 84.238281 C 112.59375 84.042969 112.523438 83.882812 112.390625 83.769531 C 112.253906 83.644531 112.078125 83.582031 111.859375 83.582031 C 111.703125 83.582031 111.535156 83.609375 111.359375 83.660156 C 111.191406 83.714844 111.007812 83.796875 110.8125 83.910156 L 110.8125 83.410156 C 111.007812 83.328125 111.191406 83.261719 111.359375 83.21875 C 111.535156 83.183594 111.695312 83.160156 111.84375 83.160156 C 112.21875 83.160156 112.515625 83.257812 112.734375 83.457031 C 112.960938 83.644531 113.078125 83.894531 113.078125 84.207031 C 113.078125 84.355469 113.050781 84.496094 113 84.628906 C 112.945312 84.761719 112.84375 84.925781 112.6875 85.113281 C 112.644531 85.15625 112.515625 85.292969 112.296875 85.519531 C 112.085938 85.75 111.78125 86.0625 111.375 86.457031 Z M 111.375 86.457031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 84.917969 108.585938 L 86.433594 108.585938 L 86.433594 110.488281 L 84.917969 110.488281 Z M 84.917969 108.585938 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 84.921875 109.546875 L 85.863281 110.277344 L 86.808594 111.003906 L 86.808594 108.089844 L 85.863281 108.820312 Z M 84.921875 109.546875 "/>
<path style=" stroke:none;fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 67.363281 118.0625 L 84.734375 117.992188 L 84.734375 100.683594 L 67.363281 100.75 Z M 67.363281 118.0625 "/>
<g clip-path="url(#clip5)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 67.363281 118.0625 L 84.734375 117.992188 L 84.734375 100.683594 L 67.363281 100.75 Z M 67.363281 118.0625 "/>
</g>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 70.339844 114.695312 L 78.910156 114.695312 L 78.910156 111.96875 L 82.367188 111.96875 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 70.359375 104.738281 L 78.929688 104.738281 L 78.929688 107.464844 L 82.390625 107.464844 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 70.390625 112.339844 C 70.792969 113.605469 71.308594 114.847656 71.894531 114.574219 C 72.535156 114.21875 73.007812 112.566406 73.441406 111.074219 C 74.003906 109.128906 74.5 106.863281 75.207031 105.472656 C 75.457031 105 75.742188 104.730469 76.050781 104.839844 C 76.714844 105.210938 77.1875 106.859375 77.621094 108.351562 L 78.308594 110.878906 C 78.527344 111.527344 78.804688 112.167969 79.121094 112.03125 C 79.464844 111.84375 79.722656 110.992188 79.957031 110.226562 C 80.261719 109.226562 80.527344 108.550781 80.910156 107.835938 C 81.046875 107.589844 81.203125 107.449219 81.367188 107.507812 C 81.726562 107.695312 81.980469 108.546875 82.214844 109.316406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 125.609375 88.867188 L 125.609375 93.960938 L 126.6875 93.960938 C 127.59375 93.960938 128.253906 93.757812 128.671875 93.351562 C 129.097656 92.945312 129.3125 92.300781 129.3125 91.414062 C 129.3125 90.53125 129.097656 89.882812 128.671875 89.476562 C 128.253906 89.070312 127.59375 88.867188 126.6875 88.867188 Z M 124.734375 88.132812 L 126.546875 88.132812 C 127.816406 88.132812 128.75 88.398438 129.34375 88.925781 C 129.945312 89.460938 130.25 90.289062 130.25 91.414062 C 130.25 92.539062 129.945312 93.367188 129.34375 93.898438 C 128.75 94.425781 127.816406 94.695312 126.546875 94.695312 L 124.734375 94.695312 Z M 124.734375 88.132812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 131.988281 93.945312 L 133.441406 93.945312 L 133.441406 88.945312 L 131.863281 89.257812 L 131.863281 88.445312 L 133.441406 88.132812 L 134.332031 88.132812 L 134.332031 93.945312 L 135.769531 93.945312 L 135.769531 94.695312 L 131.988281 94.695312 Z M 131.988281 93.945312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 139.058594 92.550781 C 138.628906 92.550781 138.292969 92.714844 138.042969 93.039062 C 137.792969 93.351562 137.667969 93.785156 137.667969 94.335938 C 137.667969 94.886719 137.792969 95.328125 138.042969 95.648438 C 138.292969 95.96875 138.628906 96.132812 139.058594 96.132812 C 139.496094 96.132812 139.839844 95.96875 140.089844 95.648438 C 140.339844 95.328125 140.464844 94.886719 140.464844 94.335938 C 140.464844 93.785156 140.339844 93.351562 140.089844 93.039062 C 139.839844 92.714844 139.496094 92.550781 139.058594 92.550781 Z M 139.886719 96.445312 L 140.667969 97.300781 L 139.964844 97.300781 L 139.308594 96.601562 C 139.246094 96.601562 139.191406 96.601562 139.152344 96.601562 C 139.121094 96.601562 139.089844 96.601562 139.058594 96.601562 C 138.441406 96.601562 137.953125 96.398438 137.589844 95.992188 C 137.222656 95.578125 137.042969 95.023438 137.042969 94.335938 C 137.042969 93.648438 137.222656 93.101562 137.589844 92.695312 C 137.953125 92.28125 138.441406 92.070312 139.058594 92.070312 C 139.671875 92.070312 140.160156 92.28125 140.527344 92.695312 C 140.902344 93.101562 141.089844 93.648438 141.089844 94.335938 C 141.089844 94.84375 140.984375 95.285156 140.777344 95.648438 C 140.578125 96.003906 140.28125 96.269531 139.886719 96.445312 Z M 139.886719 96.445312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 142.90625 92.148438 L 143.390625 92.148438 L 141.875 97.085938 L 141.375 97.085938 Z M 142.90625 92.148438 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 143.976562 92.148438 L 144.570312 92.148438 L 144.570312 96.523438 L 143.976562 96.523438 Z M 143.976562 92.148438 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 46.765625 100.777344 L 46.765625 105.871094 L 47.84375 105.871094 C 48.75 105.871094 49.410156 105.667969 49.828125 105.257812 C 50.253906 104.855469 50.46875 104.210938 50.46875 103.324219 C 50.46875 102.441406 50.253906 101.792969 49.828125 101.382812 C 49.410156 100.980469 48.75 100.777344 47.84375 100.777344 Z M 45.890625 100.042969 L 47.703125 100.042969 C 48.972656 100.042969 49.90625 100.308594 50.5 100.839844 C 51.101562 101.371094 51.40625 102.199219 51.40625 103.324219 C 51.40625 104.449219 51.101562 105.277344 50.5 105.808594 C 49.90625 106.339844 48.972656 106.605469 47.703125 106.605469 L 45.890625 106.605469 Z M 45.890625 100.042969 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 53.144531 105.855469 L 54.597656 105.855469 L 54.597656 100.855469 L 53.019531 101.167969 L 53.019531 100.355469 L 54.597656 100.042969 L 55.488281 100.042969 L 55.488281 105.855469 L 56.925781 105.855469 L 56.925781 106.605469 L 53.144531 106.605469 Z M 53.144531 105.855469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 59.042969 104.542969 L 59.042969 106.183594 L 59.777344 106.183594 C 60.058594 106.183594 60.269531 106.117188 60.417969 105.980469 C 60.574219 105.835938 60.652344 105.632812 60.652344 105.371094 C 60.652344 105.113281 60.574219 104.910156 60.417969 104.757812 C 60.269531 104.617188 60.058594 104.542969 59.777344 104.542969 Z M 58.449219 104.058594 L 59.777344 104.058594 C 60.265625 104.058594 60.636719 104.175781 60.886719 104.402344 C 61.136719 104.621094 61.261719 104.945312 61.261719 105.371094 C 61.261719 105.800781 61.136719 106.121094 60.886719 106.339844 C 60.636719 106.558594 60.265625 106.667969 59.777344 106.667969 L 59.042969 106.667969 L 59.042969 108.433594 L 58.449219 108.433594 Z M 58.449219 104.058594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 62.628906 104.542969 L 62.628906 106.183594 L 63.363281 106.183594 C 63.644531 106.183594 63.855469 106.117188 64.003906 105.980469 C 64.160156 105.835938 64.238281 105.632812 64.238281 105.371094 C 64.238281 105.113281 64.160156 104.910156 64.003906 104.757812 C 63.855469 104.617188 63.644531 104.542969 63.363281 104.542969 Z M 62.035156 104.058594 L 63.363281 104.058594 C 63.851562 104.058594 64.222656 104.175781 64.472656 104.402344 C 64.722656 104.621094 64.847656 104.945312 64.847656 105.371094 C 64.847656 105.800781 64.722656 106.121094 64.472656 106.339844 C 64.222656 106.558594 63.851562 106.667969 63.363281 106.667969 L 62.628906 106.667969 L 62.628906 108.433594 L 62.035156 108.433594 Z M 62.035156 104.058594 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 41.902344 65.238281 L 119.644531 65.238281 C 120.410156 65.238281 121.144531 65.75 121.144531 66.738281 L 121.144531 84.027344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 44.0625 64.320312 L 45.578125 64.320312 L 45.578125 66.226562 L 44.0625 66.226562 Z M 44.0625 64.320312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 44.066406 65.285156 L 45.949219 66.738281 L 45.949219 63.828125 L 45.007812 64.550781 Z M 44.066406 65.285156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 44.191406 108.605469 L 45.707031 108.605469 L 45.707031 110.503906 L 44.191406 110.503906 Z M 44.191406 108.605469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 44.195312 109.566406 L 45.136719 110.292969 L 46.078125 111.023438 L 46.078125 108.109375 L 45.136719 108.835938 Z M 44.195312 109.566406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 92.289062 85.269531 C 91.578125 85.269531 91 84.691406 91 83.980469 C 91 83.261719 91.578125 82.6875 92.289062 82.6875 C 93 82.6875 93.578125 83.261719 93.578125 83.980469 C 93.578125 84.691406 93 85.269531 92.289062 85.269531 Z M 92.289062 85.269531 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 121.148438 85.316406 C 120.4375 85.316406 119.859375 84.738281 119.859375 84.023438 C 119.859375 83.3125 120.4375 82.734375 121.148438 82.734375 C 121.859375 82.734375 122.4375 83.3125 122.4375 84.023438 C 122.4375 84.738281 121.859375 85.316406 121.148438 85.316406 Z M 121.148438 85.316406 "/>
<path style=" stroke:none;fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 24.710938 114.550781 L 44.125 114.125 L 44.125 3.253906 L 24.710938 3.675781 Z M 24.710938 114.550781 "/>
<g clip-path="url(#clip6)" clip-rule="nonzero">
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 24.710938 114.550781 L 44.125 114.125 L 44.125 3.253906 L 24.710938 3.675781 Z M 24.710938 114.550781 "/>
</g>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 30.089844 91.800781 L 34.621094 91.800781 L 34.621094 90.84375 C 34.621094 90.046875 34.441406 89.457031 34.074219 89.082031 C 33.710938 88.707031 33.136719 88.519531 32.355469 88.519531 C 31.574219 88.519531 31.003906 88.707031 30.636719 89.082031 C 30.273438 89.457031 30.089844 90.046875 30.089844 90.84375 Z M 29.449219 92.59375 L 29.449219 90.96875 C 29.449219 89.839844 29.683594 89.007812 30.152344 88.488281 C 30.621094 87.957031 31.355469 87.691406 32.355469 87.691406 C 33.355469 87.691406 34.097656 87.957031 34.574219 88.488281 C 35.042969 89.019531 35.277344 89.84375 35.277344 90.96875 L 35.277344 92.59375 Z M 29.449219 92.59375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 30.089844 85.644531 L 34.621094 85.644531 L 34.621094 84.691406 C 34.621094 83.886719 34.441406 83.300781 34.074219 82.925781 C 33.710938 82.550781 33.136719 82.363281 32.355469 82.363281 C 31.574219 82.363281 31.003906 82.550781 30.636719 82.925781 C 30.273438 83.300781 30.089844 83.886719 30.089844 84.691406 Z M 29.449219 86.441406 L 29.449219 84.816406 C 29.449219 83.683594 29.683594 82.855469 30.152344 82.332031 C 30.621094 81.800781 31.355469 81.535156 32.355469 81.535156 C 33.355469 81.535156 34.097656 81.800781 34.574219 82.332031 C 35.042969 82.863281 35.277344 83.691406 35.277344 84.816406 L 35.277344 86.441406 Z M 29.449219 86.441406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 29.449219 80.800781 L 29.449219 80.003906 L 34.371094 78.769531 L 29.449219 77.550781 L 29.449219 76.660156 L 34.371094 75.441406 L 29.449219 74.21875 L 29.449219 73.410156 L 35.277344 74.878906 L 35.277344 75.878906 L 30.214844 77.09375 L 35.277344 78.34375 L 35.277344 79.332031 Z M 29.449219 80.800781 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 29.636719 68.878906 L 30.402344 68.878906 C 30.257812 69.183594 30.152344 69.464844 30.089844 69.738281 C 30.019531 70 29.980469 70.25 29.980469 70.488281 C 29.980469 70.925781 30.066406 71.257812 30.230469 71.488281 C 30.398438 71.714844 30.632812 71.832031 30.933594 71.832031 C 31.195312 71.832031 31.394531 71.757812 31.527344 71.613281 C 31.652344 71.457031 31.757812 71.160156 31.839844 70.71875 L 31.933594 70.253906 C 32.050781 69.660156 32.246094 69.21875 32.527344 68.941406 C 32.808594 68.660156 33.191406 68.519531 33.667969 68.519531 C 34.230469 68.519531 34.660156 68.714844 34.949219 69.09375 C 35.242188 69.46875 35.386719 70.027344 35.386719 70.753906 C 35.386719 71.035156 35.355469 71.332031 35.292969 71.644531 C 35.230469 71.957031 35.136719 72.28125 35.011719 72.613281 L 34.199219 72.613281 C 34.386719 72.292969 34.527344 71.980469 34.621094 71.675781 C 34.707031 71.363281 34.746094 71.058594 34.746094 70.753906 C 34.746094 70.308594 34.660156 69.964844 34.480469 69.71875 C 34.304688 69.46875 34.054688 69.34375 33.730469 69.34375 C 33.441406 69.34375 33.214844 69.4375 33.058594 69.613281 C 32.894531 69.792969 32.769531 70.078125 32.683594 70.46875 L 32.589844 70.957031 C 32.476562 71.550781 32.292969 71.980469 32.042969 72.238281 C 31.792969 72.5 31.445312 72.628906 30.996094 72.628906 C 30.488281 72.628906 30.085938 72.449219 29.792969 72.082031 C 29.492188 71.714844 29.339844 71.214844 29.339844 70.582031 C 29.339844 70.3125 29.367188 70.035156 29.417969 69.753906 C 29.460938 69.464844 29.535156 69.171875 29.636719 68.878906 Z M 29.636719 68.878906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 29.886719 60.378906 L 30.730469 60.378906 C 30.480469 60.652344 30.292969 60.9375 30.167969 61.238281 C 30.042969 61.53125 29.980469 61.84375 29.980469 62.191406 C 29.980469 62.859375 30.191406 63.371094 30.605469 63.71875 C 31.011719 64.078125 31.601562 64.253906 32.371094 64.253906 C 33.132812 64.253906 33.722656 64.078125 34.136719 63.71875 C 34.542969 63.371094 34.746094 62.859375 34.746094 62.191406 C 34.746094 61.84375 34.683594 61.53125 34.558594 61.238281 C 34.433594 60.9375 34.246094 60.652344 33.996094 60.378906 L 34.824219 60.378906 C 35.011719 60.660156 35.152344 60.957031 35.246094 61.269531 C 35.339844 61.574219 35.386719 61.894531 35.386719 62.238281 C 35.386719 63.125 35.117188 63.824219 34.574219 64.332031 C 34.035156 64.832031 33.300781 65.082031 32.371094 65.082031 C 31.433594 65.082031 30.695312 64.832031 30.152344 64.332031 C 29.613281 63.824219 29.339844 63.125 29.339844 62.238281 C 29.339844 61.882812 29.386719 61.558594 29.480469 61.253906 C 29.574219 60.941406 29.710938 60.652344 29.886719 60.378906 Z M 29.886719 60.378906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 31.402344 57.488281 C 31.402344 57.875 31.554688 58.183594 31.855469 58.410156 C 32.160156 58.628906 32.570312 58.738281 33.089844 58.738281 C 33.613281 58.738281 34.023438 58.628906 34.324219 58.410156 C 34.628906 58.183594 34.777344 57.875 34.777344 57.488281 C 34.777344 57.105469 34.628906 56.800781 34.324219 56.582031 C 34.023438 56.355469 33.613281 56.238281 33.089844 56.238281 C 32.570312 56.238281 32.160156 56.355469 31.855469 56.582031 C 31.554688 56.800781 31.402344 57.105469 31.402344 57.488281 Z M 30.792969 57.488281 C 30.792969 56.863281 30.996094 56.375 31.402344 56.019531 C 31.808594 55.667969 32.371094 55.488281 33.089844 55.488281 C 33.808594 55.488281 34.371094 55.667969 34.777344 56.019531 C 35.183594 56.375 35.386719 56.863281 35.386719 57.488281 C 35.386719 58.113281 35.183594 58.609375 34.777344 58.96875 C 34.371094 59.328125 33.808594 59.503906 33.089844 59.503906 C 32.371094 59.503906 31.808594 59.328125 31.402344 58.96875 C 30.996094 58.609375 30.792969 58.113281 30.792969 57.488281 Z M 30.792969 57.488281 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 32.636719 50.660156 L 35.277344 50.660156 L 35.277344 51.378906 L 32.652344 51.378906 C 32.246094 51.378906 31.941406 51.464844 31.730469 51.628906 C 31.523438 51.785156 31.417969 52.027344 31.417969 52.34375 C 31.417969 52.734375 31.542969 53.042969 31.792969 53.269531 C 32.042969 53.488281 32.382812 53.59375 32.808594 53.59375 L 35.277344 53.59375 L 35.277344 54.316406 L 30.902344 54.316406 L 30.902344 53.59375 L 31.574219 53.59375 C 31.316406 53.433594 31.121094 53.234375 30.996094 53.003906 C 30.863281 52.761719 30.792969 52.496094 30.792969 52.191406 C 30.792969 51.683594 30.949219 51.300781 31.261719 51.050781 C 31.574219 50.792969 32.035156 50.660156 32.636719 50.660156 Z M 32.636719 50.660156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 29.652344 48.503906 L 30.902344 48.503906 L 30.902344 47.019531 L 31.464844 47.019531 L 31.464844 48.503906 L 33.839844 48.503906 C 34.195312 48.503906 34.425781 48.457031 34.527344 48.363281 C 34.621094 48.257812 34.667969 48.0625 34.667969 47.769531 L 34.667969 47.019531 L 35.277344 47.019531 L 35.277344 47.769531 C 35.277344 48.324219 35.175781 48.703125 34.964844 48.910156 C 34.757812 49.121094 34.382812 49.21875 33.839844 49.21875 L 31.464844 49.21875 L 31.464844 49.753906 L 30.902344 49.753906 L 30.902344 49.21875 L 29.652344 49.21875 Z M 29.652344 48.503906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 31.574219 43.535156 C 31.523438 43.621094 31.488281 43.707031 31.464844 43.800781 C 31.445312 43.894531 31.433594 44 31.433594 44.113281 C 31.433594 44.519531 31.570312 44.832031 31.839844 45.050781 C 32.101562 45.269531 32.476562 45.378906 32.964844 45.378906 L 35.277344 45.378906 L 35.277344 46.09375 L 30.902344 46.09375 L 30.902344 45.378906 L 31.574219 45.378906 C 31.316406 45.234375 31.121094 45.042969 30.996094 44.800781 C 30.863281 44.550781 30.792969 44.253906 30.792969 43.910156 C 30.792969 43.859375 30.800781 43.808594 30.808594 43.753906 C 30.808594 43.691406 30.820312 43.625 30.839844 43.550781 Z M 31.574219 43.535156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 31.402344 41.253906 C 31.402344 41.636719 31.554688 41.949219 31.855469 42.175781 C 32.160156 42.394531 32.570312 42.503906 33.089844 42.503906 C 33.613281 42.503906 34.023438 42.394531 34.324219 42.175781 C 34.628906 41.949219 34.777344 41.636719 34.777344 41.253906 C 34.777344 40.871094 34.628906 40.566406 34.324219 40.34375 C 34.023438 40.121094 33.613281 40.003906 33.089844 40.003906 C 32.570312 40.003906 32.160156 40.121094 31.855469 40.34375 C 31.554688 40.566406 31.402344 40.871094 31.402344 41.253906 Z M 30.792969 41.253906 C 30.792969 40.628906 30.996094 40.136719 31.402344 39.785156 C 31.808594 39.433594 32.371094 39.253906 33.089844 39.253906 C 33.808594 39.253906 34.371094 39.433594 34.777344 39.785156 C 35.183594 40.136719 35.386719 40.628906 35.386719 41.253906 C 35.386719 41.878906 35.183594 42.375 34.777344 42.738281 C 34.371094 43.089844 33.808594 43.269531 33.089844 43.269531 C 32.371094 43.269531 31.808594 43.089844 31.402344 42.738281 C 30.996094 42.375 30.792969 41.878906 30.792969 41.253906 Z M 30.792969 41.253906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 29.199219 37.34375 L 35.277344 37.34375 L 35.277344 38.066406 L 29.199219 38.066406 Z M 29.199219 37.34375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 29.199219 35.128906 L 35.277344 35.128906 L 35.277344 35.847656 L 29.199219 35.847656 Z M 29.199219 35.128906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 32.902344 29.878906 L 33.261719 29.878906 L 33.261719 33.191406 C 33.753906 33.160156 34.128906 33.007812 34.386719 32.738281 C 34.648438 32.464844 34.777344 32.09375 34.777344 31.628906 C 34.777344 31.34375 34.746094 31.078125 34.683594 30.816406 C 34.613281 30.558594 34.507812 30.300781 34.371094 30.050781 L 35.058594 30.050781 C 35.164062 30.3125 35.242188 30.578125 35.292969 30.84375 C 35.355469 31.121094 35.386719 31.386719 35.386719 31.660156 C 35.386719 32.359375 35.183594 32.917969 34.777344 33.332031 C 34.371094 33.738281 33.824219 33.941406 33.136719 33.941406 C 32.417969 33.941406 31.851562 33.75 31.433594 33.363281 C 31.007812 32.964844 30.792969 32.441406 30.792969 31.785156 C 30.792969 31.203125 30.988281 30.738281 31.371094 30.394531 C 31.746094 30.050781 32.257812 29.878906 32.902344 29.878906 Z M 32.699219 30.59375 C 32.304688 30.609375 31.992188 30.71875 31.761719 30.941406 C 31.523438 31.152344 31.402344 31.433594 31.402344 31.785156 C 31.402344 32.183594 31.519531 32.503906 31.746094 32.753906 C 31.976562 32.996094 32.292969 33.128906 32.699219 33.160156 Z M 32.699219 30.59375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 31.574219 26.160156 C 31.523438 26.246094 31.488281 26.332031 31.464844 26.425781 C 31.445312 26.519531 31.433594 26.625 31.433594 26.738281 C 31.433594 27.144531 31.570312 27.457031 31.839844 27.675781 C 32.101562 27.894531 32.476562 28.003906 32.964844 28.003906 L 35.277344 28.003906 L 35.277344 28.71875 L 30.902344 28.71875 L 30.902344 28.003906 L 31.574219 28.003906 C 31.316406 27.859375 31.121094 27.667969 30.996094 27.425781 C 30.863281 27.175781 30.792969 26.878906 30.792969 26.535156 C 30.792969 26.484375 30.800781 26.433594 30.808594 26.378906 C 30.808594 26.316406 30.820312 26.25 30.839844 26.175781 Z M 31.574219 26.160156 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 5.769531 30.441406 L 5.769531 34.863281 L 12.703125 34.863281 L 14.949219 32.710938 L 12.648438 30.5 Z M 5.769531 30.441406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 7.96875 22.113281 L 7.96875 22.707031 L 7.28125 22.707031 C 7.019531 22.707031 6.835938 22.757812 6.734375 22.863281 C 6.640625 22.964844 6.59375 23.15625 6.59375 23.425781 L 6.59375 23.816406 L 7.78125 23.816406 L 7.78125 24.378906 L 6.59375 24.378906 L 6.59375 28.191406 L 5.875 28.191406 L 5.875 24.378906 L 5.1875 24.378906 L 5.1875 23.816406 L 5.875 23.816406 L 5.875 23.503906 C 5.875 23.027344 5.984375 22.675781 6.203125 22.457031 C 6.429688 22.230469 6.796875 22.113281 7.296875 22.113281 Z M 7.96875 22.113281 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 11.109375 24.488281 C 11.023438 24.4375 10.9375 24.402344 10.84375 24.378906 C 10.75 24.359375 10.644531 24.34375 10.53125 24.34375 C 10.125 24.34375 9.8125 24.484375 9.59375 24.753906 C 9.375 25.011719 9.265625 25.386719 9.265625 25.878906 L 9.265625 28.191406 L 8.546875 28.191406 L 8.546875 23.816406 L 9.265625 23.816406 L 9.265625 24.488281 C 9.410156 24.230469 9.601562 24.035156 9.84375 23.910156 C 10.09375 23.777344 10.390625 23.707031 10.734375 23.707031 C 10.785156 23.707031 10.835938 23.714844 10.890625 23.71875 C 10.953125 23.71875 11.019531 23.734375 11.09375 23.753906 Z M 11.109375 24.488281 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 15.4375 25.816406 L 15.4375 26.175781 L 12.125 26.175781 C 12.15625 26.667969 12.304688 27.042969 12.578125 27.300781 C 12.847656 27.5625 13.21875 27.691406 13.6875 27.691406 C 13.96875 27.691406 14.238281 27.660156 14.5 27.59375 C 14.757812 27.527344 15.015625 27.421875 15.265625 27.285156 L 15.265625 27.96875 C 15.003906 28.078125 14.738281 28.15625 14.46875 28.207031 C 14.195312 28.269531 13.925781 28.300781 13.65625 28.300781 C 12.957031 28.300781 12.398438 28.09375 11.984375 27.691406 C 11.578125 27.285156 11.375 26.738281 11.375 26.050781 C 11.375 25.332031 11.566406 24.761719 11.953125 24.34375 C 12.347656 23.921875 12.875 23.707031 13.53125 23.707031 C 14.113281 23.707031 14.578125 23.902344 14.921875 24.285156 C 15.265625 24.660156 15.4375 25.171875 15.4375 25.816406 Z M 14.71875 25.613281 C 14.707031 25.214844 14.59375 24.90625 14.375 24.675781 C 14.164062 24.4375 13.882812 24.316406 13.53125 24.316406 C 13.132812 24.316406 12.8125 24.433594 12.5625 24.660156 C 12.320312 24.886719 12.1875 25.207031 12.15625 25.613281 Z M 14.71875 25.613281 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 17.046875 26.003906 C 17.046875 26.535156 17.15625 26.953125 17.375 27.253906 C 17.59375 27.558594 17.890625 27.707031 18.265625 27.707031 C 18.648438 27.707031 18.953125 27.558594 19.171875 27.253906 C 19.390625 26.953125 19.5 26.535156 19.5 26.003906 C 19.5 25.46875 19.390625 25.0625 19.171875 24.769531 C 18.953125 24.464844 18.648438 24.316406 18.265625 24.316406 C 17.890625 24.316406 17.59375 24.464844 17.375 24.769531 C 17.15625 25.0625 17.046875 25.46875 17.046875 26.003906 Z M 19.5 27.535156 C 19.34375 27.796875 19.148438 27.988281 18.921875 28.113281 C 18.691406 28.238281 18.414062 28.300781 18.09375 28.300781 C 17.5625 28.300781 17.128906 28.089844 16.796875 27.675781 C 16.460938 27.25 16.296875 26.691406 16.296875 26.003906 C 16.296875 25.316406 16.460938 24.761719 16.796875 24.34375 C 17.128906 23.921875 17.5625 23.707031 18.09375 23.707031 C 18.414062 23.707031 18.691406 23.769531 18.921875 23.894531 C 19.148438 24.019531 19.34375 24.214844 19.5 24.46875 L 19.5 23.816406 L 20.21875 23.816406 L 20.21875 29.863281 L 19.5 29.863281 Z M 19.5 27.535156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 21.796875 27.191406 L 22.625 27.191406 L 22.625 28.191406 L 21.796875 28.191406 Z M 21.796875 27.191406 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 5.769531 55.78125 L 5.769531 60.207031 L 12.703125 60.207031 L 14.949219 58.050781 L 12.648438 55.835938 Z M 5.769531 55.78125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 8.003906 48.523438 L 8.003906 49.195312 C 7.792969 49.082031 7.585938 49 7.378906 48.945312 C 7.179688 48.882812 6.976562 48.851562 6.769531 48.851562 C 6.300781 48.851562 5.933594 49.003906 5.675781 49.300781 C 5.425781 49.59375 5.300781 50.007812 5.300781 50.539062 C 5.300781 51.070312 5.425781 51.488281 5.675781 51.789062 C 5.933594 52.082031 6.300781 52.226562 6.769531 52.226562 C 6.976562 52.226562 7.179688 52.203125 7.378906 52.148438 C 7.585938 52.085938 7.792969 52.003906 8.003906 51.898438 L 8.003906 52.550781 C 7.804688 52.648438 7.597656 52.714844 7.378906 52.757812 C 7.160156 52.808594 6.929688 52.835938 6.691406 52.835938 C 6.035156 52.835938 5.507812 52.632812 5.113281 52.226562 C 4.726562 51.8125 4.535156 51.25 4.535156 50.539062 C 4.535156 49.832031 4.730469 49.273438 5.128906 48.867188 C 5.523438 48.453125 6.058594 48.242188 6.738281 48.242188 C 6.957031 48.242188 7.167969 48.269531 7.378906 48.320312 C 7.597656 48.363281 7.804688 48.425781 8.003906 48.523438 Z M 8.003906 48.523438 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 10.941406 52.964844 C 10.941406 52.632812 10.871094 52.375 10.738281 52.1875 C 10.601562 52 10.414062 51.90625 10.175781 51.90625 C 9.933594 51.90625 9.746094 52 9.613281 52.1875 C 9.476562 52.375 9.410156 52.632812 9.410156 52.964844 C 9.410156 53.292969 9.476562 53.546875 9.613281 53.734375 C 9.746094 53.921875 9.933594 54.011719 10.175781 54.011719 C 10.414062 54.011719 10.601562 53.921875 10.738281 53.734375 C 10.871094 53.546875 10.941406 53.292969 10.941406 52.964844 Z M 9.410156 52.011719 C 9.503906 51.851562 9.621094 51.730469 9.769531 51.65625 C 9.914062 51.574219 10.085938 51.53125 10.285156 51.53125 C 10.617188 51.53125 10.886719 51.664062 11.097656 51.921875 C 11.304688 52.183594 11.410156 52.53125 11.410156 52.964844 C 11.410156 53.398438 11.304688 53.746094 11.097656 54.011719 C 10.886719 54.277344 10.617188 54.40625 10.285156 54.40625 C 10.085938 54.40625 9.914062 54.363281 9.769531 54.28125 C 9.621094 54.199219 9.503906 54.078125 9.410156 53.921875 L 9.410156 54.328125 L 8.957031 54.328125 L 8.957031 50.53125 L 9.410156 50.53125 Z M 9.410156 52.011719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 12.007812 51.589844 L 12.460938 51.589844 L 13.023438 53.734375 L 13.585938 51.589844 L 14.117188 51.589844 L 14.679688 53.734375 L 15.242188 51.589844 L 15.679688 51.589844 L 14.976562 54.328125 L 14.445312 54.328125 L 13.851562 52.089844 L 13.257812 54.328125 L 12.726562 54.328125 Z M 12.007812 51.589844 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 5.769531 81.113281 L 5.769531 85.542969 L 12.703125 85.542969 L 14.949219 83.386719 L 12.648438 81.175781 Z M 5.769531 81.113281 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 2.835938 73.726562 L 3.601562 73.726562 L 4.976562 77.398438 L 6.335938 73.726562 L 7.101562 73.726562 L 5.460938 78.101562 L 4.476562 78.101562 Z M 2.835938 73.726562 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 8.789062 77.445312 L 8.789062 79.773438 L 8.070312 79.773438 L 8.070312 73.726562 L 8.789062 73.726562 L 8.789062 74.382812 C 8.933594 74.125 9.121094 73.925781 9.351562 73.800781 C 9.589844 73.675781 9.867188 73.617188 10.179688 73.617188 C 10.710938 73.617188 11.140625 73.832031 11.476562 74.257812 C 11.808594 74.675781 11.976562 75.226562 11.976562 75.914062 C 11.976562 76.601562 11.808594 77.160156 11.476562 77.585938 C 11.140625 78.003906 10.710938 78.210938 10.179688 78.210938 C 9.867188 78.210938 9.589844 78.148438 9.351562 78.023438 C 9.121094 77.898438 8.933594 77.707031 8.789062 77.445312 Z M 11.226562 75.914062 C 11.226562 75.382812 11.117188 74.96875 10.898438 74.675781 C 10.6875 74.378906 10.390625 74.226562 10.007812 74.226562 C 9.632812 74.226562 9.335938 74.378906 9.117188 74.675781 C 8.898438 74.96875 8.789062 75.382812 8.789062 75.914062 C 8.789062 76.445312 8.898438 76.863281 9.117188 77.164062 C 9.335938 77.464844 9.632812 77.617188 10.007812 77.617188 C 10.390625 77.617188 10.6875 77.464844 10.898438 77.164062 C 11.117188 76.863281 11.226562 76.445312 11.226562 75.914062 Z M 11.226562 75.914062 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 13.867188 77.445312 L 13.867188 79.773438 L 13.148438 79.773438 L 13.148438 73.726562 L 13.867188 73.726562 L 13.867188 74.382812 C 14.011719 74.125 14.199219 73.925781 14.429688 73.800781 C 14.667969 73.675781 14.945312 73.617188 15.257812 73.617188 C 15.789062 73.617188 16.21875 73.832031 16.554688 74.257812 C 16.886719 74.675781 17.054688 75.226562 17.054688 75.914062 C 17.054688 76.601562 16.886719 77.160156 16.554688 77.585938 C 16.21875 78.003906 15.789062 78.210938 15.257812 78.210938 C 14.945312 78.210938 14.667969 78.148438 14.429688 78.023438 C 14.199219 77.898438 14.011719 77.707031 13.867188 77.445312 Z M 16.304688 75.914062 C 16.304688 75.382812 16.195312 74.96875 15.976562 74.675781 C 15.765625 74.378906 15.46875 74.226562 15.085938 74.226562 C 14.710938 74.226562 14.414062 74.378906 14.195312 74.675781 C 13.976562 74.96875 13.867188 75.382812 13.867188 75.914062 C 13.867188 76.445312 13.976562 76.863281 14.195312 77.164062 C 14.414062 77.464844 14.710938 77.617188 15.085938 77.617188 C 15.46875 77.617188 15.765625 77.464844 15.976562 77.164062 C 16.195312 76.863281 16.304688 76.445312 16.304688 75.914062 Z M 16.304688 75.914062 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 5.769531 106.457031 L 5.769531 110.882812 L 12.703125 110.882812 L 14.949219 108.726562 L 12.648438 106.511719 Z M 5.769531 106.457031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 6.960938 99.0625 L 7.679688 99.0625 L 7.679688 103.4375 L 6.960938 103.4375 Z M 6.960938 97.359375 L 7.679688 97.359375 L 7.679688 98.261719 L 6.960938 98.261719 Z M 6.960938 97.359375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 12.335938 99.234375 L 12.335938 99.90625 C 12.125 99.792969 11.917969 99.710938 11.710938 99.65625 C 11.511719 99.589844 11.308594 99.5625 11.101562 99.5625 C 10.632812 99.5625 10.265625 99.714844 10.007812 100.011719 C 9.757812 100.308594 9.632812 100.714844 9.632812 101.25 C 9.632812 101.78125 9.757812 102.199219 10.007812 102.5 C 10.265625 102.792969 10.632812 102.9375 11.101562 102.9375 C 11.308594 102.9375 11.511719 102.914062 11.710938 102.859375 C 11.917969 102.796875 12.125 102.714844 12.335938 102.609375 L 12.335938 103.261719 C 12.136719 103.359375 11.929688 103.425781 11.710938 103.464844 C 11.492188 103.519531 11.261719 103.546875 11.023438 103.546875 C 10.367188 103.546875 9.839844 103.339844 9.445312 102.9375 C 9.058594 102.523438 8.867188 101.960938 8.867188 101.25 C 8.867188 100.542969 9.0625 99.984375 9.460938 99.578125 C 9.855469 99.164062 10.390625 98.953125 11.070312 98.953125 C 11.289062 98.953125 11.5 98.980469 11.710938 99.03125 C 11.929688 99.074219 12.136719 99.136719 12.335938 99.234375 Z M 12.335938 99.234375 "/>
<path style="fill:none;stroke-width:0.2;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(12.548828%,29.019165%,52.940369%);stroke-opacity:1;stroke-miterlimit:10;" d="M 122.082031 47.207031 C 122.488281 47.210938 122.8125 47.574219 123.167969 47.320312 C 123.292969 47.214844 123.660156 46.988281 123.871094 47.195312 C 124.074219 47.300781 124.082031 47.5625 124.457031 47.554688 C 124.847656 47.375 124.710938 47.023438 125.175781 46.894531 C 125.636719 47.179688 125.433594 47.613281 125.914062 47.878906 C 126.417969 47.4375 126.179688 46.882812 126.652344 46.441406 C 127.101562 46.949219 126.976562 47.550781 127.199219 48.09375 C 127.285156 48.195312 127.207031 48.476562 127.449219 48.503906 C 127.917969 47.53125 127.6875 46.515625 128.171875 45.558594 C 128.585938 46.609375 128.5 47.695312 128.699219 48.765625 C 128.789062 49.058594 128.695312 49.46875 128.949219 49.695312 C 129.425781 47.8125 129.210938 45.902344 129.667969 44.019531 C 130.015625 45.171875 129.921875 46.386719 130.050781 47.558594 C 130.1875 48.90625 130.117188 50.265625 130.4375 51.601562 C 130.8125 49.460938 130.730469 47.304688 130.898438 45.15625 C 131 44.058594 130.925781 42.917969 131.195312 41.835938 C 131.566406 44.613281 131.488281 47.414062 131.671875 50.195312 C 131.753906 51.070312 131.683594 51.960938 131.914062 52.816406 C 132.289062 50.210938 132.21875 47.59375 132.417969 44.980469 C 132.507812 44.261719 132.410156 43.394531 132.683594 42.757812 C 133.109375 45.46875 132.929688 48.191406 133.382812 50.902344 C 133.558594 50.835938 133.488281 50.488281 133.546875 50.339844 C 133.8125 48.398438 133.714844 46.441406 134.140625 44.503906 C 134.441406 45.128906 134.359375 45.855469 134.476562 46.519531 C 134.628906 47.46875 134.542969 48.445312 134.910156 49.382812 C 135.375 48.195312 135.15625 46.964844 135.628906 45.777344 C 135.921875 45.972656 135.8125 46.347656 135.925781 46.601562 C 136.113281 47.1875 135.996094 47.820312 136.40625 48.382812 C 136.882812 47.792969 136.636719 47.113281 137.136719 46.527344 C 137.535156 46.808594 137.441406 47.214844 137.65625 47.539062 C 137.65625 47.625 137.871094 47.96875 138.046875 47.734375 C 138.308594 47.480469 138.210938 47.128906 138.664062 46.925781 C 139.09375 47.070312 138.921875 47.445312 139.441406 47.542969 C 139.804688 47.449219 139.75 47.113281 140.238281 47.132812 C 140.511719 47.21875 140.757812 47.53125 141.167969 47.351562 C 141.324219 47.292969 141.484375 47.195312 141.726562 47.21875 "/>
<path style="fill:none;stroke-width:0.2;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(12.548828%,29.019165%,52.940369%);stroke-opacity:1;stroke-miterlimit:10;" d="M 102.371094 47.25 C 102.777344 47.253906 103.101562 47.617188 103.457031 47.363281 C 103.582031 47.257812 103.949219 47.03125 104.15625 47.242188 C 104.363281 47.34375 104.371094 47.609375 104.742188 47.597656 C 105.132812 47.417969 105 47.070312 105.464844 46.9375 C 105.925781 47.222656 105.722656 47.65625 106.203125 47.925781 C 106.707031 47.484375 106.46875 46.929688 106.941406 46.484375 C 107.390625 46.992188 107.265625 47.597656 107.488281 48.136719 C 107.574219 48.238281 107.496094 48.523438 107.738281 48.546875 C 108.207031 47.582031 107.976562 46.558594 108.457031 45.601562 C 108.875 46.652344 108.789062 47.742188 108.988281 48.8125 C 109.074219 49.101562 108.984375 49.511719 109.234375 49.738281 C 109.710938 47.855469 109.5 45.945312 109.957031 44.066406 C 110.304688 45.21875 110.210938 46.429688 110.339844 47.605469 C 110.472656 48.945312 110.402344 50.3125 110.722656 51.644531 C 111.101562 49.507812 111.019531 47.351562 111.183594 45.207031 C 111.285156 44.101562 111.214844 42.960938 111.484375 41.878906 C 111.851562 44.664062 111.777344 47.457031 111.960938 50.242188 C 112.039062 51.113281 111.972656 52.003906 112.203125 52.863281 C 112.574219 50.253906 112.507812 47.636719 112.707031 45.027344 C 112.796875 44.304688 112.699219 43.441406 112.96875 42.800781 C 113.398438 45.511719 113.214844 48.234375 113.671875 50.945312 C 113.847656 50.882812 113.773438 50.539062 113.835938 50.386719 C 114.101562 48.441406 114.003906 46.488281 114.429688 44.546875 C 114.730469 45.175781 114.648438 45.898438 114.765625 46.5625 C 114.914062 47.515625 114.832031 48.488281 115.199219 49.429688 C 115.660156 48.238281 115.445312 47.011719 115.917969 45.820312 C 116.210938 46.019531 116.101562 46.390625 116.214844 46.644531 C 116.402344 47.230469 116.285156 47.863281 116.695312 48.425781 C 117.167969 47.839844 116.925781 47.15625 117.425781 46.570312 C 117.824219 46.851562 117.730469 47.257812 117.945312 47.582031 C 117.945312 47.671875 118.160156 48.011719 118.335938 47.777344 C 118.597656 47.523438 118.5 47.171875 118.953125 46.972656 C 119.382812 47.117188 119.207031 47.488281 119.730469 47.585938 C 120.089844 47.492188 120.039062 47.164062 120.527344 47.175781 C 120.796875 47.265625 121.042969 47.574219 121.457031 47.394531 C 121.613281 47.335938 121.773438 47.238281 122.015625 47.261719 "/>
<path style="fill:none;stroke-width:0.2;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 102.371094 47.335938 C 102.617188 47.179688 103.066406 47.230469 103.226562 47.386719 C 103.425781 47.570312 103.847656 47.449219 103.925781 47.304688 C 104 47.195312 104.355469 47.007812 104.511719 47.207031 C 104.742188 47.339844 104.703125 47.613281 105.097656 47.664062 C 105.53125 47.433594 105.359375 47.054688 105.828125 46.851562 C 106.320312 47.207031 106.097656 47.691406 106.566406 48.046875 C 107.085938 47.515625 106.867188 46.878906 107.289062 46.320312 C 107.574219 46.394531 107.464844 46.695312 107.566406 46.835938 C 107.78125 47.484375 107.6875 48.171875 108.085938 48.796875 C 108.589844 47.65625 108.382812 46.464844 108.792969 45.316406 C 108.976562 45.261719 108.921875 45.589844 108.976562 45.652344 C 109.273438 47.152344 109.167969 48.671875 109.589844 50.15625 C 110 48.554688 109.90625 46.925781 110.097656 45.3125 C 110.191406 44.761719 110.101562 44.054688 110.367188 43.585938 C 110.828125 46.445312 110.648438 49.320312 111.070312 52.179688 C 111.226562 52.175781 111.167969 51.769531 111.214844 51.632812 C 111.515625 48.195312 111.449219 44.757812 111.820312 41.324219 "/>
<path style="fill:none;stroke-width:0.2;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 111.871094 41.324219 C 112.28125 44.988281 112.125 48.65625 112.558594 52.320312 C 112.707031 52.414062 112.664062 51.90625 112.707031 51.792969 C 112.992188 48.949219 112.90625 46.109375 113.316406 43.277344 C 113.480469 43.324219 113.417969 43.671875 113.46875 43.820312 C 113.742188 46.054688 113.648438 48.300781 114.074219 50.527344 C 114.363281 49.875 114.28125 49.125 114.390625 48.4375 C 114.550781 47.265625 114.460938 46.066406 114.84375 44.90625 C 115.300781 46.300781 115.09375 47.726562 115.5625 49.113281 C 115.835938 48.933594 115.726562 48.5625 115.832031 48.320312 C 116.035156 47.566406 115.910156 46.773438 116.339844 46.046875 C 116.816406 46.753906 116.566406 47.539062 117.070312 48.25 C 117.460938 47.925781 117.363281 47.484375 117.558594 47.117188 C 117.660156 47.023438 117.582031 46.695312 117.894531 46.714844 C 118.257812 47.050781 118.101562 47.480469 118.585938 47.777344 C 119.035156 47.585938 118.839844 47.199219 119.34375 47.03125 C 119.761719 47.140625 119.628906 47.492188 120.140625 47.539062 C 120.460938 47.464844 120.527344 47.113281 120.996094 47.226562 C 121.222656 47.375 121.667969 47.527344 122.003906 47.332031 C 122.042969 47.316406 122.082031 47.304688 122.128906 47.296875 "/>
<path style="fill:none;stroke-width:0.2;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 122.082031 47.292969 C 122.328125 47.136719 122.777344 47.1875 122.9375 47.34375 C 123.136719 47.527344 123.558594 47.40625 123.640625 47.261719 C 123.710938 47.148438 124.066406 46.964844 124.226562 47.15625 C 124.453125 47.292969 124.417969 47.570312 124.808594 47.617188 C 125.242188 47.390625 125.070312 47.011719 125.539062 46.808594 C 126.03125 47.164062 125.808594 47.648438 126.277344 48 C 126.796875 47.46875 126.578125 46.835938 127 46.28125 C 127.285156 46.351562 127.175781 46.648438 127.277344 46.789062 C 127.496094 47.4375 127.398438 48.128906 127.796875 48.753906 C 128.300781 47.613281 128.097656 46.421875 128.507812 45.269531 C 128.6875 45.214844 128.636719 45.542969 128.6875 45.609375 C 128.984375 47.105469 128.878906 48.625 129.304688 50.113281 C 129.714844 48.511719 129.617188 46.882812 129.808594 45.269531 C 129.90625 44.714844 129.8125 44.007812 130.082031 43.542969 C 130.539062 46.402344 130.359375 49.273438 130.78125 52.136719 C 130.9375 52.132812 130.878906 51.722656 130.925781 51.585938 C 131.226562 48.152344 131.160156 44.714844 131.53125 41.28125 "/>
<path style="fill:none;stroke-width:0.2;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 131.582031 41.28125 C 131.992188 44.945312 131.839844 48.613281 132.269531 52.277344 C 132.421875 52.367188 132.378906 51.863281 132.417969 51.742188 C 132.703125 48.90625 132.617188 46.066406 133.027344 43.230469 C 133.191406 43.28125 133.128906 43.628906 133.179688 43.777344 C 133.457031 46.011719 133.359375 48.253906 133.785156 50.480469 C 134.074219 49.832031 133.992188 49.082031 134.101562 48.394531 C 134.265625 47.222656 134.171875 46.023438 134.554688 44.863281 C 135.015625 46.253906 134.804688 47.679688 135.273438 49.070312 C 135.546875 48.890625 135.4375 48.515625 135.542969 48.273438 C 135.746094 47.523438 135.621094 46.726562 136.050781 46 C 136.527344 46.707031 136.277344 47.492188 136.78125 48.199219 C 137.171875 47.882812 137.074219 47.4375 137.269531 47.070312 C 137.371094 46.976562 137.292969 46.652344 137.605469 46.671875 C 137.972656 47.003906 137.8125 47.433594 138.296875 47.734375 C 138.75 47.539062 138.550781 47.15625 139.054688 46.988281 C 139.472656 47.097656 139.339844 47.449219 139.851562 47.488281 C 140.175781 47.421875 140.238281 47.070312 140.707031 47.179688 C 140.9375 47.324219 141.378906 47.484375 141.714844 47.28125 C 141.753906 47.273438 141.796875 47.261719 141.839844 47.25 "/>
<path style="fill:none;stroke-width:0.298878;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(12.548828%,29.019165%,52.940369%);stroke-opacity:1;stroke-miterlimit:10;" d="M 121.320312 235.00117 C 121.433594 238.830767 121.359375 242.686534 121.675781 246.498684 C 122.042969 241.683337 121.96875 236.824372 122.144531 231.991577 C 122.242188 229.950289 122.15625 227.778148 122.441406 225.815371 C 122.894531 231.232637 122.683594 236.684797 123.152344 242.093339 C 123.359375 241.814188 123.273438 240.95929 123.34375 240.496947 C 123.585938 236.885436 123.488281 233.230308 123.921875 229.644968 C 124.324219 232.279452 124.242188 235.02734 124.488281 237.705441 C 124.570312 238.019485 124.472656 238.760979 124.707031 238.900554 C 125.132812 236.69352 124.910156 234.364357 125.417969 232.183493 C 125.902344 233.692651 125.671875 235.428619 126.136719 236.972671 C 126.453125 236.763308 126.359375 236.030537 126.484375 235.646705 C 126.648438 235.00117 126.546875 234.163718 126.933594 233.622864 C 127.378906 234.303293 127.167969 235.323937 127.675781 235.96075 C 128.125 235.576918 127.929688 234.652231 128.453125 234.355634 C 128.832031 234.582444 128.75 235.446066 129.257812 235.428619 C 129.527344 235.201809 129.78125 234.373081 130.199219 234.870318 C 130.40625 235.245426 130.859375 235.306491 131.128906 234.966276 C 131.5 234.556273 131.863281 235.036063 132.136719 235.28032 C 132.636719 235.463513 132.671875 234.312017 133.144531 234.634785 C 133.429688 234.913935 133.402344 235.568194 133.808594 235.646705 C 134.226562 235.227979 134.074219 234.355634 134.546875 234.04159 C 135.007812 234.730743 134.804688 235.777557 135.289062 236.414369 C 135.789062 235.350108 135.550781 234.015419 136.027344 232.951158 C 136.480469 234.242229 136.355469 235.742663 136.59375 237.103522 C 136.660156 237.269268 136.613281 238.002038 136.832031 237.888633 C 137.28125 235.568194 137.0625 233.116903 137.542969 230.822634 C 137.964844 233.474565 137.878906 236.222453 138.089844 238.918001 C 138.175781 239.511196 138.089844 240.296307 138.3125 240.802268 C 138.800781 236.266071 138.585938 231.66881 139.03125 227.132613 C 139.273438 228.083469 139.1875 229.357094 139.269531 230.421355 C 139.484375 235.411172 139.421875 240.418436 139.800781 245.390805 C 140.160156 241.098865 140.070312 236.728414 140.214844 232.40158 C 140.339844 228.903474 140.257812 225.274517 140.566406 221.837475 C 140.851562 226.103245 140.800781 230.395185 140.914062 234.669678 " transform="matrix(1,0,0,0.447787,0,0)"/>
<path style="fill:none;stroke-width:0.298878;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(12.548828%,29.019165%,52.940369%);stroke-opacity:1;stroke-miterlimit:10;" d="M 101.609375 235.411172 C 101.722656 239.240769 101.648438 243.096536 101.960938 246.908686 C 102.332031 242.093339 102.257812 237.234374 102.429688 232.40158 C 102.53125 230.360291 102.445312 228.188151 102.730469 226.225373 C 103.183594 231.633916 102.972656 237.094799 103.441406 242.503341 C 103.648438 242.215467 103.558594 241.369292 103.632812 240.906949 C 103.871094 237.295438 103.777344 233.640311 104.210938 230.05497 C 104.613281 232.68073 104.53125 235.437342 104.777344 238.10672 C 104.859375 238.429488 104.757812 239.170981 104.996094 239.301833 C 105.421875 237.103522 105.199219 234.77436 105.707031 232.593496 C 106.191406 234.102654 105.960938 235.838621 106.425781 237.37395 C 106.742188 237.164587 106.648438 236.44054 106.773438 236.056708 C 106.9375 235.411172 106.835938 234.57372 107.222656 234.032866 C 107.667969 234.713296 107.457031 235.73394 107.960938 236.370752 C 108.410156 235.978197 108.21875 235.062234 108.742188 234.765636 C 109.121094 234.992446 109.039062 235.856068 109.546875 235.829898 C 109.816406 235.611812 110.066406 234.783083 110.488281 235.28032 C 110.695312 235.655429 111.144531 235.716493 111.417969 235.376278 C 111.789062 234.957552 112.148438 235.446066 112.425781 235.690323 C 112.925781 235.864792 112.960938 234.722019 113.433594 235.044787 C 113.714844 235.315214 113.691406 235.978197 114.097656 236.056708 C 114.515625 235.629258 114.363281 234.765636 114.835938 234.451592 C 115.296875 235.140745 115.09375 236.18756 115.574219 236.824372 C 116.074219 235.76011 115.839844 234.425422 116.316406 233.352437 C 116.769531 234.652231 116.644531 236.152666 116.882812 237.513525 C 116.949219 237.679271 116.902344 238.412041 117.121094 238.298636 C 117.566406 235.978197 117.351562 233.526906 117.832031 231.232637 C 118.253906 233.884567 118.167969 236.632456 118.378906 239.328004 C 118.464844 239.921199 118.375 240.70631 118.597656 241.21227 C 119.089844 236.676073 118.875 232.078812 119.320312 227.542615 C 119.5625 228.493472 119.472656 229.767096 119.558594 230.831358 C 119.773438 235.821174 119.710938 240.828438 120.085938 245.800808 C 120.449219 241.500144 120.355469 237.138416 120.503906 232.811582 C 120.625 229.304753 120.546875 225.684519 120.855469 222.247478 C 121.140625 226.513247 121.089844 230.805188 121.199219 235.079681 " transform="matrix(1,0,0,0.447787,0,0)"/>
<path style="fill:none;stroke-width:0.298878;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 101.609375 222.212584 C 102.035156 230.00263 101.863281 237.827569 102.308594 245.626339 C 102.472656 245.75719 102.421875 244.623141 102.46875 244.31782 C 102.746094 238.647574 102.648438 232.951158 103.078125 227.298358 C 103.363281 228.964538 103.285156 230.874975 103.394531 232.62839 C 103.554688 235.620535 103.460938 238.665021 103.84375 241.622272 C 104.304688 238.054379 104.097656 234.399251 104.5625 230.831358 C 104.828125 231.276254 104.722656 232.166047 104.824219 232.750518 C 105.027344 234.739466 104.90625 236.815648 105.34375 238.743532 C 105.820312 236.902883 105.566406 234.887765 106.070312 233.047116 C 106.460938 233.875844 106.359375 234.983723 106.550781 235.908409 C 106.664062 236.222453 106.5625 236.929053 106.878906 237.051182 C 107.277344 236.178836 107.085938 235.062234 107.589844 234.259676 C 108.042969 234.783083 107.835938 235.73394 108.347656 236.205007 C 108.765625 235.899686 108.621094 235.062234 109.125 234.879041 C 109.476562 235.05351 109.488281 235.934579 109.980469 235.725216 C 110.203125 235.454789 110.554688 234.887765 110.910156 235.341384 C 111.199219 235.742663 111.695312 235.559471 111.957031 235.236703 C 112.46875 234.844147 112.660156 236.170113 113.117188 235.637982 C 113.335938 235.446066 113.410156 234.739466 113.78125 234.931382 C 114.105469 235.28032 114.03125 236.004367 114.460938 236.205007 C 114.90625 235.664152 114.726562 234.730743 115.199219 234.242229 C 115.6875 235.105851 115.464844 236.274794 115.941406 237.120969 C 116.460938 235.829898 116.230469 234.29457 116.671875 232.959881 C 117.015625 233.492012 116.882812 234.399251 117.015625 235.05351 C 117.195312 236.318411 117.082031 237.757782 117.464844 238.926725 C 117.96875 236.143942 117.734375 233.256479 118.195312 230.473696 C 118.5625 232.453921 118.464844 234.582444 118.609375 236.623732 C 118.734375 238.464382 118.660156 240.427159 118.972656 242.19802 C 119.464844 236.955224 119.257812 231.651363 119.683594 226.391119 C 119.859375 226.399842 119.792969 227.359423 119.847656 227.68219 C 120.140625 234.163718 120.058594 240.671416 120.453125 247.14422 C 120.679688 245.75719 120.605469 244.082287 120.683594 242.581853 C 120.890625 235.350108 120.855469 228.10964 121.195312 220.877895 " transform="matrix(1,0,0,0.447787,0,0)"/>
<path style="fill:none;stroke-width:0.298878;stroke-linecap:butt;stroke-linejoin:round;stroke:rgb(64.312744%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 121.320312 221.802581 C 121.75 229.592627 121.574219 237.417567 122.019531 245.216336 C 122.183594 245.347188 122.132812 244.213139 122.179688 243.907818 C 122.457031 238.237572 122.363281 232.549879 122.789062 226.888356 C 123.074219 228.554536 122.996094 230.464973 123.105469 232.227111 C 123.269531 235.210533 123.171875 238.263742 123.554688 241.21227 C 124.015625 237.644377 123.808594 233.997972 124.277344 230.430079 C 124.539062 230.866252 124.433594 231.764768 124.535156 232.340516 C 124.738281 234.329464 124.617188 236.414369 125.054688 238.342253 C 125.53125 236.501604 125.28125 234.477762 125.785156 232.637113 C 126.171875 233.465841 126.070312 234.57372 126.261719 235.498407 C 126.375 235.821174 126.273438 236.519051 126.589844 236.641179 C 126.988281 235.768834 126.800781 234.652231 127.300781 233.849674 C 127.753906 234.373081 127.546875 235.332661 128.058594 235.795004 C 128.476562 235.489683 128.332031 234.652231 128.835938 234.469039 C 129.1875 234.643508 129.199219 235.5333 129.691406 235.315214 C 129.914062 235.044787 130.265625 234.486486 130.621094 234.931382 C 130.910156 235.341384 131.40625 235.149468 131.667969 234.826701 C 132.179688 234.434145 132.371094 235.76011 132.828125 235.236703 C 133.046875 235.044787 133.121094 234.329464 133.492188 234.52138 C 133.816406 234.870318 133.742188 235.594365 134.171875 235.795004 C 134.621094 235.25415 134.4375 234.32074 134.914062 233.84095 C 135.402344 234.695849 135.179688 235.864792 135.652344 236.710967 C 136.171875 235.419896 135.941406 233.884567 136.382812 232.549879 C 136.726562 233.082009 136.597656 233.997972 136.726562 234.652231 C 136.90625 235.908409 136.792969 237.347779 137.179688 238.516722 C 137.679688 235.742663 137.445312 232.846476 137.90625 230.063694 C 138.273438 232.043918 138.175781 234.172441 138.320312 236.21373 C 138.449219 238.054379 138.371094 240.017157 138.6875 241.796742 C 139.175781 236.545221 138.972656 231.24136 139.394531 225.98984 C 139.570312 225.98984 139.503906 226.94942 139.558594 227.272188 C 139.851562 233.762439 139.773438 240.261413 140.164062 246.734217 C 140.394531 245.355911 140.320312 243.672284 140.394531 242.180574 C 140.601562 234.940105 140.566406 227.699637 140.910156 220.467893 " transform="matrix(1,0,0,0.447787,0,0)"/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 8.003906 8.652344 C 7.136719 8.652344 6.535156 8.753906 6.191406 8.949219 C 5.855469 9.148438 5.691406 9.488281 5.691406 9.964844 C 5.691406 10.351562 5.816406 10.660156 6.066406 10.882812 C 6.324219 11.105469 6.667969 11.214844 7.097656 11.214844 C 7.699219 11.214844 8.179688 11.007812 8.535156 10.589844 C 8.898438 10.164062 9.082031 9.59375 9.082031 8.882812 L 9.082031 8.652344 Z M 10.160156 8.199219 L 10.160156 11.949219 L 9.082031 11.949219 L 9.082031 10.949219 C 8.832031 11.34375 8.523438 11.644531 8.160156 11.839844 C 7.792969 12.027344 7.347656 12.121094 6.816406 12.121094 C 6.136719 12.121094 5.601562 11.933594 5.207031 11.558594 C 4.808594 11.175781 4.613281 10.667969 4.613281 10.042969 C 4.613281 9.300781 4.855469 8.746094 5.347656 8.371094 C 5.847656 7.996094 6.585938 7.808594 7.566406 7.808594 L 9.082031 7.808594 L 9.082031 7.699219 C 9.082031 7.199219 8.914062 6.816406 8.582031 6.542969 C 8.257812 6.273438 7.804688 6.132812 7.222656 6.132812 C 6.847656 6.132812 6.476562 6.183594 6.113281 6.277344 C 5.757812 6.371094 5.417969 6.507812 5.097656 6.683594 L 5.097656 5.683594 C 5.492188 5.527344 5.871094 5.414062 6.238281 5.339844 C 6.613281 5.269531 6.976562 5.230469 7.332031 5.230469 C 8.277344 5.230469 8.988281 5.476562 9.457031 5.964844 C 9.925781 6.457031 10.160156 7.199219 10.160156 8.199219 Z M 10.160156 8.199219 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 12.222656 2.839844 L 13.160156 2.839844 C 13.742188 3.769531 14.179688 4.675781 14.472656 5.558594 C 14.761719 6.433594 14.910156 7.308594 14.910156 8.183594 C 14.910156 9.058594 14.761719 9.941406 14.472656 10.824219 C 14.179688 11.710938 13.742188 12.609375 13.160156 13.527344 L 12.222656 13.527344 C 12.730469 12.628906 13.117188 11.742188 13.378906 10.855469 C 13.636719 9.96875 13.769531 9.082031 13.769531 8.183594 C 13.769531 7.277344 13.636719 6.382812 13.378906 5.507812 C 13.117188 4.628906 12.730469 3.738281 12.222656 2.839844 Z M 12.222656 2.839844 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 88.402344 107.390625 L 90.714844 111.503906 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 87.738281 117.316406 L 89.800781 117.316406 L 89.800781 117.816406 L 87.019531 117.816406 L 87.019531 117.316406 C 87.246094 117.089844 87.554688 116.78125 87.941406 116.394531 C 88.324219 116 88.570312 115.746094 88.675781 115.628906 C 88.863281 115.410156 88.992188 115.230469 89.066406 115.082031 C 89.136719 114.9375 89.175781 114.792969 89.175781 114.644531 C 89.175781 114.417969 89.089844 114.230469 88.925781 114.082031 C 88.769531 113.9375 88.558594 113.863281 88.300781 113.863281 C 88.113281 113.863281 87.914062 113.894531 87.707031 113.957031 C 87.507812 114.019531 87.289062 114.121094 87.050781 114.253906 L 87.050781 113.660156 C 87.289062 113.558594 87.511719 113.484375 87.722656 113.441406 C 87.929688 113.386719 88.117188 113.363281 88.285156 113.363281 C 88.742188 113.363281 89.101562 113.480469 89.363281 113.707031 C 89.632812 113.925781 89.769531 114.230469 89.769531 114.613281 C 89.769531 114.792969 89.730469 114.964844 89.660156 115.128906 C 89.597656 115.285156 89.476562 115.46875 89.300781 115.691406 C 89.257812 115.746094 89.101562 115.90625 88.832031 116.175781 C 88.570312 116.449219 88.207031 116.828125 87.738281 117.316406 Z M 87.738281 117.316406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 93.824219 114.535156 L 92.636719 116.128906 L 93.886719 117.816406 L 93.246094 117.816406 L 92.292969 116.519531 L 91.339844 117.816406 L 90.699219 117.816406 L 91.980469 116.09375 L 90.808594 114.535156 L 91.449219 114.535156 L 92.308594 115.707031 L 93.183594 114.535156 Z M 93.824219 114.535156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 94.945312 117.316406 L 95.914062 117.316406 L 95.914062 113.988281 L 94.851562 114.191406 L 94.851562 113.660156 L 95.898438 113.441406 L 96.492188 113.441406 L 96.492188 117.316406 L 97.460938 117.316406 L 97.460938 117.816406 L 94.945312 117.816406 Z M 94.945312 117.316406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 100.128906 115.394531 C 99.855469 115.394531 99.644531 115.488281 99.488281 115.675781 C 99.332031 115.855469 99.253906 116.09375 99.253906 116.410156 C 99.253906 116.71875 99.332031 116.96875 99.488281 117.160156 C 99.644531 117.339844 99.855469 117.425781 100.128906 117.425781 C 100.386719 117.425781 100.597656 117.339844 100.753906 117.160156 C 100.910156 116.96875 100.988281 116.71875 100.988281 116.410156 C 100.988281 116.09375 100.910156 115.855469 100.753906 115.675781 C 100.597656 115.488281 100.386719 115.394531 100.128906 115.394531 Z M 101.300781 113.535156 L 101.300781 114.082031 C 101.152344 114.007812 101.003906 113.957031 100.847656 113.925781 C 100.699219 113.882812 100.550781 113.863281 100.394531 113.863281 C 100.007812 113.863281 99.710938 113.996094 99.503906 114.253906 C 99.292969 114.511719 99.179688 114.917969 99.160156 115.457031 C 99.273438 115.28125 99.414062 115.152344 99.582031 115.066406 C 99.757812 114.96875 99.949219 114.925781 100.160156 114.925781 C 100.597656 114.925781 100.941406 115.0625 101.191406 115.332031 C 101.449219 115.589844 101.582031 115.953125 101.582031 116.410156 C 101.582031 116.859375 101.445312 117.214844 101.175781 117.488281 C 100.914062 117.757812 100.566406 117.894531 100.128906 117.894531 C 99.617188 117.894531 99.226562 117.703125 98.957031 117.316406 C 98.695312 116.933594 98.566406 116.371094 98.566406 115.628906 C 98.566406 114.941406 98.726562 114.394531 99.050781 113.988281 C 99.382812 113.574219 99.824219 113.363281 100.378906 113.363281 C 100.523438 113.363281 100.667969 113.378906 100.816406 113.410156 C 100.972656 113.441406 101.132812 113.484375 101.300781 113.535156 Z M 101.300781 113.535156 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 105.011719 116.175781 C 105.011719 115.78125 104.925781 115.46875 104.761719 115.253906 C 104.605469 115.027344 104.378906 114.910156 104.089844 114.910156 C 103.808594 114.910156 103.582031 115.027344 103.417969 115.253906 C 103.261719 115.46875 103.183594 115.78125 103.183594 116.175781 C 103.183594 116.574219 103.261719 116.882812 103.417969 117.113281 C 103.582031 117.339844 103.808594 117.457031 104.089844 117.457031 C 104.378906 117.457031 104.605469 117.339844 104.761719 117.113281 C 104.925781 116.882812 105.011719 116.574219 105.011719 116.175781 Z M 103.183594 115.035156 C 103.285156 114.839844 103.425781 114.691406 103.605469 114.59375 C 103.78125 114.503906 103.988281 114.457031 104.230469 114.457031 C 104.625 114.457031 104.949219 114.621094 105.199219 114.941406 C 105.449219 115.253906 105.574219 115.667969 105.574219 116.175781 C 105.574219 116.699219 105.449219 117.113281 105.199219 117.425781 C 104.949219 117.738281 104.625 117.894531 104.230469 117.894531 C 103.988281 117.894531 103.78125 117.84375 103.605469 117.753906 C 103.425781 117.660156 103.285156 117.511719 103.183594 117.316406 L 103.183594 117.816406 L 102.636719 117.816406 L 102.636719 113.253906 L 103.183594 113.253906 Z M 103.183594 115.035156 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 118.929688 69.070312 L 123.042969 71.386719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 125.035156 71.648438 L 127.097656 71.648438 L 127.097656 72.148438 L 124.316406 72.148438 L 124.316406 71.648438 C 124.542969 71.421875 124.851562 71.113281 125.238281 70.726562 C 125.621094 70.332031 125.867188 70.078125 125.972656 69.960938 C 126.160156 69.742188 126.289062 69.5625 126.363281 69.414062 C 126.433594 69.269531 126.472656 69.125 126.472656 68.976562 C 126.472656 68.75 126.386719 68.5625 126.222656 68.414062 C 126.066406 68.269531 125.855469 68.195312 125.597656 68.195312 C 125.410156 68.195312 125.210938 68.226562 125.003906 68.289062 C 124.804688 68.351562 124.585938 68.453125 124.347656 68.585938 L 124.347656 67.992188 C 124.585938 67.886719 124.808594 67.816406 125.019531 67.773438 C 125.226562 67.71875 125.414062 67.695312 125.582031 67.695312 C 126.039062 67.695312 126.398438 67.8125 126.660156 68.039062 C 126.929688 68.257812 127.066406 68.5625 127.066406 68.945312 C 127.066406 69.125 127.027344 69.296875 126.957031 69.460938 C 126.894531 69.617188 126.773438 69.800781 126.597656 70.023438 C 126.554688 70.078125 126.398438 70.238281 126.128906 70.507812 C 125.867188 70.78125 125.503906 71.160156 125.035156 71.648438 Z M 125.035156 71.648438 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 131.121094 68.867188 L 129.933594 70.460938 L 131.183594 72.148438 L 130.542969 72.148438 L 129.589844 70.851562 L 128.636719 72.148438 L 127.996094 72.148438 L 129.277344 70.425781 L 128.105469 68.867188 L 128.746094 68.867188 L 129.605469 70.039062 L 130.480469 68.867188 Z M 131.121094 68.867188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 132.246094 71.648438 L 133.214844 71.648438 L 133.214844 68.320312 L 132.152344 68.523438 L 132.152344 67.992188 L 133.199219 67.773438 L 133.792969 67.773438 L 133.792969 71.648438 L 134.761719 71.648438 L 134.761719 72.148438 L 132.246094 72.148438 Z M 132.246094 71.648438 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 138.363281 70.507812 C 138.363281 70.113281 138.277344 69.800781 138.113281 69.585938 C 137.957031 69.359375 137.730469 69.242188 137.441406 69.242188 C 137.160156 69.242188 136.933594 69.359375 136.769531 69.585938 C 136.613281 69.800781 136.535156 70.113281 136.535156 70.507812 C 136.535156 70.90625 136.613281 71.214844 136.769531 71.445312 C 136.933594 71.675781 137.160156 71.789062 137.441406 71.789062 C 137.730469 71.789062 137.957031 71.675781 138.113281 71.445312 C 138.277344 71.214844 138.363281 70.90625 138.363281 70.507812 Z M 136.535156 69.367188 C 136.636719 69.171875 136.777344 69.023438 136.957031 68.925781 C 137.132812 68.835938 137.339844 68.789062 137.582031 68.789062 C 137.976562 68.789062 138.300781 68.953125 138.550781 69.273438 C 138.800781 69.585938 138.925781 70 138.925781 70.507812 C 138.925781 71.03125 138.800781 71.445312 138.550781 71.757812 C 138.300781 72.070312 137.976562 72.226562 137.582031 72.226562 C 137.339844 72.226562 137.132812 72.175781 136.957031 72.085938 C 136.777344 71.992188 136.636719 71.84375 136.535156 71.648438 L 136.535156 72.148438 L 135.988281 72.148438 L 135.988281 67.585938 L 136.535156 67.585938 Z M 136.535156 69.367188 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(12.548828%,29.019165%,52.940369%);stroke-opacity:1;stroke-miterlimit:4;" d="M 94.015625 105.113281 L 99.605469 105.113281 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 99.46875 104.203125 L 100.984375 104.203125 L 100.984375 106.105469 L 99.46875 106.105469 Z M 99.46875 104.203125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(12.548828%,29.019165%,52.940369%);fill-opacity:1;" d="M 100.980469 105.164062 L 100.039062 105.894531 L 99.097656 106.621094 L 99.097656 103.710938 Z M 100.980469 105.164062 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(12.548828%,29.019165%,52.940369%);stroke-opacity:1;stroke-miterlimit:4;" d="M 94.015625 47.3125 L 99.605469 47.3125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(100%,100%,100%);fill-opacity:1;" d="M 99.46875 46.402344 L 100.984375 46.402344 L 100.984375 48.300781 L 99.46875 48.300781 Z M 99.46875 46.402344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(12.548828%,29.019165%,52.940369%);fill-opacity:1;" d="M 100.980469 47.363281 L 100.039062 48.089844 L 99.097656 48.820312 L 99.097656 45.90625 L 100.039062 46.632812 Z M 100.980469 47.363281 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 52.070312 33.644531 L 86.910156 33.558594 L 86.910156 11.992188 L 52.070312 12.074219 Z M 52.070312 33.644531 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 49.464844 37.332031 L 84.304688 37.25 L 84.304688 15.683594 L 49.464844 15.769531 Z M 49.464844 37.332031 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:bevel;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 70.402344 26.742188 L 52.570312 26.742188 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 52.773438 34.175781 L 54.054688 34.175781 L 54.054688 29.742188 L 52.648438 30.023438 L 52.648438 29.300781 L 54.054688 29.023438 L 54.835938 29.023438 L 54.835938 34.175781 L 56.132812 34.175781 L 56.132812 34.851562 L 52.773438 34.851562 Z M 52.773438 34.175781 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 57.257812 32.335938 L 59.367188 32.335938 L 59.367188 32.976562 L 57.257812 32.976562 Z M 57.257812 32.335938 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 60.195312 30.476562 L 63.617188 30.476562 L 63.617188 31.132812 L 60.914062 34.273438 L 63.617188 34.273438 L 63.617188 34.851562 L 60.101562 34.851562 L 60.101562 34.195312 L 62.804688 31.050781 L 60.195312 31.050781 Z M 60.195312 30.476562 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 65.867188 30.089844 L 67.179688 30.089844 L 67.179688 30.480469 L 65.867188 30.480469 Z M 65.867188 30.089844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 68.121094 31.230469 L 68.917969 31.230469 L 68.917969 28.449219 L 68.042969 28.632812 L 68.042969 28.183594 L 68.917969 28.007812 L 69.417969 28.007812 L 69.417969 31.230469 L 70.214844 31.230469 L 70.214844 31.652344 L 68.121094 31.652344 Z M 68.121094 31.230469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 60.128906 20.78125 L 63.550781 20.78125 L 63.550781 21.4375 L 60.847656 24.578125 L 63.550781 24.578125 L 63.550781 25.15625 L 60.035156 25.15625 L 60.035156 24.5 L 62.738281 21.359375 L 60.128906 21.359375 Z M 60.128906 20.78125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 65.800781 20.386719 L 67.113281 20.386719 L 67.113281 20.78125 L 65.800781 20.78125 Z M 65.800781 20.386719 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 68.054688 21.53125 L 68.851562 21.53125 L 68.851562 18.75 L 67.976562 18.9375 L 67.976562 18.484375 L 68.851562 18.3125 L 69.351562 18.3125 L 69.351562 21.53125 L 70.148438 21.53125 L 70.148438 21.953125 L 68.054688 21.953125 Z M 68.054688 21.53125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 74.472656 24.476562 L 74.472656 26.648438 L 76.644531 26.648438 L 76.644531 27.320312 L 74.472656 27.320312 L 74.472656 29.492188 L 73.816406 29.492188 L 73.816406 27.320312 L 71.628906 27.320312 L 71.628906 26.648438 L 73.816406 26.648438 L 73.816406 24.476562 Z M 74.472656 24.476562 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 51.742188 91.34375 L 86.582031 91.261719 L 86.582031 69.695312 L 51.742188 69.78125 Z M 51.742188 91.34375 "/>
<path style="fill-rule:evenodd;fill:rgb(100%,100%,100%);fill-opacity:1;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 49.136719 95.03125 L 83.976562 94.945312 L 83.976562 73.386719 L 49.136719 73.46875 Z M 49.136719 95.03125 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:bevel;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:10;" d="M 70.074219 84.445312 L 52.242188 84.445312 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 52.445312 91.882812 L 53.726562 91.882812 L 53.726562 87.445312 L 52.320312 87.726562 L 52.320312 87.007812 L 53.726562 86.726562 L 54.507812 86.726562 L 54.507812 91.882812 L 55.804688 91.882812 L 55.804688 92.550781 L 52.445312 92.550781 Z M 52.445312 91.882812 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 56.929688 90.039062 L 59.039062 90.039062 L 59.039062 90.679688 L 56.929688 90.679688 Z M 56.929688 90.039062 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 59.867188 88.175781 L 63.289062 88.175781 L 63.289062 88.835938 L 60.585938 91.976562 L 63.289062 91.976562 L 63.289062 92.550781 L 59.773438 92.550781 L 59.773438 91.898438 L 62.476562 88.757812 L 59.867188 88.757812 Z M 59.867188 88.175781 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 65.539062 87.792969 L 66.851562 87.792969 L 66.851562 88.183594 L 65.539062 88.183594 Z M 65.539062 87.792969 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 67.792969 88.933594 L 68.589844 88.933594 L 68.589844 86.152344 L 67.714844 86.339844 L 67.714844 85.882812 L 68.589844 85.714844 L 69.089844 85.714844 L 69.089844 88.933594 L 69.886719 88.933594 L 69.886719 89.355469 L 67.792969 89.355469 Z M 67.792969 88.933594 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 59.800781 78.480469 L 63.222656 78.480469 L 63.222656 79.132812 L 60.519531 82.277344 L 63.222656 82.277344 L 63.222656 82.855469 L 59.707031 82.855469 L 59.707031 82.199219 L 62.410156 79.058594 L 59.800781 79.058594 Z M 59.800781 78.480469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 65.472656 78.089844 L 66.785156 78.089844 L 66.785156 78.484375 L 65.472656 78.484375 Z M 65.472656 78.089844 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 67.726562 79.234375 L 68.523438 79.234375 L 68.523438 76.453125 L 67.648438 76.636719 L 67.648438 76.1875 L 68.523438 76.011719 L 69.023438 76.011719 L 69.023438 79.234375 L 69.820312 79.234375 L 69.820312 79.65625 L 67.726562 79.65625 Z M 67.726562 79.234375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 74.144531 82.175781 L 74.144531 84.34375 L 76.316406 84.34375 L 76.316406 85.019531 L 74.144531 85.019531 L 74.144531 87.191406 L 73.488281 87.191406 L 73.488281 85.019531 L 71.300781 85.019531 L 71.300781 84.34375 L 73.488281 84.34375 L 73.488281 82.175781 Z M 74.144531 82.175781 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 88.304688 49.875 L 90.617188 53.988281 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 87.636719 59.800781 L 89.699219 59.800781 L 89.699219 60.300781 L 86.917969 60.300781 L 86.917969 59.800781 C 87.144531 59.574219 87.453125 59.261719 87.839844 58.878906 C 88.222656 58.484375 88.46875 58.230469 88.574219 58.113281 C 88.761719 57.894531 88.890625 57.714844 88.964844 57.566406 C 89.035156 57.421875 89.074219 57.277344 89.074219 57.128906 C 89.074219 56.902344 88.988281 56.714844 88.824219 56.566406 C 88.667969 56.421875 88.457031 56.34375 88.199219 56.34375 C 88.011719 56.34375 87.8125 56.378906 87.605469 56.441406 C 87.40625 56.503906 87.1875 56.605469 86.949219 56.738281 L 86.949219 56.144531 C 87.1875 56.042969 87.410156 55.964844 87.621094 55.925781 C 87.828125 55.875 88.015625 55.84375 88.183594 55.84375 C 88.640625 55.84375 89 55.964844 89.261719 56.191406 C 89.53125 56.410156 89.667969 56.714844 89.667969 57.09375 C 89.667969 57.277344 89.628906 57.449219 89.558594 57.613281 C 89.496094 57.769531 89.375 57.957031 89.199219 58.175781 C 89.15625 58.230469 89 58.386719 88.730469 58.660156 C 88.46875 58.933594 88.105469 59.3125 87.636719 59.800781 Z M 87.636719 59.800781 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 93.726562 57.019531 L 92.539062 58.613281 L 93.789062 60.300781 L 93.148438 60.300781 L 92.195312 59.003906 L 91.242188 60.300781 L 90.601562 60.300781 L 91.882812 58.582031 L 90.710938 57.019531 L 91.351562 57.019531 L 92.210938 58.191406 L 93.085938 57.019531 Z M 93.726562 57.019531 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 94.847656 59.800781 L 95.816406 59.800781 L 95.816406 56.46875 L 94.753906 56.675781 L 94.753906 56.144531 L 95.800781 55.925781 L 96.394531 55.925781 L 96.394531 59.800781 L 97.363281 59.800781 L 97.363281 60.300781 L 94.847656 60.300781 Z M 94.847656 59.800781 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 100.027344 57.878906 C 99.753906 57.878906 99.542969 57.96875 99.386719 58.160156 C 99.230469 58.339844 99.152344 58.582031 99.152344 58.894531 C 99.152344 59.207031 99.230469 59.457031 99.386719 59.644531 C 99.542969 59.824219 99.753906 59.910156 100.027344 59.910156 C 100.285156 59.910156 100.496094 59.824219 100.652344 59.644531 C 100.808594 59.457031 100.886719 59.207031 100.886719 58.894531 C 100.886719 58.582031 100.808594 58.339844 100.652344 58.160156 C 100.496094 57.96875 100.285156 57.878906 100.027344 57.878906 Z M 101.199219 56.019531 L 101.199219 56.566406 C 101.050781 56.496094 100.902344 56.441406 100.746094 56.410156 C 100.597656 56.371094 100.449219 56.34375 100.292969 56.34375 C 99.90625 56.34375 99.609375 56.480469 99.402344 56.738281 C 99.191406 57 99.078125 57.402344 99.058594 57.941406 C 99.171875 57.761719 99.3125 57.632812 99.480469 57.550781 C 99.65625 57.457031 99.847656 57.410156 100.058594 57.410156 C 100.496094 57.410156 100.839844 57.546875 101.089844 57.816406 C 101.347656 58.078125 101.480469 58.4375 101.480469 58.894531 C 101.480469 59.339844 101.34375 59.703125 101.074219 59.96875 C 100.8125 60.246094 100.464844 60.378906 100.027344 60.378906 C 99.515625 60.378906 99.125 60.1875 98.855469 59.800781 C 98.59375 59.417969 98.464844 58.855469 98.464844 58.113281 C 98.464844 57.425781 98.625 56.878906 98.949219 56.46875 C 99.28125 56.058594 99.722656 55.84375 100.277344 55.84375 C 100.421875 55.84375 100.566406 55.863281 100.714844 55.894531 C 100.871094 55.925781 101.03125 55.964844 101.199219 56.019531 Z M 101.199219 56.019531 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 104.914062 58.660156 C 104.914062 58.261719 104.828125 57.957031 104.664062 57.738281 C 104.507812 57.507812 104.28125 57.394531 103.992188 57.394531 C 103.710938 57.394531 103.484375 57.507812 103.320312 57.738281 C 103.164062 57.957031 103.085938 58.261719 103.085938 58.660156 C 103.085938 59.058594 103.164062 59.371094 103.320312 59.59375 C 103.484375 59.828125 103.710938 59.941406 103.992188 59.941406 C 104.28125 59.941406 104.507812 59.828125 104.664062 59.59375 C 104.828125 59.371094 104.914062 59.058594 104.914062 58.660156 Z M 103.085938 57.519531 C 103.1875 57.324219 103.328125 57.175781 103.507812 57.082031 C 103.683594 56.988281 103.890625 56.941406 104.132812 56.941406 C 104.527344 56.941406 104.851562 57.105469 105.101562 57.425781 C 105.351562 57.738281 105.476562 58.152344 105.476562 58.660156 C 105.476562 59.183594 105.351562 59.59375 105.101562 59.910156 C 104.851562 60.21875 104.527344 60.378906 104.132812 60.378906 C 103.890625 60.378906 103.683594 60.332031 103.507812 60.238281 C 103.328125 60.144531 103.1875 60 103.085938 59.800781 L 103.085938 60.300781 L 102.539062 60.300781 L 102.539062 55.738281 L 103.085938 55.738281 Z M 103.085938 57.519531 "/>
<path style="fill:none;stroke-width:0.8;stroke-linecap:butt;stroke-linejoin:miter;stroke:rgb(0%,0%,0%);stroke-opacity:1;stroke-miterlimit:4;" d="M 118.976562 12.449219 L 123.09375 14.765625 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 125.085938 15.027344 L 127.148438 15.027344 L 127.148438 15.527344 L 124.367188 15.527344 L 124.367188 15.027344 C 124.59375 14.800781 124.902344 14.492188 125.289062 14.105469 C 125.671875 13.710938 125.917969 13.457031 126.023438 13.339844 C 126.210938 13.121094 126.339844 12.941406 126.414062 12.792969 C 126.484375 12.648438 126.523438 12.503906 126.523438 12.355469 C 126.523438 12.128906 126.4375 11.941406 126.273438 11.792969 C 126.117188 11.648438 125.90625 11.574219 125.648438 11.574219 C 125.460938 11.574219 125.261719 11.605469 125.054688 11.667969 C 124.855469 11.730469 124.636719 11.832031 124.398438 11.964844 L 124.398438 11.371094 C 124.636719 11.269531 124.859375 11.195312 125.070312 11.152344 C 125.277344 11.101562 125.464844 11.074219 125.632812 11.074219 C 126.089844 11.074219 126.449219 11.191406 126.710938 11.417969 C 126.980469 11.632812 127.117188 11.941406 127.117188 12.324219 C 127.117188 12.503906 127.078125 12.675781 127.007812 12.839844 C 126.945312 12.996094 126.824219 13.183594 126.648438 13.402344 C 126.605469 13.457031 126.449219 13.617188 126.179688 13.882812 C 125.917969 14.160156 125.554688 14.539062 125.085938 15.027344 Z M 125.085938 15.027344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 131.171875 12.246094 L 129.984375 13.839844 L 131.234375 15.527344 L 130.59375 15.527344 L 129.640625 14.230469 L 128.6875 15.527344 L 128.046875 15.527344 L 129.328125 13.808594 L 128.15625 12.246094 L 128.796875 12.246094 L 129.65625 13.417969 L 130.53125 12.246094 Z M 131.171875 12.246094 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 132.296875 15.027344 L 133.265625 15.027344 L 133.265625 11.699219 L 132.203125 11.902344 L 132.203125 11.371094 L 133.25 11.152344 L 133.84375 11.152344 L 133.84375 15.027344 L 134.8125 15.027344 L 134.8125 15.527344 L 132.296875 15.527344 Z M 132.296875 15.027344 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 138.414062 13.882812 C 138.414062 13.492188 138.328125 13.183594 138.164062 12.964844 C 138.007812 12.738281 137.78125 12.621094 137.492188 12.621094 C 137.210938 12.621094 136.984375 12.738281 136.820312 12.964844 C 136.664062 13.183594 136.585938 13.492188 136.585938 13.882812 C 136.585938 14.285156 136.664062 14.59375 136.820312 14.824219 C 136.984375 15.050781 137.210938 15.167969 137.492188 15.167969 C 137.78125 15.167969 138.007812 15.050781 138.164062 14.824219 C 138.328125 14.59375 138.414062 14.285156 138.414062 13.882812 Z M 136.585938 12.746094 C 136.6875 12.550781 136.828125 12.402344 137.007812 12.308594 C 137.183594 12.214844 137.390625 12.167969 137.632812 12.167969 C 138.027344 12.167969 138.351562 12.332031 138.601562 12.652344 C 138.851562 12.964844 138.976562 13.378906 138.976562 13.882812 C 138.976562 14.410156 138.851562 14.824219 138.601562 15.132812 C 138.351562 15.449219 138.027344 15.605469 137.632812 15.605469 C 137.390625 15.605469 137.183594 15.558594 137.007812 15.464844 C 136.828125 15.371094 136.6875 15.226562 136.585938 15.027344 L 136.585938 15.527344 L 136.039062 15.527344 L 136.039062 10.964844 L 136.585938 10.964844 Z M 136.585938 12.746094 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 78.039062 23.707031 L 78.664062 23.707031 L 78.664062 26.847656 L 80.539062 25.191406 L 81.351562 25.191406 L 79.320312 26.988281 L 81.429688 29.019531 L 80.617188 29.019531 L 78.664062 27.144531 L 78.664062 29.019531 L 78.039062 29.019531 Z M 78.039062 23.707031 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 57.261719 18.4375 L 57.261719 19.109375 L 56.480469 19.109375 C 56.1875 19.109375 55.984375 19.171875 55.871094 19.296875 C 55.765625 19.414062 55.714844 19.621094 55.714844 19.921875 L 55.714844 20.359375 L 57.042969 20.359375 L 57.042969 20.984375 L 55.714844 20.984375 L 55.714844 25.28125 L 54.902344 25.28125 L 54.902344 20.984375 L 54.121094 20.984375 L 54.121094 20.359375 L 54.902344 20.359375 L 54.902344 20.015625 C 54.902344 19.464844 55.027344 19.0625 55.277344 18.8125 C 55.535156 18.5625 55.941406 18.4375 56.496094 18.4375 Z M 57.261719 18.4375 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 56.914062 75.855469 L 56.914062 76.527344 L 56.132812 76.527344 C 55.839844 76.527344 55.636719 76.589844 55.523438 76.714844 C 55.417969 76.832031 55.367188 77.039062 55.367188 77.335938 L 55.367188 77.777344 L 56.695312 77.777344 L 56.695312 78.402344 L 55.367188 78.402344 L 55.367188 82.699219 L 54.554688 82.699219 L 54.554688 78.402344 L 53.773438 78.402344 L 53.773438 77.777344 L 54.554688 77.777344 L 54.554688 77.433594 C 54.554688 76.882812 54.679688 76.480469 54.929688 76.230469 C 55.1875 75.980469 55.59375 75.855469 56.148438 75.855469 Z M 56.914062 75.855469 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 77.605469 81.703125 L 78.230469 81.703125 L 78.230469 84.84375 L 80.105469 83.1875 L 80.917969 83.1875 L 78.886719 84.984375 L 80.996094 87.015625 L 80.183594 87.015625 L 78.230469 85.140625 L 78.230469 87.015625 L 77.605469 87.015625 Z M 77.605469 81.703125 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 58.109375 23.191406 C 57.921875 23.191406 57.769531 23.039062 57.769531 22.851562 C 57.769531 22.660156 57.921875 22.507812 58.109375 22.507812 C 58.300781 22.507812 58.453125 22.660156 58.453125 22.851562 C 58.453125 23.039062 58.300781 23.191406 58.109375 23.191406 Z M 58.109375 23.191406 "/>
<path style=" stroke:none;fill-rule:nonzero;fill:rgb(0%,0%,0%);fill-opacity:1;" d="M 58.0625 81.007812 C 57.875 81.007812 57.722656 80.855469 57.722656 80.664062 C 57.722656 80.476562 57.875 80.320312 58.0625 80.320312 C 58.253906 80.320312 58.40625 80.476562 58.40625 80.664062 C 58.40625 80.855469 58.253906 81.007812 58.0625 81.007812 Z M 58.0625 81.007812 "/>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 150 KiB

753
static/images/biocas2018/narrow.svg Normal file
View File

File diff suppressed because one or more lines are too long
Side by Side

After

Width:  |  Height:  |  Size: 847 KiB

Some files were not shown because too many files have changed in this diff Show More