diff --git a/config.toml b/config.toml index d85719d..051e4a4 100644 --- a/config.toml +++ b/config.toml @@ -23,7 +23,7 @@ themeColor = "#494f5c" dateformShort = 'Jan 2' dateformNum = '2006-01-02' dateformNumTime = '2006-01-02 15:04 -0700' - homeSubtitle = "Welcome Friend šŸø" + homeSubtitle = "Welcome Friend" [author] name = 'L. B. Leene' @@ -48,12 +48,20 @@ themeColor = "#494f5c" [[menu.main]] name = "About" url = "about/" - weight = 16 - [[menu.main]] - name = "Projects" - url = "projects/" - weight = 16 + weight = 1 [[menu.main]] name = "Posts" url = "posts/" - weight = 16 + weight = 2 + [[menu.main]] + name = "Publications" + url = "publications/" + weight = 3 + [[menu.main]] + name = "Chips" + url = "chips/" + weight = 5 + [[menu.main]] + name = "Resume" + url = "resume/" + weight = 10 diff --git a/content/about.md b/content/about.md index c8f5f84..f5c0709 100644 --- a/content/about.md +++ b/content/about.md @@ -1,49 +1,42 @@ --- -title: "Hello friend šŸ±ā€šŸ‘¤" -date: 2021-08-23T17:52:07+02:00 +title: "About" +date: 2022-05-21T19:52:54+02:00 draft: false tags: + - personal + - introduction - about - - config --- -## About This Site +This site shares a bit of informal documentation and blog-based record keeping +reflecting my day to day activities. Hopefully it's a good mix of technical and +just-for-fun discussion. Professionally I am a mixed-signal circuit designer +which means I compose integrated circuits mostly for sensors whose signals are +then processed for interesting features. Besides that I enjoy a bit of casual +programming as a hobby which is now predominantly based on python which makes +it easy to share and adapt code. -This site shares a bit of informal documentation and more blog-based record -keeping. Providing commentary on design decisions should be just as useful as -some of the technical documentation however included in my repositories. -### Contact -You can reach me at `lieuwe at leene dot dev`. +# research interests -## My Setup +# Proficiencies -I mainly use RHEL flavours of linux having both CentOS and Fedora machines. Most -hosted services run on CentOS 8 at the moment albeit they are approaching -end-of-life. Overall the package repository for CentOS 7/8 is just right. I -rarely need to compile anything from source and packages are very stable. -I will eventually migrate to Fedora completely which is where I operate my -development environment. +I have well over 10 years of design experience using Cadence and Seimens (Mentor Graphics) +EDA design suite extensively from process-development-kit integration to mixed-signal +design verification. Having predominantly designed mixed-signal instrumentation chips most of my +proficiency lies with the Virtuoso analogue design flow. However I have historically +worked in smaller design groups of 5-10 people where you need to be familiar with +the entire development process for a device from start to finish touching on process selection, +tool configuration, and production planning. Fortunately -This is a list of my most used self-hosted services: - - Gitea: Git server with web interface for repository mirrors and personal repos - - Plex: multi-media hosting service for streaming movies and tv-shows - - NextCloud: Cloud storage for synchronizing and sharing files - - Cockpit: Web base administration portal managing linux boxes - - RoundCube: Web based email client - - Postfix/Dovcot: Email stack providing SMTP for my domain - - NGINX: HTTP server serving as proxy for internal web services - - Danbooru: Ruby-on-rails based image hosting and tagging service +with ADE/Measto verification +but I am quite comfortable with skill and any Cadence know how for speeding up design development. -There are several others that I have tried but these really have been the things -I relied on the most in the past 5 years or so. I think the only thing that is -possibly missing from this list is possibly the equivalent of a centralized LDAP -service but I simply haven't had to manage more than handful of users. +## Programming languages -Currently I develop quite a bit of python utilities for scraping, labelling, and -managing media in an automated fashion. In part I am preparing data for one of -my long term projects which is related to image classification based on -structural decomposition rather than textural features. The main idea here is -to analyse and extract structure in an image before performing in-depth analysis -such that said analysis is most specific to its context. + - Python + - Skill + - C++ + - Bash + - Matlab diff --git a/content/chips.md b/content/chips.md new file mode 100644 index 0000000..aef9af2 --- /dev/null +++ b/content/chips.md @@ -0,0 +1,25 @@ +--- +title: "Chips" +date: 2021-08-23T17:52:07+02:00 +draft: false +toc: true +tags: + - personal + - CMOS + - fabrication + - devices +--- + +Here are some of the fabricated chips that I have had the privilege of +designing over the years. These designs are the result of joint efforts with +colleges and collaborators made possible by the Engineering and Physical +Sciences Research Council (EPSRC) UK. + +{{< figure src="/images/chips/C0.png" title="AKIRA - A 18b NS-SAR ADC | 2019 | 0.18 um TSMC" width="500" >}} +{{< figure src="/images/chips/C1.jpg" title="ENGINI - A Neural Recording SoC | 2018 | 0.35 um AMS" width="500" >}} +{{< figure src="/images/chips/C2.jpg" title="ENGINI - A Wireless BMI SoC | 2017 | 0.35 um AMS" width="500" >}} +{{< figure src="/images/chips/C4_mod.png" title="PIKACHU - A Time Domain Instrumentation System | 2016 | 65 nm TSMC" width="500" >}} +{{< figure src="/images/chips/C5_mod.png" title="GOLEM - A Distributed Neural Processing SoC | 2015 | 0.18 um AMS" width="500" >}} +{{< figure src="/images/chips/C3_mod.png" title="KIITCHI - An Incremental Instrumentation System | 2013 | 0.18 um AMS" width="500" >}} +{{< figure src="/images/chips/C6.jpg" title="NGNI32 - Neural Recording ASIC | 2013 | 0.32 um AMS" width="500" >}} +{{< figure src="/images/chips/C7.jpg" title="NGNI16 - Ultra-Wide Band Transmitter | 2012 | 0.18 um AMS" width="500" >}} diff --git a/content/posts/2021/assisted-vectorization.md b/content/posts/2021/assisted-vectorization.md new file mode 100644 index 0000000..c642b97 --- /dev/null +++ b/content/posts/2021/assisted-vectorization.md @@ -0,0 +1,161 @@ +--- +title: "Image Vectorization šŸ–‡šŸ®" +date: 2021-12-08T19:26:46+01:00 +draft: false +toc: true +tags: + - svg + - python + - code + - image +--- + + +Automated vectorization and upscaling is useful in many scenarios particularly +for drawn art that can be segmented and is generally structured using strokes +and gradients. Here I will outline a methodology that is based around +structural analysis and direct regression methods then evaluate error metrics +for fine-tuning by comparing the output with non-vectorized up-scalers. + + +## Observations + +Regarding image segmentation, I suspect the most common approach is directly +clustering the entire image using the colour and position. In +most scenarios this feature-space will be separable and is a well understood +problem statement. There result still poses some issues; first cluster enclosure +is difficult to resolve (convexity is not guaranteed), second gradient +components weaken the separability of the data. In addition we may need to +sub-sample the image since clustering is computationally expensive given the +mega-samples of image data. + +## Outline + +0. Coarse Analysis + - Cluster based on colour-space and |āˆ‡Ć—F| |āˆ‡Ā·F| normalized components + - Present image colour and segmentation complexity + - Partition image in delta space using histogram method +1. Pre-processing and edge thresholding + - Compute the YCbCr equivalent representation + - Map the input colour space based on k-means / SVM for maximum cluster separation + - Compute edges in images and fit spline segments with grouping +2. Fine image segmentation + - Use edges to initialize segments and segment regions based on colour deltas + - Complete segmentation by filling image + - Regression to fit colour for each segment +4. Image restructuring and grouping + - Simplify structures by creating region hierarchy + - SVG 2.0 supports mesh-gradients / Bezier surface composition + - Detect regular patterns with auto correlation / parameter comparison +3. Error evaluation and recalibration + - Use upscaled reference to evaluate error + - Identify segments that need to be restructured with more detail + + +## Action Items + + - Colour surface fitting + - Given a set of samples, fit an appropriate colour gradient + - Image normalization and pre-processing + - Edge composition and image segmentation + - Define a model for segments of the image + - Define a model for closed and open edges + - Evaluate segment coverage of the image + - Heuristics for image hierarchy and optimizations + + +## Pre-processing Engine + +Currently histogram binning has proven to be very effective for generating +initial clusters since it scales well with image size. This allows us to +quickly gauge the complexity of an image in terms of content separability. +These regions will be used to partition the image as edges are extracted +before more accurate mapping is performed. + +The main challenge here is colour gradients that washout what should be +obvious centroids. Analysing the samples in batches can prevent this to some +extent but a more robust approach is needed. We could use a localized grouping +technique but accuracy may need be that important for this pre-processing step. +Another technique is that the image can first be clustered using the histogram +of derivative components followed by sub-classing a histogram for each gradient +cluster. + +This idea for histogram-binning is surprisingly efficiently for artificial +images where the colour pallet is rich in features. A binary search for +parameterizing the local maxima detection will very quickly segment a wide +variety of images into 10 - 30 classifications. + +## Edge extraction + +At some point we will want to construct a model representing regions and shapes. +The principle component here is identifying edges segmenting the image. Edge +detection is relatively strait-forward as we only need look for extrema in the +derivative components. In most scenarios this is actually quite noisy and +it is not obvious how we should threshold for what is and what is not an edge. + +Here we use the histogram-based clustering result for edge detection region to +region transitions are discretized and no adaptive threshold is required. +There will unavoidably be noisy regions where we see this boundary being spread +out or possibly just a select few pixels appearing in some sub-section due to +the clustering process. This can mostly be removed with a median filter if +necessary. + +If the initial segmentation are generated based on k-means in the colour space, +two families of edges will be detected along segments: hard and soft edges. +Hard edges will correspond to the intended edges seen in the image where as +soft edges will arise due to the clustering technique. We can classify these +two families by looking at the norm of the derivative component along such an +edge. There will be more than one way to asses the correctness here but the +significance here is that soft edges present boundary conditions during colour +mapping while hard edges do not. Otherwise visual artefacts will arise are the +interface of two segments that originally was a smooth transition. + + +## Structural Variability + +While we are targeting a-typical images for vectorization it is obvious that +'sharpness' in the final result depends on a subjective style that is difficult +to assess in terms of simple regress or interpolation. This problem however is +central to upscaling algorithms so the methodology here will be that a external +upscaling tool will guide the vectorization process. For example vectorizing +a pixel-art image yields better results 'nearest-neighbour' methods opposed to +Lanczos resampling. + + +## Regression over SVG colour surfaces + +The SVG standard supports three methods for specifying colour profiles or +gradients: Flat, Linear, Radial. There are more advanced mechanisms through +embedding or meshing multiple components the aforementioned three readily +allow us to fit a first order colour contour through linear +regression. This will be our first objective for parameterizing +the colour for segments in our image. Another thing to note is that the gradient +can be transformed after being parameterized. This means that the a circular +gradient can be transformed to realize a family elliptical gradients. + +Obviously this will not accommodate all colour contours that we find in images +but in such scenarios we may adopt piece-wise approximations or more accurate +masking of each component using the alpha channel. At some point we should +also be able to resolve mixtures and decompose the contour from a non-linear +or higher-order surface into multiple simpler contours. Again note that support +for advanced colour profiles is not well supported so composition through +these basic elements will yield the best support. + +Using linear regression here with a second order polynomial kernel is a very +efficient method for directly quantifying the focal point of the colour +gradient if there is one. + + +## Contour estimation + +My initial attempt to estimate the contour given a set of points was based on +using the convex-hull and recursively enclosing the outline in more detail +by interpolating in between the current outline and finding the closest point +orthogonal to the outline. This result yields a fast approximation of the +enclosing outline without many requirements on the set of points other than +having a dense outline. The drawback was that if it difficult to detect +incorrect interpolation and only resolves the outline with pixel-level +precision. If we pre-process the collection of points such that they +represent detected edges at sub-pixel resolution the later draw-back can be +addressed. Correctness or hypothesis testing could yield a more robust result +at the cost of increased complexity. diff --git a/content/posts/2021/building-svg.md b/content/posts/2021/building-svg.md index c44010d..25472e4 100644 --- a/content/posts/2021/building-svg.md +++ b/content/posts/2021/building-svg.md @@ -87,7 +87,7 @@ added directly to KGT as a feature in future releases. The final result is shown below. -![example_kgt.svg](/images/example_kgt.svg) +{{< figure src="/images/posts/example_kgt.svg" title="example_kgt.svg" >}} ## Tabatkins Railroad Diagrams @@ -118,15 +118,29 @@ would look like this: ``` python import railroad -with open("./test.svg","w+") as file: +with open("./posts/test.svg","w+") as file: obj = railroad.Diagram("foo", railroad.Choice(0, "bar", "baz"), css=style) obj.writeSvg(file.write) ``` The final result is shown below. -![example_kgt.svg](/images/example_trd.svg) +{{< figure src="/images/posts/example_trd.svg" title="example_trd.svg" >}} Note that this figure is quite a bit more compact but adding additional labels or customizations outside the scope of the library will probably require quite a bit of manual work. This could be a fun side project though. + +# Using Hugo Short Codes + + + +``` go +{< python-svg dest="/images/posts/test.svg" title="This is a pyuthon-svg exmaple." >} +railroad.Diagram("foo", railroad.Choice(0, "bar", "baz"), css=style) +{< /python-svg >} +``` + +{{< python-svg dest="/images/posts/test.svg" title="This is a python-svg exmaple." >}} +railroad.Diagram("foo", railroad.Choice(0, "bar", "baz"), css=style) +{{< /python-svg >}} diff --git a/content/posts/2021/configure-nginx.md b/content/posts/2021/configure-nginx.md index 1e37c51..b6a10f8 100644 --- a/content/posts/2021/configure-nginx.md +++ b/content/posts/2021/configure-nginx.md @@ -1,9 +1,8 @@ --- title: "Setting up a NGINX configuration šŸ§©" date: 2021-10-31T15:08:33+01:00 -draft: false +draft: true toc: false -images: tags: - website - config diff --git a/content/posts/2021/mermaid-uml.md b/content/posts/2021/mermaid-uml.md index ecb613c..fd55df0 100644 --- a/content/posts/2021/mermaid-uml.md +++ b/content/posts/2021/mermaid-uml.md @@ -42,7 +42,7 @@ graph LR This example generates the diagram show below. -![example_mermaid.svg](/images/example_mermaid.svg) +{{< figure src="/images/posts/example_mermaid.svg" title="example_mermaid.svg" >}} There are four base themes: dark, default, forest, neutral. Additional [customization](https://mermaid-js.github.io/mermaid/#/theming) is possible. @@ -73,7 +73,7 @@ diagrams of classes and inter-related structures. For example the UML diagram be [pyviewer]({{< relref "pyside.md" >}} "pyside") which is image simple browsing utility for compressed archives. -![example_pyviewer.svg](/images/example_pyviewer.svg) +{{< figure src="/images/posts/example_pyviewer.svg" title="example_pyviewer.svg" >}} This does quite well at illustrating how classes are composed and which methods are available at various scopes. It also helps organizing and structuring a @@ -153,7 +153,7 @@ function main() { esac # echo "IN:${ARGS[1]} OUT:${ARGS[3]}" mmdc ${ARGS[@]} &> /dev/null - mogrify -trim "${ARGS[3]}" + mogrify -trim "${ARGS[3]}" feh --reload 2 "${ARGS[3]}" & sleep 0.1 inotifywait -qm --event modify --format '%w' "${ARGS[1]}" | \ diff --git a/content/posts/2021/my-2018-setup.md b/content/posts/2021/my-2018-setup.md new file mode 100644 index 0000000..d3006ff --- /dev/null +++ b/content/posts/2021/my-2018-setup.md @@ -0,0 +1,38 @@ +--- +title: "My 2018 Setup" +date: 2021-08-12T10:24:27+02:00 +draft: false +toc: true +tags: + - website + - about +--- + +I mainly use RHEL flavours of linux having both CentOS and Fedora machines. Most +hosted services run on CentOS 8 at the moment albeit they are approaching +end-of-life. Overall the package repository for CentOS 7/8 is just right. I +rarely need to compile anything from source and packages are very stable. +I will eventually migrate to Fedora completely which is where I operate my +development environment. + +This is a list of my most used self-hosted services: + - Gitea: Git server with web interface for repository mirrors and personal repos + - Plex: multi-media hosting service for streaming movies and tv-shows + - NextCloud: Cloud storage for synchronizing and sharing files + - Cockpit: Web base administration portal managing linux boxes + - RoundCube: Web based email client + - Postfix/Dovcot: Email stack providing SMTP for my domain + - NGINX: HTTP server serving as proxy for internal web services + - Danbooru: Ruby-on-rails based image hosting and tagging service + +There are several others that I have tried but these really have been the things +I relied on the most in the past 5 years or so. I think the only thing that is +possibly missing from this list is possibly the equivalent of a centralized LDAP +service but I simply haven't had to manage more than handful of users. + +Currently I develop quite a bit of python utilities for scraping, labelling, and +managing media in an automated fashion. In part I am preparing data for one of +my long term projects which is related to image classification based on +structural decomposition rather than textural features. The main idea here is +to analyse and extract structure in an image before performing in-depth analysis +such that said analysis is most specific to its context. diff --git a/content/posts/2021/pyside.md b/content/posts/2021/pyside.md index 738dc30..d9736ac 100644 --- a/content/posts/2021/pyside.md +++ b/content/posts/2021/pyside.md @@ -64,18 +64,62 @@ to a qml function call "swipe.update_paths" for example. viewer.path_changed.connect(swipe.update_paths) ``` +## Example: passing images as bindary data + +For reference the code below outlines a simple example that loads an image from +a zip archive and makes the binary data available for QML to source. This +avoids the need for explicit file handles when generating or deflating images +that are needed for the QML front-end. + +```python +class Archive(ZipFile): + """Simple archive handler for loading data.""" + @property + def binarydata(self) -> bytes: + """Load file from archive by name.""" + with self.open(self.source_file, "r") as file: + return file.read() +``` + +The example class above simply inherits from the zipfile standard library where +we read a image and store it as part of the `PyViewer` class shown below. This +class inherits from `QObject` such that the property is exposed to the qml +interface. In this case the `imageloader` is an `Archive` handler that is +shown above. + +```python +class PyViewer(QObject): + """QObject for binging user interface to python backend.""" + @Property(QByteArray) + def image(self) -> QByteArray: + """Return an image at index.""" + return QByteArray(self.imageloader.binarydata).toBase64() +``` + +This setup allows a relatively clean call to the `viewer.image` property within +the QML context as shown below. Other data types such as `int`, `string`, +`float`, and booleans can be passed as expected without requiring the +QByteArray container. + +```qml +Image { + anchors.fill: parent + fillMode: Image.PreserveAspectFit + mipmap: true + source = "data:image;base64," + viewer.image +} +``` + ## Downside Debugging and designing QML in this environment is limited since the pyside python library does not support all available QML/QT6 functionality. In most cases you are looking at C++ Qt documentation for how the pyside data-types -and methods are supposed to behave without good hinting. +and methods are supposed to behave without good hinting. Having developed +native C++/QML projects previously helps a lot. The main advantage here is t +hat QML source code / frame-works can be reused. -Also the variety in data types that can be passed from one context to the other -is constrained although in this case I was able to manage with strings and byte -objects. - -## Other Notes: TODO +## Other Notes: ```python ImageCms.profileToProfile(img, 'USWebCoatedSWOP.icc', diff --git a/content/projects/super_resolution.md b/content/posts/2021/super_resolution.md similarity index 66% rename from content/projects/super_resolution.md rename to content/posts/2021/super_resolution.md index 2c7a805..cf6f75c 100644 --- a/content/projects/super_resolution.md +++ b/content/posts/2021/super_resolution.md @@ -1,8 +1,9 @@ --- title: "Super Resolution šŸ§™ā€ā™‚ļø" date: 2021-09-19T13:30:00+02:00 -draft: false +draft: true toc: true +math: true tags: - upscaling - image-processing @@ -11,4 +12,10 @@ tags: --- WIP: this is an on going effort for super-resolving images given learned context -and Super-Resolution Using a Generative Adversarial Network (SRGAN). +and Super-Resolution Using a Generative Adversarial Network (SRGAN). [^1] + +$$ y_t = \beta_0 + \beta_1 x_t + \epsilon_t $$ + +now inline math \\( x + y \\) =] + +[^1]: And that's the footnote. diff --git a/content/posts/2022/latex-to-markdown.md b/content/posts/2022/latex-to-markdown.md new file mode 100644 index 0000000..02b7bbd --- /dev/null +++ b/content/posts/2022/latex-to-markdown.md @@ -0,0 +1,75 @@ +--- +title: "Latex to Markdown" +date: 2022-04-28T13:42:40+02:00 +draft: false +tags: + - markdown + - latex + - code + - python + - hugo +--- + +Recently I started porting some of my latex articles to markdown as they would +make a fine contribution to this website in simpler format. Making a simple +parser python isn't that bad and I could have used [Pandoc](https://pandoc.org/index.html) +but I wanted a particular format for rendering a hugo markdown page. So I +prepared several regex-based functions in python to dereference and construct +a hugo-compatible markdown file. + +``` python3 +class LatexFile: + def __init__(self, src_file: Path): + sys_path = path.abspath(src_file) + src_dir = path.dirname(sys_path) + src_file = path.basename(sys_path) + self.tex_src = self.flatten_input("\\input{" + src_file + "}", src_dir) + self.filter_tex(sys_path.replace(".tex", ".bbl")) + + def filter_tex(self, bbl_file: Path) -> None: + """Default TEX filterting proceedure.""" + self.strip_tex() + self.preprocess() + self.replace_references(bbl_file) + self.replace_figures() + self.replace_tables() + self.replace_equations() + self.replace_sections() + self.postprocess() +``` + +The general process for converting a Latex document is outlined above. The +principle here is to create a flat text source which we then incrementally +format such that Latex components are translated correctly. + + +## Latex Components + +In order to structure the python code I created several named-tuples for +self-contained Latex contexts such as figures, tables, equations, etc. then +by adding a `markdown` property we can replace these sections with hugo +friendly syntax using short-codes where appropriate. + +``` python3 +class Figure(NamedTuple): + """Structured Figure Item.""" + + span: Tuple[int, int] + index: int + files: List[str] + caption: str + label: str + + @property + def markdown(self) -> str: + """Markdown string for this figure.""" + fig_str = "" + for file in self.files[:-1]: + fig_str += "{{" + f'< figure src="{file}" width="500" >' + "}}\n" + fig_str += ( + "{{" + + f'< figure src="{self.files[-1] if self.files else ""}" title="Figure {self.index}: {self.caption}" width="500" >' + + "}}\n" + ) + return fig_str +``` diff --git a/content/posts/2022/synthesizing-sinusoids.md b/content/posts/2022/synthesizing-sinusoids.md new file mode 100644 index 0000000..9f027a3 --- /dev/null +++ b/content/posts/2022/synthesizing-sinusoids.md @@ -0,0 +1,271 @@ +--- +title: "Synthesizing Sinusoids" +date: 2022-05-17T13:17:04+02:00 +draft: false +toc: true +math: true +tags: + - signal-processing + - delta-sigma-modulation + - digital-circuits + - python +--- + +Here I will go over a hardware efficient digital-technique for synthesizing a +high-fidelity sinusoidal tone for self-test and electrical characterization +purposes. This will be a application of several state-of-the-art hardware +techniques to minimize hardware complexity while readily +generating a precise tone with well over 100 dB of dynamic range. Further more +the resulting output bit-stream is delta-sigma modulated enabling the use of a +low-complexity 4 bit digital-to-analogue-converter that employs +dynamic-element-matching. + +## Synthesizer + +``` goat + +-----------------------+ 16b +--------------+ 16b +-------------+ 4b + | 32 bit Recursive | / | 1:16 | / | 3rd Order | / + | Discrete-Time +---+-->| Rotated CIC +---+-->| Delta-Sigma +---+--> Output Bitstream + | Sinusoidal Oscillator | / | Interpolator | / | Modulator | / + +-----------------------+ +--------------+ +-------------+ +``` + +The overall system composition is illustrated above and consists of three +modules. The first module is a recursive digital oscillator and operates at a +higher precision but lower clock rate to generate the target test-tone. The +proceeding modules encode this high-resolution digital signal into a low +resolution digital bit-stream there the quantization noise is shaped towards +the high-frequency band that can then be filtered out in the analogue-domain. + +## Digital Oscillation + +There are numerous all-digital methods for synthesizing a sinusoidal signal +precisely. The most challenging aspect here is the trigonometric functions that +are difficult compute given limited hardware resource. A common approach to +avoid this is to use a look-up table representing `cos(x)` for mapping phase to +amplitude but this generally requires a significant amount of memory. +Alternatively a recursive feedback mechanism can be used that will oscillate +with a known frequency and amplitude given a set of parameters. The later +approach has negligible memory requirements but instead requires full-precision +multiplication. However considering that we are required to perform delta-sigma +encoding at the output this feedback mechanism can run at a reduced clock-rate +allowing this multiplication to be performed in a pipelined fashion which is +considerably more affordable. + +``` goat + - .-. .-. + .->| Ī£ +------*----->| Ī£ +---> Digital Sinusoid + | '-' | '-' + | ^ v ^ + | | .-----. | + | | | zā»Ā¹ | '----- Offset + | | . '--+--' + | | /| | + | '+ |<---* + | K \| | + | ' v + | .-----. + '----------+ zā»Ā¹ | + '-----' +``` + +The biquad feedback configuration shown above is one of several oscillating +structures presented in [^1] with the equivalent a python model presented below. +The idea here is to perform full-precision synthesis at 64 or 32 bit with a +pipelined multiplier such that this loop runs at 1/M times the modulator clock +speed where M is the oversampling ratio that is chosen to optimize the +multiplier pipeline. In this case M=16 and we will be using 32 bit frequency +precision. + +``` python3 +class Resonator: + def __init__(self, frequency: float = 0.1, amplitude: float = 0.5): + K = 2 * np.cos(2 * np.pi * frequency) + self.A = 0.0 + self.B = amplitude * np.sqrt(2.0 - K) + self.K = K + def update(self) -> int: + self.A, self.B = (self.A * self.K - self.B, self.A) + return self.A +``` + +The coefficient K determines the frequency of oscillation as a ratio relative to +the operating clock speed. Using \\( K = 2 cos( 2 \pi freq )\\) such that the +oscillation occurs as \\( freq \cdot fclk \\). The initial condition of the two +registers will determine the oscillation amplitude. Setting the first register +to zero and the second to \\( A \sqrt{2 - K} \\) will yield amplitude of \\(A\\) +around zero. We can then offset this signal to specify the level around which +tone oscillates. + +## Band-Select Interpolation + +The main drawback of not synthesizing the sinusoid at a fractional clock rate +is that we must take care of the aliased components when we increase the +data-rate. Fortunately there are a family of filters that are extremely +efficient at up-sampling a signal while rejecting the aliasing components known +as cascaded integrator-comb filters (CIC)[^2]. These filters consist of several +simple accumulators and differentiators that can be configured to reject +aliasing components. + +$$ H(z) = \left( \frac{ 1 - z^{-M} }{ 1 - z^{-1} } \right)^N $$ + +The transfer function of such a filter is formulated above. This shows that a +CIC structures of order \\( N \\) operating at a oversampling ratio +\\( M \\) will distribute M zeros uniformly around the unit circle. This +completely removes any DC components that end up at the aliasing tones at +multiples of \\( fclk / M\\). However we know priori that we will introduce +aliasing components at integer multiples of the input tone when up-sampling: +\\( freq \cdot fclk / M \\). Making a slight modification to this structure +as discussed in [^3] allows us to further optimize a second-order CIC filter to +specifically reject these components instead. + +$$ H(z) = \frac{ 1 - K \cdot z^{-M} + z^{-2M} }{ 1 - K_M z^{-1} + z^{-2} } $$ + +Notice that the coefficient K from the resonator structure is reused here and +we introduce a new scaling coefficient \\(K_M = 2 \cdot 2 * cos(2 \pi * freq / M )\\) +which we will approximate by tailor expansion to avoid the multiplication +requirement as this factor does not require high precision. Again a python +implementation is shown below for reference. + +``` python3 +class Interpolator: + def __init__(self, frequency: float = 0.1, osr: int = 32): + K = 2 * np.cos(2 * np.pi * frequency) + KM = 2 * np.cos(2 * np.pi * frequency / osr ) + self.fir_coef = np.array([1, -K, 1]) # FIR coefficients + self.irr_coef = np.array([-KM, 1]) # IRR coefficients + self.comb_integrator = np.zeros((2,), dtype=float) + self.comb_decimator = np.zeros((3,), dtype=float) + self.osr = osr + self.count = 0 + + def update(self, new_val: float) -> float: + self.comb_integrator = np.append( + np.dot(self.fir_coef, self.comb_decimator) + + np.dot(-self.irr_coef, self.comb_integrator), + self.comb_integrator[:-1], + ) + if self.count == 0: + self.comb_decimator = np.append(new_val, self.comb_decimator[1:]) + self.count = (self.count + 1) % self.osr + return self.comb_integrator[0] +``` + +Combing the two feedback mechanisms we can construct a second-order CIC based +digital resonator with a interpolated output that fully rejects aliasing +components. This configuration is shown below. Now let us use Taylor +approximation to resolve the coefficient KM such that it is reduced to +two-component addition. The first two non-zero coefficients for cos are +\\( cos(x) = 1 - x^2 / 2 \\). Hence we can approximate as follows +\\( KM = 2 - 1 >> \lfloor 2 \log_2( 2 \pi * freq / M ) \rfloor \\) where +\\(>>\\) is the binary shift-left operator. + +``` goat + Fractional Clock Rate <+ +> Full Clock Rate + - .-. .-. .-. + .->| Ī£ +------*---------->| Ī£ +----->| Ī£ +-------*-------> Interpolated Sinusoid + | '-' | '-' '-' | + | ^ v - ^ ^ - ^ ^ . v + | | .-----. / | / | /| .--+--. + | | | zā»į“¹ | | | | '+ |<-+ zā»Ā¹ | + | | . '--+--' . | | | KM \| '--+--' + | | /| | |\ | | | ' | + | '+ |<---*--->| +-' | | v + | K \| | |/ K | | .--+--. + | ' v ' | '---------+ zā»Ā¹ | + | .-----. | '-----' + '----------+ zā»į“¹ +---------' + '-----' + +``` + +The resulting configuration only requires one multiplication to be computed at +a fractional clock-rate. Note that practically a hardware implementation will +stagger the computation in time for each of the processing stages. + +## Sigma-Delta Modulation + +The purpose of digital sigma-delta modulation is primarily to reduce the +hardware requirements for signal-processing in the analogue-domain. Digitizing +a high resolution 16 bit signal is exceedingly expensive once we consider +component variation requirements if we want to preserve the fidelity of our +signal. The main idea here is the reduce the resolution of the output bitstream +while modulating the quantization noise such that accuracy is preserved in the +lower frequencies while noise due to the truncation of the digital bits is only +present at higher frequencies. This allows us to use a low resolution +digital-to-analogue converter that employs mismatch cancellation techniques +at low cost to further remove the impact of component imperfection from +corrupting the precision in-band. + +A popular approach here is the use of multistage noise-shaping modulator +topologies. Here we will employ a special maximum-sequence-length configuration +from [^4] which avoids any unwanted periodicity commonly found in the output +of conventional modulators when processing certain static signals. A python +realization of this modulation process is shown below in the case of a first +order modulator. + +``` python3 +class Modulator: + def __init__(self, resolution: int = 16, coupling: int = 0) -> None: + self.acc = 0 + self.coupling = coupling + self.resolution = resolution + + def update(self, new_val: int) -> bool: + last_val = self.acc & 1 + pre_calc = self.acc + new_val + (self.coupling if last_val else 0) + self.acc = pre_calc % (2 ** self.resolution) + return last_val +``` + +The third-order configuration of the modulator is shown below. Here the Nx[n] +components represent the coupling factor Ī± and simply use the Cx[n-1] bitstream +from the last cycle. This factor is a small integer chosen such that +2^N-Ī± is a prime number given a fixed modulator resolution N. + +``` goat + . C1[n] .-. + D[n] |\ .-------------------------------->| Ī£ +--> Q[n] + --->+ + '-' + | \ ^ ^ + \ | . C2[n] .-------. / | + N1[n]| | S1[n] |\ .---->+ 1-zā»Ā¹ +-----' | + --->+ +--*--->+ + '-------' | + | | | | \ | + / | | \ | . C3[n] .-----+----. + | / | N2[n]| | S2[n] |\ .---->+ (1-zā»Ā¹)Ā² | + .->+ / | --->+ +--*--->+ + '----------' + | |/ | | | | | \ + | ' | / | | \ | + | .-----. | | / | N3[n]| | S3[n] + '-+ zā»Ā¹ +' .->+ / | --->+ +-. + '-----' | |/ | | | | + | ' | / | | + | .-----. | | / | + '-+ zā»Ā¹ +' .->+ / | + '-----' | |/ | + | ' | + | .-----. | + '-+ zā»Ā¹ +' + '-----' +``` + +The output Q[n] will represent a multi-bit quantization result that increases in +bit-depth as the modulator order increases as the derivative components of CX[n] +increase in dynamic range for higher order derivatives. This has a rather +unfortunate side-effect that the signal dynamic range is only a fraction of the +total output dynamic range in this case 1/8. Fortunately these components are +exclusively high-frequency and so including a 3-tap Bartlett-Window FIR a the +output alleviates this problem by amplifying the signal-band and rejecting +the quantization-noise. In that scenario the signal dynamic range uses a little +under half the full dynamic range of the signal seen at the output. + +## References: + +[^1]: C. S. Turner, ''Recursive discrete-time sinusoidal oscillators,'' IEEE Signal Process. Mag, vol. 20, no. 3, pp. 103-111, May 2003. [Online]: http://dx.doi.org/10.1109/MSP.2003.1203213. + +[^2]: E. Hogenauer, ''An economical class of digital filters for decimation and interpolation,'' IEEE Trans. Acoust., Speech, Signal Process., vol. 29, no. 2, pp. 155-162, April 1981. [Online]: http://dx.doi.org/10.1109/TASSP.1981.1163535. + +[^3]: L. Lo Presti, ''Efficient modified-sinc filters for sigma-delta A/D converters,'' IEEE Trans. Circuits Syst. II, vol. 47, no. 11, pp. 1204-1213, Nov. 2000. [Online]: http://dx.doi.org/10.1109/82.885128. + +[^4]: K. Hosseini and M. P. Kennedy, ''Maximum Sequence Length MASH Digital Deltaā€“Sigma Modulators,'' IEEE Trans. Circuits Syst. I, vol. 54, no. 12, pp. 2628-2638, Dec. 2007. [Online]: http://dx.doi.org/10.1109/TCSI.2007.905653. diff --git a/content/publications/2011/implantable-biotelemetry.md b/content/publications/2011/implantable-biotelemetry.md new file mode 100644 index 0000000..c5b3b0a --- /dev/null +++ b/content/publications/2011/implantable-biotelemetry.md @@ -0,0 +1,597 @@ +--- +title: "Implantable Biotelemetry" +date: 2012-09-13T15:26:46+01:00 +draft: false +toc: true +type: posts +math: true +tags: + - chapter + - wireless + - CMOS + - biomedical + - implants +--- + + +Lieuwe B. Leene + +B.Eng Electronic Engineering Hong Kong University of Science & Technology, 2011 + +Supervised by: Dr Timothy G. Constandinou + +A Thesis submitted in fulfilment of requirements for the degree of Master of Science Analogue and Digital Integrated Circuit Design of Imperial College London + +Department of Electrical and Electronic Engineering Imperial College London + +# Abstract + +Recent developments in the field of neuroscience and health monitoring have identified the need for biotelemetry systems based around a ultra efficient power standard to allow for next generation biomedical implants and distributed en vivo sensory networks. The work presented here engages the design of the biotelemetry forward and reverse links with a top down perspective exploring the loss mechanics and inefficiencies of concern. This development has led to the the design of an optimized class-E based inductive link that includes a improved modulation scheme specific to the operation of the power amplifier as well as a integrated low complexity BPSK demodulator. In addition a frame work was developed around a scalable UWB delay modulation scheme that improves transmitter efficiency as well as circuit level designs for a widely tunable digital oscillator and a particularly energy efficient UWB pulse generator based off the impulse response of a LC resonator. In extension an UWB antenna is designed with significant improvements in the low-frequency group-delay and reflection co-efficient and a simple energy detection receiver is developed that will allow testing of the full custom digital layout that is designed for fully integrated the UWB transceiver system in $0.18 \mu m$ CMOS technology. The presented forward link achieves achieve a power transmission efficiency of 46% and 34% while transmitting 250kb/s. The UWB transmitter consumed $68.9\mu W$ of power for a PRF of 10MHz that corresponds to a data rate of 77.5 Mb/s. + +# Acknowledgment + +I would like to sincerely thank Dr Timothy G. Constandinou for supervising this project. His insightful support and valuable opportunities that has enabled me take this project from vague ideas to a taped out chip design. I would also like to thank Song Luan for his continuous feedback and technical expertise that has allowed me to rapidly develop some of the prototyped devices through out this project. In addition I would like to thank Olive Murphy for advice on testing antennas and allowing me to use the CST MICROWAVE STUDIO software to support my project. Finally, I would like to thank my family for their support over the past year and Ching Chen Ma for always providing that inspiring ambition. + + +# 1 Motivation + +It has been slightly over 100 years since the advent of the worldā€™s first ā€˜transistorā€™ and even more now than a decade ago, revolution has almost become synonymous with the advancement of the microelectronics industry with impacts that change the very backbone of society. The revolution of the last decade surely belonged to that of mobile devices industry which experienced an increase in user end data demand by over a hundred fold. On the other end of the spectrum however this surge of wireless connectivity of the past decade has synergized and inspired a new foundation of ideas for biomedical systems. + +These novel systems are based around digitizing the medical diagnosis and treatment trough wireless en vivo sensory networks for true personalized medicine. By employing electronic implants that have demonstrated incredible potential due to the dense functionality of CMOS technology, the implantable system on chip have shown potential for restoring vision, treating paralysis, severe epilepsy and Parkinsonā€™s disease [^2]. In addition to applications for novel heath monitoring systems and home-stay medication, bio-telemetry links to implanted devices have enabled the simultaneous study of several hundreds of functioning neurons in a localized area through multi electrode arrays (MEAs). These studies have given crucial insight to behavioral models of the brain for fields such as neuroscience. Recent advances have allowed patients with a spinal impairment to interact with the world through a brain machine interface bringing society closer to visions such as J. C. R. Lickliderā€™s Man-Computer Symbiosis. + +Although the idea of wireless powering of implanted devices has been around since the early 1960s for long term artificial cardiac pacemakers, the focus of current generation bio-telemetry systems has shifted from a functional orientation to building a framework for reliability and performance directed at commercial applications. As a result of new applications finding their way to employing bio-telemetry links where there are a net set challenges associated with handling the transmission of substantial data rates. The more recent neural recording system-on-chip (SOC) in particular has presented very challenging power requirements for the radio frequency (RF) transmitter driven by the restriction on heat dissapation inorder to prevent cell damage. As the demand for number of simultaneously neurons recorded exponentially increases every year, a significant amount of interest has been directed at finding more efficient alternatives for transmitting data out of the implant wirelessly and exploiting specialized encryption algorithms that reduce data rate requirements such as inter-spike-interval figures & spike-feature extraction [^3]. + +In similitude to the miniaturization principle of microelectronics, biomedical system miniaturization is also seen as an important merit that improves the comfort of the subject. Consequently the size of radiating elements inherent to the telemetry system is also an important topic for consideration that with recent demonstrations has brought to light the viability of power and data transmission via GHz radiation and may change bio-telemetry to a more specialized RFID tag based medical system in the future. + +This thesis presents various system level reductions and efficiency optimizations on both the forward transmission link, from the external system towards the implant, as well as the reverse transmission link, from the implant to the external system. The overall focus revolves around presenting scalable topologies that may allow significant improvements in power consumption of the overhead transmission components which is key in enabling future neural studies and ultra-low power telemetry systems that can be incorporated with RF energy harvesting technologies to give way for next generation biomedical implants based on multi-element sensory networks. + +All schematic designs presented in this document are based on a 0.18\\(\mu\\)m CMOS technology using a 1.2V supply. Circuit level simulations were carried out using Cadence IC5.1.41 with foundry provided PSP models. 2D & 3D electromagnetic simulations were carried out using the CST MICROWAVE STUDIO package. + +# 2 Report Outline + +Chapter 2 is based on introducing several general principles of conventional telemetry systems. A brief review shall be presented of the various system level topologies that have been used bio-telemetry systems by evaluating the strengths and weaknesses of each design methodology. In extension a design methodology is presented for the class-E power amplifier that is found in virtually all inductively coupled power links for bio-medical applications. We shall also present a brief introduction to UWB technology as well as a review of state-of-the-art neural interface systems to project our system requirements and topology. + +Chapter 3 focuses on the forward link design by introducing a analytical description of the coil link in order to formulate target figures of merit followed by the employed power amplifier design with the associated simulation results. Techniques that minimize the loss introduced by phase transitions from BPSK modulation will be a very particular consideration that will be made at the end of the chapter together with the corresponding low complexity BSPK demodulator. + +Chapter 4 in analogy focuses on the reverse link design by first introducing the basis for UWB techniques and proposing a scalable modulation technique for low power applications. This is followed by the design considerations of a digitally calibrated oscillator as well as an energy efficient bi-phasic UWB pulse generator. We shall also present the UWB antenna design considerations and propose a receiver topology for testing purposes. + +Chapter 5 concludes upon the developments made throughout this thesis in addition to presenting a generalized evaluation. Finally aspects for future work and improvement shall be noted. + +# 3 Contributions + +The main contribution presented by this thesis are outlined below + - A complete wireless power transmission link trough coupled coil that achieves a net 45% efficiency with the measured coil characteristics as well study on the trade offs of circular and rectangular coil geometries. + - With the developed class E power amplifier an energy efficient BPSK modulation technique is introduced that not require additional supply modulation techniques in addition to a low power BPSK demodulator that consumes 1.5 uW from the unregulated supply. + - Framework for the UWB delay modulation scheme with conservative estimated on BER values and a scalable architecture for implementation. + - Complete UWB transceiver architecture is developed that transmits data at 890 fj/bit for which a full custom digital layout is designed that occupies 200 um by 300 um. + - Miniaturized UWB antenna design that occupies 1.3 cmĀ² and achieves -12 dB reflection coefficient and sub 50 ps group delay over a bandwidth of 4GHz. + +# 4 Introduction + +The neural sensory implants of interest is generally located in a vital location such as under the skull and characteristically needs to process large aggregates of data as a multitude of neurons are recorded simultaneously for prolonged periods of time. As a result it is particularly challenging to power the implant as monthly operations to replace a battery can severely endanger the subject to infection. Moreover power requirements of several milliwatt would require a large battery. The inductive link in principle allows for a relatively efficient transmission of power without puncturing the skin while giving room for data transmission. + +The overall design of telemetry systems pertains to the field of radio frequency electronic circuit design with the inclusion of a few essential aspects from power electronics. The biomedical telemetry application however tends to relax the high frequency requirements and focus more on efficient power induction that is more suitable below the 100 MHz frequency range for maximizing power gain [^4]. Although elaborate antenna systems are still designed to allow for full system-on-chip (SOC) integration the trend towards ubiquitous adoption of integrated UWB transmitters in implants seems to have given a different spin on the RF design aspect. As most bio-telemetry communication links are enabled trough near field coupling there is little gained for high antenna directivity and un-optimized RF coils have been demonstrated sufficient for UWB trough-skin broundary transmission [^5]. Moreover design theory behind UWB is more based on time-domain analysis aimed at minimizing pulse distortion where the traditional harmonic frequency analysis fails to give sufficient insight. + +In this chapter, a review of the various system level topologies that have been used in recent bio-telemetry systems is presented by evaluating the strengths and weaknesses of each design methodology. In extension, a design methodology is briefly presented for the class-E power amplifier that ubiquitus inl inductively coupled power links. In addition, an introduction to UWB technology is presented together with a review of state-of-the-art neural interface systems to project our system requirements and topology. + +# 5 Bio-Telemetry Schemes + +Abstractly speaking, modern telemetry systems can be seen as a 3 channel system. As illustrated in figure 1 these channels correspond to power transmission, forward data transmission, and reverse data transmission. Although 3-channel systems have been reported where each channel is optimized for a single function in terms of carrier frequency and coil/antenna designs the component count is very high. In accordance to the characteristic of the reverse link where a fast bit rate is generally desired, the reverse link is often designed with explicit RF considerations by introducing a far field antenna but it has been demonstrated that single loop coils have considerable potential for near field coupling of RF radiation through the skin [^6]. The power transmission is generally done through inductive coupling at a frequency where the Q-factor of the coils is maximized and losses from the environment are kept to a minimum [^7]. The forward link may very similarly be designed trough inductive coupling but a higher carrier frequency is preferred to allow for more substantial data rates while trading off losses induced by the coils which have been shown to dominate over tissue absorbtions for frequencies above 100KHz [^8]. + +{{< figure src="/images/msc-thesis/s1.png" title="Figure 1: Generalized system architechture of a bi-directional telemetry system for medical implants." width="500" >}} + +Contemporary implant systems have mainly focused on improving the system by choosing the right modulation techniques that allow two channels to by combined into one while still achieving similar performance and there by significantly reducing the number of off chip components on the implant side. In some sense this also relaxes the inter-channel interference as the as the interaction between power forward data transmission, for example, is modeled much more explicitly when combined without interference being prone to variations in the coupling coefficients. + +The simplest implementatio for data modulation is amplitude modulation, ASK, of power wave form, where the DC-DC regulator driving the supply of the PA is directly adjusted according to a binary bit stream. However a supply regulation control loop is generally implemented on a system level that fixes the average induced power such that the supply at the implant side maintains a stable voltage. This control loop is rather essential as the coils may misalign or move during operation such that the supply must be recalibrated to avoid component damage or injuries due to overheating hence it is not desirable to introduce modulation noise directly into the control loop. + +The alternative to ASK is FSK or PSK which allow for much faster data rates due to the fact that the detection of the phase/frequency shift is not limited by the relaxation time of the resonant pair at the implant side and since the Q-factors of the inductors is desirably large to minimize losses this response time limits modulation speeds [^9]. FSK generally doubles the number of resonant components required for power transmission to be efficient at both frequencies and may be considered undesirable but, unlike ASK and PSK, modulation does not degrade the power transmission efficiency. A binary phase shift keying can achieve faster uplink data rates than ASK without the need of additional passives but as will be discussed in chapter 3 the resonant modes of the two phase states are complementary to one another such that during phase transition a significant amount of power lost which results in the degradation in transmission efficiency when data is being transmitted trough the link. Technically speaking, inefficiency during modulation is not a major concern as data sent through the forward link is primarily used during system set up and remains inactive for the majority of the implantā€™s lifetime but it requires additional consideration to avoid system failure during the transmission of large amount of calibration data. + +More recently the reverse link has also been integrated into the power transmission channel as well by using Load Shift Keying (LSK). This modulation technique is based on the fact that the current drained from the secondary power coil L2 is coupled to the total power drained from the power amplifier. A common implementation of this illustrated in figure 2 where a simple transistor driven by a OOK modulated data stream pulses a short circuit current from L2 which can be detected at the primary power coil. Note that the PA can still be modulated with the forward link data stream. This approach introduces a significant amount of simplicity into the design as power and bi-directional data is transmitted through a single coil potentially eliminating all off-chip components. In addition power hungry driver circuitry required for driving the antenna/coil of the reverse link has also been eliminated. The drawback naturally lies with the fact that the two data channels interfere with one another more severely than with separate coils regardless of the modulation schemes and moreover all data rates are limited by the bandwidth the inductive link. In addition, a significant amount of strain is put on the requirements of the on-chip supply regulator as the average power induced from the coil is continuously being modulated with higher frequency components from the OOK switching characteristic and may require the high-performance analog instrumentation components to have differential architectures that require more power and area. + +{{< figure src="/images/msc-thesis/s2.png" title="Figure 2: LSK based telemetry system architechture" width="500" >}} + +# 6 Power Amplifiers for Biomedical Applications + +A quintessential aspect of power induction is minimizing losses at all stages of the power transmission link where the power amplifier used to be at the centre of attention but with the introduction of switch mode power amplifiers the near lossless operation has now become standard for MHz PA applications. The more classical load driving techniques that use class B or class C modes of operation made achieving over 70% efficiency with a varying load such as an implant challenging due to the matching requirements. Switch mode power amplifiers generally refer to amplifier topologies where the main driving transistor is severely over driven to the extent that the output is far into the non-linear domain by clipping effects such that the transistor can essentially be treated as an ideal switch. The basis of lossless switch mode operation lies with making sure the power transistor does not dissipate power and disregarding how nonlinear the intermediate waveforms are as long as a high-Q LC components are used to terminate all unwanted harmonics an ideal efficiency is expected at the load as all the sources of loss are negated. Since the switch mode structure inherently requires a LC pair it is ideal for driving an inductive load as the coil can be absorbed into the network without additional design considerations. + +In order to gain further insight to the operation of switch mode amplifiers we shall present a time domain analysis of the switch mode Class E amplifier topology which allows us to mitigate nearly all losses by absorbing the power transistor paracitics into the network. + +{{< figure src="/images/msc-thesis/pa1.png" title="Figure 3: Detailed Class-E PA schematic and the inductive link." width="500" >}} + +The topology illustrated in figure 3 shows a power transistor biased by a choke inductor driving the primary coil which is coupled to the secondary coil that drives a half-wave rectifier. It is assumed that the DC load, coil Q-factor, and coil inductance is known for this analysis as well as \\(C_{L2}\\) being choosen according to the required switching frequency such that it forms a resonant tank with \\(L_2\\). The actual Class-E operation is derived trough the biasing condition of the transistor with a over-driven digital input which allows the transistor to be approximated by an ideal switch. More over it can be assumed that the current driving the primary & secondary coils is purely sinusoidal as the $L_1 C_{L1}$ tank is used to filter out non linearities introduced by the swithcing operation of the transistors. Before going into analytical details, the overall circuit needs to be reduced to a simple PA structure driving a single complex load. Note that the effective AC load that the rectifier presents to the secondary coil can be approximated in term of expected voltage drop across the diode bridge and the DC load resistor, that is; + +$$ R_{AC} = \frac{1}{2} \frac{(V_{Load} + V_{Diode})^2}{P_{Load} P_{Diode}} || R_{Q2} $$ + +Now, using simple circuit techniques the circuit can be further reduced at the resonant switching frequency $\omega_s = (C_{L2} \cdot L_2 )^{-1/2}$ where the resonant tank at the secondary coil provides the largest reduction in coil losses [^10]. + +{{< figure src="/images/msc-thesis/pa2.png" title="Figure 4: Circuit schematic illustrating circuit reductions." width="500" >}} + +{{< figure src="/images/msc-thesis/pa3.png" title="Figure 5: Schematic of the reduced circuit representing a Class-E PA with inductive load." width="500" >}} + +Note that the series resistance of \\(L_1\\) may directly be absorbed by the effective real load \\(R_{EL}\\) and the series resistnace of \\(L_2\\) is absrobed trough equivilent loss of the the unloaded Q-factor corresponding to the resonant $L_2 C_{L2}$ tank. Formally, it has been assumed that the ac current observed at the resistive load purely sinusoidal and expressed as follows; + +$$ i_{R}(\theta) = I_{rf} \cdot cos( \omega_s t ) = m I_{dc} \cdot cos( \theta ) $$ + +Where m is the ratio between \\(I_{rf}\\) and \\(I_{dc}\\) and $\omega_s t$ is normalized to \\(\theta\\) as the system is periodic over $T = 2\pi \backslash \omega_s$. Furthermore, let the switch be closed for some abitrary reference frame defined by \\(-a_1\\) and \\(a_2\\) centered around 0, such that; + +$$ i_{sw} = \begin{cases} I_{dc} \left[1+m\cdot cos( \theta ) \right], & \mbox{for } -a_1 \textless \theta \textless a_2 0, & \mbox{ otherwise} \end{cases} $$ + +Note that the parameter \\(m\\) may be found be evaluating the charge conservation at the node \\(V_d\\) of the capcitor \\(C_{ds}\\) by; + +$$ I_{dc} = \frac{I_{dc}}{2\pi} \int \limits_{-a_1}^{a_2} \left[1+m\cdot cos( \theta ) \right] d\theta $$ + +Similarly by integration the at the node \\(V_d\\) is given by; + +$$ v_d (\theta) = \begin{cases} 0 , & \mbox{for } -a_1 \textless \theta \textless a_2 \frac{I_{dc}}{\omega C_{ds}} [ \theta - m \cdot sin(\theta) - a_2 - m \cdot sin ( a_2 ) ], & \mbox{ otherwise} \end{cases} $$ + +Given these waveforms one may perform a transform integral to find the power of the fundamental quadrature components which is expected to drive the load with the sinusoidal current \\(I_{rf}\\). + +$$ V_{di} = \frac{I_{dc}}{\pi \cdot \omega C_{ds}} \cdot \frac{1}{2m} [ m \cdot sin^2 ( a_1 ) - m \cdot sin^2 (a_2) + 2 \cdot cos^2 ( a_1 ) - 2 \cdot cos^2 ( a_2 )] $$ + +$$ V_{dq} = \frac{m \cdot I_{dc}}{2 \pi \cdot \omega C_{ds}} \left[ m \left( sin^2 ( a_1 ) + sin^2 (a_2) \right) + \frac{ sin (2 a_1 ) - sin (2 a_2 ) }{2} + 2 \cdot cos ( a_1 ) sin ( a_2 ) \right] $$ + + +With these components the phasor at the \\(V_d\\) side of \\(C_{L1}\\) must be match to the phasor at the known load $X_L + R_{EL}$ which specifies the coupling capacitor \\(C_{L1}\\) by impedence matching. + +$$ R_{EL} =\frac{ - V_{di}}{m \cdot I_{dc}} $$ + +$$ C_{L1} =\frac{ V_{dq}}{m \cdot I_{dc}} - X_{L} $$ + +Finally we need to consider the conduction angle of the transisor, that is $a_1 + a_2$ in degrees. Intuetively, the larger the conduction angle (bouned by a maximum value of 180 degrees) of the transistor the more dynamic current oscillating trough the primary tank of the circuit for a given capacitance \\(C_{ds}\\) but this also results in a very large peak voltage at the drain of the power transistor inducing a significant amound of stress at the pinch-off region in the channel. For high power applications a conduction angle of 110 degrees is generally suggested for trading off driving capability and compoent lifetime but since bio-telemetry power requirements are small and a direct interface with digital control components is desirable, the PA presented in chapter 3 has a conduction angle of 180 degrees. + +Note that one can also extract the DC component through using a transform integral which illustrates explicitly the linear scaling associated with the supply voltage and current load at the inductor. This characteristic is particularly useful for fine tuning the final PA configuration as it is initially difficult to specify the exact waveform at the rectifier, hence minimizing the power dissipated by the diodes remains challenging from the first cut design but is done at ease with simulation support. + +# 7 Ultra Wide Band Technology + +The UWB system is historically based on the spark gap transmitters developed by Marconi in the 1900s [^11]. Although there was potential for ground breaking data rates, the ability to control the UWB spectrum at the time was still in its infancy and made inter channel and multi user interference a serious problem. This ultimately resulted in the disregard for wide band communication in favor for the narrowband technology that was easier to regulate with respect to multiple end-users. The more recent 3.1GHz to 10.6GHz spectrum allocation for UWB applications that occupy at least 500MHz by the Federal Communications Commission (FCC) of United States in 2002 has sparked new interests in the field as commercial use is now permitted with a limited power spectral density of -41.3 dBm/MHz [^12]. + +The recent developments in ultra-wideband (UWB) technology have made a significant impact on a broad range of applications because it presents a set of relatively unique advantages: very short duty cycles, low power consumption and simple architectures which are ideal for modern cost efficient SOC miniaturizations that are often the focus of state-of-the-art research projects. In this respect, UWB has promised phenomenal performance for short range wireless channels allowing up to 100Mb/s data rates under very strict sub-mili watt power budgets with all-digital transmitter architectures that are much more robust in performance than their analog wave-mixing counterpart that can often not be integrated on the same chip due to substrate interference issues from other system components. + +{{< figure src="/images/msc-thesis/spec.png" title="Figure 6: Illustration of the spectral characteristics for the three main classes of communication technologies and the associated modulation schemes." width="500" >}} + +The foundation of UWB systems based around the characteristic low spectral density that results from very short pulses of energy but embody a very wide signal bandwidth. This characteristic allows the transmission of a signal with spectral energy distributed below the noise floor eliminating the chance of interference with coherent narrowband systems. The basis on which UWB is assured to attain the phenomenal bit rates suggested earlier comes from the well-known Shannon-Nyquist criterion that dictates the maximum channel capacity, \\(C\\), which can be achieved with arbitrarily small but nonzero probability of error and is given by [^13]; + +$$ C = BW \cdot log_2 \left( 1 + \frac{E_{signal}}{E_{noise}} \right) $$ + +Where \\(BW\\), \\(E_{signal}\\), \\(E_{noise}\\) are the channel bandwith, recieved in-band signal energy, recieved in-band noise energy respectively. Recognizing that SNR, \\(E_{signal}\\) / \\(E_{noise}\\) scales almost linearly with the total system power on both the transmitter and receiver side we observe that improving SNR by dissipating more power will, as disappointing as it is for high SNR environments such as nearfield biotelemetry, only improve the channel capacity in logarithmic fashion. However with a given bandwidth of several GHz we can still assure ourselves a Mb/s bit rate even with poor SNR ratios due to ultra low power transmitter operation from ther linear dependency of bandwidth. + +Some of the most significant developments in this field lie with the fully integrated CMOS pulse shapers that adhere to the FCC mask regulations [^14]. Pulse shapers not pertaining to the field of biomedical implants generally quote the energy dissipated per pulse FOM which ranges from 2nJ/pulse to some of the more recent work that nearly achievies 4pJ/pulse [^15]. There have been several publication have proposed using a UWB reverse link data transmission for biomedical telemetry with much success in terms of low power operation and have achieved 900fJ/pulse but did not present spectral compliance[^16]. + +There are three performance metrics of the UWB pulse that are of interest for commercial applications as they allow complete specification of the signal to noise and interference ratios for linear receivers [^17]. These three metrics correspond to spectral efficiency, out-of-band emissions, and time-bandwidth product [^18]. + +The first of which being the most intuitive, that is the spectral efficiency, which indicates how efficiently the designated spectrum is used in terms of how well all the radiated energy is confined within the 10dB ultra-wide bandwidth. This is expressed as; + +$$ \eta_{ch} = \frac{E_{ch}}{BW_{-10dB} \cdot max ( PSD_{W / MHz})} $$ + +Where the total in band spectral energy, \\(E_{ch}\\), is given by + +$$ E_{ch} = \frac{1}{2 \pi} \int_{BW_{-10dB}} PSD ( \omega ) d\omega $$ + +The second figure of merit for UWB pulses evaluates the normalized amount of spurious spectral energy is generated by the pulse. That is; + +$$ \eta_{0} = \frac{E_{tot} - E_{ch}}{E_{ch}} $$ + +Where the total radiated energy, \\(E_{tot}\\), is given by the time-domain integral + +$$ E_{tot} = \int^{\infty}_{-\infty} p(t)^2 dt $$ + +Finally, the time-bandwidth product primarily indicates the utility of the pulse in terms of being able to carry information. Consider for example the Sinc function which precisely has 0% out of band emissions however its time domain square power is unbounded indicated by the divergent integral for \\(d^2\\). This implies that modulation based on a ideal Sinc wavelet is non-realizable by a causal system. The time-bandwidth product being related to the standard deviation in the spectral intensity and time domain intensity which is formulated as follows; + +$$ D^2 = \frac{1}{2 \pi \cdot E_s} \int^{\infty}_{-\infty} \omega^2 \cdot | PSD(\omega)|^2 d \omega $$ + +Where the total radiated spectral energy, \\(E_{s}\\), is given by the frequency-domain integral\ + +$$ E_s = \frac{1}{2\pi} \int^{\infty}_{-\infty} | PSD(\omega)|^2 d \omega $$ + +$$ d^2 = \frac{1}{E_{tot}} \int^{\infty}_{-\infty} t^2 \cdot | f(t) |^2 dt $$ + +Such that the time-bandwidth product is summarized as; + +$$ B_{t \omega} = D \cdot d $$ + +Table 1: Summary of the UWB FOM performance for different classes of analytic pulses[^1]. +| | Spectral Efficiency | Out-of-Band Emissions | Time-BW Product| +|----|----|----|----| +|Sinc | 100% | 0% | (\infty) | +|Square | 60% | 12.8% | (\infty) | +|(2^{nd}) order | 59.2% | (2.8%) | 0.55 | +|Root-Raised cosine | 84.6% | (0.4%) | 0.85 | +|Gaussian | 56.5% | (3.3%) | 0.50 | +|Tanh | (58.4%) | (2.7%) | 0.53 | + +A significant amount of progress has already been made towards to maximizing these figures of merit in a more general UWB framework by means of photonics and microwave systems [^19]. Only a select few of these advances are fully integrated systems and since compact integrability is the strict requirement for the implant side system there is a still lot of room for improvement for current implant-compatible UWB transceivers. + +# 8 UWB Pulse Generation + +Fully integrated UWB technology is a relatively recent breakthrough, as previous pulse generation systems were primarily based on step recovery and tunnel diodes that under pulsed excitation produced a very different radiation spectrum that carrier based modulation schemes [^20]. Interestingly the spectrum used for time domain UWB encoding was essentially the modulated impulse response of the diode in operation. Moreover these wideband spectrums were found to allow much more accurate special resolution as well as exhibit some degree of immunity to passive interference (i.e. echos) [^21]. The integrated UWB framework bases its pulse generation on a more synthetic approach as the GHz operation of current CMOS technology allows pulse modulation with pulse width far below the average temporal UWB pulse duration which is around 1ns. This in many cases has allowed for piece wise reconstruction of a theoretically derive pulse shape such as those mentioned in table 1. + +{{< figure src="/images/msc-thesis/pl2.png" title="Figure 7: (left) spectrial representation of the oscilator and modulation waveforms (right) resulting UWB spectrum due to mixing." width="500" >}} + +The most elementary form of fully integrated UWB pulse generation is derived from sub GHz OOK modulation of the GHz oscillator [^22]. With the frequency domain transforms are illustrated in figure 7, since digital and analog oscillators are relatively disposable in the FCC UWB band this approach is arguably the most elementary topology that can achieve relatively good performance if the startup and dead times are well calibrated. The challenging aspect of this topology is it is difficult to both suppress the spurious frequency sidebands as well as the DC component at the output. + +{{< figure src="/images/msc-thesis/pl1.png" title="Figure 8: Illustration of the spectral characteristic of \\(1^{st}\\), \\(5^{th}\\), and \\(7^{th}\\) derivative based gaussian UWB pulses." width="500" >}} + +An alternative approach to generating UWB pulses is based on the spectrum of Gaussian derivatives [^14]. The family of Gaussian functions are generally well known for their transform limited behavior and as illustrated in the previous section the Gaussian pulse has the most optimal time bandwidth product out of all analytic reference pulses. Since the actual Gaussian pulse has a strong DC component the derivatives are more realizable in RF systems. + +$$ g^{(n)}(t) = \frac{d^n}{d t^n} \left( \frac{ A }{ āˆš{2\pi} \cdot \sigma} \cdot exp \left\{ \frac{-t^2}{2 \sigma^2} \right\} \right) $$ + +$$ |G^{(n)} (\omega) | = A \cdot (\omega)^n \cdot exp \left\{ \frac{-( \omega \cdot \sigma )^2}{2} \right\} $$ + +From the expression of the Gaussian UWB spectrum it can be observed that there are two parameters for spectral tunability that allow fitting under the FCC mask which has been done extensively [^23]. These two parameters are \\(\sigma\\) and the n which correspond to the temporal pulse width and the derivative order of the Gaussian pulse. By increasing the derivative order of the generated gaussian pulse the overall spectrum is expected to shift to the higher frequencies while simutaniously becomming more concave at the fundamental lobe. By reducing \\(\sigma\\) the spectrum also shifts towards the higher frequency spectrum but in contrast does not affect the fractional bandwith of the fundametal lobe. The \\(1^{st}\\), \\(4^{th}\\), \\(5^{th}\\), and \\(7^{th}\\) order Gaussian derivatives have been demonstrated to fit the FCC mask in literature and are thier allocation under the FCC mask is illustrated in figure 8 for a relative comparison. + +{{< figure src="/images/msc-thesis/pls1.png" title="Figure 9: Schematic of a simple Gaussian Pulse shaper." width="500" >}} + +{{< figure src="/images/msc-thesis/pls3.png" title="Figure 10: (left) Ultra short pulse control signals driving the Gaussian pulse shaper. (right) Piece wise constructed gaussian outout pulse fed to the antenna." width="500" >}} + +The integrated circuit implementation of these Gaussian pulse generators are typically fitted by a series of consecutive current pulses feeding into a coupling capacitor toward the antenna load. The pulses are typically under a 100ps long depending on the CMOS technology and by adjusting the driving capability of the MOSFET that is active during a particular phase the amplitude of the corresponding pulse can be adjusted according to the configuration that best fits the target Gaussian model. This topology has demonstrated some of the most energy efficient pulse generators yet, achieving a spectral energy density that nearly matches the FCC mask while consuming more than 4pJ per pulse. + +In extension to the Gaussian pulse generator topologies, a more generalized structure has also been introduced which focuses on efficiently generating a very board band pulse and filtering out the unwanted spectral components after amplification trough by an RF power amplifier. The filter can be implemented as an integrated on-chip LC filter or using a microwave distributed element filter topology [^24]. A particularly challenging aspect of this topology is that, although the implementation is the most robust, the filter is required to have a near constant group delay over the pass band to maintain ultra-short pulse durations and avoid pulse distortion. + +{{< figure src="/images/msc-thesis/pl3.png" title="Figure 11: (left) Schematic illustrating a RF PA amplifying a Broad band pulse that is then filtered by a lumped LC network. (right) Illustration showing how the broad band pulse is filtered to meet the FCC mask requirements by using a highpass filter. " width="500" >}} + +Overall these three topologies allows for fully integrated systems where often the implementation can be translated into a completely digital architecture where only the transistors driving the RF output need to be considered in analog terms. This benefit allow for rapid prototyping with very small chip area requirements, complete generation of a UWB transmitter by digital synthesis has also been demonstrated [^25]. + +# 9 Projecting System Requirements + +Due to the very rich physiological information neural signals carry, an overwhelming amount of interest has been seen in the monitoring of en vivo neural activity. The neural interface SOCs have since developed impressive set of performance standards that is expected to be maintained for the next few years. By cross-referencing the expected advances in neural recording technology a projection can be made on system requirements in the next 3 years [^26]. + +Table 2: Performance overview of the most recent state-of-the-art work on neural interfaces. +| | 2009 [^27] | 2010 [^28] | 2010 [^29] | 2011 [^30] | 2011 [^31] | 2012 [^32] | +|----|----|----|----|----|----|----| +|Technology | $0.35\mu m$ | $0.35\mu m$ | $0.35\mu m$ | $0.13\mu m$ | $0.18\mu m$ | $0.13\mu m$ | +|Channels | 1 | 128 | 128 | 1 | 32 | 96 | +|max BW (Hz) | 0.3k | 20k | 5k | 11.5k | 12k | 10k | +|ADC Resolution | 12b | 9b | 8b | 8b | 8b | 10b| +|ADC Sampling Rate (kS/s) | 1 | 640 | 111 | 10-100 | 125 | 31 | +|Data Rate per Channel (kb/s) | 12 | 360 | 111 | 100 | 250 | 313 | +|Power per Channel (W) | 895n | 344u | 190u | 75u | 10u | 68u | +|Power to Transmitter | - | 1.6mW | - | 400uW | - | - | + +From the references in table one can observe that although the effective power consumption per channel is steadily decreasing below $100 \mu W$. The sample resolutions and channel bandwidths tend to be slightly over 8b and 10kHz respectively as it appears to be the sweet spot that maximizes SNR with minimal power requirements. Given the expection to see 512+ channel neural SOCs in the coming 3 years it theoretically corresponds to an uncompressed data rate of 82Mb/s that needs to be transmitted through the reverse RF link. A similar analysis would estimate the required system power budget to be an optimistic 5mW system or a more pessimistic 15mW prototyping system that considers systems that have demonstrated neural recording from animal trails with more significant weighting. + +In summary, this chapter has given way for the target specification given in table 3 with the corresponding topology given by figure 12. + +{{< figure src="/images/msc-thesis/s3.png" title="Figure 12: System level abstraction of the proposed biotelemetry topology." width="500" >}} + +Table 3: Performance requirements for the implantable biotelemetry system. +|Parameter | Specification | +|----|----| +|Power Delivered to load | 15mW | +|Forwardlink Data rate | 300kb/s | +|Modulation Scheme | BPSK | +|Reverselink Data rate | 80Mb/s | +|Power to Transmitter | $\textless100\mu W$ | + +# 10 Forwardlink + +The forward link has been the primary focus of biotelemetry systems as the induction of wireless power into the body is a challenge that has been receiving attention since the 1960s and has continued to develop alongside the innovations made in power electronics and the more recent RFID technology [^8]. However, regardless of the modulation techniques presented in chapter 2, there is a very inherent limitation that the inductive link imposes in terms of data transmission. + +{{< figure src="/images/msc-thesis/s5.png" title="Figure 13: System block diagram of the forward link channel." width="500" >}} + + +With reference to figure 13, the system of interest here may be abstracted into four separate sections; the power amplifier, the inductive link, the demodulator, and the rectifier. Each of which substantiates a complete technical topic on its own and in association with the technical specifications given. This chapter will focus on first presenting an analytical description of the coil link in order to formulate target figures of merit followed by the employed power amplifier design with the associated simulation results. Techniques that minimize the loss introduced by phase transitions from BPSK modulation will be a very particular consideration that will be made at the end of this chapter together with the corresponding low complexity BSPK demodulator. + +# 11 Inductive Link Design + +{{< figure src="/images/msc-thesis/pa4.png" title="Figure 14: Circuit model of the inductive link driven by an ideal source." width="500" >}} + +With particular focus on maximizing the induced power onto the rectifier load which has be reduced to the ac equivalent \\(R_{AC}\\). With the reduced circuit illustrated in figure 14 one may be able to identify the two loss mechanisms that govern the power transmission transfer function. The first being the reflection coefficient associated with the resistive loading of inductor \\(L_1\\) due the secondary coil that is in series with the parasitic resistance of the inductor itself \\(R_1\\). The second loss mechanism abstractly lies with the self-loading of secondary inductor due to the parasitic resistor \\(R_2\\). Both of these parasitics are directly related to the Q-factor of the two inductive coils used to couple the two systems. In brief, the analytic expression for the efficiency of power induction may be derived at the resonant switching frequency, again that is $\omega_s = (C_{L2} \cdot L_2 )^{-1/2}$ , as [^33]; + +$$ \eta = \left[ \frac{V_L \cdot I_L}{V_s \cdot I_s} \right] = \frac{R_{eff}}{R_{eff} + R_{1}} \cdot \frac{L_2}{L_2 + R_{2} \cdot R_{AC} \cdot C_{L2}} $$ + +Where the effective impedance seen at the primary coil, \\(R_{eff}\\), is + +$$ R_{eff} = k^2 \cdot \frac{\omega^2 \cdot L_1 \cdot L_2}{R_2 + \frac{L_2}{R_{AC} \cdot C_{L2}}} $$ + +Further expansion will show that this equation may be optimized for a given k in terms of the load \\(R_{AC}\\) with respect to the inductor Q of coils \\(L_1\\) & \\(L_2\\). + +$$ R_{AC} \bigg|_{\eta=\eta_{max}} = \frac{\omega_s \cdot L_2}{k} \cdot āˆš{\frac{R_1 \cdot L_2}{R_2 \cdot L_1}} = \frac{\omega_s \cdot L_2}{k} \cdot āˆš{\frac{Q_2 }{Q_1}} $$ + +Such that the peak efficiency, \\(\eta_{max}\\) may be expressed as + +$$ \eta_{max} = \frac{k^2 \cdot Q_{L1} \cdot Q_{L2}}{(1+ k \cdot Q_{L1})(1+ k \cdot Q_{L2})} $$ + +The limiting factor associated with the coils is primarily the total chip area hence the coil geometry should maximize the coupling quality factor product per unit area. Previous systems will either opt for a coil integrated on to the PCB which allows improves the ability manufacture the end result or a coil that is implemented by a wrapped linz wire which makes scalable prototyping challenging but provides much better performance in terms of inductor Q-factors [^34]. PCB integrated inductors tend to be more lossy for a given inductance primarily because of the space requirements on the traces which prevent the dense inductance one may expect from a wire wrapped coil. The majority of published literature tends to prefer using circular geometries as their properties are accurately predicted by analytic formulas, it should be noted however that rectangular coils achieve higher coupling coefficients per unit area. With this in mind, the coils that tested in the laboratory were based on copper wire wrapped rectangular geometries. In analogy to closely space circular coils where it has been demonstrated that the mutual inductance is maximized when the primary and secondary coils have the same geometry we expect the same from the rectangular coils [^35]. + +{{< figure src="/images/msc-thesis/l3.png" title="Figure 15: (left) Circular Coil geometry. (center) Square coil geomerty. (right) in plane view of coils." width="500" >}} + +Using EM simulation tools a simple study was conducted to confirm these findings. Using a single turn circular loop with a diameter normalized to the parameter r and a square loop with the side length also normalized to the parameter r, we studied the behavior of the coupling coefficient k with respect the out of plane distance, d, from two identical coils and the lateral in plane displacement a. The results illustrated in figure 16 confirmed that, although circular coils achieve better quality factor, the square coils achieve better coupling coefficients implying with reference to equation 24 that square coils achieve higher peak efficiency . + +\\(\\) \frac{Q_{circle}}{Q_{square}} = 1.87 & \frac{k_{circle}}{k_{square}} = 1.88 \\(\\) + +{{< figure src="/images/msc-thesis/KUPL.eps" title="Figure 16: EM simulation results of the coupling coefficient with respect to the in-plane and out-of-plane normalized displacements." width="500" >}} + +In accordance to the above considerations and estimates on the ac load expected to be loading the secondary coil a two coil rectangular link was prototyped. The primary coil and secondary coil were measured in the lab to evaluate the mutual inductance values where the mutual inductance was evaluated through a differential measurement [^36]. + +Table 4: Measured characteristics of the two inductive coils measured at coil distance of 10mm. +|Parameter | Primary Coil (L_1) | Secondary Coil (L_2)| +|----|----|----| +|Turns | 29 | 15 | +|Dimensions (mm) | 12 x 24 | 12 x 24 | +|Inductance (uH) | 46.59 | 12.67 | +|(R_s) ((\Omega) at 1MHz) | 7.49 | 3.19 | +|(k_{21}) | 0.134| + +{{< figure src="/images/msc-thesis/loop.png" title="Figure 17: Photograph of the prototype rectangular coil used for power induction." width="500" >}} + +Given the measured coil characteristics, the Class-E PA was designed in accordance with the method presented in chapter 2. By introducing the simulation models of commercially available components the design was fine tuned to achieve a power transmission efficiency of 46%. The derived system delivers 15mW to a 600 ohm load corresponding to an unregulated supply of 3V. The losses from the primary and secondary contribute to 30% and 14% of the total power dissipation respectively. The off chip rectifier dissipated 8% of the total power which actually correspond to a marginal efficiency of 85%. The remaining 3% is dissipated by the RF choke and the power transistor. + +{{< figure src="/images/msc-thesis/pa0.png" title="Figure 18: Detailed circuit schematic of the complete power transmission system with the component names/models annotated." width="500" >}} + +Note that a the power transistor in figure 18 is a 2N7000 Fairchild N-Channel Enhancement Mode Field Effect Transistor with a maximum drain voltage rating of 60V. + +{{< figure src="/images/msc-thesis/power.png" title="Figure 19: Simulation results of the power induction system in operation illustrating a average 46% PTE." width="500" >}} + +# 12 Switch mode BPSK Modulation + +In one respect the input waveform of the Class E amplifier is no longer trivially related to the waveform driving the load in time domain and strictly speaking the degrees of freedom at the driving transistor are now limited to two states; open circuit, and closed circuit. As a result the dynamic range of this class of amplifier is limited to the unit gain circle on the constellation diagram. This inherently presents a problem for BPSK modulation as the state transitions through the zero crossing as shown in figure 20 which for many amplifier topologies is undesirable due the fact that is strains the dynamic range requirement. In the RF domain regulating the transition behavior is rather strict as state transitions that lie beyond the capability of the amplifier result in spurious frequency components from distortion that lie outside of the designated frequency band. In the case of biomedical telemetry we shall observe that such a careless transition results a significant amount of loss in the system. To alleviate this problem we shall introduce an intermediate state to allow a smoother transition without introducing additional system complexity. + +{{< figure src="/images/msc-thesis/cnst2.png" title="Figure 20: (left) Standard BPSK constellation diagram. (right) Constellation diagram of the proposed BPSK modulation scheme." width="500" >}} + +Figure 21 shows the simulation results of phase transition of two BPSK modulation techniques, the first in blue being the simple BPSK modulation of a square wave and the second in red being the proposed BPSK modulation of a square wave with an intermediate state. It is obvious that there is a dramatic difference with respect to the voltage waveform seen at the rectifier input. The simple modulation technique not only results in a slow transition but there is no energy induced for a number of cycles which is detrimental to the system PTE \\(\eta\\). The proposed modulation scheme first transitions to \\(+\pi/2\\) for half a cycle before completing the phase shift towards \\(+\pi\\). It is important to note that open circuit state of the RF switch maintains its temporal duration as this is the mechanism that provides harmonic termination to the higher order harmonics that are reflected by the LC tank. + +{{< figure src="/images/msc-thesis/MOD.eps" title="Figure 21: Simulation results illustrating the gain in average PTE and the destructive inteference of the two phase states during the phase transition without the intermediate state." width="500" >}} + + +Even with this modulation technique a linear trade off with respect to the carrier frequency and the forward data rate is still to be expected as one cycle for every phase transition fails to induce power. The expected power transfer efficiency, \\(\eta\\), during modulation is asymptotic to and approximated by the following expression. + +$$ E \left[ \eta \right] = \eta_{s} \cdot ( 1 - N \cdot \frac{f_{data}}{f_{carr}} ) $$ + +Where \\(\eta_{s}\\), \\(f_{carr}\\), \\(f_{data}\\) are the un-modulated PTE, carrier frequency, and data rate respectively. N is the model parameter that corresponds to the number of cycles skipped as a result of a phase transition which our fitting estimates to be approximately 1 for the proposed modulation scheme. It is now clear that faster switching frequencies driving the PA will also allow for proportionally faster data rates without having to sacrifice efficiency. + +{{< figure src="/images/msc-thesis/swtmd.eps" title="Figure 22: Simulation results of the PTE with respect to different data rates and the fitting parameters of the extracted model." width="500" >}} + + +# 13 Integrated BPSK Demodulator + +To reduce overhead, the demodulator illustrated in figure 23 recovers the transmitted data stream is not based on a delay locked loop topology but based on detecting the cycle skipping of phase transitions. Although it is arguable that this type of detection is prone to failure due to coil displacement when the designated patient moves these kind of environmental factors influence the induced voltage waveform in the very low frequency spectrum that typically do not exceed 100Hz. Hence a high-pass filter behavior is introduced to the peak voltage detector using the parasitic capacitance and leakage current of the transistor M9. + +{{< figure src="/images/msc-thesis/bddd.png" title="Figure 23: (left) Transistor level schematic of the threshold based phase detector. (right) Digital State machine that detects phase changes in the induced voltage waveform." width="500" >}} + +The remaining operation of the circuit is intuitive, M1 shifts the voltage wave at the input of the rectifier down so that is falls below the supply voltage and the transistors M5-M7 determine & compare the voltage \\(V_{bias}\\) and the peak voltage which is $max(V_{in}-V_{thm1} - V_{thm8})$. Due to the over driving effects the output is approximately digital in characteristic where Vclk is low then Vin is larger than \\(V_{bias}\\) and \\(V_{sig}\\) is low when Vin larger than the stored peak value. These signals are processed by some simple digital circuitry to detect when \\(V_{in}\\) drops below its peak value by more than one NMOS threshold voltage. The near digital operation of this circuit the power consumption is just under $1.5 \mu W$ and simulation results of phase detection is shown below in figure 24. + +{{< figure src="/images/msc-thesis/DBPSK.eps" title="Figure 24: Simulation results showing the operation of the threshold based phase detector" width="500" >}} + +# 14 System Summary + +In this chapter a class-E based forward transmission link was presented that couples power and transmits data. To engage the discussion on system design a common framework for coupled coils was presented to formulate a objective that brought forth the efficiency figure of merit. In addition to the schematic specifications of the transmitter, the modulation scheme was considered in detail with respect to the switch mode amplifier by identifying the underlying phase transition inefficiencies. By introducing an intermediate state the power transmission efficiency during modulation was improved an a accurate model describing the trade off between modulation rates and carrier frequency was presented. Finally the a low power BPSK demodulator was proposed. + +# Reverselink + +The reverse link of the biotelemetry system primarily pertains to the RF communication link that sends large amounts of data acquired in vivo by the sensory instrumentation devices to a receiver external to the body. The focus of this chapter will revolve around how this reverse link achieves a very high data rate with the minimum amount of power consumption, that is minimizing the energy per bit transmitted, and proposing a scalable modulation technique for low power applications. Followed by the design considerations of a digitally calibrated oscillator as well as an energy efficient bi-phasic UWB pulse generator, a UWB antenna design shall be presented with considerations towards near field pulse transmission. Finally a energy detection based UWB receiver topology is proposed for testing purposes. + +{{< figure src="/images/msc-thesis/s4.png" title="Figure 25: System level abstraction of the UWB transceiver." width="500" >}} + +# 15 UWB Pulse Modulation + +Let us first consider the two principle modulation techniques illustrated figure 26 that have been the most successful in UWB communication systems, which are binary phase shift keying (BPSK) and pulse position modulation (PPM). BPSK can be directly associated with the continuous wave modulation techniques and has shown to be a good alternative for pulse modulation that does not distort the output spectrum significantly [^37]. PPM is based on temporal delays and advances of the UWB pulse to modulate the signal. Current PPM systems are based on modulation with reference to a receiver oscillator that is locked through a digital Costas loop equivalent that requires transmitter dead time for synchronization. As current pulse generators consume at least several pJ per pulse we may assume that over 80% of the system's power consumption will be due to the actual output pulse driving the antenna.The interest here lies with encoding a single pulse with multiple bits to maximize efficiency. Simply combining the two modulation techniques is the easy way to boost efficiency but may not be worth the increase in system complexity. + +{{< figure src="/images/msc-thesis/cnst.png" title="Figure 26: (left) Time-domain representation of BPSK & PPM modulation schemes. (right) Constellation diagrams of BPSK & PPM modulation schemes illustrating the inherent SNR reduction for PPM." width="500" >}} + +The bottle neck that prevents a scalable system that encodes multiple pulse positions lies with how the temporal delay are generated in contemporary designs. For non-coherent detection systems these delays must be relatively small and accurate to maintain correct detection on the receiver end which if scaled up would result in too much calibration overhead to tune each pulse position. For coherent based UWB receivers the pulses must be orthogonal with respect to the detection window which is even more challenging for detecting multiple phase states. Instead if the delay of a fixed period is used from a calibrated digital oscillator (DCO) and multiple pulses are allowed within a short reference frame, the scaling of the position encoding mechanism can be improved in a fundamental way while maintaining system simplicity. More importantly, using a DCO allows us to dedicate a lot of resources for fine tuning the delay of a single element where if multiple delay elements need to be used the restricted resources would limit the tuning of the resulting delay and introduce unwanted phase noise. + +{{< figure src="/images/msc-thesis/n2.png" title="Figure 27: (left) Simple delay encoded pulses with reference to a DCO clock. (right) Pulses encoded by the cascading of two delay symbols in a single data word." width="500" >}} + +As illustrated above in figure 27, the data is essentially encoded in the delay between pulses. More importantly, note that the pulse package is encoded with reference to the first pulse which allows for accurate receiver phase locking. The implications of this type of ā€˜delay encodingā€™ are quite significant. First and foremost the energy detection receiver can now actually be asynchronous negating the need for startup dead time. Since efficiency improves only by the logarithm of the maximum delay it is not area efficient to encode large delays but by cascading multiple encoded delays after one another bit rate, area, and efficiency can be traded off with a significant amount of flexibility. Moreover by omitting the last pulse of the package a delay of 0 can be encoded for improved efficiency. + +It should also be apparent that this approach has two main draw backs, the first being that it is particularly sensitive to the DCO frequency off sets for long delays that integrate to large amount of phase noise over the signal window. The other drawback is to maintain FCC mask compliance the peak output power of the UWB pulse must be reduced which degrades the signal to noise ratio. On the other hand however this modulation technique can tolerate a temporal equivalent of phase noise equal to half the DCOā€™s period. + +To give further insight to the expected degradation in the bit error rate (BER), let us consider the absolute worst case scenario where the entire word needs to be detected by a linear receiver. That is, each symbol transmitted needs to be detected at the receiver and is subject to the same AWGN from the channel. For simplicity a threshold detection receiver model has been adopted that integrates the incident RF power waveform by self mixing and samples the accumulated energy before resetting the integrator for the next reference window at a period of \\(T_w\\). In addition, let us assume the signal band with is known such that the probability of detecting a pulse, \\(P_{bit}\\), for \\(\frac{E_b}{N_0}\\)\textless $\frac{T_w BW}{2}$ is given by [^17]; + +$$ P_{bit}=Q\left( \frac{E_b / N_0}{āˆš{2T_w \cdot BW + 2E_b / N_0}} \right) where Q(x)=\int^{\infty}_x \frac{exp(\frac{-t^2}{2})}{āˆš{2\pi}} dt $$ + +Here \\(E_b\\) and \\(N_0\\) denote the energy in the pulse and AWG noise over the integration window \\(T_w\\). In extension the expected value of the BER for this particular modulation scheme may be evaluated by considering the probability of detecting the whole word correctly, the probability of sending that particular word, and the number of bits transmitted per word. For simplicity assume each word is equiprobable, which is sub-optimal source coding but regardless, then for the simple case of non-cascaded delay encoding the BER may be expressed as; + +$$ BER_1 = \frac{1 - \sum\limits_{i=1}^{D_{max}} \left[ \frac{(1-P_{bit})^{i+1}}{D_{max}}\right] }{2+log_2(D_{max})} $$ + +Where \\(D_{max}\\) is the maximum delay encoded by the transmitter. If the BER of a N times cascaded delay system is to be evaluated then the previous expression is simply adjusted in the same regard to recomputing the expected value and the number of bits per word. + +$$ BER_N = \frac{1}{1 + N + \sum\limits_{j=1}^{N} log_2(A_j)} \cdot \left\{ 1 - \frac{1 - \sum\limits_{i=N}^{D_{max}} \left[a_i \cdot (1-P_{bit})^{i+1}\right] } {(\sum\limits_{i=N}^{D_{max}} a_i)} \right\} $$ + +Here the series \\(a_i\\) denoted the number of ways one can encode a word in the cascaded system with \\(i\\) delays, note that for each cascade of delays the minimum number of delays is 1. The series \\(A_j\\) denotes the maximum possible delay ecoded by the \\(j^{th}\\) cascaded delay and N denotes the number of cascaded delays. To find a closed form expression for th series \\(a_i\\) one must consider the problem of sorting i elements in N sets that are constrained to the carnality given by the series \\(A_j\\). For the proposed system where \\(N=2\\), the series is given by; + +$$ a_i \bigg|_{N=2}= (1+ i) - \sum\limits_{j=1}^{2} \left[ \sum\limits_{k=Aj+1}^{i} 1 \right] $$ + +Where $A_j=\{8 , 4\}$. These results confirm our previous statement that the expected BER worsens as the maximum possible encoded delay is increased but by increasing N this degredation can be aleviated by as the bit rate is increased by N and the N sum over the log maximum delay of each cascaded delay. + +# 16 System Architecture + +The system architecture abstraction illustrated in figure 28 is the proposed integrated UWB transmitter which consists of three main components; DCO, Delay Modulator, and Pulse shaper. Although the previous discussion has pointed out the general purpose of using an on-chip oscillator it should also be noted that such high frequency oscillators can dissipate a significant amount of power. To alleviate the power hungry behavior of the DCO a feedback loop is introduced into the system that enables very exact duty cycles such that the oscillator is only switched on to generate the required number of delays and is turned off once the delay encoded package is generated saving a significant amount of power as the complete package duration is on average only half the maximum encoded delay for single delay encoded equiproportional set of words. + +{{< figure src="/images/msc-thesis/mod.png" title="Figure 28: System level abstraction of the UWB transmitter architecture." width="500" >}} + +The proposed system uses a 10MHz reference input clock generated by an accurate crystal oscillator and will be used to both calibrate the DCO trough a frequency locked loop (FLL) as well as being the reference for the first pulse of the data package that partly acts as a preamble. The delay modulator is essentially a pulse swallow circuit where the decision to swallow a pulse (i.e. introduce a delay) is encoded in a shift register feeding the D flip flop. + +# 17 Digitally Calibrated Oscillator + +The main challenge in designing the DCO lies with the fact the digital oscillators are very prone to variation in the oscillation frequency as a result of variation in supply, process parameters, and layout parasitics/mismatch. The Monte Carlo simulation in figure 29 shows that, if the presented DCO topology were uncalibrated, the oscillation frequency would have a standard deviation of 45MHz which as discussed previously results in large amounts of phase noise at the receiver. To alleviate this problem a two stage calibration mechanism has introduced with a total resolution of 8 bit to assure a large and accurate tunability range of the oscillation center frequency. The 4 most significant bits calibrate the main capacitive load of the DCO which is a binary weighted Metal-Insulator-Metal capacitive array, with unit capacitance of 5fF, by connecting an arbitrary combination of capacitors to ground and leaving the rest floating. The 4 least significant bits calibrate the NMOS driving capability of an inverter which inherently allows for tuning at a much more precise scale as the transistors can be well matched without taking up a considerable amount of area with only fractional differences in their size. + +{{< figure src="/images/msc-thesis/MC.eps" title="Figure 29: Monte-Carlo simulation result of the uncalibrated Oscillation frequency." width="500" >}} + +The DCO also includes a Frequency Locked Loop (FLL) that during the calibration phase will tune the DCO output frequency to match that of an accurate reference clock. A fully digital implementation was chosen so minimize area and so that the self-calibration loop can be switched off during normal operation. Although Phase Locked Loops (PLLs) are generally preferred for this particular kind of functionality due to their quicker lock-on time, the all-digital FLL in figure 30 surpasses the all-digital PLL in simplicity as no digital loop filter is required. + +The principle of operation of the FLL is based on detecting which clock has a faster rate of rising edges by using a simple set reset latch that is set by reference clock and reset by the DCO clock. If the DCO is resetting the latch more often than the reference lock is setting the latch a pulse is generated at the output of the frequency detector that increments or decrements an 8 bit counter that calibrates the DCO proportionally. Similarly if the latch is set more often than reset a pulse is also generated such that the rate of pulses at the output of the frequency detector is directly equal to the absolute difference in frequency between the reference and DCO clock. The state that persists while these pulses are generated indicates whether the DCO frequency must increase or decrease. Note that the generated DCO clock is divided by a factor of 50 such that the 500MHz clock can be calibrated with respect to a low cost off the shelf 10MHz crystal. + +{{< figure src="/images/msc-thesis/dco.png" title="Figure 30: Schematic of the Frequency locked loop used to enable self-calibration of the DCO" width="500" >}} + +Figure 31 Illustrates that the presented DCO exceeds a 3 sigma tunability range with respect to the expected standard deviation in DCO frequency with a resolution of 1.58MHz which corresponds to oscillation period that is accurate to Ā±4ps. The DCO consumes an average of $72 \mu W$ during continuous operation. + +{{< figure src="/images/msc-thesis/DCO.eps" title="Figure 31: Simulation result of the frequency range capability of the DCO." width="500" >}} + +{{< figure src="/images/msc-thesis/step.eps" title="Figure 32: Transient simulation illustrating the response of the FLL due to a step decrease in reference frequency." width="500" >}} + +# 18 Bi-phasic UWB Pulse Generator + +In order to satisfy the FCC regulations for UWB communication [^12], two different approaches have been presented in previous literature. One approach is based on modulating the envelope of a RF oscillator output which allows for simultaneous UWB communication in multiple frequency bands [^22]. The other approach is based on maximizing the spectral efficiency by fitting the UWB pulse shape to a Gaussian derivative that optimally fits the FCC mask by piecewise modulation of multiple current pulses [^38]. The design proposed here is a hybrid between these two approaches employing a simple all-digital architecture that generates a UWB pulse with improved energy efficiency using an oscillator output shaped by piece wise current pulses. + +The pulse generation techniquest presented are has been partly adopted from previous work that used integrated LC components to filter out the unwanted spectrum to meet the FCC mask requirements [^39]. However instead of dissipating the unwanted spectral energy, a lossy LC resonator is used to recycle the unwanted spectral energy and modulate this to its resonant frequency. Abstractly speaking, the inductor is pulsed with current over 180ps. This induces energy that is stored in the magnetic field and is gradually dissipated in the load (over 1ns while the LC pair resonates in response to the impulse). This integrated pulse generator designed is based on a 0.18\\(\mu\\)m CMOS technology using a 1.2V supply and assuming a 50\\(\Omega\\) termination. + +{{< figure src="/images/msc-thesis/puls.png" title="Figure 33: Schematic Illustration of the Digital pre-shaping. Note that the relative temporal delays are not to scale." width="500" >}} + +The Digital pre-shaper is shown in figure 33. This uses a popular glitch generator to generate 180ps long Gaussian like pulses, which are demultiplexed to two inverter chains to boost the driving capability of the output. It is important to note that these chains have a different output polarity but both output the buffered pulse together with a delayed and inverted pulse, driving the transistors sourcing the inductor with pulsed current (shown in figure 34). The purpose of the delayed pulse is to cancel the DC component generated by the transient impulse response of the lossy LC resonator, by injecting an equal but complementary pulse at the opposite port of the inductor. By driving either the end connected to the load, or the \\(C_{res}\\) end of the inductor first, the polarity of the UWB pulse is well controlled. + +The illustration in figure 33 also shows how a simple shift register can interface the UWB transmitter with a parallel input data stream. With reference to fig, it is interesting to note that since the transistor pairs M1, M4, M2, and M3 are matched in terms of driving capability this particular topology is immune to variation in pulse length which may easily distort the performance of aggressive UWB pulse generators that use multiple glitch generators to shape the pulse. + +{{< figure src="/images/msc-thesis/rf.png" title="Figure 34: Circuit schematic of the RF section (parasitics not shown) - Lres = 4nH; Cres = 200fF." width="500" >}} + +Since both the total pulse energy and pulse width (due to ringing) is directly proportional to the Q of the resonator, one must trade off pulse length for amplitude where a higher Q results in longer ringing but also larger peak to peak values. In this particular case, a single layer 6-turn 8-sided spiral 4nH inductor with poly-silicon ground plane was used with the dimensions 4\\(\mu\\)m, 2:8\\(\mu\\)m, 96\\(\mu\\)m corresponding to the trace width, trace spacing, and outer radius respectively. The pulse energy was tuned to fall below 5% within 1ns to avoid inter symbol interference corresponding to the resonant capacitance of 200fF. + +{{< figure src="/images/msc-thesis/TRAN.eps" title="Figure 35: Simulation Results of the bi-phase UWB temporal response illustrating a 350mVpp Amplitude" width="500" >}} + +{{< figure src="/images/msc-thesis/DFT.eps" title="Figure 36: Simulated PSD of the designed UWB pulse & the indoor UWB FCC mask as annotated" width="500" >}} + +It can be observed in figure 36 that the current output spectrum does not meet the sub 2GHz FCC mask specifications and thus future work based on this UWB pulse generator will filter this particular spectrum using the geometric resonance of the UWB antenna which can efficiently implement a high Q high pass filter and has already been demonstrated feasible [^24]. On that note, this system consumes 1.65pJ/pulse, which corresponds to an average of 16.5\\(\mu\\)W with a pulse rate frequency of 10MHz and has a competitive edge over many previous publications in terms of the energy per pulse figure of merit shown in table. + +Table 5: Performance summary and comparison of UWB transmitter. +|Reference | Output (V_{pp}) | Pulse width/BW | Power (pJ/pulse)| +|----|----|----|----| +|[^14] | 700mV | 0.38ns/7.2GHz | 15.4| +|[^40] | 600mV | 0.4ns/7.5GHz | 26.4 | +|[^15] | 500mV | 0.8ns/2GHz | 4.7 | +|[^41] | 180mV | 3.5ns/0.5GHz | 18| +|[^38] | 165-710 mV | 2.4ns/300MHz | 17.5 | +|This Work | 350mV | 1ns/4GHz | 1.65| + +# 19 UWB Antenna + +With fresh insights from the UWB pulse shaper presented in the previous section, there are a number of observations that can be made with respect to the requirements of the antenna with respect to bandwidth and input impedance. In particular, we require a 22dB rejection of the sub 1.6GHz band with respect to the pass band and a 50 ohm impedance across the 3-7GHz band that needs to be radiated out to the environment. The remaining standard requirements of an antenna are primarily associated with the directionality and gain of the radiation pattern which for the biotelemetry system depend on the orientation of the two antennas which is illustrated below. The antennas will essentially be coupled in the near field which is not ideal in terms of radiation efficiency but sufficient for simple SOC applications where the receiver end is not limited as strictly by power requirements such that additional gain in the RF band can be attained. + +{{< figure src="/images/msc-thesis/chnl.png" title="Figure 37: Illustration showing orientation of the antennas with reference to the inductive coils and skin barrier." width="500" >}} + +A planar antenna that is directional with one lobe tangential to the plane would be the most desirable for the proposed antenna orientation but the compactness of the antenna is a far more valued requirement. Note that this particular orientation avoids capacitive loading on the antenna where current densities at the highest and allows the UWB antennas to be conveniently distanced from one another without compromising the implant size. Another challenging antenna property that is required is that the radiation pattern must be stable across the ultra-wide band and more importantly that the radiated energy maintains a constant group delay at the receiver side to avoid excessive distortion of the UWB pulse. The last requirement is ultimately the most challenging as it requires the single mode of radiation retained over a bandwidth of several GHz for simple electrically small antenna structures. + +A comment should be made with regard to the fundamental limitation of electrically small dipole antennas, as it can be shown that the fractional bandwidth of the antenna explicitly inverse to the quality factor of the antenna and hence it is theoretically possible to achieve UWB specification using these structures. However, the quality factor is directly related to the radiation efficiency by the Chu-Harrington limitations which inhibits the use of compact quarter wavelength dipole structures [^42]. Instead a class of ā€œfatā€ monopole antennas has been introduced that provide a similar foundation for simple geometric structures that show adequate performance for UWB applications. The success of these structures lie with the many overlapping resonant modes that the geometries exhibit and hence appear to resonate over a large bandwidth. The most successful planar structure according to the demonstrated radiation efficiencies presented in literature has been the elliptical monopole off which we have based our primitive antenna design as well [^43]. + +{{< figure src="/images/msc-thesis/ant.jpg" title="Figure 38: (left) illustration of the UWB antenna geometric variables. (right) Photo of the exposed prototype UWB antenna. Note the darker gray rectangle indicates high dielectric substrate on both sides of the metalization." width="500" >}} + +In addition to the matching requirements of the antenna, it is highly desirable if the antenna is scaled down to the smallest possible size. UWB antennas from literature are primarily based on off the self FR4 substrate have a radiating patch is on the order of $16 cm^2$. In order to scale down the antenna to around the \\(1cm^2\\) area a high dielectric substrate, RO3010, was used. More specifically, the elliptic lobe that is used to match the $50 \Omega$ co-planar transmission line is enclosed by the high dielectric substrate on both sides of the metalization leaving the radiating gap between the ground plane and the ellipse partly exposed on one face in order to avoid deteriorating the radiation efficiency. + +{{< figure src="/images/msc-thesis/PROT.eps" title="Figure 39: EM simulation results illustrating the degeneration of the first resonant mode to improve performance." width="500" >}} + +The basic geometry in figure 38 illustrates the addition of a elliptic lobe that is placed protruding from the ground plane towards the elliptic patch which was found to give the antenna the desired in-plane directivity of 3dB and improved wide band matching. The ground plane extension generally reduced the Q-factor of the first mode such that its resonance overlaps more continuously with the second mode as may be observed in figure 39 by the gradual improvement in the reflection coefficient as the lobe is extended towards the antenna. + +{{< figure src="/images/msc-thesis/A1.eps" title="Figure 40: EM simulation of the \\(S_{11}\\) reflection coefficient for the finalized UWB antenna geometry." width="500" >}} + +{{< figure src="/images/msc-thesis/TRNSM.eps" title="Figure 41: Preliminary side-by-side \\(S_{21}\\) transmission characteristic." width="500" >}} + +The preliminary EM simulation results in figure 40 show adequate performance over the 3-7 GHz band in terms of a reflection coefficient below -10dB with a constant group delay that only varies by several tens of degrees. Figure 41 illustrates a more insightful the transmission characteristic of the near field coupling that the two antennas would experience placed side by side 1cm apart. The designated bandwidth of interest, 3GHz to 7GHz, has an insertion loss of 20dB and exhibits near negligible fluctuation in the group delay, that is less than 50 ps. The corresponding finalized parameters describing the antenna geometry are listed in table 6. + +Table 6: UWB antenna parameters +|Parameter | Length $(\mu m)$| +|----|----| +|R | 5000| +|(R_g) | 400| +|(R_t) | 800| +|G | 290| +|W | 440| +|C | 260| + +{{< figure src="/images/msc-thesis/MA.eps" title="Figure 42: (top) Comparison of the measured and simulated \\(S_{11}\\) characteristic. (bot) PSD generated by the UWB pulse shaper for reference." width="500" >}} + +The first set of prototype UWB antennas were developed through manual photo chemical etching whose reflection characteristics are shown in figure 43. The sub 5GHz band appears to match the simulation results relatively well while there are some hints of over etching. The band above 5GHz however is characteristically very different from simulations. The author believes this to be the result of edge roughness introduced by uneven distribution of spray-on photo resist that was used in the development stage as a number of other antenna samples had miniature holes in the ground plane indicating a non-homogeneous etch. There is still a level of adequacy for the measured antenna as the UWB pulse PSD covers the entire band that exhibits the ability to radiate. The high Q notch at 5.5GHz however may significantly distort UWB pulses due the corresponding fluctuation in group delay. The prototype antenna does present a respectable 2GHz bandwidth. + +{{< figure src="/images/msc-thesis/chmbr.png" title="Figure 43: Photograph of the UWB antenna under test in the Imperial College anechoic chamber." width="500" >}} + + +# 20 Reciever + +The receiver presented in this section is primarily aimed at system completeness and the testability of the power optimized UWB transmitter system as many of the strict constraints that concern the implanted system no longer apply to the external system. UWB receiver architectures generally consist of almost completely digital architectures including RF ADCs with the exception of front end tunable low noise amplifiers for pre-acquisition gain. Pulse detection methods are very much translated into the DSP domain where channel approximation algorithms have proven to be very successful at filtering and detective UWB pulses mainly because of critical and overly complex filtering requirement that needs to adapt to both the channel and the effectively unknown input spectrum of the pulse that highly distorted after transmission [^44]. + +{{< figure src="/images/msc-thesis/rec.png" title="Figure 44: System level abstraction of the reciever architechture." width="500" >}} + +Since both the most basic coherent and non-coherent UWB receiver architectures are beyond the scope of this project a very simple energy detection system has been derived that assumes no strong interferer is transmitting in the UWB spectrum such that the UWB pulse can easily be detected by energy thresholding. + +Based on this detection, a set of trigger pulses are generated ideally identical to those generated at the output of the delay modulator. Using the same DCO, the delay between these triggers can be counted by a set of registers such that the encoded information is extracted from trigger circuit recovering all data sent from the transmitter. + +{{< figure src="/images/msc-thesis/dly.png" title="Figure 45: (left) Schematic of the implemented delay-locked loop. (right) Analog tuned delay element." width="500" >}} + +To synchronize the two systems a delay locked loop is introduced at the receiver that uses analog delay elements in combination with a charge pump phase detector[^45]. The control loop illustrated in figure 45 synchronizes the output of the delay line \\(V_{sync}\\) with the reference clock \\(V_{ref}\\) by continuously integrating the phase difference of the two signals. As charge accumulates onto \\(C_p\\), the resulting voltage biases four cascaded delay elements that each can efficiently introduce delays up to 25ns. The actual mechanism of the analog delay element is based on around the current starving the inverter structure of M5 M4 such that the time it takes to reach the switching point of the output inverter M12 M13 is controlled. Note that once the switching point is achieved the state rapidly regenerates itself due to M8 M9 assuring a fast transition. More importantly the structure negates short circuit currents that may be introduced by the slow switching of the first stage through the transistors M14 and M11. + +# 21 UWB System Summary + +Transient simulations of the UWB transmitter, illustrated in figure 46, have confirmed the general operation of the delay modulator and extracted simulation of the whole system have indicated a power consumption of $68.9\mu W$ for a PRF of 10MHz. Since the transmitter is encoding the pulses with an effective data rate of 77.5 Mb/s these results correspond to a energy per bit FOM of 890fJ per bit. By extrapolating these results to find the power consumption of the system excluding the UWB pulse shaper, it can be stated that the modulator consumes 470fJ per DCO oscillation and corresponds to 34% of the over power consumption. + +{{< figure src="/images/msc-thesis/POWER.eps" title="Figure 46: System level simulation results of the DCO, Modulator, and pulse shaper outputs as well as the accumulated power consumption." width="500" >}} + +Although the total phase noise expected at the output of the delay modulator still needs to be characterized, the complete UWB system presents respectable performance in terms of power consumption. And from figure 42 it can be observed that there is an expected -20dB rejection in the sub 2GHz band with reference to the 3-6GHz pass band which implies that the radiated spectrum should meet the FCC requirements accordingly. It can be observed from figure 46 that for closely spaced pulses the pulse amplitude is slightly degraded due to ISI at the transmitter. This type of hysteresis is generally unwanted but can be improved by either shortening the pulse or by reducing the DCO oscillation frequency, both of which degrade the over all system power performance. + +Table 7: Performance overview of recent UWB transmitters +|Reference | [^16] | [^46] | [^47] | [^25] | [^48] | [^38] | This Work | +|----|----|----|----|----|----|----|----| +|Technology (nm) | 65 | 90 | 90 | 65 | 65 | 65 | 180 | +|Modulation | Delay | PPM | BPSK | PPM | OOK | PPM | Delay | +|Avg. Power (W) | 660n | 718u | 3.3m | 600u | 217u | 4.36m | 68.9u | +|PRF (Hz) | 1.3M | 16.7M | 100M | 50M | 24M | 15.6M | 10M | +|Energy per bit (J/bit) | 300f | 37p | 33p | 12p | 8.5p | 17p | 890f| +|FCC compliant | No | Yes | Yes | Yes | Yes | Yes | Yes | + +With reference to table 7 it can be noted that the delay modulation generally achieves respectable energy per bit FOMs in comparison to other modulation schemes as the highly energetic pulses are encoded with multiple bits. Note that even though our design was based on a less aggressive \\(180nm\\) process the UWB pulse generator allowed us to achieve comparable performance to designs that were implemented in \\(65nm\\) technologies for which the transistors achieve a transition frequency (\\(F_T\\)) that extends far beyond the UWB bandwidth which is essentially a prerequisite for employing the piece-wise reconstruction of analytically optimal wavelets. + +The two figures 47 & 48 show the full custom layout that was designed for the proposed UWB transceiver. The actual transistor level layout of transmitter and receiver combined occupy approximately $100\mu m$ by $200\mu m$ with a separate self calibrated DCO for each section. The overall area is increased by 300% due to the on-chip inductor that was integrated for the UWB pulse generator. The figure 48 also shows a large array of decoupling capacitors (in yellow) that remove noise from the supply pads that may influence the DCO operation and introduce additional phase noise. + +{{< figure src="/images/msc-thesis/die1.png" title="Figure 47: Detail of the Full custom Digital layout of UWB, counter clockwise, TX [DCO(red), Delay Modulator(l. blue), UWB Pulse Generator(orange)] & UWB RX [DCO(purple), Demodulator(green), DLL(yellow), RF Energy detector(d. blue)]" width="500" >}} + +{{< figure src="/images/msc-thesis/die2.png" title="Figure 48: Layout sent for tape out illustrating the guard-ring (blue), RF pads (red), Integrated Inductor (green), and UWB TX/RX (green)." width="500" >}} + +# 22 Conclusion + +This thesis has addressed the design considerations of an implantable biotelemetry system with respect system level optimizations and presented the circuit level innovation that focused on optimizing power requirements. + +During the development of the forward link in particular the modulation techniques of contemporary literature were evaluated and, with respect to the projected system requirements, BPSK modulation was found to be the most promising. This was illustrated by the fact that BPSK modulation minimizes the off-chip components and by employing the proposed modulation scheme relatively high bit rates were achieved without degrading the overall power transfer efficiency of the forward link. Moreover, the efficiency achieved illustrates that the class-E amplifier operation shows a good synergy with the BPSK modulation mechanism without the need to supply modulation techniques or additional filtering components. + +Since UWB application for biomedical implants is a relatively new and emerging field a significant amount of effort was put toward developing a scalable delay encoding system that could give way for systems that maximize efficiency FOMs like sub 100fJ energy dissipation per bit transferred. The presented work allows numerous bits to reliably be encoded into a single energetic pulse with a good control over how robust the encoding scheme is towards phase noise as only one element is required to be tuned. The delay modulator presented here is for that reason integrated with a self-calibration frequency locked loop that keeps chip area to a minimum. A conservative estimate bit error rates due to channel induced AWG noise was also presented to given insight to how higher order delay encoding effects the transmission of data. With the theoretical basis covered, circuit specific elements were developed such as a widely tunable digital oscillator and a particularly energy efficient UWB pulse generator based off the impulse response of a LC resonator. In extension to the transmitter, an UWB antenna was designed where a significant improvement in the low-frequency group-delay and reflection co-efficient was found if the first resonant mode was degenerated by an asymmetric extension of the ground plane. The antenna was fabricated but fine tuning of the etching process was still required for the EM simulation results to match the measured response at the frequencies above 5GHz. Finally a simple energy detection receiver is developed that will allow testing of the full custom digital layout that was designed for fully integrated the UWB transceiver system. + +# 23 Future Work + +Due to the broad scope telemetry systems there are a wide range of possible future developments that can be considered in extension to what has been presented here. First and foremost it would be important to develop a more standardized receiver that is based on GHz sample acquisition through FPGA and uses a channel estimation adaptive filter to detect the delay encoded words sent by the implanted device. Secondly the UWB antenna needs to go through several process development cycles under a automated fabrication process until the antenna is well characterized. In addition the antenna need to be tuned to match the impedance of the human body right under the skin for maximum radiation efficiency which may even allow for the system to be placed deeper within the body and may be of interest for future work in association to RF powered implants. The final aspect that should be a worthwhile investment lies with developing an integrated rectifier and regulator for the forward transmission link. + +# Refernces: + +[^1]: D.D. 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IEEE International Symposium on, may 2009, pp. 401 --404. +[^48]: H.Miranda and T.Meng, ''A programmable pulse uwb transmitter with 34% energy efficiency for multichannel neuro-recording systems,'' in Custom Integrated Circuits Conference (CICC), 2010 IEEE, sept. 2010, pp. 1 --4. diff --git a/content/publications/2011/implantable-biotelemetry.md_bk b/content/publications/2011/implantable-biotelemetry.md_bk new file mode 100644 index 0000000..e0b17bb --- /dev/null +++ b/content/publications/2011/implantable-biotelemetry.md_bk @@ -0,0 +1,580 @@ +--- +title: "Implantable Biotelemetry" +date: 2012-09-13T15:26:46+01:00 +draft: false +toc: true +type: posts +math: true +tags: + - chapter + - wireless + - CMOS + - biomedical + - implants +--- + +Supervised by: Dr Timothy G. Constandinou + +A Thesis submitted in fulfilment of requirements for the degree of Master of Science Analogue and Digital Integrated Circuit Design of Imperial College +London, Department of Electrical and Electronic Engineering. + +# Introduction + +Recent developments in the field of neuroscience and health monitoring have identified the need for biotelemetry systems based around a ultra efficient power standard to allow for next generation biomedical implants and distributed en-vivo sensory networks. The work presented here engages the design of the biotelemetry forward and reverse links with a top down perspective exploring the loss mechanics and inefficiencies of concern. This development has led to the design of an optimized class-E based inductive link that includes a improved modulation scheme specific to the operation of the power amplifier as well as a integrated low complexity BPSK demodulator. In addition a frame work was developed around a scalable UWB delay modulation scheme that improves transmitter efficiency as well as circuit level designs for a widely tuneable digital oscillator and a particularly energy efficient UWB pulse generator based off the impulse response of a LC resonator. In extension an UWB antenna is designed with significant improvements in the low-frequency group-delay and reflection co-efficient and a simple energy detection receiver is developed that will allow testing of the full custom digital layout that is designed for fully integrated the UWB transceiver system in 0.18 um CMOS technology. The presented forward link achieves achieve a power transmission efficiency of 46% and 34% while transmitting 250 kb/s. The UWB transmitter consumed 68.9 uW of power for a PRF of 10 MHz that corresponds to a data rate of 77.5 Mb/s. + +## Motivation + +It has been slightly over 100 years since the advent of the worldā€™s first ā€˜transistorā€™ and even more now than a decade ago, revolution has almost become synonymous with the advancement of the microelectronics industry with impacts that change the very backbone of society. The revolution of the last decade surely belonged to that of mobile devices industry which experienced an increase in user end data demand by over a hundred fold. On the other end of the spectrum however this surge of wireless connectivity of the past decade has synergized and inspired a new foundation of ideas for biomedical systems. + +These novel systems are based around digitizing the medical diagnosis and treatment trough wireless en-vivo sensory networks for true personalized medicine. By employing electronic implants that have demonstrated incredible potential due to the dense functionality of CMOS technology, the implantable system on chip have shown potential for restoring vision, treating paralysis, severe epilepsy and Parkinsonā€™s disease \cite{1258173}. In addition to applications for novel heath monitoring systems and home-stay medication, bio-telemetry links to implanted devices have enabled the simultaneous study of several hundreds of functioning neurons in a localized area through multi electrode arrays (MEAs). These studies have given crucial insight to behavioural models of the brain for fields such as neuroscience. Recent advances have allowed patients with a spinal impairment to interact with the world through a brain machine interface bringing society closer to visions such as J. C. R. Lickliderā€™s Man-Computer Symbiosis. + +Although the idea of wireless powering of implanted devices has been around since the early 1960s for long term artificial cardiac pacemakers, the focus of current generation bio-telemetry systems has shifted from a functional orientation to building a framework for reliability and performance directed at commercial applications. As a result of new applications finding their way to employing bio-telemetry links where there are a net set challenges associated with handling the transmission of substantial data rates. The more recent neural recording system-on-chip (SOC) in particular has presented very challenging power requirements for the radio frequency (RF) transmitter driven by the restriction on heat dissipation in order to prevent cell damage. As the demand for number of simultaneously neurons recorded exponentially increases every year, a significant amount of interest has been directed at finding more efficient alternatives for transmitting data out of the implant wirelessly and exploiting specialized encryption algorithms that reduce data rate requirements such as inter-spike-interval figures & spike-feature extraction \cite{5709586}. + +In similitude to the miniaturization principle of microelectronics, biomedical system miniaturization is also seen as an important merit that improves the comfort of the subject. Consequently the size of radiating elements inherent to the telemetry system is also an important topic for consideration that with recent demonstrations has brought to light the viability of power and data transmission via GHz radiation and may change bio-telemetry to a more specialized RFID tag based medical system in the future. + +This thesis presents various system level reductions and efficiency optimizations on both the forward transmission link, from the external system towards the implant, as well as the reverse transmission link, from the implant to the external system. The overall focus revolves around presenting scalable topologies that may allow significant improvements in power consumption of the overhead transmission components which is key in enabling future neural studies and ultra-low power telemetry systems that can be incorporated with RF energy harvesting technologies to give way for next generation biomedical implants based on multi-element sensory networks. All schematic designs presented in this document are based on a 0.18 um CMOS technology using a 1.2 V supply. Circuit level simulations were carried out using Cadence IC5.1.41 with foundry provided PSP models. 2D & 3D electromagnetic simulations were carried out using the CST MICROWAVE STUDIO package. + +## Contributions + +The main contribution presented by this thesis are outlined below + - A complete wireless power transmission link trough coupled coil that achieves a net 45% efficiency with the measured coil characteristics as well study on the trade offs of circular and rectangular coil geometries. + - With the developed class E power amplifier an energy efficient BPSK modulation technique is introduced that not require additional supply modulation techniques in addition to a low power BPSK demodulator that consumes 1.5 uW from the unregulated supply. + - Framework for the UWB delay modulation scheme with conservative estimated on BER values and a scalable architecture for implementation. + - Complete UWB transceiver architecture is developed that transmits data at 890 fj/bit for which a full custom digital layout is designed that occupies 200 um by 300 um. + - Miniaturized UWB antenna design that occupies 1.3 cmĀ² and achieves -12 dB reflection coefficient and sub 50 ps group delay over a bandwidth of 4GHz. + +# Background + +The neural sensory implants of interest is generally located in a vital location such as under the skull and characteristically needs to process large aggregates of data as a multitude of neurons are recorded simultaneously for prolonged periods of time. As a result it is particularly challenging to power the implant as monthly operations to replace a battery can severely endanger the subject to infection. Moreover power requirements of several milliwatt would require a large battery. The inductive link in principle allows for a relatively efficient transmission of power without puncturing the skin while giving room for data transmission. + +The overall design of telemetry systems pertains to the field of radio frequency electronic circuit design with the inclusion of a few essential aspects from power electronics. The biomedical telemetry application however tends to relax the high frequency requirements and focus more on efficient power induction that is more suitable below the 100 MHz frequency range for maximizing power gain \cite{5690847}. Although elaborate antenna systems are still designed to allow for full system-on-chip (SOC) integration the trend towards ubiquitous adoption of integrated UWB transmitters in implants seems to have given a different spin on the RF design aspect. As most bio-telemetry communication links are enabled trough near field coupling there is little gained for high antenna directivity and un-optimized RF coils have been demonstrated sufficient for UWB trough-skin boundary transmission \cite{60956}. Moreover design theory behind UWB is more based on time-domain analysis aimed at minimizing pulse distortion where the traditional harmonic frequency analysis fails to give sufficient insight. + +In this chapter, a review of the various system level topologies that have been used in recent bio-telemetry systems is presented by evaluating the strengths and weaknesses of each design methodology. In extension, a design methodology is briefly presented for the class-E power amplifier that is ubiquitous in inductively coupled power links. In addition, an introduction to UWB technology is presented together with a review of state-of-the-art neural interface systems to project our system requirements and topology. + +## Bio-Telemetry Schemes + +Abstractly speaking, modern telemetry systems can be seen as a 3-channel system. As illustrated in figure 1 these channels correspond to power transmission, forward data transmission, and reverse data transmission. Although 3-channel systems have been reported where each channel is optimized for a single function in terms of carrier frequency and coil/antenna designs the component count is very high. In accordance to the characteristic of the reverse link where a fast bit rate is generally desired, the reverse link is often designed with explicit RF considerations by introducing a far field antenna but it has been demonstrated that single loop coils have considerable potential for near field coupling of RF radiation through the skin \cite{4353634}. The power transmission is generally done through inductive coupling at a frequency where the Q-factor of the coils is maximized and losses from the environment are kept to a minimum \cite{5626705}. The forward link may very similarly be designed trough inductive coupling but a higher carrier frequency is preferred to allow for more substantial data rates while trading off losses induced by the coils which have been shown to dominate over tissue absorption for frequencies above 100 KHz \cite{4502849}. + +{{< figure src="/images/msc-thesis/s1.png" title="Figure 1: Generalized system architecture of a bi-directional telemetry system for medical implants." width="500" >}} + +Contemporary implant systems have mainly focused on improving the system by choosing the right modulation techniques that allow two channels to by combined into one while still achieving similar performance and there by significantly reducing the number of off chip components on the implant side. In some sense this also relaxes the inter-channel interference as the as the interaction between power forward data transmission, for example, is modelled much more explicitly when combined without interference being prone to variations in the coupling coefficients. + +The simplest implementation for data modulation is amplitude modulation, ASK, of power wave form, where the DC-DC regulator driving the supply of the PA is directly adjusted according to a binary bit stream. However a supply regulation control loop is generally implemented on a system level that fixes the average induced power such that the supply at the implant side maintains a stable voltage. This control loop is rather essential as the coils may misalign or move during operation such that the supply must be recalibrated to avoid component damage or injuries due to overheating hence it is not desirable to introduce modulation noise directly into the control loop. + +The alternative to ASK is FSK or PSK which allow for much faster data rates due to the fact that the detection of the phase/frequency shift is not limited by the relaxation time of the resonant pair at the implant side and since the Q-factors of the inductors is desirably large to minimize losses this response time limits modulation speeds \cite{1364109}. FSK generally doubles the number of resonant components required for power transmission to be efficient at both frequencies and may be considered undesirable but, unlike ASK and PSK, modulation does not degrade the power transmission efficiency. A binary phase shift keying can achieve faster uplink data rates than ASK without the need of additional passives but as will be discussed in chapter 3 the resonant modes of the two phase states are complementary to one another such that during phase transition a significant amount of power lost which results in the degradation in transmission efficiency when data is being transmitted trough the link. Technically speaking, inefficiency during modulation is not a major concern as data sent through the forward link is primarily used during system set up and remains inactive for the majority of the implantā€™s lifetime but it requires additional consideration to avoid system failure during the transmission of large amount of calibration data. + +More recently the reverse link has also been integrated into the power transmission channel as well by using Load Shift Keying (LSK). This modulation technique is based on the fact that the current drained from the secondary power coil L2 is coupled to the total power drained from the power amplifier. A common implementation of this illustrated in figure 2 where a simple transistor driven by a OOK modulated data stream pulses a short circuit current from L2 which can be detected at the primary power coil. Note that the PA can still be modulated with the forward link data stream. This approach introduces a significant amount of simplicity into the design as power and bi-directional data is transmitted through a single coil potentially eliminating all off-chip components. In addition power hungry driver circuitry required for driving the antenna/coil of the reverse link has also been eliminated. The drawback naturally lies with the fact that the two data channels interfere with one another more severely than with separate coils regardless of the modulation schemes and moreover all data rates are limited by the bandwidth the inductive link. In addition, a significant amount of strain is put on the requirements of the on-chip supply regulator as the average power induced from the coil is continuously being modulated with higher frequency components from the OOK switching characteristic and may require the high-performance analogue instrumentation components to have differential architectures that require more power and area. + +{{< figure src="/images/msc-thesis/s2.png" title="Figure 2: LSK based telemetry system architecture." width="500" >}} + +## Power Amplifiers for Biomedical Applications + +A quintessential aspect of power induction is minimizing losses at all stages of the power transmission link where the power amplifier used to be at the centre of attention but with the introduction of switch mode power amplifiers the near lossless operation has now become standard for MHz PA applications. The more classical load driving techniques that use class B or class C modes of operation made achieving over 70\% efficiency with a varying load such as an implant challenging due to the matching requirements. Switch mode power amplifiers generally refer to amplifier topologies where the main driving transistor is severely over driven to the extent that the output is far into the non-linear domain by clipping effects such that the transistor can essentially be treated as an ideal switch. The basis of lossless switch mode operation lies with making sure the power transistor does not dissipate power and disregarding how nonlinear the intermediate waveforms are as long as a high-Q LC components are used to terminate all unwanted harmonics an ideal efficiency is expected at the load as all the sources of loss are negated. Since the switch mode structure inherently requires a LC pair it is ideal for driving an inductive load as the coil can be absorbed into the network without additional design considerations. + +In order to gain further insight to the operation of switch mode amplifiers we shall present a time domain analysis of the switch mode Class E amplifier topology which allows us to mitigate nearly all losses by absorbing the power transistor paracitics into the network. + +{{< figure src="/images/msc-thesis/pa1.png" title="Figure 3: Detailed Class-E PA schematic and the inductive link." width="500" >}} + +The topology illustrated in figure 3 shows a power transistor biased by a choke inductor driving the primary coil which is coupled to the secondary coil that drives a half-wave rectifier. It is assumed that the DC load, coil Q-factor, and coil inductance is known for this analysis as well as \\( C_{L2} \\) being chosen according to the required switching frequency such that it forms a resonant tank with \\( L_2 \\). The actual Class-E operation is derived trough the biasing condition of the transistor with a over-driven digital input which allows the transistor to be approximated by an ideal switch. More over it can be assumed that the current driving the primary & secondary coils is purely sinusoidal as the \\( L_1 C_{L1} \\) tank is used to filter out non linearities introduced by the switching operation of the transistors. Before going into analytical details, the overall circuit needs to be reduced to a simple PA structure driving a single complex load. Note that the effective AC load that the rectifier presents to the secondary coil can be approximated in term of expected voltage drop across the diode bridge and the DC load resistor, that is; + +$$ R_{AC} = \frac{1}{2} \frac{(V_{Load} + V_{Diode})^2}{P_{Load} P_{Diode}} || R_{Q2} $$ + +Now, using simple circuit techniques the circuit can be further reduced at the resonant switching frequency \\( \omega_s = (C_{L2} \cdot L_2 )^{-1/2} \\) where the resonant tank at the secondary coil provides the largest reduction in coil losses \cite{861917}. + +{{< figure src="/images/msc-thesis/pa2.png" title="Figure 4a: Circuit schematic illustrating circuit reductions." width="500" >}} +{{< figure src="/images/msc-thesis/pa3.png" title="Figure 4b: Schematic of the reduced circuit representing a Class-E PA with inductive load." width="500" >}} + +Note that the series resistance of \\( L_1 \\) may directly be absorbed by the effective real load \\( R_{EL} \\) and the series resistance of \\( L_2 \\) is absorbed trough equivalent loss of the unloaded Q-factor corresponding to the resonant \\( L_2 C_{L2} \\) tank. Formally, it has been assumed that the ac current observed at the resistive load purely sinusoidal and expressed as follows; + +$$ i_{R}(\theta) = I_{rf} \cdot cos( \omega_s t ) = m I_{dc} \cdot cos( \theta ) $$ + +Where m is the ratio between \\( I_{rf} \\) and \\( I_{dc} \\) and \\( \omega_s t \)) is normalized to \\( \theta \\) as the system is periodic over \\( T = 2\pi \backslash \omega_s \\). Furthermore, let the switch be closed for some arbitrary reference frame defined by \\( -a_1 \\) and \\( a_2 \\) centred around 0, such that; + +$$ i_{sw} = \begin{cases} I_{dc} \left[1+m\cdot cos( \theta ) \right], & \mbox{for } -a_1 \textless \theta \textless a_2 \\ 0, & \mbox{ otherwise} \end{cases} $$ + +Note that the parameter $m$ may be found be evaluating the charge conservation at the node $V_d$ of the capacitor \\( C_{ds} \\) by; + +$$ I_{dc} = \frac{I_{dc}}{2\pi} \int \limits_{-a_1}^{a_2} \left[1+m\cdot cos( \theta ) \right] d\theta $$ + +Similarly by integration the at the node \\( V_d \\) is given by; + +$$ v_d (\theta) = \begin{cases} 0 , & \mbox{for } -a_1 \textless \theta \textless a_2 \\ \frac{I_{dc}}{\omega C_{ds}} [ \theta - m \cdot sin(\theta) - a_2 - m \cdot sin ( a_2 ) ], & \mbox{ otherwise} \end{cases} $$ + +Given these waveforms one may perform a transform integral to find the power of the fundamental quadrature components which is expected to drive the load with the sinusoidal current \\( I_{rf} \\). + +$$ V_{di} = \frac{I_{dc}}{\pi \cdot \omega C_{ds}} \cdot \frac{1}{2m} [ m \cdot sin^2 ( a_1 ) - m \cdot sin^2 (a_2) + 2 \cdot cos^2 ( a_1 ) - 2 \cdot cos^2 ( a_2 )] $$ + +$$ V_{dq} = \frac{m \cdot I_{dc}}{2 \pi \cdot \omega C_{ds}} \left[ m \left( sin^2 ( a_1 ) + sin^2 (a_2) \right) + \frac{ sin (2 a_1 ) - sin (2 a_2 ) }{2} + 2 \cdot cos ( a_1 ) sin ( a_2 ) \right] $$ + +With these components the phasor at the \\( V_d \\) side of \\( C_{L1} \\) must be match to the phasor at the known load \\( X_L + R_{EL} \\) which specifies the coupling capacitor \\( C_{L1} \\) by impedance matching. + +$$ R_{EL} =\frac{ - V_{di}}{m \cdot I_{dc}} $$ + +$$ C_{L1} =\frac{ V_{dq}}{m \cdot I_{dc}} - X_{L} $$ + +Finally we need to consider the conduction angle of the transistor, that is \\( a_1 + a_2 \\) in degrees. Intuitively, the larger the conduction angle (bounded by a maximum value of 180 degrees) of the transistor the more dynamic current oscillating trough the primary tank of the circuit for a given capacitance \\( C_{ds} \\) but this also results in a very large peak voltage at the drain of the power transistor inducing a significant amount of stress at the pinch-off region in the channel. For high power applications a conduction angle of 110 degrees is generally suggested for trading off driving capability and component lifetime but since bio-telemetry power requirements are small and a direct interface with digital control components is desirable, the PA presented in chapter 3 has a conduction angle of 180 degrees. + +Note that one can also extract the DC component through using a transform integral which illustrates explicitly the linear scaling associated with the supply voltage and current load at the inductor. This characteristic is particularly useful for fine tuning the final PA configuration as it is initially difficult to specify the exact waveform at the rectifier, hence minimizing the power dissipated by the diodes remains challenging from the first cut design but is done at ease with simulation support. + +## Ultra Wide Band Technology + +The UWB system is historically based on the spark gap transmitters developed by Marconi in the 1900s \cite{marconi}. Although there was potential for ground breaking data rates, the ability to control the UWB spectrum at the time was still in its infancy and made inter channel and multi user interference a serious problem. This ultimately resulted in the disregard for wide band communication in favour for the narrowband technology that was easier to regulate with respect to multiple end-users. The more recent 3.1 GHz to 10.6 GHz spectrum allocation for UWB applications that occupy at least 500 MHz by the Federal Communications Commission (FCC) of United States in 2002 has sparked new interests in the field as commercial use is now permitted with a limited power spectral density of -41.3 dBm/MHz \cite{RFCC}. + +The recent developments in ultra-wideband (UWB) technology have made a significant impact on a broad range of applications because it presents a set of relatively unique advantages: very short duty cycles, low power consumption and simple architectures which are ideal for modern cost efficient SOC miniaturizations that are often the focus of state-of-the-art research projects. In this respect, UWB has promised phenomenal performance for short range wireless channels allowing up to 100Mb/s data rates under very strict sub-mili watt power budgets with all-digital transmitter architectures that are much more robust in performance than their analogue wave-mixing counterpart that can often not be integrated on the same chip due to substrate interference issues from other system components. + +{{< figure src="/images/msc-thesis/spec.png" title="Illustration of the spectral characteristics for the three main classes of communication technologies and the associated modulation schemes." width="500" >}} + +The foundation of UWB systems based around the characteristic low spectral density that results from very short pulses of energy but embody a very wide signal bandwidth. This characteristic allows the transmission of a signal with spectral energy distributed below the noise floor eliminating the chance of interference with coherent narrowband systems. The basis on which UWB is assured to attain the phenomenal bit rates suggested earlier comes from the well-known Shannon-Nyquist criterion that dictates the maximum channel capacity, $C$, which can be achieved with arbitrarily small but nonzero probability of error and is given by \cite{BKSS};\\ + +$$ C = BW \cdot log_2 \left( 1 + \frac{E_{signal}}{E_{noise}} \right) $$ + +Where \\( BW \\), \\( E_{signal} \\), \\( E_{noise} \\) are the channel bandwidth, received in-band signal energy, received in-band noise energy respectively. Recognizing that SNR, \\( E_{signal} \\) / \\( E_{noise} \\) scales almost linearly with the total system power on both the transmitter and receiver side we observe that improving SNR by dissipating more power will, as disappointing as it is for high SNR environments such as nearfield biotelemetry, only improve the channel capacity in logarithmic fashion. However with a given bandwidth of several GHz we can still assure ourselves a Mb/s bit rate even with poor SNR ratios due to ultra low power transmitter operation from the linear dependency of bandwidth. + +Some of the most significant developments in this field lie with the fully integrated CMOS pulse shapers that adhere to the FCC mask regulations \cite{1363659}. Pulse shapers not pertaining to the field of biomedical implants generally quote the energy dissipated per pulse FOM which ranges from 2 nJ/pulse to some of the more recent work that nearly achieves 4 pJ/pulse \cite{4253320}. There have been several publication have proposed using a UWB reverse link data transmission for biomedical telemetry with much success in terms of low power operation and have achieved 900 fJ/pulse but did not present spectral compliance\cite{5986090}. + +There are three performance metrics of the UWB pulse that are of interest for commercial applications as they allow complete specification of the signal to noise and interference ratios for linear receivers \cite{474590}. These three metrics correspond to spectral efficiency, out-of-band emissions, and time-bandwidth product \cite{1489046}. + +The first of which being the most intuitive, that is the spectral efficiency, which indicates how efficiently the designated spectrum is used in terms of how well all the radiated energy is confined within the 10dB ultra-wide bandwidth. This is expressed as; + +$$ \eta_{ch} = \frac{E_{ch}}{BW_{-10dB} \cdot max ( PSD_{W / MHz})} $$ + +Where the total in band spectral energy, \\( E_{ch} \\), is given by + +$$ E_{ch} = \frac{1}{2 \pi} \int_{BW_{-10dB}} PSD ( \omega ) d\omega $$ + +The second figure of merit for UWB pulses evaluates the normalized amount of spurious spectral energy is generated by the pulse. That is; + +$$ \eta_{0} = \frac{E_{tot} - E_{ch}}{E_{ch}} $$ + +Where the total radiated energy, \\( E_{tot} \\), is given by the time-domain integral + +$$ E_{tot} = \int^{\infty}_{-\infty} p(t)^2 dt $$ + +Finally, the time-bandwidth product primarily indicates the utility of the pulse in terms of being able to carry information. Consider for example the Sinc function which precisely has 0% out of band emissions however its time domain square power is unbounded indicated by the divergent integral for \\( d^2 \\). This implies that modulation based on a ideal Sinc wavelet is non-realizable by a causal system. The time-bandwidth product being related to the standard deviation in the spectral intensity and time domain intensity which is formulated as follows; + +$$ D^2 = \frac{1}{2 \pi \cdot E_s} \int^{\infty}_{-\infty} \omega^2 \cdot | PSD(\omega)|^2 d \omega $$ + +Where the total radiated spectral energy, \\( E_{s} \\), is given by the frequency-domain integral: + +$$ E_s = \frac{1}{2\pi} \int^{\infty}_{-\infty} | PSD(\omega)|^2 d \omega $$ + +$$ d^2 = \frac{1}{E_{tot}} \int^{\infty}_{-\infty} t^2 \cdot | f(t) |^2 dt $$ + +Such that the time-bandwidth product is summarized as; + +$$ B_{t \omega} = D \cdot d $$ + +\begin{table}[h!] +\begin{center} +\begin{tabular}{l c c c} + & Spectral Efficiency & Out-of-Band Emissions & Time-BW Product\\ +\hline +Sinc & 100\% & 0\% & $\infty$ \\ +Square & 60\% & 12.8\% & $\infty$ \\ +$2^{nd}$ order & 59.2\% & $2.8\%$ & 0.55 \\ +Root-Raised cosine & 84.6\% & $0.4\%$ & 0.85 \\ +Gaussian & 56.5\% & $3.3\%$ & 0.50 \\ +Tanh & $58.4\%$ & $2.7\%$ & 0.53 \\ +\end{tabular} +\end{center} +\caption{Summary of the UWB FOM performance for different classes of analytic pulses\cite{thsis}.} +\ context.TABLE: 1 +\end{table} + + +A significant amount of progress has already been made towards to maximizing these figures of merit in a more general UWB framework by means of photonics and microwave systems \cite{4427280}. Only a select few of these advances are fully integrated systems and since compact integrability is the strict requirement for the implant side system there is a still lot of room for improvement for current implant-compatible UWB transceivers. + +## UWB Pulse Generation + +Fully integrated UWB technology is a relatively recent breakthrough, as previous pulse generation systems were primarily based on step recovery and tunnel diodes that under pulsed excitation produced a very different radiation spectrum that carrier based modulation schemes \cite{1449159}. Interestingly the spectrum used for time domain UWB encoding was essentially the modulated impulse response of the diode in operation. Moreover these wideband spectrums were found to allow much more accurate special resolution as well as exhibit some degree of immunity to passive interference \cite{1006348}. The integrated UWB framework bases its pulse generation on a more synthetic approach as the GHz operation of current CMOS technology allows pulse modulation with pulse width far below the average temporal UWB pulse duration which is around 1ns. This in many cases has allowed for piece wise reconstruction of a theoretically derive pulse shape such as those mentioned in table 1. + +{{< figure src="/images/msc-thesis/pl0.png" title="Figure 5a: Spectral representation of the oscillator and modulation waveforms" width="500" >}} +{{< figure src="/images/msc-thesis/pl2.png" title="Figure 5b: Resulting UWB spectrum due to mixing." width="500" >}} + +The most elementary form of fully integrated UWB pulse generation is derived from sub GHz OOK modulation of the GHz oscillator \cite{4526201}. With the frequency domain transforms are illustrated in figure 5, since digital and analogue oscillators are relatively disposable in the FCC UWB band this approach is arguably the most elementary topology that can achieve relatively good performance if the start-up and dead times are well calibrated. The challenging aspect of this topology is it is difficult to both suppress the spurious frequency sidebands as well as the DC component at the output. + +{{< figure src="/images/msc-thesis/pl1.png" title="Figure 6: Illustration of the spectral characteristic of $1^{st}$, $5^{th}$, and $7^{th}$ derivative based gaussian UWB pulses." width="500" >}} + +An alternative approach to generating UWB pulses is based on the spectrum of Gaussian derivatives \cite{1363659}. The family of Gaussian functions are generally well known for their transform limited behaviour and as illustrated in the previous section the Gaussian pulse has the most optimal time bandwidth product out of all analytic reference pulses. Since the actual Gaussian pulse has a strong DC component the derivatives are more realizable in RF systems. + + +$$ g^{(n)}(t) = \frac{d^n}{d t^n} \left( \frac{ A }{ \sqrt{2\pi} \cdot \sigma} \cdot exp \left\{ \frac{-t^2}{2 \sigma^2} \right\} \right) $$ + +$$ |G^{(n)} (\omega) | = A \cdot (\omega)^n \cdot exp \left\{ \frac{-( \omega \cdot \sigma )^2}{2} \right\} $$ + +From the expression of the Gaussian UWB spectrum it can be observed that there are two parameters for spectral tunability that allow fitting under the FCC mask which has been done extensively \cite{5683697}. These two parameters are \\( \sigma \\) and the n which correspond to the temporal pulse width and the derivative order of the Gaussian pulse. By increasing the derivative order of the generated gaussian pulse the overall spectrum is expected to shift to the higher frequencies while simultaneously becoming more concave at the fundamental lobe. By reducing \\( \sigma \\) the spectrum also shifts towards the higher frequency spectrum but in contrast does not affect the fractional bandwidth of the fundamental lobe. The \\( 1^{st} \\), \\( 4^{th} \\), \\( 5^{th} \\), and \\( 7^{th} \\) order Gaussian derivatives have been demonstrated to fit the FCC mask in literature and are their allocation under the FCC mask is illustrated in figure 6 for a relative comparison. + +{{< figure src="/images/msc-thesis/pls1.png" title="Schematic of a simple Gaussian Pulse shaper." width="500" >}} +{{< figure src="/images/msc-thesis/pls2.png" title="Ultra short pulse control signals driving the Gaussian pulse shaper." width="500" >}} +{{< figure src="/images/msc-thesis/pls3.png" title="Piece wise constructed gaussian output pulse fed to the antenna." width="500" >}} + +The integrated circuit implementation of these Gaussian pulse generators are typically fitted by a series of consecutive current pulses feeding into a coupling capacitor toward the antenna load. The pulses are typically under a 100ps long depending on the CMOS technology and by adjusting the driving capability of the MOSFET that is active during a particular phase the amplitude of the corresponding pulse can be adjusted according to the configuration that best fits the target Gaussian model. This topology has demonstrated some of the most energy efficient pulse generators yet, achieving a spectral energy density that nearly matches the FCC mask while consuming more than 4 pJ per pulse. + +In extension to the Gaussian pulse generator topologies, a more generalized structure has also been introduced which focuses on efficiently generating a very board band pulse and filtering out the unwanted spectral components after amplification trough by an RF power amplifier. The filter can be implemented as an integrated on-chip LC filter or using a microwave distributed element filter topology \cite{1606192}. A particularly challenging aspect of this topology is that, although the implementation is the most robust, the filter is required to have a near constant group delay over the pass band to maintain ultra-short pulse durations and avoid pulse distortion. + +{{< figure src="/images/msc-thesis/pls4.png" title="Schematic illustrating a RF PA amplifying a Broad band pulse that is then filtered by a lumped LC network." width="500" >}} +{{< figure src="/images/msc-thesis/pl3.png" title="Illustration showing how the broad band pulse is filtered to meet the FCC mask requirements by using a high pass filter." width="500" >}} + +Overall these three topologies allows for fully integrated systems where often the implementation can be translated into a completely digital architecture where only the transistors driving the RF output need to be considered in analogue terms. This benefit allow for rapid prototyping with very small chip area requirements, complete generation of a UWB transmitter by digital synthesis has also been demonstrated \cite{5615627}. + +## Projecting System Requirements + +Due to the very rich physiological information neural signals carry, an overwhelming amount of interest has been seen in the monitoring of en-vivo neural activity. The neural interface SOCs have since developed impressive set of performance standards that is expected to be maintained for the next few years. By cross-referencing the expected advances in neural recording technology a projection can be made on system requirements in the next 3 years \cite{nat}. + +\begin{table}[h!] +\begin{center} +\begin{tabular}{p{3cm} | c c c c c c} + & 2009 \cite{s5} & 2010 \cite{s7} & 2010 \cite{s9} & 2011 \cite{s2} & 2011 \cite{s10} & 2012 \cite{s11} \\ +\hline +Technology & $0.35\mu m$ & $0.35\mu m$ & $0.35\mu m$ & $0.13\mu m$ & $0.18\mu m$ & $0.13\mu m$ \\ +Channels & 1 & 128 & 128 & 1 & 32 & 96 \\ +max BW (Hz) & 0.3k & 20k & 5k & 11.5k & 12k & 10k \\ +ADC Resolution & 12b & 9b & 8b & 8b & 8b & 10b\\ +ADC Sampling Rate (kS/s) & 1 & 640 & 111 & 10-100 & 125 & 31 \\ +Data Rate per Channel (kb/s) & 12 & 360 & 111 & 100 & 250 & 313 \\ +Power per Channel (W) & 895n & 344u & 190u & 75u & 10u & 68u \\ +Power to Transmitter & - & 1.6mW & - & 400uW & - & - \\ + +\end{tabular} +\end{center} +\caption{Performance overview of the most recent state-of-the-art work on neural interfaces.} +\end{table} + +From the references in table one can observe that although the effective power consumption per channel is steadily decreasing below 100 uW. The sample resolutions and channel bandwidths tend to be slightly over 8 bits and 10 kHz respectively as it appears to be the sweet spot that maximizes SNR with minimal power requirements. Given the expectation to see 512+ channel neural SOCs in the coming 3 years it theoretically corresponds to an uncompressed data rate of 82 Mb/s that needs to be transmitted through the reverse RF link. A similar analysis would estimate the required system power budget to be an optimistic 5 mW system or a more pessimistic 15 mW prototyping system that considers systems that have demonstrated neural recording from animal trails with more significant weighting. + +In summary, this chapter has given way for the target specification given in table 2 with the corresponding topology given by figure 7. + +{{< figure src="/images/msc-thesis/s3.png" title="Figure 7: System level abstraction of the proposed biotelemetry topology." width="500" >}} + + +\begin{table}[h!] +\begin{center} +\begin{tabular}{l | c } +Parameter & Specification \\ +Power Delivered to load & 15mW \\ +Forwardlink Data rate & 300kb/s \\ +Modulation Scheme & BPSK \\ +Reverselink Data rate & 80Mb/s \\ +Power to Transmitter & $\textless100\mu W$ \\ +\end{tabular} +\end{center} +\caption{ Performance requirements for the implantable biotelemetry system.} +\ context.TABLE: 2 +\end{table} + +# Forward Link + +## System Abstraction + +The forward link has been the primary focus of biotelemetry systems as the induction of wireless power into the body is a challenge that has been receiving attention since the 1960s and has continued to develop alongside the innovations made in power electronics and the more recent RFID technology \cite{4502849}. However, regardless of the modulation techniques presented in chapter 2, there is a very inherent limitation that the inductive link imposes in terms of data transmission. + +{{< figure src="/images/msc-thesis/s5.png" title="Figure 8: System block diagram of the forward link channel." width="500" >}} + + +With reference to figure 8, the system of interest here may be abstracted into four separate sections; the power amplifier, the inductive link, the demodulator, and the rectifier. Each of which substantiates a complete technical topic on its own and in association with the technical specifications given. This chapter will focus on first presenting an analytical description of the coil link in order to formulate target figures of merit followed by the employed power amplifier design with the associated simulation results. Techniques that minimize the loss introduced by phase transitions from BPSK modulation will be a very particular consideration that will be made at the end of this chapter together with the corresponding low complexity BSPK demodulator. + +## Inductive Link Design + +{{< figure src="/images/msc-thesis/pa4.png" title="Figure 9: Circuit model of the inductive link driven by an ideal source." width="500" >}} + +With particular focus on maximizing the induced power onto the rectifier load which has be reduced to the ac equivalent \\( R_{AC} \\). With the reduced circuit illustrated in figure 9 one may be able to identify the two loss mechanisms that govern the power transmission transfer function. The first being the reflection coefficient associated with the resistive loading of inductor \\( L_1 \\) due the secondary coil that is in series with the parasitic resistance of the inductor itself \\( R_1 \\). The second loss mechanism abstractly lies with the self-loading of secondary inductor due to the parasitic resistor \\( R_2 \\). Both of these parasitics are directly related to the Q-factor of the two inductive coils used to couple the two systems. In brief, the analytic expression for the efficiency of power induction may be derived at the resonant switching frequency, again that is \\( \omega_s = (C_{L2} \cdot L_2 )^{-1/2} \\), as \cite{sarpes}; + +$$ \eta = \left[ \frac{V_L \cdot I_L}{V_s \cdot I_s} \right] = \frac{R_{eff}}{R_{eff} + R_{1}} \cdot \frac{L_2}{L_2 + R_{2} \cdot R_{AC} \cdot C_{L2}} $$ + +Where the effective impedance seen at the primary coil, \\( R_{eff} \\), is + +$$ R_{eff} = k^2 \cdot \frac{\omega^2 \cdot L_1 \cdot L_2}{R_2 + \frac{L_2}{R_{AC} \cdot C_{L2}}} $$ + +Further expansion will show that this equation may be optimized for a given k in terms of the load \\( R_{AC} \\) with respect to the inductor Q of coils \\( L_1 \\) & \\( L_2 \\). + +$$ R_{AC} \bigg|_{\eta=\eta_{max}} = \frac{\omega_s \cdot L_2}{k} \cdot \sqrt{\frac{R_1 \cdot L_2}{R_2 \cdot L_1}} = \frac{\omega_s \cdot L_2}{k} \cdot \sqrt{\frac{Q_2 }{Q_1}} $$ + +Such that the peak efficiency, \\( \eta_{max} \\) may be expressed as + +$$ \eta_{max} = \frac{k^2 \cdot Q_{L1} \cdot Q_{L2}}{(1+ k \cdot Q_{L1})(1+ k \cdot Q_{L2})} $$ + +The limiting factor associated with the coils is primarily the total chip area hence the coil geometry should maximize the coupling quality factor product per unit area. Previous systems will either opt for a coil integrated on to the PCB which allows improves the ability manufacture the end result or a coil that is implemented by a wrapped linz wire which makes scalable prototyping challenging but provides much better performance in terms of inductor Q-factors \cite{4432391}. PCB integrated inductors tend to be more lossy for a given inductance primarily because of the space requirements on the traces which prevent the dense inductance one may expect from a wire wrapped coil. The majority of published literature tends to prefer using circular geometries as their properties are accurately predicted by analytic formulas, it should be noted however that rectangular coils achieve higher coupling coefficients per unit area. With this in mind, the coils that tested in the laboratory were based on copper wire wrapped rectangular geometries. In analogy to closely space circular coils where it has been demonstrated that the mutual inductance is maximized when the primary and secondary coils have the same geometry we expect the same from the rectangular coils \cite{503178}.\\ + +{{< figure src="/images/msc-thesis/l1.png" title="Circular Coil geometry." width="500" >}} +{{< figure src="/images/msc-thesis/l2.png" title="Square coil geometry." width="500" >}} +{{< figure src="/images/msc-thesis/l3.png" title="In plane view of coils." width="500" >}} + +Using EM simulation tools a simple study was conducted to confirm these findings. Using a single turn circular loop with a diameter normalized to the parameter r and a square loop with the side length also normalized to the parameter r, we studied the behaviour of the coupling coefficient k with respect the out of plane distance, d, from two identical coils and the lateral in plane displacement a. The results illustrated in figure 10 confirmed that, although circular coils achieve better quality factor, the square coils achieve better coupling coefficients implying with reference to equation 23 that square coils achieve higher peak efficiency. + +$$ \frac{Q_{circle}}{Q_{square}} = 1.87 \hspace{10mm} \& \hspace{10mm} \frac{k_{circle}}{k_{square}} = 1.88 $$ + +{{< figure src="/images/msc-thesis/KUPL.png" title="Figure 10: EM simulation results of the coupling coefficient with respect to the in-plane and out-of-plane normalized displacements." width="500" >}} + +In accordance to the above considerations and estimates on the ac load expected to be loading the secondary coil a two coil rectangular link was prototyped. The primary coil and secondary coil were measured in the lab to evaluate the mutual inductance values where the mutual inductance was evaluated through a differential measurement \cite{AGI}. + + +\begin{table}[h!] +\begin{center} +\begin{tabular}{l | c | c} +Parameter & Primary Coil $L_1$ & Secondary Coil $L_2$\\ +\hline +Turns & 29 & 15 \\ +Dimensions (mm) & 12 x 24 & 12 x 24 \\ +Inductance (uH) & 46.59 & 12.67 \\ +$R_s$ ($\Omega$ at 1MHz) & 7.49 & 3.19 \\ +$k_{21}$ * & 0.134\\ +\end{tabular} +\end{center} +\caption{Measured characteristics of the two inductive coils.} +\begin{flushleft} +* measured at coil distance of 10mm\\ +\end{flushleft} +\end{table} + +{{< figure src="/images/msc-thesis/loop.png" title="Photograph of the prototype rectangular coil used for power induction." width="500" >}} + +Given the measured coil characteristics, the Class-E PA was designed in accordance with the method presented in chapter 2. By introducing the simulation models of commercially available components the design was fine tuned to achieve a power transmission efficiency of 46%. The derived system delivers 15mW to a 600 ohm load corresponding to an unregulated supply of 3V. The losses from the primary and secondary contribute to 30% and 14% of the total power dissipation respectively. The off chip rectifier dissipated 8% of the total power which actually correspond to a marginal efficiency of 85%. The remaining 3% is dissipated by the RF choke and the power transistor. Note that a the power transistor in figure 11 is a 2N7000 Fairchild N-Channel Enhancement Mode Field Effect Transistor with a maximum drain voltage rating of 60 V. + +{{< figure src="/images/msc-thesis/pa0.png" title="Figure 11: Detailed circuit schematic of the complete power transmission system with the component names/models annotated." width="500" >}} + +{{< figure src="/images/msc-thesis/power.png" title="Simulation results of the power induction system in operation illustrating a average 46% PTE." width="500" >}} + + +## Switch mode BPSK Modulation + +In one respect the input waveform of the Class E amplifier is no longer trivially related to the waveform driving the load in time domain and strictly speaking the degrees of freedom at the driving transistor are now limited to two states; open circuit, and closed circuit. As a result the dynamic range of this class of amplifier is limited to the unit gain circle on the constellation diagram. This inherently presents a problem for BPSK modulation as the state transitions through the zero crossing as shown in figure 12 which for many amplifier topologies is undesirable due the fact that is strains the dynamic range requirement. In the RF domain regulating the transition behaviour is rather strict as state transitions that lie beyond the capability of the amplifier result in spurious frequency components from distortion that lie outside of the designated frequency band. In the case of biomedical telemetry we shall observe that such a careless transition results a significant amount of loss in the system. To alleviate this problem we shall introduce an intermediate state to allow a smoother transition without introducing additional system complexity. + +{{< figure src="/images/msc-thesis/cnst2.png" title="Figure 12: (left) Standard BPSK constellation diagram. (right) Constellation diagram of the proposed BPSK modulation scheme." width="500" >}} + +Figure 13 shows the simulation results of phase transition of two BPSK modulation techniques, the first in blue being the simple BPSK modulation of a square wave and the second in red being the proposed BPSK modulation of a square wave with an intermediate state. It is obvious that there is a dramatic difference with respect to the voltage waveform seen at the rectifier input. The simple modulation technique not only results in a slow transition but there is no energy induced for a number of cycles which is detrimental to the system PTE $\eta$. The proposed modulation scheme first transitions to $+\pi/2$ for half a cycle before completing the phase shift towards $+\pi$. It is important to note that open circuit state of the RF switch maintains its temporal duration as this is the mechanism that provides harmonic termination to the higher order harmonics that are reflected by the LC tank. + +{{< figure src="/images/msc-thesis/mod_tran.png" title="Figure 13: Simulation results illustrating the gain in average PTE and the destructive interference of the two phase states during the phase transition without the intermediate state." width="500" >}} + +Even with this modulation technique a linear trade off with respect to the carrier frequency and the forward data rate is still to be expected as one cycle for every phase transition fails to induce power. The expected power transfer efficiency, \\( \eta \\), during modulation is asymptotic to and approximated by the following expression. + +$$ E \left[ \eta \right] = \eta_{s} \cdot ( 1 - N \cdot \frac{f_{data}}{f_{carr}} ) $$ + +Where \\( \eta_{s} \\), \(( f_{carr} \\), \\( f_{data} \\) are the un-modulated PTE, carrier frequency, and data rate respectively. N is the model parameter that corresponds to the number of cycles skipped as a result of a phase transition which our fitting estimates to be approximately 1 for the proposed modulation scheme. It is now clear that faster switching frequencies driving the PA will also allow for proportionally faster data rates without having to sacrifice efficiency. + +{{< figure src="/images/msc-thesis/swtmd.png" title="Simulation results of the PTE with respect to different data rates and the fitting parameters of the extracted model." width="500" >}} + +## Integrated BPSK Demodulator + +To reduce overhead, the demodulator illustrated in figure 14 recovers the transmitted data stream is not based on a delay locked loop topology but based on detecting the cycle skipping of phase transitions. Although it is arguable that this type of detection is prone to failure due to coil displacement when the designated patient moves these kind of environmental factors influence the induced voltage waveform in the very low frequency spectrum that typically do not exceed 100 Hz. Hence a high-pass filter behaviour is introduced to the peak voltage detector using the parasitic capacitance and leakage current of the transistor M9. + +{{< figure src="/images/msc-thesis/bdmd.png" title="Figure 14a: Transistor level schematic of the threshold based phase detector." width="500" >}} +{{< figure src="/images/msc-thesis/bddd.png" title="Figure 14b: Digital State machine that detects phase changes in the induced voltage waveform." width="500" >}} + +The remaining operation of the circuit is intuitive, M1 shifts the voltage wave at the input of the rectifier down so that is falls below the supply voltage and the transistors M5-M7 determine & compare the voltage \\( V_{bias} \\) and the peak voltage which is \\( max(V_{in}-V_{thm1} - V_{thm8}) \\). Due to the over driving effects the output is approximately digital in characteristic where \\( V_{clk} \\) is low then \\( V_{in} \\) is larger than \\( V_{bias} \\) and \\( V_{sig} \\) is low when \\( V_{in} \\) larger than the stored peak value. These signals are processed by some simple digital circuitry to detect when \\( V_{in} \\) drops below its peak value by more than one NMOS threshold voltage. The near digital operation of this circuit the power consumption is just under 1.5 uW and simulation results of phase detection is shown below in figure 15. + +{{< figure src="/images/msc-thesis/DBPSK.png" title="Figure 15: Simulation results showing the operation of the threshold based phase detector." width="500" >}} + +## System Summary + +In this chapter a class-E based forward transmission link was presented that couples power and transmits data. To engage the discussion on system design a common framework for coupled coils was presented to formulate a objective that brought forth the efficiency figure of merit. In addition to the schematic specifications of the transmitter, the modulation scheme was considered in detail with respect to the switch mode amplifier by identifying the underlying phase transition inefficiencies. By introducing an intermediate state the power transmission efficiency during modulation was improved an a accurate model describing the trade off between modulation rates and carrier frequency was presented. Finally the a low power BPSK demodulator was proposed. + +# Reverse Link + +The reverse link of the biotelemetry system primarily pertains to the RF communication link that sends large amounts of data acquired in vivo by the sensory instrumentation devices to a receiver external to the body. The focus of this chapter will revolve around how this reverse link achieves a very high data rate with the minimum amount of power consumption, that is minimizing the energy per bit transmitted, and proposing a scalable modulation technique for low power applications. Followed by the design considerations of a digitally calibrated oscillator as well as an energy efficient bi-phasic UWB pulse generator, a UWB antenna design shall be presented with considerations towards near field pulse transmission. Finally a energy detection based UWB receiver topology is proposed for testing purposes. + +{{< figure src="/images/msc-thesis/s4.png" title="System level abstraction of the UWB transceiver." width="500" >}} + +## UWB Pulse Modulation + +Let us first consider the two principle modulation techniques illustrated figure 16 that have been the most successful in UWB communication systems, which are binary phase shift keying (BPSK) and pulse position modulation (PPM). BPSK can be directly associated with the continuous wave modulation techniques and has shown to be a good alternative for pulse modulation that does not distort the output spectrum significantly \cite{947480}. PPM is based on temporal delays and advances of the UWB pulse to modulate the signal. Current PPM systems are based on modulation with reference to a receiver oscillator that is locked through a digital Costas loop equivalent that requires transmitter dead time for synchronization. As current pulse generators consume at least several pJ per pulse we may assume that over 80% of the system's power consumption will be due to the actual output pulse driving the antenna.The interest here lies with encoding a single pulse with multiple bits to maximize efficiency. Simply combining the two modulation techniques is the easy way to boost efficiency but may not be worth the increase in system complexity. + +{{< figure src="/images/msc-thesis/mmd.png" title="Figure 16a: Time-domain representation of BPSK & PPM modulation schemes." width="500" >}} +{{< figure src="/images/msc-thesis/cnst.png" title="Figure 16b: Constellation diagrams of BPSK & PPM modulation schemes illustrating the inherent SNR reduction for PPM." width="500" >}} + +The bottle neck that prevents a scalable system that encodes multiple pulse positions lies with how the temporal delay are generated in contemporary designs. For non-coherent detection systems these delays must be relatively small and accurate to maintain correct detection on the receiver end which if scaled up would result in too much calibration overhead to tune each pulse position. For coherent based UWB receivers the pulses must be orthogonal with respect to the detection window which is even more challenging for detecting multiple phase states. Instead if the delay of a fixed period is used from a calibrated digital oscillator (DCO) and multiple pulses are allowed within a short reference frame, the scaling of the position encoding mechanism can be improved in a fundamental way while maintaining system simplicity. More importantly, using a DCO allows us to dedicate a lot of resources for fine tuning the delay of a single element where if multiple delay elements need to be used the restricted resources would limit the tuning of the resulting delay and introduce unwanted phase noise. + +{{< figure src="/images/msc-thesis/n1.png" title="Figure 17a: Simple delay encoded pulses with reference to a DCO clock." width="500" >}} +{{< figure src="/images/msc-thesis/n2.png" title="Figure 17b: Pulses encoded by the cascading of two delay symbols in a single data word." width="500" >}} + +As illustrated above in figure 17, the data is essentially encoded in the delay between pulses. More importantly, note that the pulse package is encoded with reference to the first pulse which allows for accurate receiver phase locking. The implications of this type of ā€˜delay encodingā€™ are quite significant. First and foremost the energy detection receiver can now actually be asynchronous negating the need for start-up dead time. Since efficiency improves only by the logarithm of the maximum delay it is not area efficient to encode large delays but by cascading multiple encoded delays after one another bit rate, area, and efficiency can be traded off with a significant amount of flexibility. Moreover by omitting the last pulse of the package a delay of 0 can be encoded for improved efficiency. + +It should also be apparent that this approach has two main draw backs, the first being that it is particularly sensitive to the DCO frequency off sets for long delays that integrate to large amount of phase noise over the signal window. The other drawback is to maintain FCC mask compliance the peak output power of the UWB pulse must be reduced which degrades the signal to noise ratio. On the other hand however this modulation technique can tolerate a temporal equivalent of phase noise equal to half the DCOā€™s period. + +To give further insight to the expected degradation in the bit error rate (BER), let us consider the absolute worst case scenario where the entire word needs to be detected by a linear receiver. That is, each symbol transmitted needs to be detected at the receiver and is subject to the same AWGN from the channel. For simplicity a threshold detection receiver model has been adopted that integrates the incident RF power waveform by self mixing and samples the accumulated energy before resetting the integrator for the next reference window at a period of $T_w$. In addition, let us assume the signal band with is known such that the probability of detecting a pulse, \\( P_{bit} \\), for \\( \frac{E_b}{N_0} \)) < \\( \frac{T_w BW}{2} \\) is given by \cite{474590}; + +$$ P_{bit}=Q\left( \frac{E_b / N_0}{\sqrt{2T_w \cdot BW + 2E_b / N_0}} \right) \hspace{10mm} where \hspace{5mm} Q(x)=\int^{\infty}_x \frac{exp(\frac{-t^2}{2})}{\sqrt{2\pi}} dt $$ + +Here \\( E_b \\) and \\( N_0 \\) denote the energy in the pulse and AWG noise over the integration window \\( T_w \\). In extension the expected value of the BER for this particular modulation scheme may be evaluated by considering the probability of detecting the whole word correctly, the probability of sending that particular word, and the number of bits transmitted per word. For simplicity assume each word is equiprobable, which is sub-optimal source coding but regardless, then for the simple case of non-cascaded delay encoding the BER may be expressed as; + +$$ BER_1 = \frac{1 - \sum\limits_{i=1}^{D_{max}} \left[ \frac{(1-P_{bit})^{i+1}}{D_{max}}\right] }{2+log_2(D_{max})} $$ + +Where \\( D_{max} \\) is the maximum delay encoded by the transmitter. If the BER of a N times cascaded delay system is to be evaluated then the previous expression is simply adjusted in the same regard to recomputing the expected value and the number of bits per word. + +$$ BER_N = \frac{1}{1 + N + \sum\limits_{j=1}^{N} log_2(A_j)} \cdot \left\{ 1 - \frac{1 - \sum\limits_{i=N}^{D_{max}} \left[a_i \cdot (1-P_{bit})^{i+1}\right] } {(\sum\limits_{i=N}^{D_{max}} a_i)} \right\} $$ + +Here the series \\( a_i \\) denoted the number of ways one can encode a word in the cascaded system with \\( i \\) delays, note that for each cascade of delays the minimum number of delays is 1. The series \\( A_j \\) denotes the maximum possible delay ecoded by the \\( j^{th} \\) cascaded delay and N denotes the number of cascaded delays. To find a closed form expression for th series \\( a_i \\) one must consider the problem of sorting i elements in N sets that are constrained to the carnality given by the series \\( A_j \\). For the proposed system where \\( N=2 \\), the series is given by; + +$$ a_i \bigg|_{N=2}= (1+ i) - \sum\limits_{j=1}^{2} \left[ \sum\limits_{k=Aj+1}^{i} 1 \right] $$ + +Where \\( A_j=\{8 , 4\} \\). These results confirm our previous statement that the expected BER worsens as the maximum possible encoded delay is increased but by increasing N this degradation can be alleviated by as the bit rate is increased by N and the N sum over the log maximum delay of each cascaded delay. + +## System Architecture + +The system architecture abstraction illustrated in figure 18 is the proposed integrated UWB transmitter which consists of three main components; DCO, Delay Modulator, and Pulse shaper. Although the previous discussion has pointed out the general purpose of using an on-chip oscillator it should also be noted that such high frequency oscillators can dissipate a significant amount of power. To alleviate the power hungry behaviour of the DCO a feedback loop is introduced into the system that enables very exact duty cycles such that the oscillator is only switched on to generate the required number of delays and is turned off once the delay encoded package is generated saving a significant amount of power as the complete package duration is on average only half the maximum encoded delay for single delay encoded equi-proportional set of words. + +{{< figure src="/images/msc-thesis/mod.png" title="Figure 18: System level abstraction of the UWB transmitter architecture." width="500" >}} + +The proposed system uses a 10 MHz reference input clock generated by an accurate crystal oscillator and will be used to both calibrate the DCO trough a frequency locked loop (FLL) as well as being the reference for the first pulse of the data package that partly acts as a preamble. The delay modulator is essentially a pulse swallow circuit where the decision to swallow a pulse (i.e. introduce a delay) is encoded in a shift register feeding the D flip flop. + +## Digitally Calibrated Oscillator + +The main challenge in designing the DCO lies with the fact the digital oscillators are very prone to variation in the oscillation frequency as a result of variation in supply, process parameters, and layout parasitics/mismatch. The Monte Carlo simulation in figure 19 shows that, if the presented DCO topology were uncalibrated, the oscillation frequency would have a standard deviation of 45MHz which as discussed previously results in large amounts of phase noise at the receiver. To alleviate this problem a two stage calibration mechanism has introduced with a total resolution of 8 bit to assure a large and accurate tunability range of the oscillation centre frequency. The 4 most significant bits calibrate the main capacitive load of the DCO which is a binary weighted Metal-Insulator-Metal capacitive array, with unit capacitance of 5 fF, by connecting an arbitrary combination of capacitors to ground and leaving the rest floating. The 4 least significant bits calibrate the NMOS driving capability of an inverter which inherently allows for tuning at a much more precise scale as the transistors can be well matched without taking up a considerable amount of area with only fractional differences in their size. + +{{< figure src="/images/msc-thesis/MC.png" title="Figure 19: Monte-Carlo simulation result of the uncalibrated Oscillation frequency." width="500" >}} + +The DCO also includes a Frequency Locked Loop (FLL) that during the calibration phase will tune the DCO output frequency to match that of an accurate reference clock. A fully digital implementation was chosen so minimize area and so that the self-calibration loop can be switched off during normal operation. Although Phase Locked Loops (PLLs) are generally preferred for this particular kind of functionality due to their quicker lock-on time, the all-digital FLL in figure 20 surpasses the all-digital PLL in simplicity as no digital loop filter is required. + +The principle of operation of the FLL is based on detecting which clock has a faster rate of rising edges by using a simple set reset latch that is set by reference clock and reset by the DCO clock. If the DCO is resetting the latch more often than the reference lock is setting the latch a pulse is generated at the output of the frequency detector that increments or decrements an 8 bit counter that calibrates the DCO proportionally. Similarly if the latch is set more often than reset a pulse is also generated such that the rate of pulses at the output of the frequency detector is directly equal to the absolute difference in frequency between the reference and DCO clock. The state that persists while these pulses are generated indicates whether the DCO frequency must increase or decrease. Note that the generated DCO clock is divided by a factor of 50 such that the 500 MHz clock can be calibrated with respect to a low cost off the shelf 10 MHz crystal. + +{{< figure src="/images/msc-thesis/dco.png" title="Figure 20: Schematic of the Frequency locked loop used to enable self-calibration of the DCO." width="500" >}} + +Figure 21 Illustrates that the presented DCO exceeds a 3 sigma tunability range with respect to the expected standard deviation in DCO frequency with a resolution of 1.58 MHz which corresponds to oscillation period that is accurate to Ā±4 ps. The DCO consumes an average of 72 uW during continuous operation. + +{{< figure src="/images/msc-thesis/dco_sweep.png" title="Figure 21: Simulation result of the frequency range capability of the DCO." width="500" >}} + +{{< figure src="/images/msc-thesis/step.png" title="Transient simulation illustrating the response of the FLL due to a step decrease in reference frequency." width="500" >}} + +## Bi-phasic UWB Pulse Generator + +In order to satisfy the FCC regulations for UWB communication \cite{RFCC}, two different approaches have been presented in previous literature. One approach is based on modulating the envelope of a RF oscillator output which allows for simultaneous UWB communication in multiple frequency bands \cite{4526201}. The other approach is based on maximizing the spectral efficiency by fitting the UWB pulse shape to a Gaussian derivative that optimally fits the FCC mask by piecewise modulation of multiple current pulses \cite{4982876}. The design proposed here is a hybrid between these two approaches employing a simple all-digital architecture that generates a UWB pulse with improved energy efficiency using an oscillator output shaped by piece wise current pulses. + +The pulse generation techniques presented are has been partly adopted from previous work that used integrated LC components to filter out the unwanted spectrum to meet the FCC mask requirements \cite{5773985}. However instead of dissipating the unwanted spectral energy, a lossy LC resonator is used to recycle the unwanted spectral energy and modulate this to its resonant frequency. Abstractly speaking, the inductor is pulsed with current over 180 ps. This induces energy that is stored in the magnetic field and is gradually dissipated in the load (over 1ns while the LC pair resonates in response to the impulse). This integrated pulse generator designed is based on a 0.18 um CMOS technology using a 1.2 V supply and assuming a 50 ohms termination. + +{{< figure src="/images/msc-thesis/puls.png" title="Figure 22: Schematic Illustration of the Digital pre-shaping. Note that the relative temporal delays are not to scale." width="500" >}} + +The Digital pre-shaper is shown in figure 22. This uses a popular glitch generator to generate 180ps long Gaussian like pulses, which are demultiplexed to two inverter chains to boost the driving capability of the output. It is important to note that these chains have a different output polarity but both output the buffered pulse together with a delayed and inverted pulse, driving the transistors sourcing the inductor with pulsed current (shown in figure 23). The purpose of the delayed pulse is to cancel the DC component generated by the transient impulse response of the lossy LC resonator, by injecting an equal but complementary pulse at the opposite port of the inductor. By driving either the end connected to the load, or the $C_{res}$ end of the inductor first, the polarity of the UWB pulse is well controlled. + +The illustration in figure 22 also shows how a simple shift register can interface the UWB transmitter with a parallel input data stream. With reference to fig, it is interesting to note that since the transistor pairs M1, M4, M2, and M3 are matched in terms of driving capability this particular topology is immune to variation in pulse length which may easily distort the performance of aggressive UWB pulse generators that use multiple glitch generators to shape the pulse. + +{{< figure src="/images/msc-thesis/rf.png" title="Figure 23: Circuit schematic of the RF section (parasitics not shown) - Lres = 4 nH; Cres = 200 fF." width="500" >}} + +Since both the total pulse energy and pulse width (due to ringing) is directly proportional to the Q of the resonator, one must trade off pulse length for amplitude where a higher Q results in longer ringing but also larger peak to peak values. In this particular case, a single layer 6-turn 8-sided spiral 4 nH inductor with poly-silicon ground plane was used with the dimensions 4 um, 2.8 um, 96 um corresponding to the trace width, trace spacing, and outer radius respectively. The pulse energy was tuned to fall below 5% within 1ns to avoid inter symbol interference corresponding to the resonant capacitance of 200 fF. + +{{< figure src="/images/msc-thesis/TRAN.png" title="Figure 24a: Simulation Results of the bi-phase UWB temporal response illustrating a 350 mVpp Amplitude." width="500" >}} +{{< figure src="/images/msc-thesis/DFT.png" title="Figure 24b: Simulated PSD of the designed UWB pulse & the indoor UWB FCC mask as annotated." width="500" >}} + +It can be observed in figure 24 that the current output spectrum does not meet the sub 2 GHz FCC mask specifications and thus future work based on this UWB pulse generator will filter this particular spectrum using the geometric resonance of the UWB antenna which can efficiently implement a high Q high pass filter and has already been demonstrated feasible \cite{1606192}. On that note, this system consumes 1.65 pJ/pulse, which corresponds to an average of 16.5 uW with a pulse rate frequency of 10 MHz and has a competitive edge over many previous publications in terms of the energy per pulse figure of merit shown in table. + +\begin{table}[h!] +\centering +\begin{tabular}{c|c|c|c} +Reference & Output $V_{pp}$ & Pulse width/BW & Power (pJ/pulse)\\ +\hline +\cite{1363659} & 700mV & 0.38ns/7.2GHz & 15.4\\ +\cite{4405600} & 600mV & 0.4ns/7.5GHz & 26.4 \\ +\cite{4253320} & 500mV & 0.8ns/2GHz & 4.7 \\ +\cite{4295131} & 180mV & 3.5ns/0.5GHz & 18\\ +\cite{4982876} & 165-710 mV & 2.4ns/300MHz & 17.5 \\ +This Work & 350mV & 1ns*/4GHz & 1.65\\ +\end{tabular} +\begin{flushleft} +\caption{ Performance summary and comparison of UWB transmitter. } +*time taken for pulse energy to fall below 5\%.\\ +\end{flushleft} +\end{table} + +## Ultra-Wide-Band Antenna + +With fresh insights from the UWB pulse shaper presented in the previous section, there are a number of observations that can be made with respect to the requirements of the antenna with respect to bandwidth and input impedance. In particular, we require a 22dB rejection of the sub 1.6GHz band with respect to the pass band and a 50 ohm impedance across the 3-7GHz band that needs to be radiated out to the environment. The remaining standard requirements of an antenna are primarily associated with the directionality and gain of the radiation pattern which for the biotelemetry system depend on the orientation of the two antennas which is illustrated below. The antennas will essentially be coupled in the near field which is not ideal in terms of radiation efficiency but sufficient for simple SOC applications where the receiver end is not limited as strictly by power requirements such that additional gain in the RF band can be attained. + +{{< figure src="/images/msc-thesis/chnl.png" title="Illustration showing orientation of the antennas with reference to the inductive coils and skin barrier." width="500" >}} + +A planar antenna that is directional with one lobe tangential to the plane would be the most desirable for the proposed antenna orientation but the compactness of the antenna is a far more valued requirement. Note that this particular orientation avoids capacitive loading on the antenna where current densities at the highest and allows the UWB antennas to be conveniently distanced from one another without compromising the implant size. Another challenging antenna property that is required is that the radiation pattern must be stable across the ultra-wide band and more importantly that the radiated energy maintains a constant group delay at the receiver side to avoid excessive distortion of the UWB pulse. The last requirement is ultimately the most challenging as it requires the single mode of radiation retained over a bandwidth of several GHz for simple electrically small antenna structures. + +A comment should be made with regard to the fundamental limitation of electrically small dipole antennas, as it can be shown that the fractional bandwidth of the antenna explicitly inverse to the quality factor of the antenna and hence it is theoretically possible to achieve UWB specification using these structures. However, the quality factor is directly related to the radiation efficiency by the Chu-Harrington limitations which inhibits the use of compact quarter wavelength dipole structures \cite{1219625}. Instead a class of ā€œfatā€ monopole antennas has been introduced that provide a similar foundation for simple geometric structures that show adequate performance for UWB applications. The success of these structures lie with the many overlapping resonant modes that the geometries exhibit and hence appear to resonate over a large bandwidth. The most successful planar structure according to the demonstrated radiation efficiencies presented in literature has been the elliptical monopole off which we have based our primitive antenna design as well \cite{1421157}. + +{{< figure src="/images/msc-thesis/geo.png" title="Figure 25a: Illustration of the UWB antenna geometric variables." width="500" >}} +{{< figure src="/images/msc-thesis/ant.jpg" title="Figure 25b: Photo of the exposed prototype UWB antenna. Note the darker grey rectangle indicates high dielectric substrate on both sides of the metallization." width="500" >}} + +In addition to the matching requirements of the antenna, it is highly desirable if the antenna is scaled down to the smallest possible size. UWB antennas from literature are primarily based on off the self FR4 substrate have a radiating patch is on the order of $16 cm^2$. In order to scale down the antenna to around the $1cm^2$ area a high dielectric substrate, RO3010, was used. More specifically, the elliptic lobe that is used to match the $50 \Omega$ co-planar transmission line is enclosed by the high dielectric substrate on both sides of the metallization leaving the radiating gap between the ground plane and the ellipse partly exposed on one face in order to avoid deteriorating the radiation efficiency. + +{{< figure src="/images/msc-thesis/PROT.png" title="Figure 26: EM simulation results illustrating the degeneration of the first resonant mode to improve performance." width="500" >}} + +The basic geometry in figure 25 illustrates the addition of a elliptic lobe that is placed protruding from the ground plane towards the elliptic patch which was found to give the antenna the desired in-plane directivity of 3dB and improved wide band matching. The ground plane extension generally reduced the Q-factor of the first mode such that its resonance overlaps more continuously with the second mode as may be observed in figure 26 by the gradual improvement in the reflection coefficient as the lobe is extended towards the antenna. + +{{< figure src="/images/msc-thesis/A1.png" title="Figure 27: EM simulation of the \\( S_{11} \\) reflection coefficient for the finalized UWB antenna geometry." width="500" >}} +{{< figure src="/images/msc-thesis/TRNSM.png" title="Figure 28: Preliminary side-by-side \\( S_{21} \\) transmission characteristic." width="500" >}} + +The preliminary EM simulation results in figure 27 show adequate performance over the 3-7 GHz band in terms of a reflection coefficient below -10dB with a constant group delay that only varies by several tens of degrees. Figure 28 illustrates a more insightful the transmission characteristic of the near field coupling that the two antennas would experience placed side by side 1cm apart. The designated bandwidth of interest, 3-7 GHz, has an insertion loss of 20 dB and exhibits near negligible fluctuation in the group delay, that is less than 50 ps. The corresponding finalized parameters describing the antenna geometry are listed in table 3. + +\begin{table}[h!] +\begin{center} +\begin{tabular}{ c | c } +Parameter & Length $(\mu m)$\\ +R & 5000\\ +$R_g$ & 400\\ +$R_t$ & 800\\ +G & 290\\ +W & 440\\ +C & 260\\ +\end{tabular} +\end{center} +\caption{UWB antenna parameters} +\ context.TABLE: 3 +\end{table} + +{{< figure src="/images/msc-thesis/MA.png" title="Figure 29: (top) Comparison of the measured and simulated $S_{11}$ characteristic. (bot) PSD generated by the UWB pulse shaper for reference." width="500" >}} + +The first set of prototype UWB antennas were developed through manual photo chemical etching whose reflection characteristics are shown in figure 30. The sub 5GHz band appears to match the simulation results relatively well while there are some hints of over etching. The band above 5GHz however is characteristically very different from simulations. The author believes this to be the result of edge roughness introduced by uneven distribution of spray-on photo resist that was used in the development stage as a number of other antenna samples had miniature holes in the ground plane indicating a non-homogeneous etch. There is still a level of adequacy for the measured antenna as the UWB pulse PSD covers the entire band that exhibits the ability to radiate. The high Q notch at 5.5GHz however may significantly distort UWB pulses due the corresponding fluctuation in group delay. The prototype antenna does present a respectable 2GHz bandwidth. + +{{< figure src="/images/msc-thesis/chmbr.png" title="Figure 30: Photograph of the UWB antenna under test in the Imperial College anechoic chamber." width="500" >}} + +## Reciever + +The receiver presented in this section is primarily aimed at system completeness and the testability of the power optimized UWB transmitter system as many of the strict constraints that concern the implanted system no longer apply to the external system. UWB receiver architectures generally consist of almost completely digital architectures including RF ADCs with the exception of front end tuneable low noise amplifiers for pre-acquisition gain. Pulse detection methods are very much translated into the DSP domain where channel approximation algorithms have proven to be very successful at filtering and detective UWB pulses mainly because of critical and overly complex filtering requirement that needs to adapt to both the channel and the effectively unknown input spectrum of the pulse that highly distorted after transmission \cite{1599606}. + +{{< figure src="/images/msc-thesis/rec.png" title="System level abstraction of the reciever architechture." width="500" >}} + +Since both the most basic coherent and non-coherent UWB receiver architectures are beyond the scope of this project a very simple energy detection system has been derived that assumes no strong interferer is transmitting in the UWB spectrum such that the UWB pulse can easily be detected by energy thresholding. +Based on this detection, a set of trigger pulses are generated ideally identical to those generated at the output of the delay modulator. Using the same DCO, the delay between these triggers can be counted by a set of registers such that the encoded information is extracted from trigger circuit recovering all data sent from the transmitter. + +{{< figure src="/images/msc-thesis/dll.png" title="Figure 31a: Schematic of the implemented delay-locked loop." width="500" >}} +{{< figure src="/images/msc-thesis/dly.png" title="Figure 31b: Analog tuned delay element." width="500" >}} + +To synchronize the two systems a delay locked loop is introduced at the receiver that uses analogue delay elements in combination with a charge pump phase detector\cite{5537714}. The control loop illustrated in figure 31 synchronizes the output of the delay line $V_{sync}$ with the reference clock $V_{ref}$ by continuously integrating the phase difference of the two signals. As charge accumulates onto $C_p$, the resulting voltage biases four cascaded delay elements that each can efficiently introduce delays up to 25ns. The actual mechanism of the analogue delay element is based on around the current starving the inverter structure of M5 M4 such that the time it takes to reach the switching point of the output inverter M12 M13 is controlled. Note that once the switching point is achieved the state rapidly regenerates itself due to M8 M9 assuring a fast transition. More importantly the structure negates short circuit currents that may be introduced by the slow switching of the first stage through the transistors M14 and M11. + +## UWB System Summary + +Transient simulations of the UWB transmitter, illustrated in figure 32, have confirmed the general operation of the delay modulator and extracted simulation of the whole system have indicated a power consumption of 68.9 uW for a PRF of 10 MHz. Since the transmitter is encoding the pulses with an effective data rate of 77.5 Mb/s these results correspond to a energy per bit FOM of 890fJ per bit. By extrapolating these results to find the power consumption of the system excluding the UWB pulse shaper, it can be stated that the modulator consumes 470 fJ per DCO oscillation and corresponds to 34% of the over power consumption. + +{{< figure src="/images/msc-thesis/power.png" title="Figure 32: System level simulation results of the DCO, Modulator, and pulse shaper outputs as well as the accumulated power consumption." width="500" >}} + +Although the total phase noise expected at the output of the delay modulator still needs to be characterized, the complete UWB system presents respectable performance in terms of power consumption. And from figure 29 it can be observed that there is an expected -20 dB rejection in the sub 2 GHz band with reference to the 3-6 GHz pass band which implies that the radiated spectrum should meet the FCC requirements accordingly. It can be observed from figure 32 that for closely spaced pulses the pulse amplitude is slightly degraded due to ISI at the transmitter. This type of hysteresis is generally unwanted but can be improved by either shortening the pulse or by reducing the DCO oscillation frequency, both of which degrade the over all system power performance. + +\begin{table}[h!] +\begin{center} +\begin{tabular}{ p{3cm} | c | c | c | c | c | c | c } +Reference & \cite{5986090} & \cite{4242293} & \cite{5117770} & \cite{5615627} & \cite{5617608} & \cite{4982876} & This Work \\ +Technology (nm) & 65 & 90 & 90 & 65 & 65 & 65 & 180 \\ +Modulation & Delay & PPM & BPSK & PPM & OOK & PPM & Delay \\ +Avg. Power (W) & 660n & 718u & 3.3m & 600u & 217u & 4.36m & 68.9u \\ +PRF (Hz) & 1.3M & 16.7M & 100M & 50M & 24M & 15.6M & 10M \\ +Energy per bit (J/bit) & 300f & 37p & 33p & 12p & 8.5p & 17p & 890f\\ +FCC compliant & No & Yes & Yes & Yes & Yes & Yes & Yes* \\ +\end{tabular} +\end{center} +\caption{Performance overview of recent UWB transmitters} +\ context.TABLE: 4 +\begin{flushleft} +*to be confirmed with measurements\\ +\end{flushleft} +\end{table} + +With reference to table 4 it can be noted that the delay modulation generally achieves respectable energy per bit FOMs in comparison to other modulation schemes as the highly energetic pulses are encoded with multiple bits. Note that even though our design was based on a less aggressive 180 nm process the UWB pulse generator allowed us to achieve comparable performance to designs that were implemented in 65 nm technologies for which the transistors achieve a transition frequency \\( F_T \\) that extends far beyond the UWB bandwidth which is essentially a prerequisite for employing the piece-wise reconstruction of analytically optimal wavelets. + +The two figures 33 & 34 show the full custom layout that was designed for the proposed UWB transceiver. The actual transistor level layout of transmitter and receiver combined occupy approximately 100 um by 200 um with a separate self calibrated DCO for each section. The overall area is increased by 300% due to the on-chip inductor that was integrated for the UWB pulse generator. The figure~ \ref{LL2} also shows a large array of decoupling capacitors (in yellow) that remove noise from the supply pads that may influence the DCO operation and introduce additional phase noise. + +{{< figure src="/images/msc-thesis/die1.png" title="Figure 33: Detail of the Full custom Digital layout of UWB, counter clockwise, TX [DCO(red), Delay Modulator(l. blue), UWB Pulse Generator(orange)] & UWB RX [DCO(purple), Demodulator(green), DLL(yellow), RF Energy detector(d. blue)]." width="500" >}} +{{< figure src="/images/msc-thesis/die2.png" title="Figure 34: Layout sent for tape out illustrating the guard-ring (blue), RF pads (red), Integrated Inductor (green), and UWB TX/RX (green)." width="500" >}} + +# Conclusion + +This thesis has addressed the design considerations of an implantable biotelemetry system with respect system level optimizations and presented the circuit level innovation that focused on optimizing power requirements. + +During the development of the forward link in particular the modulation techniques of contemporary literature were evaluated and, with respect to the projected system requirements, BPSK modulation was found to be the most promising. This was illustrated by the fact that BPSK modulation minimizes the off-chip components and by employing the proposed modulation scheme relatively high bit rates were achieved without degrading the overall power transfer efficiency of the forward link. Moreover, the efficiency achieved illustrates that the class-E amplifier operation shows a good synergy with the BPSK modulation mechanism without the need to supply modulation techniques or additional filtering components. + +Since UWB application for biomedical implants is a relatively new and emerging field a significant amount of effort was put toward developing a scalable delay encoding system that could give way for systems that maximize efficiency FOMs like sub 100 fJ energy dissipation per bit transferred. The presented work allows numerous bits to reliably be encoded into a single energetic pulse with a good control over how robust the encoding scheme is towards phase noise as only one element is required to be tuned. The delay modulator presented here is for that reason integrated with a self-calibration frequency locked loop that keeps chip area to a minimum. A conservative estimate bit error rates due to channel induced AWG noise was also presented to given insight to how higher order delay encoding effects the transmission of data. With the theoretical basis covered, circuit specific elements were developed such as a widely tuneable digital oscillator and a particularly energy efficient UWB pulse generator based off the impulse response of a LC resonator. In extension to the transmitter, an UWB antenna was designed where a significant improvement in the low-frequency group-delay and reflection co-efficient was found if the first resonant mode was degenerated by an asymmetric extension of the ground plane. The antenna was fabricated but fine tuning of the etching process was still required for the EM simulation results to match the measured response at the frequencies above 5 GHz. Finally a simple energy detection receiver is developed that will allow testing of the full custom digital layout that was designed for fully integrated the UWB transceiver system. + +## Future Work + +Due to the broad scope telemetry systems there are a wide range of possible future developments that can be considered in extension to what has been presented here. First and foremost it would be important to develop a more standardized receiver that is based on GHz sample acquisition through FPGA and uses a channel estimation adaptive filter to detect the delay encoded words sent by the implanted device. Secondly the UWB antenna needs to go through several process development cycles under a automated fabrication process until the antenna is well characterized. In addition the antenna need to be tuned to match the impedance of the human body right under the skin for maximum radiation efficiency which may even allow for the system to be placed deeper within the body and may be of interest for future work in association to RF powered implants. The final aspect that should be a worthwhile investment lies with developing an integrated rectifier and regulator for the forward transmission link. diff --git a/content/publications/2013/a-890-fj-bit-uwb-transmitter-for-soc-integration-in-high-bit-rate-transcutaneous-bio-implants.md b/content/publications/2013/a-890-fj-bit-uwb-transmitter-for-soc-integration-in-high-bit-rate-transcutaneous-bio-implants.md new file mode 100644 index 0000000..0974b50 --- /dev/null +++ b/content/publications/2013/a-890-fj-bit-uwb-transmitter-for-soc-integration-in-high-bit-rate-transcutaneous-bio-implants.md @@ -0,0 +1,146 @@ +--- +title: "A 890 fj bit UWB Transmitter for SOC Integration in High Bit-Rate Transcutaneous Bio-Implants" +date: 2013-05-19T15:26:46+01:00 +draft: false +toc: true +type: posts +math: true +tags: + - publication + - wireless + - CMOS + - biomedical + - telemetry +--- + + +Lieuwe B. Leene, Song Luan, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +The paper presents a novel ultra low power UWB transmitter system for near field communication in transcutaneous bio-telemetries. The system utilizes an all-digital architecture based on minimising the energy dissipated per bit transmitted by efficiently encoding a packet of pulses with multiple bits and utilizing oscillator referenced delays. This is achieved by introducing a novel bi-phasic 1.65 pJ per pulse UWB pulse generator together with a 72 Ī¼W DCO that provide a transmission bandwidth of 77.5 Mb/s with an energy efficiency of 890 fJ per bit from a 1.2 V supply. The circuit core occupies a compact silicon footprint of 0.026 mmĀ² in a 0.18 Ī¼m CMOS technology. + +# 2 Introduction + +Since Pulsed Ultra Wide Band (UWB) technology has become available for unlicensed communication, a broad spectrum of ideas have been presented over the past decade with regard to UWB pulse modulation, generation and detection techniques[^1]. Recent literature has primarily demonstrated the potential all-digital UWB transmitters have in achieving ultra low power budgets by operating with aggressive duty cycles while maintaining substantial data rates. These developments are of considerable interest to biomedical applications, for example in neural interfaces estimates indicate that state-of-the-art systems already require data rates up to 40Mb/s without compression and a power budget of several mili-watt[^2]. Moreover, based on the recent projection regarding the steady exponential growth in number of neurons recorded[^3], we expect a considerable demand for a ultra low power wireless link that is capable of transmitting 80 Mb/s and is viable for integration on chip with the neural sensory devices in the coming years. + +The UWB transmitter presented here is based on developing a transcutaneous biotelemetry system where the transmitter is coupled to a receiver trough a near field communication channel across the skin boundary. The adoption of near field transmission for power and data is nearly ubiquitous in biotelemetry systems because it alleviates the challenge of coping with the lossy radiation environment of the human body and power restrictions due to thermal dissipation constraints. Moreover, near field communication should allow high SNR values with respect to interfering UWB devices such that a simple energy detection based receiver can fully detect the individual transmitted UWB pulses. + +This work presents an UWB transmitter architecture for asynchronous communication that achieves ultra low power consumption by minimising the energy dissipated per bit transmitted (EPB). This is achieved through circuit level optimizations in addition to encoding a packet of pulses with multiple bits. Furthermore scalable PPM modulation is achieved with significant improvements in both resource requirements and phase integrity over conventional techniques that either use a tuneable delay element or multiple delay lines[^4]. + +This paper is organized as follows. Section 3 presents a discussion on the operation of the proposed architecture. Section 4 presents the transistor level implementations of a Digitally Calibrated Oscillator (DCO) and an novel UWB pulse shaper. Section 7 completes the design aspects of the transmitter by presenting the employed UWB antenna. Sections 8 & 13 demonstrate the performance of the proposed system and conclude upon this paper's findings. + +# 3 UWB Transmitter System Concept + +The system architecture of the UWB transmitter is shown in Fig. 1. This is based on using a DCO as a reference for the encoded delays intermediate to the pulse positions. This approach allows accurate definition of all relative pulse positions by calibrating a single element thereby reducing the system's resource requirement while maintaining scalability. The bi-phasic pulse generator extends this flexibility by allowing pulses to be modulated in terms of position and phase simultaneously. + +{{< figure src="/images/iscas2012/s1.png" title="Figure 1: System level architecture of the UWB Transmitter capable of M-arry PPM and BPSK modulation" width="500" >}} + +The PPM modulation mechanism relies on the removal or 'swallowing' of extraneous clock pulses generated by the DCO, hence introducing inter-pulse delays quantized by the DCO's period. This is achieved by disconnecting the power supply from the inter-stage buffer driving the pulse generator for specific intervals. These intervals are specified by a synchronized D flip-flop fed by a shift register with decisions to swallow or transmit the incoming pulse. Exact duty cycles are achieved by enabling the DCO on the rising edge of the input for a burst of clock cycles and disabling the DCO when the shift register detects the end of the pulse package. + +A high speed all-digital frequency locked loop is used on system start up to calibrate the DCO to a fixed oscillation frequency. Calibration is an important consideration as DCO frequency off-sets for this topology results in increasingly larger temporal off-sets for increasingly longer pulse packages and amounts to significant phase noise at the receiver. + +In order to maximize the efficiency of the transmitter, this system essentially cascades two delay-hopped time-reference (DHTR) pulse pairs where the second pulse is the reference pulse for the third pulse [^5]. The phase of each pulse is given by a 3-bit word, D2 - D0. The implemented design allows the second pulse to be delayed to 8 different positions. The third pulse can then be delayed to 4 different positions with reference to the second pulse including a null position where the pulse is omitted. Note that when the third pulse is omitted standard DHTR modulation is achieved and the bit D0 is ignored. As a result each pulse package encodes 7.75 effective number of bits (ENOBs) with an average of 2.75 pulses per package for a equiprobable code book. The transmitted package may be represented analytically as + +$$ s(t)= a_{i} w(t) + b_{i} w(t - A_i \cdot T_{DCO}) + c_i w( t - (A_i + B_i) \cdot T_{DCO} ) $$ + +where i is the package index, w(t) is the UWB pulse shape, and TDCO is the unit delay introduced by the DCO's period. ai, bi, ci in { +1, -1 } are the respective first, second, and third pulse phases. Ai & Bi are the respective delays of the first and second pulse pairs. Fig. 2 exemplifies two pulse packets with reference to the DCO clock whose encoding is given by; A1, B1, D(2-0)1 = [010, 10, 010] and A2, B2, D(2-0)2 = [001, 01, 110]. + +{{< figure src="/images/iscas2012/ex.png" title="Figure 2: Waveforms illustrating two different DHTR modulated pulse packages. a) DCO reference, b) package index 1 [010, 10, 010], c) package index 2 [001, 01, 110]$. " width="500" >}} + +# 4 Circuit Implementation + +The circuit has been implemented in a commercially available 0.18 Ī¼m CMOS technology provided by AMS/IBM (C18A4/7sf) and has been designed to operate from a 1.2 V supply. This section details the circuit level design and implementation. + +## 5 Digitally Calibrated Oscillator + +The DCO employed by the UWB transmitter is an 8-bit calibrated 5-stage ring oscillator as shown in Fig. 3. The five most significant bits of the calibration state C7 to C3 adjust the main capacitive load by shorting a select set of capacitors from a binary weighted array to ground and leaving others floating. The lower 3 bits C2 to C0 fine tune the oscillation frequency by adjusting the NMOS side driving capability of an the inverter stage achieving a resolution in the order of tens of pico-seconds by making fractional changes in aspect ratio for different matched transistors. Since the transistor 'on' resistance is inversely proportional to the tuned driving capability of the inverter, a 3-input look-up-table-based remapping is introduced. This improves the performance of the fine calibration bits by linearizing the tuneable delay with respect to the control bits. Note that the main delay elements are primarily dependent on the NMOS devices and the parasitic capacitance which by reducing the dependence on PMOS devices improves the sensitivity to process variation. + +{{< figure src="/images/iscas2012/s2.png" title="Figure 3: Circuit schematic of the 5-stage digitally calibrated Ring oscillator" width="500" >}} + +## 6 UWB Pulse Shaper + +The pulse shaper presented here has been partly adopted from previous work that used integrated LC components to filter out the unwanted spectrum to meet the FCC mask requirements[^6]. An integrated inductor is differentially pulsed with current over 180 ps which perturbs the LC resonator to start oscillating with the induced energy. This resonating energy is leaked towards the resistive load of the antenna over a longer time frame of 1ns. There is an explicit capacitive impedance mismatch at the bond-pad such that most of the energy induced by the driving transistors is fed into the inductor. + +The circuit consists of a two part design, including digital and RF sections. The Digital pre-shaper is shown in Fig. 4. This uses a popular glitch generator to generate 180ps long Gaussian like pulses, which are demultiplexed to two inverter chains to boost the driving capability of the output. It is important to note that these chains have a different output polarity but both output the buffered pulse together with a delayed and inverted pulse. The driving transistors in Fig. 5 source the inductor with pulsed current proportional to the glitch duration. The purpose of the delayed pulse is to cancel the DC component generated by the transient impulse response of the lossy LC resonator, by injecting an equal but complementary pulse at the opposite port of the inductor. By driving either the end connected to the load, or the Cres end of the inductor first, the polarity of the UWB pulse is well controlled. + +The circuit shown in Fig. 4 also illustrates how a shift register can interface the UWB transmitter with a parallel input data stream. In the RF section (Fig. 5), it is interesting to note that since the transistor pairs M1, M4, M2, and M3 are matched in terms of driving capability this particular topology is immune to variations in pulse length. This would easily distort the output spectrum of aggressive UWB pulse generators that use multiple glitch generators to shape the pulse. The integrated 4 nH inductor is a single layer 6-turn 8-sided spiral with poly-silicon ground plane and dimensions 4 Ī¼m, 2.8 Ī¼m, 66 Ī¼m corresponding to the trace width, trace spacing, and outer radius respectively. + +{{< figure src="/images/iscas2012/s3.png" title="Figure 4: Circuit Schematic of the digital pre-shaping" width="500" >}} + +{{< figure src="/images/iscas2012/s4.png" title="Figure 5: Circuit schematic of the RF section with L = 4nH; Cres = 200fF; - Note that the relative temporal delays of the driving signals are not to scale." width="500" >}} + +# 7 Miniaturized UWB Antenna + +An omni-directional UWB antenna that radiates in the plane of the skin boundary is used for near field coupling instead of an RF coil to reduce the potential interference from echos and other UWB sources. The antenna here is based on a generic elliptic co-planar mono-pole geometry which has been shown to have good non-dispersive radiation characteristics over the entire bandwidth[^7]. To assure that the radiated pulse meets the FCC requirements in the sub 2 GHz band, the antenna is required to reject this band by at least 20 dB with respect to the insertion loss in the 3.1 GHz - 10.6 GHz band. + +{{< figure src="/images/iscas2012/gg.png" title="Figure 6: Illustration of the antenna geometry and a high contrast photograph of a prototype next to a British pound with dielectric cover removed." width="500" >}} + +The antenna geometry is shown in Fig. 6, with the various antenna dimensions designed as follows; R = 5mm, RG = 400 Ī¼m, RT = 800 Ī¼m, G = 290 Ī¼m, W = 440 Ī¼m, C = 260 Ī¼m, td = 635 Ī¼m, tm = 35 Ī¼m. + +The antenna uses an asymmetric extended ground plane to damp the first strong resonance that is usually centred around 3-4GHz and can introduce significant pulse distortion. To improve the viability of the antenna for an implanted system a high dielectric laminate with copper metallization, RO1030, was used on both sides of the metallization to scale down the dimensions to allow an off-chip imprint below 2 cmĀ². + +# 8 Results + +The design was simulated in Cadence IC 5.141 ISR with foundry-supplied PSP models. This section details the DCO, pulse generator, antenna and system performance. + +## 9 Digitally Calibrated Oscillator + +Monte Carlo simulation revealed the proposed DCO has a standard deviation in oscillation frequency of 44.9 MHz. The calibration mechanism allows the DCO to sweep through from 750 MHz to 390 MHz with a resolution of approximately 4.5 MHz as shown in Fig. 7. The DCO consumes an average of 72 Ī¼W during continuous operation at 500MHz. + +{{< figure src="/images/iscas2012/swp.png" title="Figure 7: Transient simulation of the DCO sweeping through all calibration states" width="500" >}} + +## 10 Pulse Generator + +The transient simulation of the UWB pulse generator is illustrated in Fig. 8. This demonstrated a power dissipation of 1.65 pJ per pulse with a 344 mVpp Amplitude. Spectral analysis further shows a peak power spectral density of -50.6 dBm/MHz and FCC mask compliance over the 3.1 GHz - 10 GHz band. + +{{< figure src="/images/iscas2012/tr.png" title="Figure 8a: bi-phasic UWB temporal response." width="500" >}} + +{{< figure src="/images/iscas2012/dfs.png" title="Figure 8b: Simulated PSD of the designed UWB pulse & the indoor UWB FCC mask as annotated." width="500" >}} + +## 11 UWB antenna + +{{< figure src="/images/iscas2012/a1.png" title="Figure 9: Simulated reflection co-efficient S11 for the UWB antenna radiating in free space." width="500" >}} + +Preliminary EM simulations were carried out using CST MICROWAVE STUDIO package with a 50 ohm port impedance. Fig. 9 shows the UWB antenna achieves a -10 dB reflection over the 3.66 GHz to 7 GHz band without significant phase distortion. + +## 12 System Performance + +The complete system level simulation is shown in Fig. 10. This demonstrates the transmitter operating with a package frequency rate (PRF) of 20 MHz transmitting a 155 Mb/s bit stream of pseudo random data while consuming less than 40 pJ under 300 ns. For the target 10MHz PRF, the system consumes an average of 68.9 Ī¼W corresponding to a 890 fJ of energy dissipated per bit transmitted. The custom digital layout is shown in Fig. 11. This measures 135 Ī¼m by 60 Ī¼m excluding the 132 Ī¼m by 132 Ī¼m integrated inductor, giving a total core area of 0.026 mmĀ². + +{{< figure src="/images/iscas2012/ps.png" title="Figure 10: Simulation result illustrating the voltage waveforms generated by the different components with a 20 MHz PRF and a random input data stream." width="500" >}} + +{{< figure src="/images/iscas2012/tx.png" title="Figure 11: Core Layout of the UWB transmitter with each block annotated as; a) UWB Pulse shaper b) Pulse Swallowing c) Serial Interface d) DCO." width="500" >}} + +# 13 Conclusion + +An all-digital UWB transmitter architecture has been presented for biomedical SOC integration that seeks to improve system efficiency by achieving asynchronous ultra low power operation for arbitrary bit rates. A DCO based modulation scheme is introduced that significantly reduces the on-chip resource requirements for PPM modulation and allowed efficient 8-bit encoding onto 3 UWB pulses. The novel low power bi-phasic UWB pulse generator further allows this system to achieve 890 fJ EPB on a 0.18 Ī¼m CMOS process to make integration with state of the art neural interfaces viable. The overall system achieves very aggressive performance in terms of power consumption for 10MHz PRF as illustrated in table 1. Future work will focus on tuning the UWB antenna to match the tissue impedance and characterizing the near field communication channel. + +Table 1: Performance overview of recent UWB transmitters +|Reference | [^8] | [^9] | [^10] | [^11] | [^12] | This Work | +|----|----|----|----|----|----|----| +|Tech. (nm) | 65 | 130 | 65 | 65 | 65 | 180 | +|Modulation | DHTR | BPSK | PPM | OOK | BPSK | DHTR | +|Power (W) | 660n | 3.3m | 820u | 217u | 4.36m | 68.9u | +|PRF (Hz) | 0.6M | 100M | 50M | 24M | 15.6M | 10M | +|EPB (J/bit) | 300f | 33p | 12p | 8.5p | 17.5p | 890f| +|FCC compliant | - | Yes | Yes | Yes | Yes | Yes | + +# Refernces: + +[^1]: A.Chandrakasan, F.Lee, D.Wentzloff, V.Sze, B.Ginsburg, P.Mercier, D.Daly, and R.Blazquez, ''Low-power impulse uwb architectures and circuits,'' Proc. IEEE, vol.97, no.2, pp. 332 --352, 2009. +[^2]: A.Eftekhar, S.Paraskevopoulou, and T.Constandinou, ''Towards a next generation neural interface: Optimizing power, bandwidth and data quality,'' in Proc. IEEE BioCAS, 2010, pp. 122 --125. +[^3]: I.Stevenson and K.Kording, ''How advances in neural recording affect data analysis,'' Nature neuroscience, vol.14, no.2, pp. 139--142, 2011. +[^4]: T.Buchegger, G.Ossberger, A.Reisenzahn, A.Stelzer, and A.Springer, ''Pulse delay techniques for ppm impulse radio transmitters,'' in Proc. IEEE Conf. UWB Syst. Tech., 2003, pp. 37 -- 41. +[^5]: R.Hoctor and H.Tomlinson, ''Delay-hopped transmitted-reference rf communications,'' in Proc. IEEE Conf. UWB Syst. Tech., 2002, pp. 265--269. +[^6]: L.Moreira, W.van Noije, D.Silveira, S.Kofuji, and C.Sassaki, ''A small area 2.8pj/pulse 7th derivative gaussian pulse generator for ir-uwb,'' in Proc. CJMW, 2011, pp. 1 --4. +[^7]: J.Liang, C.Chiau, X.Chen, and C.Parini, ''Study of a printed circular disc monopole antenna for uwb systems,'' IEEE Trans. Antennas and Propagation, vol.53, no.11, pp. 3500 -- 3504, 2005. +[^8]: M.Mark, Y.Chen, C.Sutardja, C.Tang, S.Gowda, M.Wagner, D.Werthimer, and J.Rabaey, ''A 1mm$^3$ 2mbps 330fj/b transponder for implanted neural sensors,'' in Proc. IEEE VLSIC, 2011, pp. 168--169. +[^9]: B.Qin, H.Chen, X.Wang, A.Wang, Y.Hao, L.Yang, and B.Zhao, ''A single-chip 33pj/pulse 5th-derivative gaussian based ir-uwb transmitter in 0.13$\mu$m cmos,'' in Proc. IEEE ISCAS, 2009, pp. 401--404. +[^10]: Y.Park and D.Wentzloff, ''An all-digital 12pj/pulse 3.1 - 6.0ghz ir-uwb transmitter in 65nm cmos,'' in Proc. IEEE ICUWB, vol.1, 2010, pp. 1--4. +[^11]: H.Miranda and T.Meng, ''A programmable pulse uwb transmitter with 34% energy efficiency for multichannel neuro-recording systems,'' in Proc. IEEE CICC, 2010, pp. 1--4. +[^12]: P.Mercier, D.Daly, and A.Chandrakasan, ''An energy-efficient all-digital uwb transmitter employing dual capacitively-coupled pulse-shaping drivers,'' IEEE JSSC, vol.44, no.6, pp. 1679--1688, 2009. diff --git a/content/publications/2013/a-compact-recording-array-for-neural-interfaces.md b/content/publications/2013/a-compact-recording-array-for-neural-interfaces.md new file mode 100644 index 0000000..9bea86d --- /dev/null +++ b/content/publications/2013/a-compact-recording-array-for-neural-interfaces.md @@ -0,0 +1,131 @@ +--- +title: "A Compact Recording Array for Neural Interfaces" +date: 2013-09-13T15:26:46+01:00 +draft: false +toc: true +type: posts +math: true +tags: + - publication + - instrumentation + - CMOS + - biomedical + - sensor +--- + +Lieuwe B. Leene, Yan Liu, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +This paper presents a 44-channel front-end neural interface for recording both Extracellular Action Potentials (EAPs) and Local Field Potentials (LFPs) with 60 dB dynamic range. With a silicon footprint of only 0.011 mmĀ² per recording channel this allows an unprecedented order of magnitude area reduction over state-of-the-art implementations in 0.18 Ī¼m CMOS. This highly compact configuration is achievable by introducing an in-channel Sigma Delta assisted Successive Approximation Register (\\(\Sigma\Delta\\)-SAR) hybrid data converter integrated into the analogue front-end. A pipelined low complexity FIR filter is distributed across 44-channels to resolve a 10-bit PCM output. The proposed system achieves an input referred noise of 6.41 Ī¼Vrms with a 6 kHz bandwidth and sampled at 12.5 kS/s, with a power consumption of 2.6 Ī¼W per channel. + +# 2 Introduction + +The recent trend in on-chip instrumentation for neural electrophysiological recording has largely been motivated by the growing interest in observing large scale neuronal activity using small chronic implants. Such tools are crucial in the quest to better understand the brain, but also in revealing fundamental mechanisms behind neurological and psychiatric diseases for developing new diagnostics and therapeutic devices. Microelectronic bio-instrumentation systems currently have the capacity for profoundly impact such key scientific efforts [^1]. + +State-of-the-art neural recording systems have made significant progress over past years by objectively improving figures of merit, most notably that of the Noise Efficiency Factor (NEF) [^2]. This progress has not however generally had the same impact on silicon footprint, which is also critical for the long term increase in recording capacity and System-on-Chip (SOC) platforms. Although a number of compact circuits including analogue amplifiers and data converters have been proposed for biomedical applications, less attention has been given to area reduction from a system perspective apart from the typical multiplexing of the Analogue-to-Digital Converter (ADC). This is partly due to the challenge in multiplexing ultra low power analogue without significantly degrading performance (i.e. due to parasitics and inter-channel interference). The work presented herein applies a number of ideas aimed at collectively reducing the silicon area towards highly scalable systems. Through a combination of novel structures and circuit level implementations that allow for hardware reuse (and thus area reduction), this work demonstrates the capacity for unprecedented area efficiency at the system level. + +The target system specifications herein apply to a Brain Machine Interface (BMI) recording the (raw) signal including both LPFs and EAPs. Furthermore, such a system can provide undistorted EAP recordings which are typically due to a high pass filter centred around 100--500 Hz. This implies an input-referred signal amplitude ranging from 10 Ī¼V to 10 mV, which has a dynamic range equivalent to that of a10-bit converter with a frequency bandwidth of 100 mHz to 3 kHz for optimal data post processing [^1]. This system aims towards a robust SOC platform, utilising a fully-differential structure to reject supply noise, as well as even order distortion harmonics, for the integration of a very large number of recording channels with wireless and digital post-processing systems. + +This organisation of this paper is as follows: Section 3 outlines the proposed system-level architecture; Section 4 details the circuit level implementation; Section 9 presents simulated system and circuit level results; and finally, Section 10 compares the overall system characteristics to the current state-of-the-art and concludes the paper. + +# 3 System Architecture + +{{< figure src="/images/biocas2013/I1.png" title="Figure 1: Top level architecture of the proposed system." width="500" >}} + +The top level system is illustrated in Fig 1, showing the in-channel architecture consisting of two multiplexed low noise amplifiers, a hybrid data converter, and two ultra compact digital filters. The system integrates 44-channels together with the primary objective being to combine state-of-the-art instrumentation techniques to achieve a substantial reduction in area through a novel implementation. The Front End Amplifier (FEA) utilises a chopper technique to alleviate the need for very large transistors and a Sigma Delta assisted Successive Approximation Register (\\(\Sigma\Delta\\)-SAR) is developed to significantly reduce the size of the capacitor bank typically required for a 10-bit resolution output. This capacitor bank is also used to implement a switched-capacitor digital filter to reject the unwanted chopper harmonics thus avoiding the requirement for additional analogue filter blocks. Finally, the filter needed to decimate the \\(\Sigma\Delta\\)-SAR modulator output is shared in the digital domain through a pipeline structure that require only a low resolution accumulator, thereby mitigating the computational costs typically associated with \\(\Sigma\Delta\\) decimation. + +# 4 Circuit Implementation + +## 5 Chopper Modulated Analog Front End + +{{< figure src="/images/biocas2013/I2.png" title="Figure 2:FEA structure illustrating the feedback and chopper configuration." width="500" >}} + +The AFE is illustrated in Fig. 2. This Capacitively-Coupled Chopper Instrumentation Amplifier (CCIA) [^3] consists of a Miller compensated 2-stage design with capacitive feedback. Using a single analogue block for amplification naturally has its trade-off as the high gain requirement implies a large input capacitance Cin = 6.5 pF) but at the same time reduces the value of the Miller capacitor that introduces the dominant pole of the system for a given thermal noise floor. The feedback network is configured to introduce 34 dB of differential gain and improve the input impedance of the amplifier through positive feedback where Cfp = Cfb, Zin=\\( \frac{Gain}{2 \cdot f_{chop} \cdot C_{in}}\\) = 77 MĪ©, and fchop = 50 kHz. + +{{< figure src="/images/biocas2013/I5.png" title="Figure 3:Circuit level schematic of the FEA." width="500" >}} + +The circuit level schematic of the FEA is shown in Fig. 3. This implementation uses the complementary input pair to allow good current efficiency for the 1.8 V analogue supply together with a class-AB, low output resistance, cascade gain stage to drive the large switching capacitance loading the output from the feedback network. The circuit also includes the common mode feedback and ADC sampling capacitors. A MOS capacitor is used to introduce the dominant pole at 6 kHz while the feedback network is implemented using MIM capacitors. The overall high pass behaviour of this structure is implemented through the periodic reset of the input and the output which also auto-zeros the input pair offset. This offset compensation is maintained outside the reset phase by biasing the gate of the reset switch at the mid-rail voltage such that it behaves as a traditional MOS-based pseudo-resistor. This reset mechanism benefits due to the improved noise characteristic over a DC-servo loop implementation that also requires a significant amount of additional area. However, the signal distortion introduced though this technique can be compensated in the digital domain [^4]. All current sourcing transistors (M5-M10) have cascode implementations (not shown in Fig. 3) to provide adequate common mode rejection and common mode input range of \\(\pm\\)200 mV, which is biased and filtered through the reset switch. + +## 6 Hybrid \\(\Sigma\Delta\\) assisted SAR ADC + +The data converter is based on extending the resolution of a small 6-bit SAR ADC with a continuous time \\(\Sigma\Delta\\) modulator that resolves the remaining quantisation error residue from the SAR algorithm. The primary components of the modulator are integrated into the pre-gain stage structure of the comparator as illustrated in Fig. 4. During initial SAR operation the gm-C filter is switched out and the input pair directly feeds into a diode-connected load for wideband operation while the filter capacitors are reset. Once the last SAR bit is resolved the loop filter is enabled implementing a second-order chain of integrators with a weighted feedforward summation modulator topology that allows low power operation with minimised signal distortion. Note that in Fig. 4 during SAR operation V\\(\Sigma\Delta\\) is at the common mode and is then modulated between Ā±Vref such that the feedback is necessarily always twice as large as the residue error to ensure modulator stability and optimal residue quantisation. + +{{< figure src="/images/biocas2013/I3.png" title="Figure 4: Circuit level schematic of the hybrid \\(\Sigma\Delta\\)-SAR converter." width="500" >}} + +The general organisation and operation of the ADC is illustrated in Fig. 7. Given that N=6 is the resolution of the SAR DAC and OSR=44 is the conventional oversampling ratio of the modulator. It can be observed that both SAR and \\(\Sigma\Delta\\) operation is at 5 MHz and takes N+OSR cycles to finish or a total of 10 Ī¼s for a sampling rate of 25 kHz at the 25 % duty cycle. In addition to using 5 reference voltages this topology makes a extreme reduction in size by a factor of 32 and will allow large 8 by 8 Ī¼mĀ² unit capacitors to reduce the sensitivity of process variation thereby achieving a 10-bit resolution without any in-channel calibration. + +## 7 Chopper Rejection + +In order to reject chopper harmonics introduced by the up-modulated offset aggressors, the capacitive array is used as a switched capacitor network to implement a notch filter centred around the odd harmonics of the chopper frequency when the data converter is not operational. The output of the AFE is sampled in the time domain and weighted using different sets of capacitors to implement a 3rd order Bartlett window filter before ADC conversion. This technique avoids the need for a ripple reduction loop which typically also requires an analogue filter with large capacitors. Fig. 5 shows the 4-phase sampling sequence that operates at 50 kHz. The net charge, Qtotal, quantised by the converter is expressed as follows. + +$$ \frac{Q_{total}}{C_{unit}} = 8 V_{diff} \left[ n-1 \right] + 16 V_{diff} \left[ n-2 \right] + 8 V_{diff} \left[ n-3 \right] $$ + +Where Vdiff is the sampled differential output voltage of the amplifier and Cunit is the 120 fF unit capacitance of the converter that also averages sampling noise during conversion. This allows the notch filter characteristic illustrated in Fig. 5, to reject a significant amount of high frequency aggressors. + +{{< figure src="/images/biocas2013/F2.png" title="Figure 5:Switched capacitor filter timing diagram (left) and frequency response (right)" width="500" >}} + +## 8 Digital Filter + +The filter structure used to process the \\(\Sigma\Delta\\) output is illustrated in Fig. 6. This structure distributes the overall structure across all channels such that each channel requires only a 7-bit register, a 12-bit registered add/subtract accumulator as well as the two 7-bit registers from the SAR to implement the hybrid functionality demonstrated here. The filter coefficients are hardwired into each channel's 7-bit register such that it is loaded during reset and circulated through all channels. + +{{< figure src="/images/biocas2013/I6.png" title="Figure 6:Implementation of the pipelined FIR structure." width="500" >}} + +The \\(\Sigma\Delta\\) output sign modulates the accumulator which integrates over a 44-point hanning window, implementing a FIR filter without multipliers. A more traditional decimation filter implemented using a cascaded integrator comb (CIC) filter is much less effective here. This is because the structures cannot be shared (across channels) and will require a larger number of samples than the OSR to evaluate the residue error which due to the intermediate SAR process being continuously disrupted. Fortunately the resolution only needs to be extended by 4-bits to achieve the required 60 dB dynamic range. Therefore a compact 44th order window at 7-bit unsigned resolution suffices. The structure has shown to make a good estimate of the stationary input to the modulator even with high levels of quantisation noise allowing us to decrease to resolution of the stored coefficients that are given by the following expression. + +$$ w[n] = C \cdot \left[ 1 - cos \left( \frac{2 \pi n}{N-1}\right) \right]^{0.7} $$ + +The coefficients, w[n], represent a modified hanning window that results in a better Differential Non-Linearity (DNL) characteristic over other FIR windows when quantised to 7-bits. Note that C=0.024, N=46, and $n \in \left[1, 2, ..., N-2 \right]$ represent the normalisation constant, effective filter order, and the non-zero coefficient index respectively. + +{{< figure src="/images/biocas2013/example.png" title="Figure 7: Transient operation of the ADC conversion." width="500" >}} + +{{< figure src="/images/biocas2013/os.png" title="Figure 8: Output of the analogue channel with a 19 mV peak to peak 1 kHz input." width="500" >}} + +# 9 Simulation Results + +Preliminary validation of the proposed implementation has been done through schematic level simulations in the Cadence IC 6.1.5 Design Environment using industry provided PSP models for the commercially available 6 Metal 0.18 Ī¼m CMOS technology (AMS/IBM C18A6/7SF). The entire channel has been stimulated with 19 mV peak to peak 1 kHz differential signal for full swing at the ADC input of which a single ADC conversion is illustrated in Fig. 7. The quantised output spectrum of this simulation is shown in Fig. 8 which indicates a 1.2% total harmonic distortion for a full swing output that is due to the AFE. Fig. 10 illustrates the characteristics of the FIR filter in time and frequency domain respectively. Fig. 11 presents 10.2 ENOB performance through the 0.5 LSB bounded integral and differential non-linearities of the converter. The channel level layout is shown in Fig. 12 indicating a 440 Ī¼m by 50 Ī¼m area requirement for 2 recording channels. + +{{< figure src="/images/biocas2013/noise.png" title="Figure 9: Noise density simulated at the output of the FEA" width="500" >}} + +{{< figure src="/images/biocas2013/F1.png" title="Figure 10: 7-bit quantised Hanning FIR filter showing frequency (top) and time (bottom) domain responses." width="500" >}} + +{{< figure src="/images/biocas2013/F3.png" title="Figure 11: \\(\Sigma\Delta\\)SAR non-linearities showing INL (top), DNL (bottom)" width="500" >}} + +{{< figure src="/images/biocas2013/Area2.png" title="Figure 12: Layout of 4 Channels integrated together with CMIM capacitors overlaying the 440 Ī¼m by 100 Ī¼m silicon footprint." width="500" >}} + +# 10 Conclusion + +The ultra compact topology presented has demonstrated the means by which the recording channel can scale down below a 0.01 mmĀ² area while maintaining its recording fidelity and advanced spectral filtering characteristics. In addition the proposed 10 bit hybrid data converter achieves a factor of 32 reduction in area over equivalent data converters through pipelining and \\(\Sigma\Delta\\) modulation. With an input referred noise of 6.4 Ī¼Vrms this system consumes 2.6 Ī¼W resulting in excellent Noise Area product of 0.007 Ī¼Vrms mmĀ². The overall system characteristics are shown in Table 1 demonstrating respectable performance particularly with respect to the order of magnitude reduction in area per channel and the 60 dB dynamic range for the given power budget. + +Table 1: Performance per channel of Neural Recording Arrays +|Reference | [^5] | [^6] | [^7] | [^8] | This work | +|----|----|----|----|----|----| +|Year | 2011 | 2012 | 2012 | 2012 | 2013 | +|Tech. [nm] | 180 | 250 | 130 | 130 | 180 | +|Power [Ī¼W] | 10.1 | 3.96 | 68 | 5.9 | 2.59 | +|High Pass [Hz] | 126m | 100m | 1 | 200 | 100m | +|Low Pass [Hz] | 12k | 17k | 10K | 6.9K | 6K | +|Noise [Ī¼Vrms] | 5.4 | 4.8 | 2.2 | 3.8 | 6.41 | +|NEF | 4.4 | 2.9 | 4.5 | 2.16 | 2.27 | +|Area [mmĀ²] | 0.31 | 0.07 | 0.19 | 0.16 | 0.011 | +|ADC Res. | 8 | 9 | 10 | 8 | 10 | +|Sample [kS/s] | 125 | 60 | 31 | 27 | 12.5 | + +# 11 Acknowledgment + +This work was supported by the UK EPSRC (grants EP/I000569/1 and EP/K015060/1). + +# Refernces: + +[^1]: F.K. etal., ''Drug discovery: A jump-start for electroceuticals,'' Nature, vol. 496, pp. 159--161, 2013. +[^2]: R.Rieger, Y.-Y. Pan, and J.Taylor, ''Design strategies for multi-channel low-noise recording systems,'' in Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, 2007, pp. 561--564. +[^3]: Q.Fan, F.Sebastiano, J.Huijsing, and K.Makinwa, ''A 1.8 w 60 nv hz capacitively-coupled chopper instrumentation amplifier in 65 nm cmos for wireless sensor nodes,'' Solid-State Circuits, IEEE Journal of, vol.46, no.7, pp. 1534--1543, 2011. +[^4]: Y.Chen, A.Basu, and M.Je, ''A digitally assisted, pseudo-resistor-less amplifier in 65nm cmos for neural recording applications,'' in Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on, 2012, pp. 366--369. +[^5]: W.Wattanapanitch and R.Sarpeshkar, ''A low-power 32-channel digitally programmable neural recording integrated circuit,'' Biomedical Circuits and Systems, IEEE Transactions on, vol.5, no.6, pp. 592--602, 2011. +[^6]: K.Al-Ashmouny, S.-I. Chang, and E.Yoon, ''A 4 $\mu$w/ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-d neural microsystems,'' in Biomedical Circuits and Systems Conference (BioCAS), 2011 IEEE, 2011, pp. 1--4. +[^7]: H.Gao, R.Walker, P.Nuyujukian, K.Makinwa, K.Shenoy, B.Murmann, and T.Meng, ''Hermese: A 96-channel full data rate direct neural interface in 0.13 m cmos,'' Solid-State Circuits, IEEE Journal of, vol.47, no.4, pp. 1043--1055, 2012. +[^8]: A.Rodriguez-Perez, J.Masuch, J.Rodriguez-Rodriguez, M.Delgado-Restituto, and A.Rodriguez-Vazquez, ''A 64-channel inductively-powered neural recording sensor array,'' in Biomedical Circuits and Systems Conference (BioCAS), 2012 IEEE, 2012, pp. 228--231. diff --git a/content/publications/2014/an-adaptive-16-64-khz-9-bit-sar-adc-with-peak-aligned-sampling-for-neural-spike-recording.md b/content/publications/2014/an-adaptive-16-64-khz-9-bit-sar-adc-with-peak-aligned-sampling-for-neural-spike-recording.md new file mode 100644 index 0000000..a790ec0 --- /dev/null +++ b/content/publications/2014/an-adaptive-16-64-khz-9-bit-sar-adc-with-peak-aligned-sampling-for-neural-spike-recording.md @@ -0,0 +1,144 @@ +--- +title: "An adaptive 16/64 kHz, 9-bit SAR ADC with peak-aligned sampling for neural spike recording" +date: 2014-06-01T15:26:46+01:00 +draft: false +toc: true +math: true +type: posts +tags: + - publication + - instrumentation + - CMOS + - biomedical + - sampling +--- + +Lirong Zheng, Lieuwe B. Leene, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +This paper presents a novel method and circuit for feature-driven data acquisition in single neuron recording. By dynamically adjusting the phase of the sampling clock in a Successive Approximation Register (SAR) Analogue to Digital Converter (ADC), the samples can be maximally aligned to the spike extrema (peaks). This is achieved by using spike detection to switch from a 'coarse' to 'fine' sampling clock, and triggering a peak-search algorithm to determine the offset between the peak occurrence and the coarse clock. Subsequent samples are then aligned to the peak by shifting the coarse clock by the measured offset. This adaptive sampling scheme thus allows for improved temporal precision on features of interest (i.e. peaks) whilst maintaining a coarse effective sampling rate, also minimising power consumption. The proposed method reduces the output data bandwidth by approximately 70% in comparison to a fixed-sampling rate data converter that would achieve similar precision in peak alignment. The circuit implementation achieves 9-bit resolution with a 93 fJ/conversion-step energy efficiency in a standard 0.35\\( \mu\\)m CMOS technology. + +# 2 Introduction + +In the quest towards understanding the human brain, neuroscientists are now using 'new' research tools to record single neuron activity in-vivo. Neural probes consisting of micro-fabricated multi-electrode arrays (MEAs) together with supporting recording electronics are providing the opportunity to observe the extracellular activity of an increasing number of neurons in real-time [^1]. To this end, the Neural Engineering and BioCAS communities have made significant progress in the past decade, developing countless integrated, multi-channel neural recording interfaces, Eg. \cite{harrison2007low, bonfanti2010multi, gao2012hermese}. These amplify, filter and digitise the Extracellular Action Potentials (EAPs) with hardware specifications carefully selected so as to maintain signal integrity for post-processing or offline analysis [^5]. + +Spike sorting allows the decomposition of extracellular recordings into single unit EAP activities. This process typically involves spike detection, alignment, feature extraction and clustering. Although neural interfaces maintain the signal bandwidth in front-end conditioning and comply to Nyquist criteria in digitisation, the temporal precision of spike features can still be compromised in quantisation. Specifically, spike peaks can be 'missed' if incident between sampling cycles, and can then be prone to sampling error causing the peak magnitude be undersampled. The precise detection of spike peaks is critical in ensuring good alignment for spike sorting [^6]. In methods such as template matching it has been shown that spike sorting accuracy degrades significantly with poor alignment [^5]. However, if good alignment can be maintained, then decreasing the template size (i.e. using a reduced sampling rate to provide fewer samples for a fixed spike window) has a negligible impact on spike sorting accuracy. In practice, good alignment can be achieved either by: (1) increasing the sampling rate, thus increasing the temporal resolution, or (2) reducing the sampling rate and interpolating (i.e. upsampling) to 'reconstruct' the peak. Both these methods however are undesirable, as they increase complexity and thus hardware resource (power and area) requirements. + +This paper presents a novel data converter design that aligns its samples to the spike peak by adapting its sampling rate, thus combining the good alignment accuracy of a high sampling rate, with the reduced data bandwidth (and power consumption) of a low sampling rate. The core is based on a SAR charge redistribution ADC, which is the topology used in all integrated neural interfaces due to low area and power requirements for low to medium resolution converters. Although adaptive SAR ADCs have previously been reported for neural recording applications \cite{o2011adaptive, huang20121}, these adapt the resolution rather than sampling rate and therefore would not provide benefit to spike alignment as presented herein. + +The paper is organised as follows: Section 3 introduces the concept and system architecture; Section 4 details the circuit implementation; Section 10 describes the simulated results and target specifications; and Section 11 concludes the paper. + +{{< figure src="/images/iscas2014/concept.svg" title="Figure 1: Proposed concept of fine (high sampling rate) peak alignment with coarse (low sampling rate) data output. Shown is: (a) fixed uniform sampling; and (b) proposed adaptive sampling method." width="500" >}} + +# 3 Concept and System Architecture + +The basic idea is to use fine sampling at 64 kHz to locate the spike peak, and then sample the rest of the spike using coarse sampling at 16 kHz. It is essential however, that the coarse sampling is peak-aligned (by adjusting sampling clock phase. The adaptive sampling rate is controlled using threshold-based spike detection. This concept is illustrated in Fig. 1. The system architecture is shown in Fig. 2. This consists of two main sub-systems: the core SAR ADC, and the digital alignment controller; responsible for the spike detection, peak search and detection, and timing/sampling alignment. + +{{< figure src="/images/iscas2014/architecture.svg" title="Figure 2: System architecture of the proposed peak-aligned ADC with adaptive sampling rate." width="500" >}} + +# 4 Circuit Implementation + +The circuit has been implemented as a mixed-signal design in a commercially available 0.35\\( \mu\\)m 2P4M CMOS technology provided by AMS. + +## 5 Digital Alignment Control + +The adaptive sampling algorithm has been implemented in Verilog using a digital design flow. A standard cell based circuit implementation has been realised using Cadence RTL compiler for synthesis and Encounter for place & route. + +The controller, which operates at the 64 kHz clock frequency, consists of 3 main blocks to first detect the spike, then search for and detect the peak and finally to provide the aligned samples to the output register. + +## 6 Spike Detection + +This is achieved using a double threshold detection method as previously illustrated in Fig. 1. This provides the system sensitivity to both positive and negative peaks. The thresholds are externally calibrated after recording and analysing a training dataset. + +## 7 Peak Search & Detection + +The state diagram for the peak search and detection is shown in Fig. 3. Here the concern lies with the noise corrupted neural spike that will present fluctuations around the peak maximum. To avoid detecting these artifacts as multiple peaks, a 4 sample window is used that succeeds the peak sample. Analyzing these samples will indicate whether the signal is still increasing or if the peak maximum has been detected. + +{{< figure src="/images/iscas2014/state2.svg" title="Figure 3: State diagram of the Peak-Search and Detection Algorithm." width="500" >}} + +## 8 Timing Control + +Once the a peak location in confirmed, the data steam is then re-aligned by updating the valid data phase off-set of the down sampled stream and the logic returns to a to the low frequency data monitoring state. In coherence with the spike detection algorithm, data points are continuously throughput at the 16 kS/s rate. Only upon the re-alignment event does the sampling phase at of the data shift. This implies that when the ADC is driven to record at 64kS/s the extraneous data used for aligning will need to be removed from the output steam by means of latching the digital data buffer at valid data times. + +## 9 Analog To Digital Converter + +{{< figure src="/images/iscas2014/sar_adc.svg" title="Figure 4: 9-bit Differential SAR ADC." width="500" >}} + +{{< figure src="/images/iscas2014/clk.png" title="Figure 5: Time Sequencing for a 9-bit Successive Approximation." width="500" >}} + +Fig. 4 illustrated the SAR ADC structure. The topology presented here employs a fully differential binary weighted capacitor array that allows for a highly linear 9-bit output that is driven by standard FSM logic. Moreover the top plate sampling technique will minimize the number of buffered voltage sources required for operation. The fully differential configuration is key for mixed signal systems as a significant amount of noise is rejected from the voltage supplies particularly the common mode of the differential input. The typical timing sequence of 10 cycles for the data converter is illustrated in Fig. 5. The basic binary weighter array is highly insensitive towards mismatch and process variation relative to split cap and C2C structures as parasitics load less significant charge with respect to the net capacitance. This justifies the use of minimum feature size $5 \mu m \times 5 \mu m$ poly-poly unit capacitors that have a capacitive value of 23.22fF. + +The successive approximation is initiated by sampling the differential input on the top plate of the two capacitor banks and tying the bottom plates the the respective positive and negative reference supplies \\(GND\\) & \\(V_{ref}\\). This is followed by disconnecting the input from the top plate to allow charge redistribution due to changing the polarity of most significant bit (MSB). Each successive evaluation of the comparator will determine in logical value of the quantization bits in decreasing magnitude. The resulting voltage at the input of the comparator due to digital feedback on the bottom plates may be evaluated by use of charge balance equations. + +A positive evaluation of the comparator after sampling with the MSB set high will imply the differential input is positive and hence the MSB changes polarity and the second to most significant bit is now 1. The following will be true for both differential and single ended signals; + +\\(\\) V_{x} = V_{in} - \frac{V_{ref}}{4} \\(\\) + +A negative evaluation of the comparator implies the differential input is positive and hence both the MSB and the second to most significant bit are now 1. Similarly the following will be true for both differential and single ended signals; + +\\(\\) V_{x} = V_{in} + \frac{V_{ref}}{4} \\(\\) + +Where \\(V_{x}\\) is the resulting voltage at which the input of the comparator settles. It is important to note that due to sampling with the MSB as high this value will is bounded between $GND & Vref$ which is important to prevent forward biasing any diode to substrate. This can be confirmed by considering the input either as slightly higher than \\(V_{ref}/2\\) or as GND. + +{{< figure src="/images/iscas2014/comp.svg" title="Figure 6: Schematic Illustration of Comparator." width="500" >}} + +The edge triggered comparator structure used in this design is illustrated in Fig. 6. This dynamic latch structure allows good trade offs with respect to speed and the off-set as speed is limited by the gate to drain capacitive component on the input transistors (M1 & M2). These transistors are required to be large in order to minimize off-set components while the latching transistor can be minimum feature size to maximize evaluation speed. The kick back noise of the comparator is alleviated as the feed through capacitance of the input pair is not coupled to the differential output and the differential structure of the DAC cancels the common mode switching components of the comparator. The output is buffered by a latch that will absorb the glitches on the evaluation transitions when both outputs float around the middle of the rail. + +The sampling switches are driven by a boot strap circuit [^9] that will drive the gate voltage of the transistor to \\(V_{dd}+V_{s}\\) for a constant over drive voltage of \\(V_{dd}-V_{th}\\). This allow a full dynamic range on the input signal while preventing signal dependent charge injection to be sampled on the top plate. The switch network for the capacitor array employs stacked transmission gates [^10] on the top plates that minimize leakage components which is important for low frequency operation and single complementary transmission gates on the bottom plates that connect the supplies for rapid charge settling. + +# 10 Simulation Results + +Preliminary validation of the proposed implementation has been done through schematic level simulations in the Cadence IC 6.1.5 Design Environment using industry provided PSP models. + +{{< figure src="/images/iscas2014/dnlinl.png" title="Figure 7: Simulated DNL & INL results." width="500" >}} + +The ADC INL & DNL performance in Fig. 7 illustrates the 8.9 effective number of bits (ENOB) accuracy of the converter where the INL is limiting figure of merit. This result was produced using a slow input ramp on the ADC input that is sampled 2048 times across the full 3.3V scale and is aligned with the critical sampling points. The excelent DNL figure is a consequence of not using a split capacitor in the capacitor array. + +The performance of this system is summarized in Table 1. The average power dissipation of the data converter from the 3.3V supply is $3 \mu W$ when processing typical neural activity that contain 200 spikes per second. This results in a respectable 93.3 fJ per conversion Figure of Merit (FOM) for the $0.35 \mu m$ CMOS technology given the control overhead for timing both the ADC and data buffer. Where the FOM is given by; + +\\(\\) \frac{power}{F_{sample} \cdot 2^{ENOB}}\\(\\) + +{{< figure src="/images/iscas2014/result2.svg" title="Figure 8: Simulation Results (top) Analog (bottom) Digital output." width="500" >}} + +The simulated transient results in Fig. 8 demonstrate the dynamic sampling of a neural signal that has been measured in-vivo at both 16kHz as well as 64kHz. It can be observed that both positive and negative peaks are sampled with fine temporal resolution and their respective peak amplitude & position are also recorded accurately. Note that if a second peak is detected outside of the 4 sample window this peak will also be registered as a maxima ans will realign the data according to the last peak event. Although in this case these positions are very close to one another, a larger window buffer may be required for better tolerance towards spikes that occur consecutively. + +Table 1: Data converter Performance Summary}\label{summary +|Reference | [^11] | [^12] | This work | +|----|----|----|----| +|Year | 2007 | 2011 | 2013 | +|Tech. [nm] | 90 | 130 | 350 | +|Power [(\mu)W] | 700 | 1580 | 3.06 | +|Supply [V] | 1 | 1.2 | 3.3 | +|Rate [S/s] | 50M | 50M | 16k (64k) | +|INL [LSB] | \textless 0.6 | - | +0.55/-0.59 | +|DNL [LSB] | \textless 0.6 | - | +0.25/-0.25 | +|FOM [fJ/bit] | 4.5 | 55 | 93.3 | +|Data Reduction | - | - | 70% | + +# 11 Conclusion + +In this paper, we have presented the design of a novel, resource-efficient, 9-bit SAR ADC with adaptive (16/64 kHz) rate for peak-aligned sampling. This strategy has been adopted to improve alignment precision to enable high performance spike sorting. Furthermore, by combining high precision peak-alignment with a reduced (effective) sampling rate in this way, good efficiency is achieved in both power consumption and data bandwidth utilisation. The design reported achieves a FOM of 93.3 fJ/conversion-step in a standard 0.35\\( \mu\\)m CMOS technology which is comparable to the state-of-the-art. Future work will focus on also achieving adaptive spike detection in addition to further optimisation of the peak search and detection algorithm. + +# 12 Acknowledgment + +This work was in part funded by EPSRC grants EP/I000569/1 and EP/K015060/1. The authors would like to thank Song Luan for useful discussion and technical support. + +# References: + +[^1]: I.H. Stevenson and K.P. Kording, ''How advances in neural recording affect data analysis,'' Nature neuroscience, vol.14, no.2, pp. 139--142, 2011. +[^12]: S.-J. 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Lewicki, ''A review of methods for spike sorting: the detection and classification of neural action potentials,'' Network: Computation in Neural Systems, vol.9, no.4, pp. 53--R7, 1998. +[^8]: G.-Y. Huang, S.-J. Chang, C.-C. Liu, and Y.-Z. Lin, ''A 1-$\mu$w 10-bit 200-ks/s sar adc with a bypass window for biomedical applications,'' Solid-State Circuits, IEEE Journal of, vol.47, no.11, pp. 2783--2795, 2012. +[^2]: R.R. Harrison, P.T. Watkins, R.J. Kier, R.O. Lovejoy, D.J. Black, B.Greger, and F.Solzbacher, ''A low-power integrated circuit for a wireless 100-electrode neural recording system,'' Solid-State Circuits, IEEE Journal of, vol.42, no.1, pp. 123--133, 2007. +[^4]: H.Gao, R.M. Walker, P.Nuyujukian, K.A. Makinwa, K.V. Shenoy, B.Murmann, and T.H. Meng, ''Hermese: A 96-channel full data rate direct neural interface in 0.13< formula formulatype=,'' IEEE JSSC, vol.47, no.4, pp. 1043--1055, 2012. +[^3]: A.Bonfanti, M.Ceravolo, G.Zambra, R.Gusmeroli, T.Borghi, A.Spinelli, and A.Lacaita, ''A multi-channel low-power ic for neural spike recording with data compression and narrowband 400-mhz mc-fsk wireless transmission,'' Proc. IEEE ESSCIRC, pp. 330--333, 2010. +[^5]: D.Y. Barsakcioglu, A.Eftekhar, and T.G. Constandinou, ''Design optimisation of front-end neural interfaces for spike sorting systems,'' Proc. IEEE ISCAS, pp. 2501--2504, 2013. diff --git a/content/publications/2014/ultra-low-power-design-strategy-for-two-stage-amplifier-topologies.md b/content/publications/2014/ultra-low-power-design-strategy-for-two-stage-amplifier-topologies.md new file mode 100644 index 0000000..c5567be --- /dev/null +++ b/content/publications/2014/ultra-low-power-design-strategy-for-two-stage-amplifier-topologies.md @@ -0,0 +1,115 @@ +--- +title: "Ultra-low power design strategy for two-stage amplifier topologies" +date: 2014-05-08T15:26:46+01:00 +draft: false +toc: true +math: true +type: posts +tags: + - publication + - instrumentation + - analogue + - circuits +--- + +Lieuwe B. Leene, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# Abstract + +This letter presents a novel two stage amplifier topology and ultra low power design strategy for two stage amplifiers that utilises pole zero cancellation to address the additional power requirements for stability. For a 288nA total bias, the presented amplifier achieves a 1.07 MHz unity gain frequency with a 8560 pF MHz/mA figure of merit. + +# 1 Introduction + +Power efficient amplifier topologies are fundamental analogue processing both in the continuous and discrete time domains. The feasibility of a system is often established using a relevant figure of merit (FOM) that quantifies performance. The prevalence of limited power budgets in medical sensors indicates that advances in low power analogue are critical for the future of implantable biomedical systems that are constrained through battery life and wireless telemetry [^1] [^2]. Ultra low power analogue design is best motivated through aggressively maximising a FOM that indicates how effectively power is used to achieve a desired performance characteristic such as noise, speed, or linearity in order to reveal the underlying limitation. + +Taking the differential pair in Fig. 1 for example to illustrate the driving motivation behind sub-threshold operation. The FOM with all transistors in strong inversion can reduced to a single operational parameter; + +$$ FOM_{si} \left[ \frac{pF \cdot MHz} {mA} \right] = \frac{UGF \cdot C_{L}}{I_{total}} = \frac{10^{3}}{2 \pi V_{ov}} $$ + +Where \\(UGF\\), \\(C_{L}\\), \\(I_{total}\\), and \\(V_{ov}\\) are the unity gain frequency, load capacitance, total bias current, and over drive voltage of the input transistors respectively. With the input transistors biased in weak inversion however the FOM is derived as; + +$$ FOM_{wi} = \frac{10^{3}}{4 \pi \cdot \eta U_{T}} $$ + +With \\(\eta\\) & \\(U_{T}\\) being the sub-threshold slope factor and thermal voltage respectively. With \\(V_{ov}\\) usually being 200mV, operation in weak inversion can directly improve the FOM by 6 times. In addition to sub-threshold biasing a number of current recycling techniques can be applied to further gain in FOM [^3]. By coupling the input signal to biasing transistors \\(M_{3-4}\\) for instance, a larger transconductance can be achieved with the same bias current. This allows a simple reduction in power by a factor of two for single stage systems, but a second stage is often required in switched capacitor (SC) applications for high gain and wide output swing. The constraint of the second stage lies with the non-dominant pole at the output that needs to lie beyond the unity gain frequency. The output load capacitance dictates the minimum transconductance of the second stage and will often result in the second stage dissipating significantly more power than the first stage. In this letter, we propose zero cancellation of this non-dominant pole in order to minimise power dissipation in the second stage. Secondly, we identify appropriate scaling factors for the FOM such as to make this applicable to two stage amplifiers. + +{{< figure src="/images/el-opamp/TB.png" title="Figure 1: circuit schematics for: (a) simple differential pair with differential output; (b) unity feedback configuration used for testing the transient step response of a fully differential amplifier. " width="500" >}} + +# 2 Proposed amplifier + +The circuit configuration is shown in Fig. 2. This differential topology extends the complementary input stage with a current conveyor (CC) structure to achieve high gain and wide output swing. The high open loop gain is provided by the cross coupled PMOS devices \\(M_{11-14}\\) in addition to the traditional gain stage \\(M_{19-22}\\) that also allows for a rail to rail output swing. The circuit is configured to drain the same amount of current in the output branch as in the input transistor pair such that the transistors \\(M_{1-6}\\) \& \\(M_{19-22}\\) have a transconductance \\(gm_{1}\\). The cross coupled PMOS branch drains a fraction (1/M = 0.25) of this same current such that the total current dissipated by the amplifier is \\(2I_{M1} \cdot (2 + 1/M)\\). The NMOS current mirror \\(M_{15-18}\\) implements a wideband positive feedback loop with a ratio of 1:N-1 where N = 1.5 to boost the bandwidth of the structure. Note that transistors \\(M_{23-24}\\) bias the input stage through common mode feedback and transistors \\(M_{7-10}\\) bias the output stage. The input transistors \\(M_{1-6}\\) are biased with a drain current \\(I_{input}\\) of 50nA with a 1.2V supply. This biasing current in addition to the ratio \\(M\\) determine the observed single ended slew rate (SR) at the output as it is limited by the low gain path in the NMOS current mirror. In the step response scenario the current drained by \\(M_{23}\\) sources entirely into \\(M_{15}\\) \\(M_{18}\\) which is multiplied to \\(M_{19}\\) \\(M_{20}\\) by a factor \\(M\\), that is; + +$$ SR = M \cdot \frac{2 I_{input}}{C_{L}} $$ + +{{< figure src="/images/el-opamp/CC.png" title="Figure 2: Circuit schematic of the proposed amplifier topology including the input stage (on left) and CC stage (on right). Vp & Vn are externally provided DC biasing voltages. " width="500" >}} + +For preliminary design considerations it is useful to assess the dependence of different component parameters through the open loop gain, unity gain frequency, pole and zero locations with simple approximations. First it should be noted the bandwidth product is twice as large as a conventional amplifier though current recycling in the complementary input transistor pairs and evaluated as; + +$$ UGF = \frac{gm_{1} }{ \pi \cdot C_{F}} $$ + +Where \\(C_{F}\\) is a 500 fF compensation capacitor that couples the output to the input stage via a low impedance node in the NMOS differential pair utilising split length indirect compensation, thus avoiding the right hand plane pole [^4]. With \\(\lambda\\) as the channel length modulation parameter the open loop DC gain is evaluated as; + +$$ A_{dc} \approx NM \left( \frac{1}{\eta U_{T} \lambda} \right)^{2} $$ + +Furthermore in the midband frequencies the Miller capacitor \\(C_{F}\\) performs pole splitting both poles in the CC stage through the feedback loop. This will move the pole at the cross coupled PMOS outside the UGF, more specifically \\(\omega_{p2}\\), and move the pole due to \\(C_{L}\\) towards; + +$$ \omega_{p1} \approx \frac{2M \cdot gm_{1}}{C_{L} + C_{z}} $$ + +If \\(gm_{1}\\) is kept small this pole will remain in-band of the amplifier. For adequate phase margin that is larger than \\(65^{\circ}\\), to prevent excess ringing at the output, we use pole zero cancellation. With \\(\omega_{p1} = \omega_{z}\\), \\(C_{z}\\) is determined according to; + +$$ \omega_{z} \approx \frac{gm_{M15} \cdot (2-N)}{ C_{z}} $$ + +\noindent Past the zero location, the signal path loads into the diode-connected NMOS \\(M_{15}\\) that now drives both \\(M_{21}\\) & \\(M_{19}\\) pushing out the unity gain frequency. With \\(C_{gs}\\) as the total gate capacitance from both NMOS & PMOS current mirrors and taking \\(C_{z}\\) as a short circuit, the pole location \\(\omega_{p2}\\) can be confirmed to lie outside the unity gain frequency; + +$$ \omega_{p2} \approx \frac{2 gm_{1}}{C_{gs}} $$ + +$$ FOM \approx \frac{10^{3}}{4 \pi \cdot \eta U_{T}} \cdot \frac{2 \cdot C_{F}/C_{L}}{2 + 1/M} = 3.56 \times FOM_{wi} $$ + +As a result, when the FOM is reformulated (see above) for this particular configuration, it can be observed that this is increased, compared to the conventional single stage topology. A significant contribution of this improvement in FOM naturally comes from the factor \\(C_{F}/C_{L}\\) as a reduction in the dominant capacitive load allows a overall reduction in bias current to achieve a given bandwidth. This also illustrates that relative to a single stage, a two stage configuration may trade off noise for a better FOM by adjusting the \\(C_{F}/C_{L}\\) ratio. As the total input referred integrated thermal noise \\(e^{2}_{in}\\) for a single pole system is related to the capacitor \\(C\\) that introduces the dominant pole of the system through: + +$$ e^2 = \frac{ kT }{C} \frac{ kT NEF^{2} \cdot I_{input}}{ \eta A_{cl} I_{total} } $$ + +Which is directly derived from the definition of the noise efficiency factor (NEF) [^5] by substituting the expression for bandwidth as the closed loop gain \\(A_{cl}\\) multiplied by UGF. + +{{< figure src="/images/el-opamp/results4.png" title="Figure 3: Simulation Results: (a) open loop frequency response (b) closed loop step response of differential signals (c) input referred noise density." width="500" >}} + + +Table 1: Performance Summary +|Reference |[^6] |[^7] |[^4] | This work | +|----|----|----|----|----| +|Year |2009 |2010 |2010 | 2013 | +|Tech. [nm] |180 |180 |500 | 180 | +|Power [W] |5.5m |600Ī¼ |1.2m | 345n | +|Supply Voltage [V] |1.2 |1.5 |3 | 1.2 | +|DC Gain [dB] |85 |59 |82 | 96 | +|UGF [MHz] |450 |111 |20 | 1.07 | +|Slew Rate [V/Ī¼s] |- |233 |8 | 0.12 | +|Load/Miller [pF] |-/3 |5 |5, 0.2/500 | 2/0.5 | +|Phase Margin [Ā°] | 68 | 80 | 72 | 64 | +|Noise Floor [V/āˆšHz] |- |125n | - | 60n | +|FOM [MHz pF/mA] |295 |1267 |8333 | 8560 | + +# 3 Simulation Results + +Preliminary validation of the proposed implementation has been achieved using schematic level simulations in the Cadence IC 6.1.5 Design Environment using industry provided transistor models for the commercially available 6 Metal 0.18 Ī¼m CMOS technology (AMS/IBM C18A6/7SF). Fig. 3 shows key simulation results, including small signal, transient, and noise characteristics. The common mode feedback configuration used in these simulations is a conventional differential difference amplifier with a current mirror to drive both M23 & M24 transistors biasing the input stage simultaneously. In order to normalise performance with respect to requirements on the common mode feedback circuit its 45nW power contribution is excluded in FOM calculations. The simulated frequency characteristics were close to the analytical expectation achieving a 1.07MHz unity gain frequency and a phase margin of 64 degrees. The step response indicates settling of the output to <0.1 % within 10 Ī¼s with the feedback configuration illustrated in Fig. 1. The configuration also demonstrates good noise performance as the input transistors have a larger transconductance than the first active load by a factor of M for a smaller input referred noise figure. The 60 nV/āˆšHz input referred thermal noise floor from 100kHz to 1MHz is good for auto zeroing SC topologies that rejects the flicker noise and low frequency aggressors. + +# 4 Conclusion + +The application of pole zero cancellation for achieving ultra low power in two stage amplifier has been demonstrated. In addition the Miller to load capacitor ratio and current recycling have been discussed as techniques to improve the FOM with the respective trade off. The overall performance characteristics are summarized in table 1. This demonstrates comparable performance to state of the art three stage nested miller systems in terms of FOM in addition to a 345nW power budget that is well within the power constraints of many biomedical analogue processing applications. The proposed topology achieves a 3.56 times improvement in FOM over conventional single stage structures. + +# 5 Acknowledgment + +This work was supported by the UK EPSRC (grants EP/I000569/1 and EP/K015060/1). + +# Refernces: + +[^1]: A.Eftekhar, E.P. Sivylla, and G.C. Timothy, ''Towards a next generation neural interface: Optimizing power, bandwidth and data quality,'' in IEEE Proc. BIOCAS, 2010, pp. 122--125. +[^2]: W.Wattanapanitch and R.Sarpeshkar, ''A low-power 32-channel digitally programmable neural recording integrated circuit,'' IEEE Trans. Biomed. Circuits Syst., vol.5, no.6, pp. 592--602, 2011. +[^3]: R.Assaad and J.Silva-Martinez, ''Enhancing general performance of folded cascode amplifier by recycling current,'' IET Elec. Letters, vol.43, no.23, 2007. +[^4]: V.Saxena and R.J. Baker, ''Indirect compensation techniques for three-stage fully-differential op-amps,'' in IEEE Proc. MWSCAS, 2010, pp. 588--591. +[^5]: R.Harrison and C.Charles, ''A low-power low-noise cmos amplifier for neural recording applications,'' IEEE J. Solid-State Circuits, vol.38, no.6, pp. 958--965, 2003. +[^6]: M.Fan, J.Ren, Y.Guo, Y.Li, N.Li, F.Ye, and J.Xu, ''Low-voltage low-power operational amplifier for sc circuits,'' IET Elec. Letters, vol.45, no.25, pp. 1274--1276, 2009. +[^7]: M.Yavari, ''Single-stage class ab operational amplifier for sc circuits,'' IET Elec. Letters, vol.46, no.14, pp. 977--979, 2010. diff --git a/content/publications/2015/a-novel-neural-recording-system-utilising-continuous-time-energy-based-compression.md b/content/publications/2015/a-novel-neural-recording-system-utilising-continuous-time-energy-based-compression.md new file mode 100644 index 0000000..560f25c --- /dev/null +++ b/content/publications/2015/a-novel-neural-recording-system-utilising-continuous-time-energy-based-compression.md @@ -0,0 +1,14 @@ +--- +title: "A novel neural recording system utilising continuous time energy based compression" +date: 2015-05-24T15:26:46+01:00 +draft: true +toc: true +type: posts +math: true +tags: + - publication + - instrumentation + - CMOS + - biomedical + - sampling +--- diff --git a/content/publications/2015/continuous-time-micropower-interface-for-neural-recording-applications.md b/content/publications/2015/continuous-time-micropower-interface-for-neural-recording-applications.md new file mode 100644 index 0000000..b2cf895 --- /dev/null +++ b/content/publications/2015/continuous-time-micropower-interface-for-neural-recording-applications.md @@ -0,0 +1,173 @@ +--- +title: "Continuous-time micropower interface for neural recording applications" +date: 2015-10-16T15:26:46+01:00 +draft: false +toc: true +type: posts +math: true +tags: + - publication + - instrumentation + - CMOS + - biomedical +--- + +Marios Elia, Lieuwe B. Leene, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +This paper presents a novel amplifier architecture intended for low power neural recording applications. By using continuous-time signal representation, the proposed topology predominantly leverages digital circuits and is thus well-suited for scaling to new technologies. +This includes digital integration providing direct quantization of the input voltage and superior filtering. Schematic-level simulations demonstrated the amplifier's bandwidth to be 6 kHz, with highly linear full dynamic range output. Achieving a static power consumption of 1.145 Ī¼W from a 0.5V supply voltage with an input referred thermal noise of 7.7 Ī¼Vrms. + +# 2 Introduction + +Recent advancements in neuroscience have enabled simultaneous activity monitoring from multiple neurons, creating the need for fully implantable multi-neuron recording. Next-generation implanted systems must be able to simultaneously monitor between 100 and 1000 neurons [^1]. With neural signals being as small as 30 Ī¼V, a dedicated low-noise amplifier (LNA) is required for each electrode. However, implantable devices have restricted power budget so that tissue cells are not destroyed by the generated heat. It is therefore suggested that front-end amplifiers should dissipate no more than 2 Ī¼W. Thus, a trade-off between noise performance and power consumption emerges as thermal noise is directly related to bias current. + +Utilising a current-mirror OTA topology with weakly-inverted PMOS inputs, authors of [^1] where able to achieve an input referred noise of 2.2 Ī¼V integrated over 0.25 Hz - 7 kHz. However, the amplifier dissipated 80 Ī¼W of power, potentially exceeding thermal-dissipation safe limits if scaling to hundreds of channels. + +Extracellularly recorded neural action potentials have amplitudes in the range of 30 Ī¼V - 500 Ī¼V and frequency content in 100 Hz- 7kHz spectrum. On the other hand, local-field potentials can be as large as 5mV with energy present in sub-Hz frequencies, putting a system's dynamic range (DR) to the test. Moreover, electrodes demonstrate DC offsets up to 2 V [^1], requiring the integration of a sub-Hz high-pass filter. The design is further challenged by technological scaling; shrinking devices lead to reduced transistor impedances requiring higher power to maintain intrinsic gain and linearity. + +Reduced DC gain can be effectively mitigated by the use of voltage controlled oscillator (VCO) based integrators [^3], [^4]. Furthermore, VCO-based topologies preserve signal information in the time domain allowing for very large dynamic range (DR). Similarly, authors of [^5] propose a switched-mode Op-Amp with a class-D output stage. The two-level operation renders the system inherently more linear, alleviating the linearity-power consumption trade-off. It is therefore beneficial to devise architectures based on these digital circuits, suited to fabrication using digitally-oriented CMOS technology. This is further motivated by the fact that biomedical instrumentation applications make extensive use of Digital-Signal Processing (DSP). + +This paper presents the implementation of a low-power, VCO-based amplifier for neural recording applications. The system encodes information in time domain by utilising differential oscillators. A Phase-Frequency Detector (PFD) detects relative phase/frequency variations and generates high-frequency UP/DN pulses. An up/down binary counter integrates the PFD output and tracks the quantization of the signal; the binary value is now ready for digital processing. +The remainder of the paper is organised as follows. Section II introduces and analyses the proposed system architecture with circuit implementation presented in section III. Section IV demonstrates simulated results followed by conclusions in Section V. + +# 3 Concept and System Architecture + +The proposed amplifier architecture is shown in Fig 1. A fully differential Gm-cell integrates the residue signal, on the Miller-equivalent capacitance, and drives the VCO blocks. + +A digitally registered integrator rejects high frequency harmonics and produces the system's quantized output. This integrator is implemented with a 9-bit binary up/down counter that is driven by events generated by the PFD. The asynchronous behaviour prevents down modulation of coherent noise in the system and quantization from producing strong tones in band. Finally all active integration nodes feedback to through a charge-scaling capacitive array. Utilizing multi-pathing of signal components, this topology attempts to reject out of band noise in the GM-VCO signal loop such that the band limited counter output contains a clean signal band without needing in large band limiting capacitors. + +## 4 Amplifier Compensation + +A pole is contributed to the transfer function, by each of the following stages; Gm-cell, VCO and counter integrator. Feed-forward compensation is achieved by capacitively coupling the PFD output to the charge-scaling array output with gain Av. As such, a zero is introduced in the transfer function, cancelling the effect of the counter-contributed pole. The amplifier is then approximated by a two-pole system allowing for Miller compensation. The Miller equivalent of CM places a DC pole at the output of the Gm-cell and pushes the VCO pole to higher frequencies. Laplace-domain analysis yields the system's transfer function; Eq. 1. + +$$ H(s) = Gm\frac{1+\frac{s}{\omega_{z}}}{s(1+\frac{s}{\omega_{p2}})} $$ + +$$ \omega_z = A_{v}K_{INT},\ \omega_{p1} = DC $$ + +$$ \omega_{p2} = \frac{1+C_{M}A_{v}K_{VCO}K_{PFD}K_{INT}}{C_{M}K_{VCO}K_{PFD}} $$ + +The amplifier has sufficient phase margin (PM) if \\(\omega\\)p2 and \\(\omega\\)z are very close in the frequency response, cancelling each other out. This will be satisfied if CMAvKVCOKPFDKINT >> 1, reducing \\(\omega\\)\textsubscript{p2} to AvKINT. The transfer function can then be approximated to \\(\frac{Gm}{s}\\) suggesting a single pole system and ideal integrator behaviour near DC. + +{{< figure src="/images/iscas2016/system.svg" title="Figure 2: System Architecture with unit capacitor as 4 fF." width="500" >}} + +It should be noted that KINT is input-dependent, in other words the integrator's gain dynamically changes when the amplifier is slewing. Nonetheless, both \\(\omega\\)\textsubscript{p2} and \\(\omega\\)z are a function of KINT thus, the system's overall transfer function is not affected. + +## 5 Topological Advantages + +The amplifier's digital nature offers a number of benefits compared to the analogue equivalent. As technology scales, propagation delays and power consumption are also expected to scale down offering increased performance. Moreover, reduced input capacitance yields higher input impedance. This is particularly useful in biomedical LNAs, as tissue built-up increases the electrode's impedance with time [^7]. + +Another key advantage, is that the binary counter continuously quantizes the input signal. As such the system's output is compatible with arbitrary & event-based processing rates. The circuit contains a minimal number of analogue nodes; the input node and the Gm-cell's output node. External and internal feedback ensure negligible voltage swing on all nodes. Resulting in minimal linearity restrictions by the power rails allowing the use of very low supply voltage. + +Signal quantisation is performed in closed-loop. As such, quantization noise and non-linearities, induced by the counter-DAC combination, are shaped and pushed to higher frequencies. With distortion being suppressed by the internal feedback, aggressive reduction of the capacitors used in the charge-scaling array is allowed. + +Another mechanism that improves noise performance results from the feed-forward stage Av. As it bypasses the counter circuit, any high frequency noise, generated by the Gm-cell and VCO circuits, will bypass the counter and propagate through the feedback loop. Thus, only low frequency noise components will reach the system's digitised output. As such, it is essential to maintain signal specific counter bandwidth. + +# 6 Circuit Implementation + +The circuit has been designed and simulated in a 0.18 Ī¼m CMOS process provided by AMS (H18A4). A circuit-level analysis of the system blocks follows. + +## 7 Gm-cell + +The first stage is implemented using a differential pair topology, Fig. 2. + +{{< figure src="/images/iscas2016/1.svg" title="Figure 3: Gm-cell" width="500" >}} + +For DC signals, devices M1 and M3 behave as diode-connected transistors, providing a well-defined output biasing as well as the high-pass DC off-set rejection cut off at 1 Hz. Noise analysis reveals that thermal noise is inversely proportional to device transconductance. By AC coupling the input signal to both NMOS and PMOS devices, the circuit's transconductance efficiency is significantly boosted. Small-signal analysis yields the circuit's transfer function; Eq. 2. + +$$ H(s) = Gm\frac{r_{O}}{1 + sr_{O}C^{eq}_{M}} $$ + +$$ Gm = g_{m1} + g_{m2},\ r_O = r_{O1}//r_{O2} $$ + +$$ C^{eq}_{M} = C_{M} \frac{K_{VCO}}{s} K_{PFD} ( \frac{K_{INT}}{s} + \frac{1}{A_{v}} ) $$ + +Eq. 2 reveals that the finite output impedance of MOSFET devices, pushes the first stage pole to frequencies higher than DC. However, owed to the nearly infinite gain provided by the second stage integrators, the Miller capacitor will appear very large, pushing the pole back to very low frequencies. + +## 8 Voltage-Controlled Oscillator + +The implemented VCO circuit is shown in Fig. 3. Devices M2 and M3 form an inverter-based ring-oscillator. The oscillator's frequency is a linear function of the current it sinks and it is given by Eq. 3 [^8]. + +$$ f_{OSC} = \frac{I_{DS}}{N C_{TOT} VDD} $$ + +N being the number of inverter stages and CTOT the total capacitance per inverter stage. Device M1 directly controls the oscillator's frequency by modulating the current available to it. The circuit's gain is then given by + +$$ K_{VCO} = 2\pi \frac{g_{m1}}{N C_{TOT} VDD} [radians V^{-1} s^{-1}] $$ + +{{< figure src="/images/iscas2016/4.svg" title="Figure 4: Voltage-Controlled Oscillator" width="500" >}} + +Transistor M4 is biased in the triode region acting as a level shifter. It serves a dual purpose by ensuring correct biasing of device M6 and isolating the oscillator from high frequency noise present on the ground rail. + +## 9 Phase-Frequency Detector + +The circuit of the 3-state PFD utilised is shown in Fig. 4(a) [^9]. It is based on True-Single Phase Logic and its operation principle follows. Assuming VCO1 and VCO2 are low, nodes U1 and D1 are pre-charged to VDD via M1. On the rising edge of VCO1, M5 turns ON, and the dynamic inverter formed by M4 and M6 pull node U2 down causing UP signal to rise. On the rising edge of VCO2, DN signal also rises. M2 and M3 discharge nodes UI and D1 thus UP and DN signals are also pulled down. The circuit has returned to its initial condition [^9]. It should however be noted that to ensure reset of UP/DN signals at equal instances, IDS2,3 >> IDS1 must be satisfied. + +Maximum output voltage is produced when the two input signals are perfectly out-of-phase; that is, they are 2\\(\pi\\) apart. The circuit's gain is then defined as KPFD = 1/2\\(\pi\\). + +{{< figure src="/images/iscas2016/pfd_2.svg" title="Figure 5: (a) PFD circuit (b) SIGN bit generation" width="500" >}} + +## 10 Counter Driving Circuit + +Clock generation is achieved by the circuit in Fig. 5(a). Two edge-detector circuits generate pulses of well-defined width, at every rising edge generated by the VCOs. The pulses propagate through the OR, driving the DFF, to the divide-by-two circuit. Thus, the generated clock's frequency is the average of the two VCOs'. + +{{< figure src="/images/iscas2016/clk_circuit.svg" title="Figure 6: (a) CLK circuit generation (b) 2-state to 3-state signal conversion" width="500" >}} + +The circuit of Fig. 4(b) illustrates the PFD implementation. DFF1 detects the leading signal and accordingly registers a logic output. DFF2 ensures that the SIGN bit can only change after the clock's rising edge. As such, the SIGN bit is always stable when the counter registers its value, avoiding metastability issues. + +The SIGN bit is also used to convert the 2-state UP/DN outputs to 3-state signals. This is achieved by using the SIGN bit to determine whether the signal oscillates between -1 and 0 or 0 and +1. By increasing the available logic levels, the maximum quantisation noise present on the signals is reduced improving system dynamics. The circuit implementing this function is shown in Fig. 5(b). The 3-state signals are now fed forward to the output node in order to introduce a zero in the transfer function and satisfy the stability requirements mentioned in Section II. %cancelling the effect of the output pole. %State +1 is represented by the binary value 11, zero by 01 and -1 by 00. + +## 11 Integrator + +The binary counter's building element is a Toggle Flip-Flop and a multiplexer; the multiplexer being controlled by the SIGN bit. Each TFF will toggle or hold its state, depending on the value presented to it by the multiplexer. + +The counter's binary value is converted to an analogue signal by a charge-scaling capacitive array. The integrator's transfer function can be derived as follows. Each time the counter increments its value, the output voltage increases by VDD/2N; N being the number of binary bits. Approximating the output voltage by a ramp, it is given by + +$$ V_{out}(t) = \frac{V_{DD}}{2^{N}}t\times u(t)\times f_{OSC} $$ + +yielding the following transfer function + +$$ \frac{\Delta V_{out}}{\Delta\Phi_{in}}(s) = \frac{V_{DD}}{2^N}\times \frac{f_{OSC}}{\Delta\Phi_{in}}\times \frac{1}{s} $$ + +Eq. 6 suggests that the integrator's transfer function is input dependent as stated in Section II. + +# 13 Simulated Results + +The design was simulated in Cadence IC 6.1.5 Design Environment, using foundry-supplied PSP models. Owed to the circuit's dynamic time domain behaviour, only transient noise simulations can correctly predict system performance. As such, the provided bode plots were generated by simulating the linearized system transfer function. + +{{< figure src="/images/iscas2016/bode.svg" title="Figure 8: Frequency response of linearised model" width="500" >}} + +Fig. 6 demonstrates the system's frequency response revealing a closed loop 40dB voltage gain. The system's static current consumption is measured to be 2.29 Ī¼A from a 0.5V supply voltage yielding a power dissipation of 1.145 Ī¼W. Spectrum analysis of the output for a 2kHz, 5mV peak-to-peak input signal is shown in Fig. 7. The input referred noise floor of the transconductance state evaluated at 100nV/āˆšHz with the corner frequency at 1 kHz. High levels of flicker noise can be mitigated with common signal chopping techniques. Table I summarises system performance and compares with a typical analogue design. The used figure-of merit is defined by Eq. 7. + +$$ FoM = v_{ni,RMS}\sqrt{\frac{2I_{TOT}V^2_{DD}}{\pi U_{T} 4KT\times BW}} $$ + +Table 1: Performance Comparison +| Parameter | This work |[^1]| +|----|----|----| +|Power [Ī¼W] | 1.14 | 80 | +|Supply [V] | 0.5 | Ā±2.5 | +|Bandwidth [Hz] | 1- 6k | 25m-7.2k | +|THD [%] | 1.05 | 1 | +|Noise [Ī¼Vrms] | 7.7 | 2.2| +|Figure of Merit | 2.25 | 20| + +# 14 Conclusion + +A novel amplifier architecture is proposed, that makes extensive use of digital circuits attempting to overcome the issues resulting from technological scaling. By encoding and processing the information in time-domain, the system's DR is no longer restricted by the power rails. As such the entire system operates from a supply voltage of 0.5V consuming 2.29 Ī¼A of current. + +The complementary input stage increases the circuit's transconductance efficiency while the capacitive feedback applied to the second stage ensures superior low voltage integration characteristics owed to the feedback mechanics. The output capacitive DAC, artificially increases closed loop gain of the second stage, further relaxing the noise-bandwidth trade-off as both depend on input transconductance. Lastly, the noise shaping on the output guarantees relaxed requirements in supply noise, capacitor matching while retaining linearity under very low supply voltages. Based on an event driven design, utilisation of Continuous-Time DSP could prove especially advantageous for this particular system [^6]. + +# Refernces: + +[^1]: R.R. Harrison and C.Charles, ''A Low-Power Low-Noise CMOS Amplifier for Neural Recording Applications,'' IEEE JSSC, vol.38, no.6, pp. 958--965, 2003. +[^2]: S.I. Chang and E.Yoon, ''A 1$\mu$W 85nV/āˆšHz pseudo open-loop preamplifier with programmable band-pass filter for neural interface system,'' Proc. IEEE EMBS Conf., pp. 1631--1634, 2009. +[^3]: B.Drost, M.Talegaonkar, and S.Member, ''Analog Filter Design Using Ring Oscillator Integrators,'' IEEE JSSC, vol.47, no.12, pp. 3120--3129, 2012. +[^4]: C.-w. Hsu and P.R. Kinget, ''A 40MHz 4th-order Active-UGB-RC Filter using VCO-Based Amplifiers with Zero Compensation,'' pp. 359--362, 2014. +[^5]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-Mode Operational Amplifiers and Their Application to Continuous-Time Filters in Nanoscale CMOS,'' IEEE JSSC, vol.49, no.12, pp. 2758--2772, 2014. +[^6]: Y.Tsividis, ''Continuous-time digital signal processing,'' Electronics Letters, vol.39, 2003. +[^7]: J.Xu, T.Wu, W.Liu, and Z.Yang, ''A frequency shaping neural recorder with 3 pF input capacitance and 11 plus 4.5 bits dynamic range,'' IEEE BIOCAS, vol.8, no.4, pp. 510--527, 2014. +[^8]: R.J. Baker, CMOS Circuit Design, Layout and Simulation, 3rded.\hskip 1em plus 0.5em minus 0.4em elax JOHN WILEY & SONS, 2010. +[^9]: B.Lee and L.Siek, ''A CMOS Phase Frequency Detector for Charge Pump Phase-Locked Loop,'' Electronic Engineering, pp. 5--8, 1999. diff --git a/content/publications/2016/a-0-45-v-continuous-time-domain-filter-using-asynchronous-oscillator-structures.md b/content/publications/2016/a-0-45-v-continuous-time-domain-filter-using-asynchronous-oscillator-structures.md new file mode 100644 index 0000000..c03f212 --- /dev/null +++ b/content/publications/2016/a-0-45-v-continuous-time-domain-filter-using-asynchronous-oscillator-structures.md @@ -0,0 +1,119 @@ +--- +title: "A 0.45 V continuous time-domain filter using asynchronous oscillator structures" +date: 2016-12-11T15:26:46+01:00 +draft: false +toc: true +type: posts +math: true +tags: + - publication + - instrumentation + - CMOS + - time-domain + - asynchronous +--- + +Lieuwe B. Leene, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +This paper presents a novel oscillator based filter structure for processing time-domain signals with linear dynamics that extensively uses digital logic by construction. Such a mixed signal topology is a key component for allowing efficient processing of asynchronous time encoded signals that does not necessitate external clocking. A miniaturized primitive is introduced as analogue time-domain memory that can be modelled, synthesized, and incorporated in closed loop mixed signal accelerators to realize more complex linear or non-linear computational systems. This is contextualized by demonstrating a compact low power filter operating at 0.45 V in 65 nm CMOS. Simulation results are presented showing an excess of 50 dB dynamic range with a FOM of 7 fJ/pole which promises an order of magnitude improvement on state-of-the-art filters in nanometre CMOS. + +# 2 Introduction + +The challenges for advancing digital devices and energy constrained computation no longer exhibit the coherent virtues dictated by Moore's Law[^1]. Instead current research is driven to find new solutions inspired by the natural world for solving problems that are dissonant with today's computational paradigm. This has led to the re-emergence of processing in the analogue domain as accelerator to the digital framework [^2]. Motivated by the fact that when tailored to a specific computational problem analogue efficiency can be vastly superior to its digital equivalent [^3][^4]. However there remain many challenges that prevent a clear advantage for such architectures in practice. Current state-of-the-art demands fully integrated SOCs in nanometre CMOS for a cost effective solution. This substantially degrades analogue performance in addition to the difficulty in miniaturizing analogue elements. More importantly analogue tends to drastically lose fidelity for near threshold supply voltages which is an essential aspect to ultra low power digital systems [^5]. To address such challenges oscillator based topologies have been proposed in association with a new computational paradigm [^6][^7]. There are two critical advantages that such an approach can leverage. The first is that the signals pertaining to these systems are digital in nature where the information is encoded with respect to the timing between logical events equivalent to clock edges. This implies that a single binary bit stream can represent multiple bits of information artificially increasing the density of CMOS interconnect. Moreover such signals allow them selves to be manipulated by standard logic gates and asynchronous digital controllers for very rich yet highly efficient signal control[^8]. The second aspect is that voltage controlled oscillators suffer very little performance degradation from aggressive technology scaling or poor transistor characteristics. In fact the perpetual improvement fT increases the maximum temporal resolution achievable using time-domain quantizers for unparalleled dynamic range. + +{{< figure src="/images/icecs2016/td_system.svg" title="Figure 1: Oscillator based computing to realize linear and non-linear dynamics that utilize a phase domain state as memory." width="500" >}} + +In an effort to explore the potential of such a modality this work considers the use of oscillator structures for processing neural activity in extension to a previously developed oscillator based instrumentation system in [^9]. As implantable brain machine interfaces present one of the most demanding applications for realizing power efficient structures that acquire and classify neural activity to treat neurophysiological disorders. The ring oscillator concept shown in Fig. 1. This oscillator plays the role of analogue memory by retaining a state in the phase domain. A transconductive element adjusts the phase subject to the digital control signals. The digital logic dictates the overall response of the structure by using single or multiple phases of the oscillator. This presents negative feedback that stabilizes the operation of the system by rejecting frequency off-sets and noisy aggressors external to the circuit. As will be demonstrated this closed loop dynamic has true analogue aliasing properties due to the nature of VCO based integration. This implies that any logical approximations that induce errors or distortion at high frequency can be rejected. This paper is organized as follows. The basic aspects of the filter architecture is introduced in Sec. 3. This is followed by the circuit level implementation that is detailed in Sec. 4. Sec. 5 presents preliminary simulation results which are concluded upon in Sec. 7. + +# 3 Ring Oscillator based Filter + +{{< figure src="/images/icecs2016/TD_L1.svg" width="500" >}} + +{{< figure src="/images/icecs2016/TD_L1.svg" title="Figure 2: Proposed Single pole ROF structure where VR represents the only analogue node in the system. " width="500" >}} + +A first order realization of this Ring Oscillator based Filter (ROF) is presented in Fig. 2. This simpler structure will allow the discussion to give insight the elementary operation. Here the digital signals D and Q are pulse width modulated (PWM) encoded time domain signals and are typically not modulated using the same carrier frequency. In essence a digital adder injects current into the oscillator such that the phase recedes or advances with respect another local oscillator by comparing the two pulse width components of D & Q. By using a differential structure the phase can be encoded as self referenced timing events that do not require global frequency synchronization to decode phase information. It is also important to note this structure differs characteristically from classic literature examples [^10] but remain very useful for analysis. This discrepancy arises from sub-threshold and current starved operation of the oscillator which implies that the conduction phases of the NMOS and PMOS transistors for each inverter are non-overlapping. In a general sense however the output voltage Vout of the structure is often modelled as: + +$$ V_{out} (t) = A(t) \cdot f\left[ \omega_0 t + \phi(t) \right] $$ + +$$ \phi (t) = \int_{-\infty}^{\infty} h_{\phi}(t,\tau) i(\tau) \: d\tau = \int_{-\infty}^{t} \Gamma(\omega_0 , \tau) i(\tau) \: d\tau $$ + +In Eq. 1 A and \pphi represent the amplitude and phase state variables of the system as a function of time. \\(f\\) describes the limit cycle of the oscillation that captures the non-linearities of Vout as a function of phase. Our primary interest lies with Eq. 2 which captures the dependency of phase with respect to the impulse response h\pphi and the cyclo stationary impulse sensitivity function (ISF) \gGamma. \gGamma is evaluated with respect to a specific small signal source. This dependency is what gives rise to the inherent integral behaviour of oscillators where parasitics diminish the integration constant but will not effect the ideal loop gain of the circuit. The transconductance Gm is introduced to translate the digital output to currents injected into the oscillator represented by I\dDelta. The resulting behaviour can be summarized in the s-domain by assuming \gGamma Gm is approximately independent of the phase[^11]: + +$$ H_{\phi}(s)=\frac{1}{s} \frac{Gm}{2\pi q_{max}} \text{where} q_{max} = N V_R C_{T} $$ + +$$ V_R = V_{th} + \eta U_T \ln \left( \frac{2 I_B}{2\eta U_T^2 \mu C_{ox}} \frac{L}{W} \right) $$ + +In Eq. 3 N, VR, and CT represent the number of inverter stages, voltage across the oscillator, and total capacitance seen as load to each gate in the oscillator. Note qmax physically represents the total charge that is dissipated each period which implies a frequency of oscillation in terms of fosc=IB/qmax. For simplicity the carrier mobility \mmu and Vth for both PMOS and NMOS are taken as equivalent such that their conductivity is equal. In practice W must be adjusted to compensate this difference but will typically lead to improved supply noise rejection. Fig. 3 shows the phase dependency of \gGamma with respect to IB and constituent NMOS & PMOS devices of all gates together for a 5 stage ring oscillator. Although H\pphi due to IB exhibits some dependency with respect to phase it is well estimated by Eq. 3. The phase information is extracted using an XOR gate which has a gain of 1/\ppi. + +{{< figure src="/images/icecs2016/ISF.svg" title="Figure 3: Impulse sensitivity function for a 5-stage ring oscillator with respect to the bias current and NMOS/PMOS contributions from all stages together. " width="500" >}} + +Although the first order structure has very low complexity the drawback is that the bandwidth is directly related to the the frequency of oscillation when H\pphi is put into feedback. This coupling is undesirable for two reasons. The first is from a noise perspective which is that for a fixed frequency decreasing I\dDelta increases the input-referred noise power (eĀ²n) of this circuit approximately as (UT\\(\cdot\\)IB/I\dDelta)Ā² which may become very pronounced. This forces the structure to dissipate excessive amounts of power to maintain adequate dynamic range. The second aspect is that the capability to control the oscillator frequency independent of loop bandwidth is useful to adjusting digital power dissipation and its interaction with other system blocks. + +{{< figure src="/images/icecs2016/TD_L2.svg" title="Figure 4: Proposed two-pole ROF structure with the digital output Q represented by K PWM phases for reduced analogue distortion." width="500" >}} + +For this reason the second order structure is introduced in Fig. 4. This has equivalent characteristics to that of a miller compensated amplifier where the switched current loads into a capacitor across a high gain stage which is realized by the first order structure. As a result noise/bandwidth and oscillator characteristics are decoupled by being represented through two different capacitors CL and CT. The additional consideration required here is that the digital feedback Q over CL can cause large signal swings on the gate of MB degrading transconductive linearity. Generally if MB is also in sub threshold operation its input range is limited to 2UT before excessive distortion is introduced. However capacitively coupling M phases of Q in parallel the quantization levels are reduced to VDD/M. Each phase is simply represented by taking more taps from the ring oscillator in parallel. Moreover if M is chosen proportional to VDD/2UT this structure actually reduces in complexity and improves efficiency as the supply voltage decreases. Note that for high frequency operation the switched current DAC exhibit poor switching dynamics due to the reduced supply voltage. In such a case it is sufficient to replace this block with parallel resistors equivalent to active RC integrators. As such it may be expected that this configuration implies the 3dB frequency equivalent to f3dB=I\dDelta/CL where CL is approximated as UT kT/eĀ²n to match the required noise levels. In extension the oscillator spurs can be set to match this noise floor by considering the filter response and quantizer level dependency such that fosc\textgreater f3dB SNR/N for a first order system. + +# 4 Circuit Implementation + +The presented implementation realizes a 0.45 V second order ROF using commercially available TSMC \cmostech LP MS RF technology (1P9M\_6X1Z1U\_RDL). Fig. 5 shows transistor level implementation of the transconductor and oscillator structure that retains the phase state of the system. Here a bias current is simply switched differentially into the capacitive load while M\tss{1-2} provide common mode feedback. The transistors M\tss{3-4} realize a current mirror that biases the ring oscillators proportionally to IB. The control switches SA/SC/SB correspond to +1/0/-1 transconductive gains that realize a 1.5 bit current DAC. The oscillators are floating in the middle the supplies due to M5 which has its body connected to source. This improves the switching behaviour of the proceeding XOR gate by providing good high/low voltage levels while also reducing the noise coupling from ground/substrate if the oscillator is allowed to use isolated P/N-wells. The capacitor CL is split into 11 MIM fringe capacitors for a total of 100 fF load on each terminal. + +{{< figure src="/images/icecs2016/TD_sch1.svg" width="500" >}} +{{< figure src="/images/icecs2016/TD_sch2.svg" title="Figure 5: The proposed transistor level implementation of the second order ROF" width="500" >}} + +The digital logic used to realize unity gain feedback is presented in Fig. 6. Three out of the 11 phases are used in the feedback logic for demonstration. Typically this number of phases is directly related to the frequencies of D & Q or their intermodulation products that will introduce spurs outside of the filter bandwidth. Increasing the number of phases used reduces distortion components while increasing the effective carrier frequencies. This can and should be reconfigurable in addition to tuning IB to accommodate the typical process variance for transistor characteristics. While other types of phase detectors beside the XOR gate can be used it is important to realize its impact on distortion due to the finite bandwidth of digital gates. The XOR realization grantees that for near zero input Q will exhibit the smallest bandwidth requirement due to its 50 % duty cycle which gradually increases as the phase difference approaches 0 or \ppi. + +{{< figure src="/images/icecs2016/TD_logic.svg" title="Figure 6: Boolean operator used that allows a unity gain configuration of the ROF." width="500" >}} + +# 5 Simulation Results + +In practice the primary difficulty with time domain structures is their associated simulation effort because the bandwidth of operation is many orders larger than the signals of interest. For this reason the analytic model is also presented to perform behavioural simulations and guide the design effort. The results presented here are based on transient noise simulations using industry provided PSP models for completeness. Fig. 7 shows these simulation results where a 1 kHz PWM encoded input signal is driving the system at 95 % of the full input range. VR shows the oscillator providing capacitive feedback on the miller integration node while the phase difference of the two ring oscillators tracks the pulse width of the input. Fig. 9 presents the frequency content when three of the phases are summed together and Fig. 8 shows the oscillator phase difference as a function of time. The 56 dB THD shown is critically related to the current DAC characteristics near the cut-off frequency as it not adequately shaped by the integration loop which is challenging to enhance with limited voltage overhead. Table 1 compares the performance presented here using a figure of merit defined where SINADMAX is the maximum signal to noise and distortion ratio as: FOM = Power/(Npoles BW SINADMAX). + +{{< figure src="/images/icecs2016/visual.svg" title="Figure 7: Digital input (D) & output (Q) components together with the integration node VR and oscillator outputs internal to the system. " width="500" >}} + +{{< figure src="/images/icecs2016/Delta.svg" title="Figure 8: Phase difference of the oscillator structure measured as time delay." width="500" >}} + +{{< figure src="/images/icecs2016/Spectrum.svg" title="Figure 9: Spectral power densities of the multi-phase PWM signal Q" width="500" >}} + +Table 1: Performance summary and comparison with state of the art +| Specification | This Work | [^6] | [^12] | [^13] | +|----|----|----|----|----| +| modality | Time | Time | Volt. | Volt. | +| Order | 1 | 4 | 3 | 3 | +| Technology | 65nm | 90nm | 0.5\mmu | 0.5\mmu | +| Supply [V] | 0.45 | 0.55 | 3.3 | 1.8 | +| Supply [A] | 35n | 5.3m | 1.4m | 2m | +| Bandwidth [Hz] | 6k | 7M | 1.5M | 500k | +| SINAD [dB] | 52 | 61 | 60 | 65 | +| FoM [fJ] | 7.4 | 93 | 1026 | 1350 | +| Area [mmĀ²] | 0.001 | 0.29 | 2.2 | 0.68 | + +# 6 Acknowledgement + +This work was supported by EPSRC grants EP/K015060/1 and EP/M020975/1. + +# 7 Conclusion + +The model and implementation of a oscillator based filter has been demonstrated to complement that of FIR structures [^14] for asynchronous time domain structures. High linearity is demonstrated at full input dynamic range while operating with a 0.45 V supply voltage. The extensive use of digital logic in its construction allows highly synthesizable oscillator based computing for future ultra low power systems in nanometre CMOS. Preliminary simulation result indicates a FOM of 7.4 fJ/pole for the 6 kHz bandwidth which is a substantial improvement over previous time-domain implementations. While it remains to be seen if the efficiency can be maintained in more complex systems the proposed topology shows much promise for ultra low power systems. Moreover we expect that both the first & second order primitives proposed here will find many other applications like \\(\Delta\Sigma\\) ADCs due to its simplicity and flexibility towards process parameters for low voltage operation. + +# Refernces: + +[^1]: I.L. Markov, ''Limits on fundamental limits to computation,'' Nature, vol. 512, pp. 147--154, August 2014. +[^2]: N.Guo etal., ''Energy-efficient hybrid analog/digital approximate computation in continuous time,'' IEEE J. Solid-State Circuits, vol.51, no.7, pp. 1514--1524, July 2016. +[^3]: M.Verhelst and A.Bahai, ''Where analog meets digital: Analog-to-information conversion and beyond,'' IEEE Solid-State Circuits Mag., vol.7, no.3, pp. 67--80, September 2015. +[^4]: R.Sarpeshkar, ''Analog versus digital: Extrapolating from electronics to neurobiology,'' Neural Computation, vol.10, no.7, pp. 1601--1638, Oct 1998. +[^5]: M.Alioto, ''Understanding dc behavior of subthreshold cmos logic through closed-form analysis,'' IEEE Trans. Circuits Syst. I, vol.57, no.7, pp. 1597--1607, July 2010. +[^6]: B.Drost, M.Talegaonkar, and P.K. Hanumolu, ''Analog filter design using ring oscillator integrators,'' IEEE J. Solid-State Circuits, vol.47, no.12, pp. 3120--3129, December 2012. +[^7]: W.Y. Tsai etal., ''Enabling new computation paradigms with hyperfet - an emerging device,'' IEEE Trans. Multi-Scale Comput. Syst., vol.2, no.1, pp. 30--48, Jan 2016. +[^8]: T.S. Lande etal., ''Running cross-correlation using bitstream processing,'' Electronics Letters, vol.43, no.22, Oct 2007. +[^9]: M.Elia, L.B. Leene, and T.G. Constandinou, ''Continuous-time micropower interface for neural recording applications,'' in IEEE Proc. ISCAS, May 2016. +[^10]: A.Hajimiri and T.Lee, ''A general theory of phase noise in electrical oscillators,'' IEEE J. Solid-State Circuits, vol.33, no.2, pp. 179--194, February 1998. +[^11]: A.Hajimiri, S.Limotyrakis, and T.Lee, ''Phase noise in multi-gigahertz cmos ring oscillators,'' in IEEE Proc. CICC, May 1998, pp. 49--52. +[^12]: C.Garcia-Alberdi etal., ''Tunable class ab cmos gm-c filter based on quasi-floating gate techniques,'' IEEE Trans. Circuits Syst. I, vol.60, no.5, pp. 1300--1309, May 2013. +[^13]: J.Galan etal., ''A very linear low-pass filter with automatic frequency tuning,'' IEEE Trans. VLSI Syst., vol.21, no.1, pp. 182--187, Jan 2013. +[^14]: M.Kurchuk etal., ''Event-driven ghz-range continuous-time digital signal processor with activity-dependent power dissipation,'' IEEE J. Solid-State Circuits, vol.47, no.9, pp. 2164--2173, September 2012. diff --git a/content/publications/2016/a-2-7-rmu-w-mips-0-88-gops-mm-tsqrd-distributed-processor-for-implantable-brain-machine-interfaces.md b/content/publications/2016/a-2-7-rmu-w-mips-0-88-gops-mm-tsqrd-distributed-processor-for-implantable-brain-machine-interfaces.md new file mode 100644 index 0000000..e790ad6 --- /dev/null +++ b/content/publications/2016/a-2-7-rmu-w-mips-0-88-gops-mm-tsqrd-distributed-processor-for-implantable-brain-machine-interfaces.md @@ -0,0 +1,119 @@ +--- +title: "A 2.7 Ī¼W/MIPS, 0.88 GOPS/mmĀ² distributed processor for implantable brain machine interfaces" +date: 2016-10-17T15:26:46+01:00 +draft: false +toc: true +type: posts +math: true +tags: + - publication + - processor + - CMOS + - biomedical +--- + + +Lieuwe B. Leene, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +This paper presents a scalable architecture in 0.18 um CMOS for implantable brain machine interfaces (BMI) that enables micro controller flexibility for data analysis at the sensor interface. By introducing more generic computational capabilities the system is capable of high level adaptive function to potentially improve the long term efficacy of invasive implants. This topology features a compact ultra low power distributed processor that supports 64-channel neural recording system on chip (SOC) with a computational efficiency of 2.7 \\( \mu\\)W/MIPS with a total chip area of 6.2 mmĀ². This configuration executes 1024 instructions on each core at 20 MHz to consolidate full spectrum high precision recordings from 4 analogue channels for filtering, spike detection, and feature extraction in the digital domain. + +# 2 Introduction + +A key challenge for state-of-the-art neuroscience is real-time data analysis at a massive scale for the diagnosis, treatment and recovery of incapacitating neurological conditions[^1]. While this field has advanced substantially in the realization of signal acquisition and methods for decoding activity. Current systems show a disconnect between implantable devices and the development of algorithms. The initiatives for next generation BMIs focus on scaling recording capabilities and do not consider a strategy for providing highly efficient processing which is imperative implantable SOCs. Moreover it is rare to see methods actively utilize the reconfigurability of modern sensor systems while maximizing the integrity of decoding spike train activity. Numerous aspects with regard to the signal integrity cannot be anticipated and thus assuming a specific method or signal modality will lead to conservative design because an excessively noisy environment is a potentiality. This reveals that chronic instrumentation have yet to be take advantage of more generic real-time processing to improve the efficacy of these invasive devices. Implantable systems predominantly struggle in finding compact and power efficient architectures for signal decomposition. Moving towards fully packaged millimetre scale devices that can support wireless spike train analysis of hundreds of neurons is a highly contested target for many research groups[^2][^3]. As a result high level reconfigurability is yet to be adopted in the current state-of-the-art. + +The approach to specialized DSP in the literature reflects two problems pertaining to neural recording systems. The first is signal extraction from recordings that consists of spike detection to extract compressed spike train data. The other is associated with accelerating adaptive filters that map these spike trains to estimate cognitive dynamics or invoked limb movement. Typical examples for acquiring neural activity are fully synthesized cores [^4] [^4]\cite\{2\} that have been successful in realizing implantable solutions. In contrast high level decoding is predominantly performed by FPGAs as integration makes less sense at the system level [^6]. However highly reconfigurable instrumentation have been suggested to leverage both adaptive noise shaping or artefact removal [^7] [^8]. + +In line with such work this paper presents a distributed processor architecture. Sec. 3 motivates the direction taken here and models the principle constraints for processing at the sensor interface. The proposed system is introduced in Sec. 4 and contextualized by a software development driven platform. The execution unit implementation is detailed in Sec. 5 and accompanied with performance results in Sec. 6. + +# 3 On-Node Processing + +In order anticipate how future processing methods can be accomodated in SOCs it is essential to capture high level trends with respect to processing capacity of neural implants. Here digital resource requirements are normalized in terms of state variables for evaluating technology dependency. The number of state variables in a dynamic process is a good indicator for complexity whether is a digital classifier or an analogue filter. Here the focus is exclusively on processing such that the signal of interest is idealized with respect amplitude and representation. Consider \\(L\\) as a normalized feature size that allows the evaluation of parameters for a particular technology and extrapolate them based on constant field scaling factors. This remain adequate considering BMIs are fabricated using wide range of 65 nm to 1 \mmu m CMOS technologies. +$$ R_{D} = \underbrace{ \alpha f_s C_{g} V_{dd}^2 L^2 \log_2(SNR) }_{power} \cdot \underbrace{ \alpha \log_2(SNR) A_{g} L^2}_{Area} $$ +Eq. 1 represents the power area product for a digital state variable. \\(C_{g}\\), \\(A_{g}\\), \\(\alpha\\) parametrise typical gate capacitance, area, and overhead for each register respectively [^9]. Similarly \\(f_s\\), \\(V_{DD}\\) reflect the sampling frequency and supply voltage. Generally the scaling of \\(R_D\\) constituents are well known and guide maximizing system efficiency in an abstract sense [^10]. For the sake of this discussion we assert that analogue instrumentation is limited to a large extent to having an area power product \\(R_A\\) larger than $10^{-15} Wm^2$ when considering an SNR of 60 dB for a 1.2V system. The derivation comes from the fact that neural signal levels require a specific current dissipation associated with the thermal noise levels and filtering & sampling imply a certain capacitor size according to the supply voltage. The later two terms trade off power with area that can be improved by optimization of the instrumentation topology but will be bounded by signal dynamic range and minimum capacitor sizes. + +{{< figure src="/images/biocas2016/Operations.svg" title="Figure 1: Analytic number of digital operations available with respect to different technologies (red) with references to the normalized performance of image processors (blue)." width="500" >}} + +With this understanding Fig. 1 illustrates the expected number of digital state variables that aggregate to an equivalent power area product to that of the instrumentation circuit. This shows standard logic in 0.18 um CMOS allows 100 state variables or equivalently 100 operations per sample taken. As reference specialized image processors that similarly rely heavily on data intensive operations are normalized in Fig. 1 to illustrate how technology scaling exhibits the predicted characteristics. As a result it is expected that even for ultra low power BMIs digital processing capacity will be an abundant resource in future systems. + +# 4 Neuron-Processor Interface + +The high level objective for this system is illustrated in Fig. 2. The application of a generic IoT platform is used to support an unconstrained software stack for networking, data analysis, or system interrogation that best described by high-level languages. This simplifies the development with non-hardware specific software abstractions and accommodates the ease incorporating other modules. The proposed Neuron-Processor Inteface (NPI) device may directly be integrated with the sensor as ASIC and receive configuration commands from this platform to adjust its operation. In extension it follows that peripherals for regulating power and distributing clocks must be integrated on chip. This conforms the interface towards simply providing power and bi-directional data in terms of a SPI protocol. + +{{< figure src="/images/biocas2016/Sys_iP.svg" title="Figure 2: Proposed development platform for highly reconfigurable neural recording systems." width="500" >}} + +The proposed architecture introduces a large number of on-chip DRAM macros to support the retention of 1024x32-bit instructions. This represents program that is pipelined to each execution unit to instruct filtering coefficients or feature extraction in a manner that can be extended to an arbitrary the number of processing units. Local to each unit is another 1 kbit macro that enables memory intensive methods such as template matching to take place. Four analogue instrumentation channels with a 12 bit ADC is multiplexed to the 8 b processing unit with 68 dB SNDR maximal precision. This is an extension to prior work in [^15] which details the analogue recording implementation. + +{{< figure src="/images/biocas2016/NPI_TLT.svg" title="Figure 3: Implemented Neuron-Processor Interface (NPI) system architecture for realizing high performance reconfigurable processing." width="500" >}} + +The system is illustrated in Fig. 3, there are multiple layers from system peripheral to the internal units where average data rates progressively increase. We adopt an in-data processing methodology such that the signal is maximally reduced to its principle components at the sensor interface with high-performance digital methods. This mitigates any redundant energy dissipation for data telecommunication. The primary mechanism of operation is the program memory that continuously feeds the stored instructions into the array of processors that operate locally on the recorded data. The execution of these instructions are handled with what is essentially a instruction decoder, memory module and an arithmetic operator. Inherently this implementation will sacrifice the availability of more intricate functionality found in DSPs since the data is not funnelled into one processing unit that can be very elaborate in complexity. The distributed structure is rationalized by the fact that typical methods such as clustering operate at a much lower speed due to the sporadic spiking activity which makes statistical convergence slow. Furthermore these adaptations need to be performed on the order of minutes by which such functions may also be implemented through the redundancy of elementary operations. It is important to mention that multiplexing loses its effectiveness in memory intensive applications such as neural decoding. This is because it does not mitigate the power & area scaling associated with memory allocation and in fact becomes less efficient. + +## 5 Execution Unit + +It is clear that although all recording channels should execute the same algorithm they will typically not share the same state of operation. This state dependency is exemplified with respect to intermittent processing during bursting neural activity and idling during quiet periods. This is an inherent limitation to sharing the program memory as the dynamic execution of the code where each core has its own program counter or a top level scheduler is not feasible for an arbitrary number of channels. The quasi-out-of-order execution makes it challenging for us to adopt scalable tile structures found in image processing [^11]. + +Instead branch control or conditional execution is mediated by skipping a section of the incoming instructions if a condition is not met. In this context individual cores may need to execute any section code and branching will only be limited by the dissipation related to the registers pipe-lining the instructions across the chip. As a result any resources associated with cycling through the program has a diminishing contribution to system requirements as the number of channels is increased. This implies that as more sensors are integrated the complexity in algorithm can also increase proportionally which will not be characteristic of conventional implementations that do not pipeline high-level control signals. + +{{< figure src="/images/biocas2016/Sys_uC.svg" title="Figure 4: Functional connectivity of the embedded execution unit and sub-blocks" width="500" >}} + +The individual components of the execution unit are shown in Fig. 4 and details the main data buses used for exchanging data. The majority operations revolve around manipulating data in the registers R1-R16 as A operand in association with any other data sources that can be used as B operand. In terms of instructions there are always two components where the first is simply the operation executed by the ALU in addition to the two memory sources. The second component optionally extends this simple functionality by writing these intermediate values to multiple other locations or arbitrary branching operations that will take the unit out of sleep. + +# 6 Results & Discussion + +{{< figure src="/images/biocas2016/Lay_sH.png" title="Figure 5: Fabricated NPI SOC using a 6-metal $0.18 \mu m$ CMOS process showing the system block annotation and top metal routing. " width="500" >}} + +This system has been fabricated using a commercially available 6 Metal \cmostech technology (AMS/IBM C18A6/7SF) for validation. The chip micrograph is shown in Fig. 5 measuring 6.2mmĀ² including test circuits and pad ring. While the architecture is capable of achieving very dense configurations at the system level we emphasize that the sensor interface plays an crucial role for noise isolation and chip area overhead. + +{{< figure src="/images/biocas2016/TPhw.svg" title="Figure 6: Realization of the development platform used for characterization system functionality." width="500" >}} + +The testing platform is photographed in Fig. 6 which interfaces the NPI system with a raspberry pi module. This set-up supports a embedded Linux operating system with low level device control to meed a diverse set of needs. By monitoring the internal data-bus of one core the specialized processing structure has been exhaustively validated at the design point for operating frequencies of 5 MHz to 20 MHz with varying sampling rates on the ADC. Currently the synthesis of instructions remain tailored in associated to the hardware specific compiler because the low level control is crucial for active ADC and amplifier control. + +{{< figure src="/images/biocas2016/uC_PS.svg" title="Figure 7: Measured power dissipation with respect to specific operations for the same operand A=113 & B=114 in randomized order." width="500" >}} + +The results in Fig. 7 shows the dependency of power dissipation with respect to different operators for the same operand A and B. It should be expected that the is a strong operand dependency with respect to power consumption but these results follow post layout simulations closely. When the unit is in a sleep or branching state the power dissipation is mainly associated with the instruction pipeline. As this 32-bit pipeline transverses the entire execution unit it represents a considerable baseline power contribution. While typical power consumption for full activity lies around 45\\( \mu\\)A at 20 MHz. The reduced complexity local to each channel allows this configuration to achieve \\(2.7 pJ/Cycle\\) or $2.7 \mu W/MIPS$. The specifications given in Table 1 summarize the main features associated with this system on chip for processing neural data at the sensor interface. + +Table 1: Comparison of performance specifications for the NPI system. +| Specification | This Work | 2011 [^11] | 2011 [^4] | +|----|----|----|----| +| Scaling | Fine | Fine | Coarse | +| Tech. [nm] | 180 | 65 | 65 | +| Supply [V] | 1.2 | 1.2 | 0.27| +| Units | 64 | 2048 | 16| +| Freq. [MHz] | 20 | 300 | 0.48 | +| Sys. Power [mA] | 1.42 | 300 | 0.28 | +| Sys. Memory [kb] | 32 | - | 50 | +| Tile Memory [kb] | 1 | 1 | - | +| Processor Area [mm(^2)] | 1.37 | 5.10 | 2.09 | +| P-Merit [GOPS/mW] | 1.52 | 0.31 | - | +| A-Merit [GOPS/mm(^2)] | 0.88 | 36.1 | -| + +# 7 Acknowledgement + +This work was supported by EPSRC grants EP/K015060/1 and EP/M020975/1. + +# 8 Conclusion + +A scalable processing architecture is proposed in effort to realize compact and efficient neural recording arrays. The topology reflects the nature of processing neural data in the context of extracting signal components and we expect the application of this architecture to be relevant to many high channel count neural SOCs. This discussion details both low-level and system level considerations that look towards better software integration. The proposed system power consumption is on the order of \\(1.5 mW\\) with a power density \\(26 mW/cm^2\\). However this figure is subject to the physical & software reconfiguration that allows extensive optimization for different neural recording applications using the same fabricated device. This work aims to realize long term solution for neural recording implants directed at validating neural decoding methods with in-vivo settings. Importantly standardization off-chip interfacing protocols with self-sustained operation should grantee the ease of integrating existing wireless solutions in extension to this system. + +# Refernces: + +[^1]: I.H. Stevenson and K.P. Kording, ''How advances in neural recording affect data analysis,'' Nature neuroscience, vol.14, no.2, pp. 139--142, February 2011. +[^2]: A.Khalifa etal., ''A compact, low-power, fully analog implantable microstimulator,'' in IEEE Proc. ISCAS, May 2016, pp. 2435--2438. +[^3]: J.S. Ho etal., ''Midfield wireless powering for implantable systems,'' Proc. IEEE, vol. 101, no.6, pp. 1369--1378, June 2013. +[^4]: V.Karkare etal., ''A 75- $\mu$w, 16-channel neural spike-sorting processor with unsupervised clustering,'' IEEE J. Solid-State Circuits, vol.48, no.9, pp. 2230--2238, September 2013. +[^5]: A.M. Sodagar etal., ''A fully integrated mixed-signal neural processor for implantable multichannel cortical recording,'' IEEE Trans. Biomed. Eng., vol.54, no.6, pp. 1075--1088, June 2007. +[^6]: Y.Xin etal., ''An fpga based scalable architecture of a stochastic state point process filter (ssppf) to track the nonlinear dynamics underlying neural spiking,'' Microelectronics Journal, vol.45, no.6, pp. 690 -- 701, June 2014. +[^7]: C.Qian etal., ''A low-power configurable neural recording system for epileptic seizure detection,'' IEEE Trans. Biomed. Circuits Syst., vol.7, no.4, pp. 499--512, August 2013. +[^8]: Y.Xin etal., ''An application specific instruction set processor (asip) for adaptive filters in neural prosthetics,'' IEEE/ACM Trans. Comput. Biol. Bioinformatics, vol.12, no.5, pp. 1034--1047, September 2015. +[^9]: T.N. Theis and P.M. Solomon, ''In quest of the "next switch" prospects for greatly reduced power dissipation in a successor to the silicon field-effect transistor,'' Proc. IEEE, vol.98, no.12, pp. 2005--2014, December 2010. +[^10]: M.Verhelst and A.Bahai, ''Where analog meets digital: Analog-to-information conversion and beyond,'' IEEE Solid-State Circuits Mag., vol.7, no.3, pp. 67--80, September 2015. +[^11]: T.Kurafuji etal., ''A scalable massively parallel processor for real-time image processing,'' IEEE J. Solid-State Circuits, vol.46, no.10, pp. 2363--2373, October 2011. +[^12]: H.Noda etal., ''The design and implementation of the massively parallel processor based on the matrix architecture,'' IEEE J. Solid-State Circuits, vol.42, no.1, pp. 183--192, Jan 2007. +[^13]: J.Y. Kim etal., ''A 201.4 gops 496 mw real-time multi-object recognition processor with bio-inspired neural perception engine,'' IEEE J. Solid-State Circuits, vol.45, no.1, pp. 32--45, Jan 2010. +[^14]: C.C. Cheng etal., ''ivisual: An intelligent visual sensor soc with 2790 fps cmos image sensor and 205 gops/w vision processor,'' IEEE J. Solid-State Circuits, vol.44, no.1, pp. 127--135, Jan 2009. +[^15]: L.B. Leene etal., ''A compact recording array for neural interfaces,'' in IEEE Proc. BIOCAS, October 2013, pp. 97--100. diff --git a/content/publications/2016/brain-machine-interfaces-low-power-techniques-for-cmos-based-system-integration.md b/content/publications/2016/brain-machine-interfaces-low-power-techniques-for-cmos-based-system-integration.md new file mode 100644 index 0000000..f164856 --- /dev/null +++ b/content/publications/2016/brain-machine-interfaces-low-power-techniques-for-cmos-based-system-integration.md @@ -0,0 +1,1429 @@ +--- +title: "Brain machine interfaces: low power techniques for CMOS based system integration" +date: 2016-08-08T15:26:46+01:00 +draft: false +toc: true +math: true +type: posts +tags: + - chapter + - thesis + - CMOS + - biomedical +--- + +Lieuwe B. Leene, Yan Liu, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +The emergence of miniaturized electronic sensors for recording neural activity is opening up new opportunities for better health care and understanding brain function. The precise instrumentation for sensing these signals has been developed extensively, but no implantable system available today is capable of providing a high density recording structures that can be scaled to accommodate the large number of electrodes and processing neuro-prosthetics need for functional limb replacement. The design of these systems is complicated by micro-volt levels of signal that contain convoluted mixtures of information. This demands highly accurate signal quantization and exhaustive processing that is constrained by the scarce power availability. The resulting difficulty in realizing viable solutions for chronic implants necessitates cutting-edge fabrication technologies and state-of-the-art circuit optimization techniques. + +This thesis presents the understanding behind optimizing these instrumentation systems in order to maximize the simultaneous sensing capabilities of brain machine interfaces that can be implanted wirelessly into living systems. These analytics enabled this work to outperform state of the art in terms of delivering high precision at 56 dB SINAD with a sub 0.01mm\\(^2\\) silicon footprint and a 800 nW power budget by employing novel time-domain circuit techniques. This advancement will enable BMIs to be integrated & minimutrized using nanometre CMOS with extensive digital processing capabilities that are capable of decoding neural signals without supervision such that therapy in a fully implanted fashion. Moreover by introducing distributed processing architecture this work is the first to allows scalable fully reconfigurable functionality at the instrumentation interface for complex algorithmic operations while maintaining a power efficiency of 2.7\\(\mu\\)W per MIPS. + +I would like to express my sincere gratitude for the opportunities and guidance that Dr. Timothy Constandinou has given me. It has been a wonderful experience to peruse my passion for electronics and do research guided by his generous supervision. He has made working with the next generation neural interfaces group has been a genuine privilege. I also extend my thanks to my colleges at the centre for bio inspired technology for providing an amazing environment in B422. It is inspiring to see so much talent come together and find ways to work and have fun together. I especially want to thank Tor Sverre Lande for his the inspiration and insightful discussions. Finally I would like to thank my friends and family for their support and encouragement. + +# 2 Introduction + +The ability to tap into the electrical activity of the central nervous system holds the promise of personalised health-care with unparalleled capabilities such as restoration of vision or paralysis [^2]. The development of implantable electronics that enable these capabilities are a key component to any future of bio-electronic medicines termed as electroceuticals that exhibit superior spatial and temporal precision than the chemical counterpart. This follows a vision for electronics that can be distributed throughout the body to treat a plethora of neurological conditions and psychological disorders by attaching to nerve endings to decode and modulate neural signalling[^3]. These devices provide a means to model neurological activity and find a basis for diagnosing of brain related diseases. However the human brain alone distributes the activity of \\(8\times10^{10}\\) neurons over a \\(1200 cm^3\\) volume with intricate structures where current recording systems can only observe a minute fraction of isolated activity with centimetre scale devices. Making these systems practical and useful requires more effective ways to distribute the recording of activity. This requires techniques for miniaturization towards minimally invasive implantable recording devices. + +""" +Todayā€™s best brain-computer interface systems are like two supercomputers trying to talk to each other using an old 300-baud modem + 2016 - Phillip Alvelda [^4] +""" + +One exemplary effort directed at achieving better sensors for decoding neural activity is currently a $60 million project under a Neural Engineering System Design (NESD) program that is lead by the Defence Advanced Research Project Agency (DARPA). This is one of eight aspects under the brain initiative that is lead by research in the US which signifies the explicit importance of developing better interfaces to enable new technologies. From a data processing perspective the principle issue with current systems is the limited information rates that can be extracted from chronic neural recording devices. + +# 3 Motivation + +Brain machine interfaces have long been seen imagined as a solution to incapacitating neurological injuries like paralysis, spinal cord lesion, stroke, and brain trauma. However such a solution has eluded science for a number of decades. The functional interaction between electronics and neural tissue dates back to 1870 when Gustav Fritsch and Eduard Hitzig first questioned the muscular contractions due to electrical stimulation of the motor cortex [^5]. This extensive development took many years in part because modulating neural signalling electronically in well controlled manner requires exquisite precision and correctly decoding the brain activity is a challenging processing problem that requires a intricate understanding in underlying brain function. The first success for interfacing electronics with neural circuitry is that of the cochlear implant which was approved by the American Food and Drug Administration (FDA) in 1985 [^6]. In 2015 these implants help 13 thousand individuals over come their hearing disability in the UK alone [^7]. + +Today we face an unprecedented and increasing number of patients with neurological disorders which we have yet to find rehabilitating treatment for. In fact 350 thousand people in the UK lost their self-reliance due to a disabling neurological condition [^8]. Many of these cases are the result of unsuccessful rehabilitation after stoke, spinal cord/brain injury or our inability to treat progressive neurodegenerative conditions such as amyotrophic lateral sclerosis. While these disorders still challenge our scientific understanding, the application of machine assisted intervention for neural repair and rehabilitation has demonstrated promising results with invasive implants [^9] and non-invasive robotics [^10]. Such experimental results encourage us to continue these efforts but it is also evident that this domain requires substantial improvements towards clinical solutions equivalent to that of deep-brain stimulators, pacemakers or the cochlear implants. In retrospect the guiding imperatives currently perused by leading research for better bioelectronic medicines in humans hope are aimed at meeting a number of neuroscience achievements by 2020 [^3]. These efforts can be classified with five essential components; + +{{< figure src="introduction/Mapping_A.pdf}" width="500" >}} + +{{< figure src="introduction/Mapping_B.pdf}" title="Figure 1: " width="500" >}} + +** Structural & functional mapping ** Revealing the signalling interconnect for organ-centric nerve wiring and functional signalling patterns provides a baseline for the diagnosis and understanding of nervous system. Similar to that in Figure 1 where the learning process of a rat brain is investigated with regard to functional patterns. This objective includes establishing correlations between organ function and neural activity. In order to catalogue these details we require tools for high-resolution imaging of fibre anatomy and taxonomy at micrometer resolution. The scale of exploring inter- and intra-species variation in neuroanatomy necessitates the collaboration through documenting a library or repository of tracers for visualization and standardized data collection. Moreover we need to find methods for precise identification and referencing nerve structures in a clinical environment. + +{{< figure src="introduction/Organ_A.pdf}" width="500" >}} + +{{< figure src="introduction/Organ_B.pdf}" title="Figure 2: " width="500" >}} + +** Sensing organ functions ** Finding better means to support the close-loop functionality of bioelectronic factors in the body and organ behaviour is essential. Due to natural development and biological adaptation we require detailed understanding of physiological dynamics and thereby inferring organ function from marker variation. Here we need microscopic sensors that monitor and survey a variety of markers that allow us to characterize the changes in physiological markers in relation to organ and neural activity. Introducing low risk and highly reliable sensors is crucial for performing well defined and chronic data collection on patient variance. Here Figure 2 exemplifies such a sensor interfaced with the lower spinal cord to study the efficacy of neuro-reconstruction techniques to recover bladder control [^12]. + +{{< figure src="introduction/electrode_A.pdf}" width="500" >}} + +{{< figure src="introduction/electrode_B.pdf}" title="Figure 3: " width="500" >}} + + +** Electrodes for visceral nerves ** Improving electrode-based interfaces for reliable recording and modulation is a proven enabler for many clinical applications. Miniaturization of cuff-electrodes is necessary for interfacing small nerves that are \textless100\\( \mu\\)m in diameter adjacent to organs that provide greater specificity for treatment. As shown in Figure 3 these are complex structures that require delicate application in a clinical setting. Furthermore high-density arrays that exhibit shape-adaptable contacts could allow us to further maximize signal-to-noise and reliability. These platforms will need algorithms in order to track time evolving activity across multiple fascicles. + +** Signal imaging and actuation ** Exploring other biophysical techniques that allow us to decode and actuate neural activity with less invasive means may result in more effective means for clinical applications with lower risk factors than cortical implants. This includes expanding on the current optogenetic methods to distribute excitatory or inhibitory activity in highly specific neuronal populations. Scaling electromagnetic and ultrasonic imaging to more practical form factors may also enable improved sensing modalities. Using nano-particles to enable remote interrogation by aforementioned sensing modalities also requires evaluating in-vivo reliability. + +{{< figure src="introduction/Viceral_A.pdf}" width="500" >}} + +{{< figure src="introduction/Viceral_B.pdf}" title="Figure 4: " width="500" >}} + +** Visceral control modules ** Enabling implantable sensors like that in Figure 4 requires integrating the interface with power management, wireless connectivity, and processing capabilities in highly miniaturized configurations. In particular these platforms need to provide modular support that enables recording, stimulation and blocking experiments for proof of concept. Developing the support for characterizing organ specific neural activity on-chip facilitates closed loop control without intervention. Moreover the capacity for signal processing and pattern recognition will improve bandwidth management for sensors with larger channels counts. + +# 4 Research Objectives + +Contemporary objectives for sensor design used in neuroscience applications can be approached from a number of perspectives. One could focus on wireless connectivity of body sensor networks, the chronic behaviour of miniaturized electrode interfaces, Analysis methods for distributed neural activity, or exploring organ specific functional indicators. All of which reflect how the research imperatives can be addressed in the domain of electronics. This work will specifically focus on the miniaturization and optimization of integrated electronic instrumentation. This work will form a basis for maximizing the capacity of implantable systems in a general sense irrespective of their functional purpose. In particular we raise the question: how does one enable a wireless implant to record from thousands of channels without being constrained by the bandwidth of telecommunication? Moreover how do we grantee that the integrated chip uses the absolute minimum amount of power and silicon area such that the system becomes viable for implantation? Can we find better ways to miniaturize these devices with existing technologies and what are the current limitations? + +Here we attempt to approach the design of brain machine interfaces specifically with the objective of integrating thousands of channels on a single CMOS chip. This perspective implies not only that we need to find ways to miniaturize the electronic circuits used for sensing but also find processing architectures that perform highly efficient signal analysis irrespective of channel count. This reflects our consideration towards a fixed communication bandwidth that results from the limited power budget. The implication is that the neural recordings need to be compressed by representing only high level features of collective activity. As the number of channels increases our processing capacity must proportionally increase to accommodate the increased compression rate. + +** More explicitly, this work aims to develop a fully integrated instrumentation system for brain machine interfaces that is functionally far more capable and much more power efficient than conventional systems though analytic optimization methods and circuit level techniques.** + +# 5 Thesis Outline + +The elementary components to these systems are discussed in Chapter 6. We review how neural activity is sensed electronically and the physiological components that affect these measurements. In addition we address how modern technologies are advancing the capabilities of neural recording systems to give insight to future prospects for BMIs. In particular we will discuss the associated impact CMOS integration has on sensor characteristics based on trends in on going efforts. Finally we overview brain machine interfaces that are currently presented in the literature by reviewing the current considerations in designing these sensors. + +The principle discussion presented in Chapter 16 is based on the analysis of instrumentation circuit design and the optimization there of that enables us to achieve state of the art sensing efficiency. The methodology discussed informs us how resource efficiency is dependent on both topology and CMOS process parameters. In particular by introducing the underlying resource relations for amplifiers and data converters we can present a perspective on their system level implications. This discussion addresses the impact of circuit topologies to leverage the fundamental relationship between resource requirements and the performance specifications. In association we propose several topologies in each domain that can excel at maximizing performance with the minimum area and power requirements specifically for these low frequency signals. Finally these results are extrapolated to introduce the dependency on voltage scaling and higher order filter configurations. This reveals observable relations and limits with regard where our expectations lie given the direction of miniaturizing instrumentation structures. + +Section 30 continues this notion of resource optimization by abstractly quantifying the extent we can perform processing on chip under the assumption that the design should dedicate as much resources on analogue instrumentation as on signal processing. This leads to the impression that depending on the construction of the algorithm there is an increasing amount of capacity for distributed digital processing as these systems employ more modern CMOS fabrication processes. Here we introduce an efficient implementation of two spike classification algorithms in association with a detection operator to quantify the resource requirements for methods commonly used in the literature. With this context we introduce a scalable microcontroller topology the enables distributed processing across an arbitrary number of channels and executes reprogrammable algorithms with exceptional efficiency when large channel counts integrated on chip. + +Section 43 uses the observations from the foregoing discussions to identify two components that allow integrated sensors to substantially improve performance. The first is using time domain topologies to realize a instrumentation topology based on digital logic gates that do not diminish performance due to transistor imperfections. By employing sub-threshold oscillator structures in amplification circuits the topology can achieves near ideal noise efficiency similar to conventional sensing but with improved characteristics. This structure exhibits significantly increased input impedance and reduced power dissipation than a more conventional realization would. The second component is that we propose performing adaptive classification of spike signals in the analogue domain in order to avoid digital processing data at the Nyquist frequency. This takes advantage of reduced feature bandwidth in neural recordings. Finally the different approaches to neural classification with minimal hardware requirements is evaluated in the analogue and digital domain. The proposed mixed signal method shows that we may opt to use an analogue integrator for every cluster extracted without needing analogue to digital conversion. + +Section 53 summarizes this work by considering how the proposed architectures can be improved upon to approach better system integration. Reflecting on the current capabilities of the proposed system we conclude that much effort is still needed for realizing chips that are capable of directly decoding neural activity. While proposed platform already exhibits the necessary flexibility to accommodate a number of scientific inquiries there are two directions that are clearly exemplified with regard continuing research objectives. This outline can summarized in terms of the following technical details listed below. + +**Section 6** + - Fundamental aspects for sensing of neural activity electronically and the trends in current BMI technologies. + - Review of the fully integrated BMI systems presented in recent literature. + +**Section 16** + - Chopped amplifier structure for the miniaturization of power efficient instrumentation and the design considerations there of. + - Power efficient oversampling ADC topology for compact signal quantization with minimal area requirements. + - System level resource models that addresses the configuration/optimization of amplifiers, data converters and digital processing. + +**Section 30** + - Rationale for in-channel processing and the design of template-matching and PCA based methods for that context. + - Scalable processing architecture based on software-defined instrumentation and the implementation there of. + - Linux-based ASIC interfacing platform that enables real-time data visualization and high level instrumentation protocols. + +**Section 43** + - Introduction for using sub-threshold ring oscillators as resilient time-domain memory that allows analogue processing with ultra-low supply voltages. + - VCO based instrumentation topology for nano-metre CMOS capacitively coupled amplifiers and filter structures. + - Develop a basis for performing adaptive neural spike detection & classification in the analogue domain. + +# 6 Background + +In order to detail how we might be able improve the current approach of using electronic sensors to record neural activity. This chapter will review the primitive components to sensing brain signals and associate them with research developments that are promoted though the miniaturization in microelectronics. The discussion will give insight to trends like Moore's law that allow us to envisage what to expect from BMIs several years beyond current state-of-the-art and reveal challenges that still need to be overcome. This chapter is organized by introducing the basics of sensing of neural activity in Section 7 followed by a discussion on technology impact in Section 8. Finally we summarize what current systems look like today with respect to their capacity for decoding brain function in Section9. + +# 7 Electrical Sensing of Neural Activity + +The basis for interacting with neural activity electronically is derived from charged carrier exchange that couples electronic devices to the intracellular or extracellular potentials found in neural tissue and its fluids. Neurons found in the human brain signal information throughout the body by releasing various types of neurotransmitters at synaptic connections. Because the release of these chemical species is mediated by triggers from the localized membrane potential. A neuron's chemical activity can be inferred sensing voltage fluctuations at the cell membrane. Individual neurons will exhibit a variety of dynamics across the their cell membrane, the most prominent of which is the spiking response due to an excitatory threshold crossing in it membrane potential. These dynamics also include membrane oscillations and sub-threshold responses which can be detected but are substantially less energetic. However all of these phenomena derive from the interaction of gated ion-channels in these excitable membranes that enable the transmission of neural activity across the body of the neuron [^15]. The specificity of this behaviour arise from specific neural characteristics that play a vital role in brain structure. For instance pyramidal neurons found in the hippocampus with slow-firing characteristics gain high place specificity with increased plasticity while fast-firing neurons have low selectivity but hypothetically promote neural network stability [^16]. Plasticity refers to how easily a neuron changes it synaptic weights to increase sensitivity to trigger a response from the incident action potential of specific neuron. Evaluating factors relating to response latency, tuning and extracellular waveforms of individual neurons allows us to study their role in the network passively or in response to external stimulus. + +{{< figure src="literature/record_neuron.pdf" title="Figure 5: Instrumentation for probing neural electro-physiology intra cellularly (above) and extracellularly (below)." width="500" >}} + +The small signals generated by migration of ionic species is historically studied using the patch clamp method where an amplifier directly senses intracellular potential by means of a pipette sealed to the cell's membrane[^17]. This is illustrated in Figure 5. In addition we could perform extra cellular recording where an electrode is placed in close proximity to the cell. A critical difference separating these two measurements is that extracellular recording is significantly effected by the electrostatics of surrounding tissue. In particular intermediate neurons, genial cells, or astrocytes due to tissue scarring will attenuate the signal making it more difficult to detect activity. The defining advantage on the other hand is that embedding a shank with multiple electrodes will record the activity of numerous neurons without needing a clamping or sealing procedure. This allows close inspection of localized neural circuits and their interaction instead of the intricacies of single cell mechanisms. Either method however will allow the use of ion or protein sensitive electrode membranes for precise analysis of cellular fluid constituents. + +{{< figure src="literature/coupling_phys.pdf}" width="500" >}} + +{{< figure src="literature/coupling_elec.pdf}" title="Figure 6: Representation of measuring neural activity with extracellular recording due to ion displacement. " width="500" >}} + +Figure 6 illustrates the physiological and circuit equivalent understanding of how conduction dynamics at the membrane are coupled to an extracellular electrode. This coupling defined as \\(V_{MEM}/V_{OUT}\\) is related to what signals appear on the voltage output of the amplifier from which we want to infer how ionic species are being modulated at the cell membrane. That is we want to detect the time dependent or reactive variations in ionic membrane conduction \\(g_{Na-}\\) and \\(g_{K+}\\) which will be loaded by various components before appearing at the input of the amplifier. This is particularly important when considering electrode composition in order to couple to the input of the amplifier. One such consideration would be avoiding faradaic charge injection from the electrode that may result in the disassociation of molecules that form harmful by-products [^18]. The physiological representation of spiking activity gives the idea that upon membrane stimulus the activation of sodium channels displaces charge inwards. This induces a localized recess in charge near the electrode before the potassium channels activate to initiate the repolarization of the cell. The effect of any intermediate tissue can be modelled by lossy coupling represented by the impedance \\(R_{e}\\), \\(R_{cell}\\), and \\(C_{cell}\\). Similarly the electrode response can be modelled using Randeles circuit by extracting the equivalent parameters \\(R_{ct}\\) and \\(Z_{CPE}\\) [^19]. + +In this respect we observe that the response observed at the amplifier is both dependent with respect to frequency and stay loading from biological or electronic elements in the signal path. Particularly the high frequency content or spiking activity is inhibited from coupling effectively through the tissue due to shunt resistance and stray capacitive loading. This also highlights that because the impedance of the electrode is proportional to its surface area when we reduce its size we must make sure to proportionally reduce the parasitic loading from the instrumentation in terms of \\(C_{par}\\) and \\(R_{par}\\). + +{{< figure src="literature/cp_m1.pdf}" width="500" >}} +{{< figure src="literature/cp_m3.pdf}" width="500" >}} +{{< figure src="literature/cp_m2.pdf}" title="Figure 7: " width="500" >}} + +These relations are well understood and summarized in Figure 7 following a review on multi-electrode array technologies in [^20]. The nature of this analysis similarly extends towards larger scale recordings like electrocorticography and electroencephalography where we increasingly subject the signals to a larger tissue barrier which limits propagation of electrostatic dipole effects. It also clarifies why low-frequencies tend to be more a prominent basis for analysis in the case of less invasive methods because they are less effected by the attenuation effects. In contrast consider the advantage related to high spacial resolution at higher frequency bands as the measurement of single unit activity is isolated from distant sources by means of this attenuation. This will infer that recordings associated with analysing action potential activity are more invasive but will lead to better confidence in observing specific functional and temporally precise diagnosis of brain structures. + +# 8 A Technology Perspective + +The prolific impact developments in the microelectronics industry is compelling enough that its prediction, Moore's law, has come to represent an established achievement for integrated electronics [^21]. The perpetual reduction in cost and sustained performance enhancement has become a strong driving force that many technologies exhibit similar growth characteristics in exponential progress simply by association with CMOS integrated circuits. While it could be considered a self-fulfilling prophesy, the expectation of progress has had a profound impact on science and engineering where research can be directed at objectives five to ten years ahead of contemporary technology to address emerging challenges. As a result leading research is not only associated with advancing our current understanding but also finding new ways to augment the methods used to validate these studies. + +{{< figure src="literature/trend-TPY.pdf}" width="500" >}} + +{{< figure src="literature/trend-NPY.pdf}" title="Figure 8: Exponential growth in research driven technologies." width="500" >}} + +In 2015 Moore's Law celebrated its 50\\(^{th}\\) year and in Figure 8 we look back at its uncanny accuracy. While not evident, CMOS as a technology has had to address numerous hurdles like gate leakage, thermal limits of packaging, and the break down of mesoscopic carrier transport. The exponential growth in computational capacity per Watt in particular has played a mayor role in enabling mobile devices that are seeing new opportunities in point of care medical systems. Cost reduction is most certainly not the only factor that is driving the translation of CMOS to enhance a technology like patch clamp electrophysiology. The application of miniaturized electronics to a field like neuroscience introduces a considerable amount of added-value as 'Moore than Moore' scaling benefits beside digital processing power. These include increased sensor sensitivity, material diversification, sensor in package integration, or specific manipulation of quantum effects. The characteristic growth in the number of simultaneously recorded neurons in Figure 8 is a exemplary indicator how Moore's law is accelerating development in neuroscience. Upon the introduction of using microfabrication techniques to create electrode arrays on glass in 1972 [^24] there has been a rapid growth in the number of simultaneously recorded neurons used in experiments. This growth accelerated again in the late 1990s when silicon based micro-fabrication techniques for micro-machined probes that established unprecedented capabilities. This trend can be interpreted to reflect that current systems are still unable to over come the complexity of how information in encoded within neural activity such that these application seek to acquire more recordings and measures. Nevertheless a substantial progress has been made over the past decade where only recently we have started to see successful real-time prosthetic control with a few degrees of freedom [^25]. + +{{< figure src="literature/RND-for.pdf" title="Figure 9: Primary factors influencing development of neural interfaces." width="500" >}} + +Figure 9 outlines the external drivers for innovation and more effective neural interface systems. As shown there is a engineering domain that primarily revolves around technology translation and pushing the capabilities of current integrated systems. The research driven factors from a bio-medical standpoint come from developing better models of the human body and finding new ways to interact with electronics or interpret signals. A large part of bio-medical research effort for interfaces is in order to explore basic science where we take the brain initiative[^26] or the human brain project[^27] as example. The nature of this research allows us to envision more effective ways to perform chronic treatment of neurological disorders and improving diagnostics by interfacing electronics with the human nervous system in the form of electroceuticals[^28] or optogenetics[^29]. While there remain many questions in regard to what the most effective means is to interact with the nervous system there are very clear short term goals associated with limb replacement and real time prosthetic control [^30]. Although our focus here is with regard to the fundamental challenges associated with electronic sensors and instrumentation of neurons it is important to acknowledge their role in facilitating of high level objectives associated with these efforts. The impact technology has on sensors systems in particular can be derived from three factors; CMOS-Scaling, specialized processing architectures, and More-Moore System integration. The most obvious is that of the CMOS-Scaling which primarily correlates digital performance with the decrease in technology feature size. Because power dissipation is directly related to the switching losses used for clocking operations in digital systems. Reducing the physical size of devices implies a reduction in transistor capacitance \\(C_{gate}\\). This well known relation for power dissipation; $Power = N_{tran} C_{gate} V^2_{DD} f_{c}/2$ tells us for given supply voltage \\(V_{DD}\\) and clock frequency \\(f_{c}\\), the complexity of our digital system will infer how many transistors \\(N_{tran}\\) are used or equivalently how much capacitance is switched. In fact we can accurately anticipate to what extent different CMOS parameters will change under different scaling laws as technology progresses to finer transistor sizes[^31]. + +Table 1: +| **Description** | **Parameter** | **Constant Field** | **Maximum Speed** | **Multi Core** | **Adiabatic Scaling** | +|----|----|----|----|----|----| +| Gate Length | (L_{gate}) | (1/\alpha) | (1/\alpha) | (1/\alpha) | 1 | +| Wire Geometry | (W,L_{wire}) | (1/\alpha) | (1/\alpha) | (1/\alpha) | (\alpha^2) | +| Supply Voltage | (V_{DD}) | (1/\alpha) | 1 | 1 | 1 | +| Gate Capacitance | (C_{gate}) | (1/\alpha) | (\alpha) | (1/\alpha) | 1 | +| Clock frequency | (f_{c}) | (\alpha) | (\alpha) | 1 | (1/\alpha) | +| Transistors per Core | (N_{tran}/core) | (\alpha^2) | (\alpha) | 1 | 1 | +| Core Density | (N_{core}/A) | 1 | 1 | (1/\alpha) | (\alpha) | +| Power Density | (Power/A) | 1 | (\alpha) | 1 | 1 | +| Digital Throughput | $f_c N_{tran} N_{core}$ | (\alpha^3) | (\alpha) | (\alpha) | (\alpha)| + + +The nature of the scaling laws in Table 1 reflect the different limitations for processing capacity in terms of \\(\alpha\\) using different scaling modalities. Constant field scaling has been the predominant drive for improved performance that extends from the 1970s. Until the late 1990s where the threshold in particular was preventing \\(V_{DD}\\) to be scaled proportionally due to off-leakage in the deep sub-micron domain. This implied a combination of constant field and maximum frequency scaling was employed to increase processing throughput. While average power densities of integrated chips increased it became more evident other solutions were needed. This led to the commercialization of multi-core scaling in the mid 2000s that physically distributed the performance across a multitude of integrated circuits. This was known to be limited Amdahl's law[^32] where the bottleneck transforming software to become highly parallel in execution. Anticipating this inevitable bottle neck the current direction for performance enhancement is looking for other scaling modalities that exploit the availability very large number of specialized transistors structures. Adiabatic operation for charge recovery has in fact been studied as a power reduction technique for over a decade [^33]. This is currently being proposed in association with the processor in memory solution to address some of the data intensive problems [^34]. + +$$ U_{Adiabetic} = \frac{ C V^2_{DD} }{ 2 } \cdot \frac{\tau_{RC}}{ t_s } $$ + +It is interesting to note the fundamental concept behind this motivation as detailed in [^31] in attempt to explore new mechanisms that reduce energy dissipation in switching systems. We can derive Equation 1 when we consider the power dissipation of a digital switching circuit \\(U_{Adiabetic}\\) when instead of a fixed supply voltage we have a fixed supply current. We observe that if the charging phase \\(t_s\\) is much larger than the circuit's time constant \\(\tau_{RC}\\) the dissipated energy is reduced and charge is recycled with other logic blocks. Moreover if this is configured with a resonant inductor \\(L\\) for energy recovery we fundamentally expect significant improvements over conventional CMOS in power dissipation based on fundamental principles in nano-meter CMOS [^35]. This has conceptually already been applied to neural stimulation circuits [^36] as wireless sensors are typically powered by a resonant power source this technique's prevalence is expected to be more frequent. + +While the fundamentals of devices and processing architectures continue to evolve, where do we find analogue sensors in this changing context? Because the disparate nature of analogue sensing is continuous in operation the improvement in switching characteristics of the transistors will not be reflected. Fortunately the concept of semiconductor based instrumentation is well abstracted to the extent that we can predict the performance of analogue sensors with equivalent accuracy as that of digital circuits. In particular it turns out that many process parameters do not significantly affect the power dissipation of analogue sensors which we aim to aggressively minimize [^37]. + +$$ Power \propto kT \cdot SNR \cdot BW \cdot \frac{1}{V_{DD}} \frac{\Gamma}{gm/I_D} $$ + +Equation 2 embodies the main dependencies with respect to power dissipation for sensing signals electronically with a certain bandwidth \\(BW\\) and uses constants \\(kT\\) and \\(q\\) to represent the Boltzmann energy and the electron charge respectively. Here \\(gm/I_D\\) and \\(\Gamma\\) represent transistor efficiency in terms of its transconductance per ampere and noise excess factors respectively. With respect to the different technology scaling we can see two elements that will change as process parameters change. That is the voltage supply which scales somewhat inversely to that of digital dependency and the transconductance efficiency. This efficiency factor generally is equivalent the the transistor sub-threshold slope in the low-power domain which ideally approaches a theoretical value of \\(ln(10) kT/q\\) independent of technology. This factor is as important to analogue as it is to digital operation so we expect a constancy in good transconductance efficiency for most CMOS technologies. The supply scaling however directly deters all-analogue sensor systems from migrating to more advanced processes because it may imply increased power dissipation if we naively attempt to use the same topology. + +{{< figure src="literature/gain2tech.png}" width="500" >}} +{{< figure src="literature/lin2tech.png}" title="Figure 10: " width="500" >}} + + +In addition to an increased power budget it is typical to see trends similar to those illustrated in Figure 10. This shows that using more advanced technologies may result in the minimum size transistor to behave less like an ideal transconductance element than its previous generation. This manifests itself by reducing amplifier gain or distorting filter linearity that prevent linear amplification of small signals. Ideally we want predictable relations between the small gate voltage variation and drain current of a device but this is becoming more difficult to achieve due to the dependency on the drain potential and short channel scattering effects. In addition these scaling laws will also imply variability in impurity doping concentrations have a proportionality to the scaling factor \\(\alpha\\). In fact we can estimate its effect on threshold voltage variance \\(\sigma_{Vth}\\) using the process parameters \\(t_{ox}\\), \\(N_{A}\\), \\(t_{ox}\\), and $L_{eff} W_{eff}$ which represent the transistor's gate oxide thickness, channel doping concentration, and effective channel area resprectively [^38]. + + +$$ \sigma_{Vth} \approx 3.19 \times 10^{-8} \left( \frac{t_{ox} N^{0.4}_{A}}{āˆš{L_{eff} W_{eff}}} \right) \propto \alpha^{0.4} - \alpha^{1.4} $$ + +Most terms in Equation 3 will correlate to some extent between similar analogue transistors due to the fact when that they are placed close to one another and will experience similar statistical distribution in their parameters. It is not possible to prevent the over all variance for degenerating as the sensitivity literally approaches discretization at quantum levels. This has lead to the prevalence of digital calibration and pre-distortion techniques to counteract these shortcomings and still take advantage of increased bandwidth of analogue circuits. In addition this trend also explains the recurrence of mixed signal systems in modern sensor systems where the availability of immediate signal processing can effortlessly be taken advantage of. Dealing with transistor imperfections for circuits is one of the biggest effort in current analogue circuit design theory[^39]. + +This brings us to the importance algorithms and machine learning for sensor systems in particular. It is becoming more common that modern systems have an abundance of data and processing capacity at its disposal. This has generally lead to 'smart' sensors that can extract an adaptive set of indicators or refine signal structure at the source instead of using supervision to fine tune any changing characteristics for each sensor exhaustively. For BMIs in particular the input data has unknown mixtures of information that we can only generally assume as relevant by probing the right sections of brain structure in the area of implantation. Dealing with this decoding problem can be quite demanding in the context of recording from large ensembles of neurons. If we inevitably want to achieve a mobile solution for brain controlled prosthetics it would be imperative to develop specialized hardware and processing topologies that can achieve efficient computation on a implantable platform [^40]. + +{{< figure src="literature/learning.pdf}" title="Figure 11: Different classes of processing modalities with respect to topology where supervised processes are in white and adaptive processes are in grey." width="500" >}} + + +The classes of methods being applied to neural sensors are very rich where some focus on extracting various characteristics in recordings while others focus on reinforcement learning associated with subjects adapting to a prosthetic[^45]. Figure 11 depicts the typical structure for methods used in neural signal decoding with references and annotated automation. We note that at least in the literature there is a general trend to wards full automated feature mapping and representation discovery because a priori understanding on signal encoding is not needed at the cost of being less resource efficient. This is a highly diversifying field because there are many challenges that remain to be addressed effectively such as the effect if long term behavioural dynamics on cognitive state variables [^46]. Even assuming spike rate based cortical recordings are used it is difficult to assert to which decoding method these systems will converge to in the long term. More typically novel methods approach improving performance by contributing to the framework of signal analysis. Typically this is not done in conjunction with the hardware or computational requirements which has led to some disparity with respect to methods that are feasible for integration and those that are not. Fortunately we can also find many promising hardware realizations that do allow the acceleration or an increase efficiency for these decoding methods. Although the more progressive deep learning methods still struggle with finding compact configurations [^47] initial results appear promising with respect to power efficiency [^48] due to digital scaling. However this is a common trend among integrated classifiers where power dissipation is on the order of several microwatt but due to complexity such a system requires several mm\\(^2\\) of silicon area for operating on tens of channels [^49] [^129]\cite{folding_}. + +{{< figure src="literature/lfpcor.pdf" title="Figure 12: Extracted correlation in local field potentials for different frequency bands in the human superior temporal gyrus." width="500" >}} + + +While these methods represent a corner stone for BMIs, it can be argued that carefully accounting for the spacial distribution of neural activity within brain tissue plays a much more significant role towards information extraction than the intricacy of the decoding method. In fact over the past decade, while we have been able to record from many more neurons and use more advanced processing, the rate of information extracted from neural recording has only marginally doubled to 2 bits per second [^51]. In fact this paper argues that if adjustment of electrode positioning is allowed these rates can be fine tuned to achieve much better information rates experimentally. This is still a significant improvement over non-invasive recording that is generally limited to less than 0.5 bits per second. A main consideration is illustrated in Figure 12 where low frequency neural activity are spatially correlated due to the propagation of local field activity [^52]. Implantable devices need careful consideration towards electrode distribution to prevent high correlation in recorded data. These physiological parameters are highly varied in different sections of the brain and the motor cortex in particular exhibits high single unit correlations that impedes effective recording [^53]. As such electrode distribution across the cortex of the brain is revealing to be critical aspect to implantation and approaching a more spatially distributed system design. + +With that in mind we can interpret the current trend for monolithic integration of active electronics and neural electrodes. Fundamentally we know that in order to enhance the basic tasks seen in BMI experiments, a significantly larger number of neurons may be needed for recording. This is both from a reliability point of view as neurons will 'drop out' as tissue ages and inferring more degrees of freedom requires even better signal integrity. Moreover we are not definite in our current understanding of information encoding in relation to the anatomy of the brain. However scaling the current paradigm for neural recording platform will not allow implantation of micro-wires with external recording for very high channel counts. Both in terms of surgical feasibility and chronic stability of the system. The use of silicon probes with integrated CMOS devices have demonstrated superior viability for chronic implants with high density electrodes, flexible structures, drug delivery [^54], and hermetically sealed micro-packaging [^55]. In extension these devices are significantly more scalable due to wireless capability and on-chip compression or data analysis which can be attributed to translating advancements in system integration. In particular the fine control over micro-fabrication structural or chemical composition is enabling chronic stability with less abrasive lesion when inserted into neural tissue. + +{{< figure src="literature/probe1.pdf}" width="500" >}} +{{< figure src="literature/probe2.pdf}" title="Figure 13: " width="500" >}} + + +Figure 13 shows the structure of current active probe technology where circuits can be integrated underneath the distributed array of contacts that are exposed to the tissue [^56]. Such a shank is capable of monitoring activity from multiple cortical layers of the brain simultaneously corresponding to various structural and functional neurons that exhibit different dynamics at each layer. In fact it typical to see electrode structures use very dense configurations such that we can be selective with regard to which neurons are decoded though electrode proximity. Currently the head stage extruding from the shank is of considerable size due to the contacts to external circuitry and possibly analogue to digital converters. Ideally this can be minimized by redesigning the instrumentation and allowing for only a few contacts that connect to a inductive link. It is important to point out that freely moving cortical probes with a reduced footprint appears to be the most significant factor for preventing haemorrhaging and the formation of scar tissue that impedes chronic utility of such a device[^18]. We can attribute significant improvements in chronic electrode behaviour with functional probes that leverage chemical agents in combination with micro-meter size incisions to reduce tissue damage [^57]. To a certain extent it is beneficial to have active recording electronics to be on the same order of scale as electrode structures. Such that electrodes can form in relatively arbitrary configuration from a fabrication standpoint and our data processing capacity would scale proportional to the number of recording sites in the system. + +{{< figure src="literature/chronic_neuron.pdf" title="Figure 14: " width="500" >}} + + +As illustrated in Figure 14 many of the earlier penetrating electrode structures can experience detrimental loss of recording capacity in chronic settings. The integrity of electrodes over the course of several years is scrutinized by a number of practicalities during and after implantation. Researchers have found effective methods to recover most of the recording activity by adjusting the electrode shank by a few micrometers or introducing neural growth factors after the primary inflammatory response from invasive surgery has passed [^58]. In fact this remains a major challenge for integrated modules because once these are implanted we lose substantial access to manipulate these devices. Many of these techniques must be mediated by accompanied micro-mechanical structures that coordinate with the electronic system. This aspect represents the leading edge of biomedical device integration where chronic solutions still struggle with attempting to achieve a multitude of capabilities beside simply recording activity. + +While it is easy to identify the demand for miniaturized packaging with electronic, mechanical and chemical sub-systems that are hermetically sealed for long term stability. The fabrication methods play a major role in enabling wafer-level or scalable fabrication techniques that are a crucial requirement for cost-effective commercialization. Silicon MEMS allow well established techniques to be applied to fabricating medical devices [^59] but also exhibit drawbacks in long term bio-compatibility associated material composition and structural stiffness. Emerging techniques in 3D-printing [^60] or distributed mesh structures [^61] may address these challenges but have yet to be evaluated with respect to long-term stability to the same extent that we understand the failure modes in silicon MEMS structures. + +# 9 Integrated Recording Systems + + + +Here we shall discuss the novelties presented recent publications to review some of the typical system level design considerations. These works present state-of-the-art specifically in the context of fully integrated systems. This implies that the design considers a multitude of functionalities simultaneously to enable isolated operation for implantation. + +## 10 Power Density Target for High Channel Count Recording + + + +The trend towards increased recording capacity emphasises the importance for careful sensor design that maintains adequate thermal dissipation. Particularly when current systems extensively perform processing on chip. It remains to be the case that electrode configurations like the Utah array [^62] are distributed over a volume of cortex while sensing take place on a two dimensional array of instrumentation circuits. Clearly fabrication technologies could provide 3D integration of sensor circuits. However this may actually exhibit worse thermal capacity than 2D integration due to reduced surface area per recording unit. The key requirement is then that integrated devices should realize very high 2D density in order to probe the different layers & columns of cortical tissue. + +{{< figure src="literature/sys_density.pdf}" title="Figure 15: System power density with respect to sensing area for state of the art recording systems." width="500" >}} +% + +In order to reveal the challenge of managing thermal capacity experienced by state of the art recording systems we have surveyed a number of sensor systems published over the past 5 years. This is summarized in Figure 15 which illustrates how well high density recording is achieved with respect to the thermal budget of 80mW/cmĀ²[^68]. In particular the system power density is considered with respect to the sensor density. The power density is evaluated in terms of the total system power dissipation and the fabricated silicon die size which typically dissipates its heat into the surrounding tissue. On the other hand the sensor size is taken with respect to the size of integrated electrode pitch or the size of the corresponding instrumentation circuits in order to emulate the achievable electrode pitch. + +Probably the most interesting aspect of this depiction is the constraint imposed by the thermal noise limit. This results from the minimum current dissipation from each sensing circuit in order to achieve 5\mmu Vrms input referred noise given a 5 kHz bandwidth. A strict amount of power needs to be dissipated irrespective of the instrumentation size resulting in a power density inversely proportional to sensor area. The closer a system is to this limit the better the NEF it will exhibit. Unless the supply voltage, noise requirement, or bandwidth is readjusted the system power density cannot fall below this limit. As a consequence, managing the thermal budget is an imperative design consideration for future systems that target extreme miniaturization. This is usually required in order to minimize device impact on biological tissues. For such a scenario, reducing the acquisition bandwidth may become a predominant reason for using LFP recordings over spiking activity. This could be the only way to allow several thousand channels to be integrated onto a sub-millimetre size CMOS device without thermal concerns. + +The flicker noise sources for active readout transistors also plays an important role that can impair such achievements. If we assume transistors are equal in size to that of the sensing area then it should be expected that below a certain size the flicker components inhibit signal detection. Conventional readout topologies can not achieve very high densities due to flicker noise if chopping or electrode multiplexing techniques are not utilized. However such structures guarantee DC blocking behaviour which is desirable for safety regulations. It is well known that chopper instrumentation can achieve substantially smaller configurations but degrades instrumentation input impedance [^69]. The system in [^70] shows how the use of chopping can achieve 50\mmu m electrode pitch for exceptional spacial resolution with 768 active recording channels. This particular configuration performs quantization at the sensor interface using a ramp ADC and a open loop amplifying structure to minimize the number of analogue components in the system. A similar structure is employed in [^66] with the addition of digital feedback in order to introduce high-pass filtering behaviour. This key modification allows robust in-vivo recording that is not impaired by electrode drift or large fluctuation in local field potentials that are typically not present en-vitro. + +Another means to accommodate higher sensing densities is achieved by actively multiplexing the electrode array and only selecting the most informative electrode locations for the decoding task. This allows the work in [^67] to interface over 26 k electrodes while simultaneously recording from 1024 units for the en-vitro study of cell cultures. By embedding SRAM memory cells within the electrode switch matrix this system presents a highly versatile MEA platform that can perform extensive signal conditioning. The main challenge is that the system complexity results in a 76mmĀ² die size which is difficult to translate towards an implantable solution. For this reason the work in [^71] focuses explicitly using a silicon probe as substrate to allow 52 simultaneous recording channels from 455 electrodes. This approach seems to be one of the most promising for future BMI systems as the electrodes can be fabricated together with the electronics using well established microfabrication [^72]. + +In addition to these high density recording systems a number of promising circuit techniques have been proposed that may allow considerable improvements in performance. For instance the application of bulk switching in [^73] is capable of reducing flicker noise without sacrificing the DC blocking characteristics. On the other hand [^74] suggests removing the capacitive coupling structure altogether by extensively utilizing digital feedback which could achieve very high recording densities if electrode multiplexing is also incorporated. Overall this trend towards higher recording densities is expected to remain a sustained effort where both fabrication and circuit techniques will play a key role for miniaturization. + + +Table 2: Performance specifications for integrated neural instrumentation systems found in the literature. \\({\dagger}\\) integrated power management, \\({\star}\\) integrated silicon probe, \\({\triangle}\\) commercialized system, \\({\diamond}\\) integrated stimulator, \\(\circ\\) integrated chemical readout. +| Reference | |Intan [^75] |Yoon [^76] |Je [^77] |Gielen [^71] |Rabaey [^64] |Chan [^63] | +|----|----|----|----|----|----|----|----| +| Year | | 2012 | 2012 | 2013 | 2014 | 2015 | 2016 | +| Technology | [nm] | - | 250 | 180 | 180 | 65 | 180 | +| Supply | [V] | 3.3 | 0.9 | 0.45 | 1.8 | 1 | 1.8 | +| Power | [(\mu)W] | 830 | 3.96 | 0.96 | 27.8 | 3.6 | 9.1 | +| Channels | | 64 | 16 | 100 | 455 | 64 | 200 | +| Area | [mm(^2)] | 0.47 | 1.56 | 0.25 | 0.19 | 0.075 | 0.067 | +| Bandwidth | [Hz] | 10k | 11k | 10k | 6k | 8k | 10k | +| Highpass | [Hz] | 0.1-1k | 0.1-1.2k | 0.25 | 1-500 | 10-1k | 0.1 | +| Noise | [$\mu V_{rms}$] | 2.4 | 4.8 | 3.8 | 3.2 | 7.5 | 4.07 | +| Note | | ({\triangle}) | ({\star}) | ({\dagger}) | ({\star}) | ${\dagger \diamond}$| ({\circ}) | + +Here we highlight the digital electro physiology interface chips provided by Intan technologies as one of the few commercialized integrated instrumentation systems [^75]. These chips are the base line for numerous other advanced neural sensors. The mixed signal architecture it self can still be identified in newer systems. The on-chip configuration is relatively straightforward where there are 16-64 channels with differential inputs that are amplified and filtered by \\(3^{rd}\\) order low-pass filter. In addition to a combination of \\(1^{st}\\) order analogue and \\(1^{st}\\) order digital high-pass filter are used to reject low-frequency content. The digital back-end directly clocks the data converter as slave to sample the various channels. The key component to these systems is the robust simplicity and guided application that has accelerated the research for many groups. + +{{< figure src="literature/R2_IC.pdf}" width="500" >}} +{{< figure src="literature/R2_SYS.pdf}" title="Figure 16: " width="500" >}} + + +The multi channel device in [^76] is some of the earlier work that focuses explicitly on the miniaturization of analogue recording. This work was later improved upon in [^77] where a dual sample and hold structure was proposed to mitigate the class-A power-bandwidth trade off associated with the buffer driving the ADC by using two separate capacitor arrays. This system can be seen in Figure 16. More importantly this system introduced on-chip power management to that would allow a telemetry module to power the implant. There is also an attempt here for using the dynamic range at different supply voltages more effectively to marginally reduce the system power budget. By using a charge pump to drive the supply on stages that have a large output swing the low voltage component have reduced power requirement. + +{{< figure src="literature/R9_IC.pdf}" width="500" >}} +{{< figure src="literature/R9_SYS.pdf}" title="Figure 17: " width="500" >}} + + +The authors of [^71] introduce the conceptual hurdles and advantages of using a fully integrated active probe that is fabricated by post processing standard CMOS wafers. This system can be seen in Figure 17. Here the active electrodes are demonstrated to deal with the cross-coupling of high density electrode configuration and enabling a significant amount of multiplexing for electrode selection. Because we see the use of analogue voltage transmission across the chip the discussion addresses a number of limitations due to the limited drive capability of the active electrode structure. We may be quick to suggest alternative structures that does not suffer from such complications but it is difficult to avoid open-loop behaviour will not allow good linearity or matching drawbacks. + +{{< figure src="literature/R11_IC.pdf}" width="500" >}} +{{< figure src="literature/R11_SYS.pdf}" title="Figure 18: " width="500" >}} + + +The work in [^65] exemplifies an alternative to closed loop amplifier structures by performing direct quantization. This system can be seen in Figure 18. Similar to oversampling data converters this approach resolves a number of issues like the limited linearity of analogue blocks or variance in their characteristics. However these complications can now be seen in the feedback structure where the digital to analogue conversion requires fine linearity calibration in the feedback and most of the digital processing has a considerable dynamic range. This approach does well to leverage deep sub-micron CMOS. + +{{< figure src="literature/R7_IC.pdf}" width="500" >}} +{{< figure src="literature/R7_SYS.pdf}" title="Figure 19: " width="500" >}} + + +The system presented in [^64] by the same authors as is exceptional because it demonstrated a fully integrated system on chip solution that can perform closed loop stimulation while processing neural activity. This system can be seen in Figure 19. Moreover the system integrates power regulation that adaptively scales the stimulator supply in order to maximize the efficiency of current stimulation. The embedded digital processing is capable of extracting spikes that are detected by a non-linear energy operator and evaluate long term firing rates as a form of data compression. Moreover the 65 nm CMOS technology allows this system to achieve a respectable power budget while performing extensive digital processing. + +\TFigure{ + \centering + \subfigure[Fabricated device in 180 nm CMOS.]{\includegraphics[height=7cm]{literature/R6_IC.pdf}} + + \subfigure[Integrated system architecture.]{\includegraphics[height=6cm]{literature/R6_SYS.pdf}} + \caption[Neural recording system from the literature showing the fabricated and system level implementation.]{Proposed neural recording system from [^63] showing the fabricated and system level implementation.} + \label{fig:LT_R6} +} + +The acquisition platform in [^63] merges the capability to perform electrical and chemical sensing of biological cultures. This system can be seen in Figure \ref{fig:LT_R6}. The discussion on the different sensing modes motivates discreet-time biasing of the current feedback. This is followed by careful transistor sizing accordance to the detailed noise analysis that attempts to maximize the power efficiency. This work also reviews a number of other works with respect to their performance and draws our attention towards the difficulty of achieving good linearity and input impedance. + +Generally we find that systems published in the recent literature are pressed to achieve good power efficiency in the analogue and digital domain because this component are well understood as a critical factor. The focus for innovation is typically the introduction integrating more axillary circuits that improve the viability for wireless implantation and wafer-level fabrication with electrodes. We do find that typically the compactness is not viewed as stringent because it is presumed to be largely technology dependent. Moreover integrated processing methods are strictly evaluated with respect to their algorithmic complexity and not the memory requirements which are equally scarce resources. + +The fully integrated realization of neuromodulation ICs has been an outstanding endeavour for a number of research efforts that is rapidly becoming more successful. As demonstrated by Medtronic's pioneering work [^78] that is one of the few to realize neuromodulation devices with FDA approval. Similar closed loop systems extensively use LFP signals for seizure prevention have been particularly successful at realizing integrated solutions. For instance the system in [^79] uses extensive segregation of different LFP frequency bands from 0.5 to 30 Hz as features which allows a support vector machine in the digital baseband to to perform classification on EEG activity. While this is not quite as invasive a solution as the Medtronic device this work illustrates that the processing architecture plays a key role in on-chip resource requirements. Generally the level of invasiveness will reflect in the system's latency to detect events in neural activity while exhibiting more challenging instrumentation requirements for EEG systems when compared to ECoG or intracortical recordings. In fact the newer implementation in [^80] uses a non-linear basis SVM engine to improve its hardware efficiency resulting in an accuracy improvement from 84% to 95%. + +To some extent the integrated form factor allows these SOCs to deliver substantially increased sensing & stimulation capabilities when compared to benchtop alternatives. In fact the overall experimental complexity is considerably less and environmental noise sources are less likely to perturb an integrated system. For instance the system in [^81] uses 64 recording and stimulation channels for cortically implanted electrode arrays to deliver electrical stimulation therapy based on closed loop control. This type of active neuromodulation can improve clinical efficacy in freely moving rats. Earlier results [^82] indicated that such an approach can reduce epileptic seizures by 90% in addition to improving chronic viability owning to a reduced implant size and wireless capability. This particular system uses phase synchrony in specific LFP frequency bands to trigger current mode stimulation with minimal feedback latency. A similar wireless system in [^83] also uses LFP energies to deliver stimulation but proposes to take advantage of log-based signal encoding in neural activity to improve energy efficiency. This is just one of many examples where the physiology of neural activity can be used to allow more effective processing methods. The target application here is using deep brain stimulation to treat essential tremor and Parkinson's disease using a programmable PI controller. + +An isolated number of works have used neural spiking activity to realize closed loop stimulation control of neural activity on SOC platforms. This is possibly due to the large stimulation artefacts that can disturb the instrumentation front end but also because most target applications are directed at external motor control. The system in [^84] suggests adiabatic charge-recycling may potentially realize better efficiencies. However the recorded spike rates are not directly used to adjust the stimulation pattern without off-chip intervention. On that note the system in [^85] utilizes the spiking rates from classified neurons to infer bladder volume and thereby provide a well informed condition for stimulation. This should indicate that peripheral nerve control is more adequate for this class of devices simply due to the lack of information in local field fluctuations. Instead chemical measures or the associated nerve activity is used for closed loop control. + +## 11 Emerging Technologies + + + +It is becoming apparent that increasing the capacity current BMIs requires us to find more efficient means to perform signal extraction as well as finding more effective interfacing strategies. For this reason we will highlight a few of the promising technologies that will hopefully make substantially more effective systems in the future. + +## 12 Advanced CMOS Technologies + + + +A number of recent BMI publications show a growing interest for using advanced CMOS technologies in order to accommodate more digital processing capabilities on chip. This is particularly relevant for closed loop neuromodulation that needs more sophisticated diagnostics to perform therapeutic feedback. To some extent the high channel count recording systems also necessitate extensive processing for various types of signal compression. As a result there are a number of opportunities associated with using nano metre CMOS processes. For example the 0.25 V neural processor in [^86] is able to perform feature extraction on quantized recordings with exceptional power efficiency in part due to the 65 nm technology. Combining this with existing sensor interfaces that operate at very low supply voltages [^87] [^88] may result in an order of magnitude improvement in power dissipation when compared to previously proposed systems. + +It is important to point out that there are other challenges that prevent conventional instrumentation structures to deliver precise sensing at these technology nodes. Particularly when attempting to achieve a compact configuration with good linearity at these reduced supply voltages[^89]. It should not be surprising that the use of oscillators have been particularly successful to leverage the digital design style [^90]. Our group recently demonstrated that oscillator based structures, while high digital in nature, can allow exceptional performance for filtering time domain signals [^91]. In fact the concept of encoding signals in the time domain has been proposed in a number of recent works [^92] [^93] [^94]. This is motivated by asynchronous processing capabilities for sparse neural activity that could drastically reduce power dissipation [^95]. However this is still an ongoing effort where the current realizations show exceptional dynamic range but have not yet been able to demonstrate the same noise efficiency conventional methods. This is partly because such benefits can only be realized when both instrumentation and signal processing is performed using the time domain signal modality. Some further argument can be made that the reduced parasitics and smaller geometries from this trend make chopper circuits substantially more viable. This is because the input capacitance can be reduced if the closed loop gain is maintained relatively large. Such a reduction should translate towards boosting the sensor's input impedance to hundreds of mega ohm. Again this works in favour of VCO topologies because they inherently exhibit excessive open-loop gain. + +## 13 Chemical Sensing + + + +In addition to the electrical activity that can be recorded from neural populations, chemical markers such as dopamine concentrations can play a key role in utilizing neurochemistry to refine the diagnostic fidelity of BMIs. The neurochemostat is a recent innovation that allows a means to perform closed-loop regulation of endogenous neurotransmitters [^96]. Because a number of neuropathologies relate explicitly to deficiencies in specific neurotransmitters this development can enable new therapeutic strategies that probe different pathways using rich neurochemistry. While chemical sensors face other challenges associated to the electrode composition & interface that can can degrade sensitivity in chronic settings [^97]. However there are a number of promising means to prevent such degradation such as anti-fouling coatings [^98]. Moreover a number of existing sensor platforms already allow simultaneous sensing of electrical and chemical activity with hundreds of different channels to study neurodegenerative diseases [^99]. + + +## 14 Optical Sensing + + + +The use of optics in implantable sensors is possibly one of the newer themes in brain machine interfaces as a result of the enabling success in optogenetics. Such sensors may provide essential clinical tools to precisely guide neurosurgery as well as new high resolution imaging tools for brain structures [^100]. That said there are also efforts to perform label-free imaging sensors that use the polarization of reflected light which does not require optogenetic transfection [^101]. While there is a great amount of functional flexibility, implantable optics face a demanding challenge in relation to developing compact devices. This is exemplified by the implantable prototype in [^102] which uses a coupled fibre to deliver optical stimulation from a battery powered system. This is primarily an outstanding challenge for recording activity from large volumes [^103] that has the potential to be integrated along side more conventional recording circuits [^70]. + +# 15 Summary + + + +In hindsight to the trends in BMI innovation there is an definite expectation with regard to seeing more integrated probes with better processing capacity. Particularly because active probe integration solves many problems associated with electrode configuration and scalable data processing that is not limited by communication links. In some cases like closed loop stimulation it may even be necessary in order to avoid inconsistent signal latency which neural plasticity is highly sensitive to[^104]. Moreover there are not many clear answers towards optimizing area and power of analogue instrumentation. Particularly when dealing with noise limited systems. It is more typical to see strategies proposed for solving problems that are emergent from the implementation which is difficult to isolate from the fundamental aspects for signal amplification in a well defined manner. We also note that the number of neural recording system with integrated processing is very limited in terms of reconfigurability. In contrast to the work done with image processing ASICs that allow very efficient acceleration of various algorithms [^108][^107][^106][^105]. The reconciliation of software and algorithm developments is an important aspect which these specialized systems have yet to accommodate. + + +# 16 Neural Recording Front End Design + + + +This chapter focuses on the multitude of questions associated with the mixed signal design for multi channel integrated neural recording systems. As a result, a significant section will be directed at developing an abstract understanding of how design parameters influence the various design challenges. This discussion will clarify the key limitations for these systems and propose how they can be mitigated or efficiently designed for. In the scope of integrating a large number of recording channels together, clearly understanding how each resource trades for another is crucial for optimizing a complex system. Optimization methods found in the literature typically assume a certain configuration which limits to what extent improvements can be made [^109]. However here we specifically identify abstractions that allow us to consider the impact of different topologies and filter structures simultaneously. This should enable a much boarder sense of optimization that will reflect in the improved performance characteristics demonstrated here. + +We will focus on elaborately evaluating the dominant resource requirements with respect to noise, mismatch, quantization, and functional aspects for signal conditioning together that is mostly implementation independent. In addition we propose several circuit implementations based on this analysis that present highly efficient and compact instrumentation. The corresponding abstractions that we use attempt to realize clarity respect to underlying dependencies. This should allow better analytic models that make the limiting factors appear obvious and reveal means to circumvent specific constraints with alternative techniques. For example we may be interested to know when it is worthwhile to put certain functions in the digital domain in terms of the CMOS technology parameters. Approaching the ideal instrumentation structure in such a scenario remains highly desirable for constrained applications. Thus conforming to the technology parameters could reveal that conventional methods do not deliver the most effective solution. + +The chapter is organized as follows; Section 17 describes the general problem statement related to the analogue front end which is followed by the associated amplifier design considerations in Section 19. The method for improving the analogue to digital conversion is outlined in Section \ref{ch:T1_converter}. These results are then collected in Section \ref{ch:T1_model} to evaluate the impact of system level parameters as a function of resource requirements. + +\ifbrief + +\else + +# 17 Architecture for Neural instrumentation + + + +The analogue dimension of neural recording system can be broken down into two objectives for signal conditioning that will maximize the performance of the proceeding digital signal processing. The first is related to getting adequate signal quantization by amplifying the signals to full input range of the data converter without corrupting the signal of interest. The second objective is performing some kind of filtering that removes noisy or irrelevant components in the recording and only captures the relevant signals of interest. + +{{< figure src="technical_1/T1_SIG_Spectrum.pdf" title="Figure 20: Illustration of the spectral power density characteristic for a typical neural recording with the associated frequency bins. " width="500" >}} + + +As depicted in Figure 20, the input spectrum of a typical \text{in-vivo} electrode recording can be classified using a few frequency bands. The energy from extracellular spiking activity is primarily concentrated around \\(300 Hz\\) to \\(6 kHz\\) and is characteristically intermittent resulting in a distinct difference between the average and instantaneous spectral power [^110]. This characteristic is also present in the LFP band to a lesser extent. From an electrical standpoint the design constraints are derived from the tolerated noise levels in each frequency band to maintain a proper signal to noise ratio. As a consequence it important to specify the signal to noise ratio in terms of noise density opposed to integrated noise figures as digital processing accuracy is not limited by the later term. Here we should also note that the electrode spectral noise power $N^2_{electrode} = 4 kT R_{en} \Delta f$ depends on the resistive component of the electrode impedance. This is typically matched by that of the amplifier noise characteristic \\(N_{amp}\\) so that no excess power is wasted and is expressed in terms of the electrode resistance \\(R_{en}\\), Boltzmann energy \\(kT\\), and the frequencies of interest $\Delta f$. + + +## 18 Instrumentation Requirements + + + +This kind of electrical sensing can be broken down in the a number of system blocks each of which perform an essential operation to this process. These are shown in Figure 21 and consist of an amplifier, a filter, a sampler, and a quantizer. Occasionally one circuit can combine multiple of these operations together depending on the construction. Table 3 presents the overall performance requirements that should be demonstrated when these components are integrated together. These are also the specifications that we will target as the design is being considered in the following discussion. The reasoning behind these specific requirements are mainly related to conventional signal acquisition given the bandwidth and noise requirements. Moreover these seem to be sufficient for most decoding/characterization methods hence similar figures can be found in most BMI publications. + +{{< figure src="technical_1/ISYS.pdf" title="Figure 21: " width="500" >}} + + +Table 3: Summary of the target specifications for the analogue instrumentation system. +| Parameter | Symbol | Specification | +|----|----|----| +| Integrated Channels | | 64 | +| Supply Voltage | (V_{DD})| (<)1.8V | +| Power Dissipation | (P_{SYS}) | (<)5 (\mu)W | +| Diff. Signal | | 5 (\mu) - 5 mVpp | +| Common Signal | | 50 mVpp | +| CMRR/PSRR | | (>)80 dB | +| Input Referred Noise | (e^2_{in}) | (<)5 (\mu)Vrms | +| Total Gain | (A_T) | (>)40 dB | +| THD at max input | | (>)40 dB | +| 3dB Bandwidth | (f_{3dB}) | 6 kHz | +| High pass frequency | (f_{hp}) | (<)1 Hz | +| Sampling rate | (f_{smp}) | 25 kS/s | +| Input Impedance | (R_{IN}) | (>)50$ M \Omega$ @( 1 )kHz | +| ADC Resolution | (ENOB) | 12 bits | +| Active Area | | 0.01 mm(^2) | + + +# 19 Amplifier Principles for Miniaturization + + + + +{{< figure src="technical_1/Harrison.pdf" title="Figure 22: " width="500" >}} + + +The principle design considerations for neural instrumentation have been well established particularly with regard to the Harrison topology [^111] that been widely adopted in many systems and shown in Figure 22. Objectively the optimization techniques have become both more specialized and specific for maximizing the average signal to noise ratio in the LFP or EAP bandwidth with the absolute minimum power budget. Interestingly due to the use of more advanced CMOS technologies there is a persistent trend towards sub-threshold operation. This is motivated by trading in the excess transistor bandwidth for improved current efficiency that measured in terms of the achieved transconductance per dissipated ampere of current. In fact this is purely a result of maximizing the individual transistor performance with respect to the speed efficiency product [^112]. This is expressed in Eq 4 using \\(f_T\\), \\(U_T\\), \\(v_sat\\), \\(\mu\\) as the transition frequency, thermal voltage, velocity saturation voltage, and carrier mobility respectively. + +$$ \max\limits_{IC} \left\lbrace f_{T} \frac{gm}{I_{DS}} \right\rbrace = \frac{v_{sat}^2}{4\pi \mu \eta U_{T}^2} \: \frac{1}{IC_{max}} \approx \frac{22}{IC_{max}} \left[ \frac{THz}{V} \right] Where IC_{max} = \left( \frac{L_{sat}}{L_{tech}} \right)^2 $$ + +Here \\(L_{sat}\\) is a technology independent BSIM6 parameter that reflects the impact of ballistic carrier transport during velocity saturation and normalizes the minimum feature length \\(L_{tech}\\) for a specific technology as an effective length. The implication of Equation 4 is that the transistors for optimized low frequency instrumentation amplifiers are exclusively in the sub-threshold regime because \\(f_T\\) is always in excess with respect to the signals of interest. The subthreshold operation results in each transistor's transconductance being defined as $gm = \frac{I_{DS}}{\eta U_{T}}$ which only depends on drain current. Instead of noise optimization though the overdrive voltage, \\(V_{ov}\\), the topology can only reduce noise by removing non-amplifying transistors or biasing them with reduced drain current when compared to the input transistor(s). This reflects the need for a different design methodology as the input referred contribution is dominated by how the total amplifier current distributed to all the transistors. At least in the small signal sense the key requirement is that the amplifying transistors dissipate all the current while biasing/non-amplifying transistors dissipate relatively very little. + +In principle due to the under-determined nature of transistor level design the optimization methodology is initially constrained by one of the most important objective characteristics. This could be low noise, wide bandwidth, good linearity, etc. Hence this discussion will digress by distinguishing the design considerations for noise or bandwidth limited amplifiers as separate cases. This should reveal some key relations with respect how power efficiency is achieved. For each case we evaluate the implications with respect to different resource requirements. + +## 20 Noise limited Amplifiers + + + +This discussion is guided by the leading challenge for instrumentation systems which is maximizing efficiency while maintaining good linearity. For this reason a noise efficiency factor (NEF) was first introduced in [^113] and is expressed in Equation 5. + +$$ NEF^2 = e^2_{in} \frac{I_{tot}}{ U_T 4kT \omega_{3db}} $$ + +This figure represents a normalized efficiency or in other words it evaluates how much extra current is dissipated by a particular circuit when compared to an ideal bipolar junction transistor for the same noise performance. Here \\(e^2_{in}\\), \\(I_{tot}\\) and \\(\omega_{3db}\\) represent the input referred noise power, the total current dissipation and the -3dB bandwidth in radians respectively. NEF reflects how well a particular topology achieves efficient amplification for a particular noise floor and thus it inherently trades off with a multitude of other parameters. Here we shall use it as design parameter that reflects the chosen transistor level topology. With this in mind, we propose the following reformulation from Equation 5: + +$$ e^2_{in} = \frac{kT}{C} \frac{NEF^2}{\eta A_{cl}} \frac{I_{in}}{I_{tot}} \text{where} C = \frac{gm}{\omega_{3db} A_{cl}} \text{and} gm=\frac{I_{in}}{\eta U_T} $$ + +This result leads to: + +$$ gm = \omega_{3db} \frac{kT}{e^2_{in}} \frac{\zeta}{\eta} Equivalently I_{in} = \omega_{3db} \frac{q U_T^2}{e^2_{in}} \zeta \text{where} \zeta = NEF^2 \frac{I_{in}}{I_{tot}} $$ + +Note that this relation is exclusive to noise limited characteristics and implies nothing with regard to the output load or linearity conditions. Moreover there is a fundamental requirement for transconductance with respect to noise and an implementation related factor \\(\zeta\\). This factor represents the noise efficiency of the topology and the slope factor \\(\eta\\) that tells us about the transistor performance as a fundamental process parameter. Numerous techniques for improving NEF can be found in the literature. As a generalization these can be put into two categories. The first reducing the transconductance of non-signal amplifying transistors using degeneration such that their input referred noise is minimized [^114]. The second approach is AC coupling the amplifier's input signal to biasing transistors such that the total transconductance is increased and the current efficiency is improved. Interestingly because this factor relates to current efficiency the NEF can be smaller than 1 or exceed the efficiency of a BJT using a stacked mixer structure that reuses the same biasing current for multiple amplifiers [^115]. This hints at the fact that NEF should be normalized to the voltage supply but in some sense these structures trade off dynamic range for power efficiency. Theoretical NEF figures for some of the primitive low noise topologies are listed in Table 4 assuming biasing transistors have negligible contribution and taking \\(V_{th}\\) as the NMOS & PMOS threshold voltage. + +Table 4: Theoretical figures for NEF for various amplifier topologies. \\(^\star\\) N is the number of stages sharing the structure. +| Topology | NEF | Minimum (Vdd) | Reference | +|----|----|----|----| +| Single Transistor | $\eta $ | (V_{th}) | - | +| Differential Pair | $\eta āˆš{2}$ | $V_{ds} + V_{th}$ | [^116] | +| Complementary Pair | $\eta $ | $2 V_{th}+2 V_{ds}$ | [^117] | +| Common Reference(^\star) | $ \eta āˆš{\frac{1+N}{N}}$ | $V_{ds} + V_{th}$ | [^118] | +| Common Bias(^\star) | $ \eta āˆš{\frac{2}{N}}$ | $(1+N) V_{ds} + V_{th}$ | [^115] | + + +These relations highlight the fact NEF primarily dependent on the chosen topology and less sensitive to the actual transistor design after optimization. Choosing a topology for the instrumentation amplifier with respect to its ideal NEF performance is significantly more effective than starting with a particular structure and introducing resistive degeneration on transistors that should not contribute noise. + +Also notice that the expression for noise in Equation 6 only has one degree of freedom and that is the ratio between the closed loop gain and capacitive load of the amplifier. This implies the 3dB bandwidth of the amplifier is fixed but its unity gain frequency is arbitrary. In fact by satisfying the relation for Equation 7 it is automatically the case the the equivalent noise density requirement is also satisfied. This is significant because we could allow the first stage to provide wide band gain and rely on a second stage to perform filtering. The second stage will have a capacitor gain product that is \\(A_1^2\\) times smaller than if the fist stage had to perform filtering. This can has a large impact on analogue circuit area that is typically dominated by capacitors used for filtering and setting closed loop gain. + +{{< figure src="technical_1/flickker.png" title="Figure 23: " width="500" >}} + + +So far we have only considered the implication thermal noise requirements on the design. We must also address the flicker noise sources because neural signals have a lot of low frequency content. Moreover because flicker noise sources concentrate the noise power at the lower frequencies, the total noise profile inside the LFP frequency band can be dominated by this type of noise. The nature of flicker noise from transistor physics can be due to a number of phenomena; mobility fluctuation $\Delta \mu$, carrier density fluctuation $\Delta N$, and changes in access resistances $\Delta R$. Each of these phenomena will exhibit a \\(1/f\\) frequency dependence when computing the input referred power spectrum. Typically for a given inversion coefficient IC only one of these phenomena will dominate the overall noise characteristic of a transistor. This is illustrated in Figure 23 which shows that $\Delta N$ is typically the leading cause for flicker noise generated additively to the drain current. IC is a factor that indicates to what extent a transistor is operating in the subthreshold region by using the definition IC=ID/($2\mu C_{ox} W/L U^2_T$). This uses The more general parameters \\(q\\), \\(W\\), \\(L\\), \\(C_{ox}\\) that represent electron charge, transistor width, transistor length, and gate oxide sheet capacitance respectively. The region of interest for biomedical circuits is typically when \\(IC<1\\) which exhibits good current efficiency and subthreshold operation. The phenomenological model corresponding to carrier density fluctuation $\Delta N$ component is expressed in Equation 8 after being referred to the transistor gate as an equivalent voltage noise density [^119]. + +$$ e^2_{fl} \Delta f = \frac{q^2 kT \lambda N_T}{W L C^2_{ox} f} \cdot K_{G} \text{where} K_{G} \approx (1 + \frac{\alpha \mu}{2})^2 \text{for} IC < 1 $$ + +Here \\(\alpha\\) and \\(\lambda\\) represent the coulomb scattering coefficient and tunnelling attenuation distance respectively. Notice that this expression has relatively weak biasing dependency in weak inversion contrast to the strong inversion region as shown in Figure 23. This trend follows very closely to the \\((gm/I_D)^2\\) characteristic which implies a fixed SNR for varying IC. The parameter \\(N_T\\) reflects the density of trapped charges at the oxide interface inside the transistor's conducting channel. Whether this parameter is consistent across various technology nodes is naturally put into question [^120] but similarly there is evidence supporting that indeed this factor is process independent [^121]. Now we should keep in mind that increasing the input transistor size will accommodate lower flicker noise but also result in increased noise. This is because of the signal loss when coupling \\(C_{in}\\) to \\(C_{fb}\\) that is loaded by the parasitic input capacitance of the amplifier \\(C_{g}\\) (see Figure 22). Keeping the ratio \\(C_{g}/C_{fb}\\) fixed as a \\(\delta\\), we can express the required input capacitance in Equation 9 in terms of general amplifier requirements using \\(A_{cl}\\), \\(K_F\\), \\(f_{cor}\\) as the closed loop gain, flicker charge density, corner frequency respectively. + +$$ C_{in} = \delta A_{cl} C_{g} = \frac{3}{4} \delta A_{cl} C_{ox} W L = \frac{3}{4} \frac{K_F A_{cl} \delta }{C_{ox} e^2_{in} f_{cor}} \text{where} K_F = q^2 kT \lambda N_T K_G $$ + +This expression indicates that attempting to achieve all desirable characteristics; small \\(e^2_{in}\\), small \\(f_{cor}\\), large \\(A_{cl}\\) simultaneously in a single amplifier structure comes at the cost of a very large input capacitance that scales proportionally to all factors. This representation suggests the Harrison topology has limited flexibility for improving input capacitance as the only solution appears to be minimising \\(\frac{KF}{C_{ox}}\\) through CMOS process selection. Moreover \\(\delta\\) cannot be made arability small as it will more typically be bounded by the minimum feedback capacitor \\(C_{fb}\\). This need to be large enough to set the high pass pole location at sufficiently small frequency to prevent the resistor \\(R_{fb}\\) from introducing noise inside the signal band which has a integrated power of \\(\frac{kT}{C_{fb}}\\) [^111]. Not to mention that the resulting size of the input transistors can be very large for this particular topology. + +## 21 Chopper Stabilized Amplifiers + + + +Alternatively we can apply chopping techniques to deal with these noise requirements which is used extensively in bio-signal instrumentation systems [^69]. By up modulating the signal to a higher frequency before amplification, the flicker noise is added to the usual near-DC band which no longer coincides with out input signal. The output is then demodulated to recover the input. The difference is that the flicker components now lie at the chopper frequency \\(f_{chp}\\) which is typically out of band and can be rejected easily. This eliminates the requirements from Eq 9 on the input capacitance and shifts the focus to rejecting up modulated aggressors at higher frequencies. We suggest using keeping the sampling and chopper frequency coherent because it allows low order FIR filter reject all up modulated harmonics. For instance by chopping at the half the Nyquist frequency (\\(f_s/2\\)) or odd multiples of it (i.e. \\([2n+1] f_s/2\\) $|$ $n \in \mathbb{Z}$) will fold chopper harmonics onto \\(f_s/2\\). The resulting filter are quite relaxed because of the large fractional bandwidth in the transition band that separates our signal bandwidth \\(f_{3dB}\\) from \\(f_{chop}\\). In this particular case we employ a sampling frequency of \\(25 kS/s\\) and use a chopping frequency at \\(37.5 kHz\\) to achieve this functionality [^122]. Conveniently any common mode signals from the sensor or analogue supplies are also rejected using this configuration because they will appear at the chopper frequency. + +In addition to basic chopping functionality, the performance can be further improved by providing closed loop feedback to actively cancel aggressors on top of filtering the resulting up modulated aggressors. This can be achieved in multiple ways and in some cases could improve linearity. One possible technique is using a DC-servo loop and another is performing ripple rejection both of which remove different components [^123]. Here we will consider the implementation of three such techniques that improve chopping performance that specifically have negligible power and area requirements. The considerations made here will be similar to that of [^124] [^125] but with explicit focus on area reduction. + +{{< figure src="technical_1/T1_CAMP.pdf}" width="500" >}} +{{< figure src="technical_1/T1_CAMP_T.pdf}" title="Figure 24: Proposed compact chopper stabilized neural amplifier topology. " width="500" >}} + + +Figure 24 shows the proposed configuration that promises a significant reduction in input capacitance and the required silicon area. This configuration has two gain stages where the first stage A1 is a wideband low noise stage and the second provides A2 low pass filtering as motivated by Section 20. This enables the rejection of flicker noise from the first stage completely and effectively shifts the corner frequency of the second stage by gain of first stage squared. Moreover this the configuration does not require auxiliary integrators provide feedback on the capacitive feedback network around A1 that would lead to increased complexity. + +The pseudo resistor across A1 in this configuration provides closed loop rejection of low frequency noise below the high pass pole with the time constant $\tau_{HP} = C_{F1} R_{HP}$. The noise components in the band from \\(f_{HP}\\) to \\(f_{CHP}\\) will be a mixture of flicker and thermal noise that are up-modulated by the chopper proceeding A1. This is because A1's corner frequency will lie inside of this band after sizing the input transistors such that \\(C_G\\) is about 5% of \\(C_{IN}\\) which usually leads to a target area of about 100 $\mu m^2$. + +It is important that the gains of A1 and A2 are carefully selected because this configuration only provides a first order role off in terms of analogue filtering. It could be that \\(f_{CHP}\\) is not sufficiently outside of the \\(6kHz\\) filter bandwidth resulting in some aggressors to appear on the output of A2. For this reason we require an aggressive high pass pole location to minimize this total up modulated power. More specifically we can say that the total noise contribution below the \\(f_{HP}\\) is mainly from \\(R_{HP}\\) which has a noise power of $\frac{kT}{A1^2 C_{F1}}$ when referred to the input of A1. The main concern here is that we have to sacrifice a small amount of dynamic range on A2 to prevent distortion. Although this power is quite limited, we need make sure the FIR filter can reject up-modulated noise components effectively. + +In addition we take advantage of the reduced output referred sampling noise a the input of the second stage that scales by \\(f_{3dB}/f_{CHP}\\). This is because most of the sampling noise will lie outside of the filter bandwidth. The size of \\(C_{I2}\\) can be reduced to alleviate the slewing errors due to the band limited behaviour of A1. In addition the parasitics at the output of A1 will pre-charge before \\(C_{I2}\\) is connected reducing the settling error due to the active nodes switching at the input and output. + +A common concern for chopper stabilized circuits is the resistive element of each chopper which in this case is seen at the input of the amplifier. This resistance is due to the switching capacitor \\(C_{I1}\\) that is continuously dissipating dynamic current. This can partially be compensated for by performing positive feedback from the output to assist in cancelling the dynamic current through \\(C_{PF}\\) [^123]. However this will rely on the matching of the capacitor ratios $\frac{C_{I1}}{C_{F1}} \frac{C_{I2}}{C_{F2}}$ to be equal to \\(\frac{C_{I1}}{C_{PF}}\\). This can be quite challenging if small configurations are desired that do not need exhaustive calibration. The use of a high precision ADC makes this somewhat easier because the total gain A1\\(\cdot\\)A2 does not need to be as large implies smaller ratios and better matching. Evaluating this resistance in terms of the switching capacitance will result in the expression in Equation 10. + +$$ R_{in} = \frac{1}{2 f_{CHP} \cdot (C_{I1} + C_{par} - \frac{C_{I1}}{C_{F1}} \frac{C_{I2}}{C_{F2}} C_{PF})} $$ + +This dependency should indicate that if the dynamic switching current cannot be well matched due to parasitics or variability the next objective would be to reduce the total switching capacitance. From our discussion however it appears that reducing the input capacitance is limited by the psuedo resistive noise that induces aggressors at the chopper frequency. This constraint can be mitigated using a distributed amplifier structure that splits A1 into two identical sections. This should be configured such that the second stage has its high pass pole and corner frequency proportionally larger than the first stage but scaled the gain of the prior stage. However such a topology is more constrained by parasitics that worsen the settling errors in $0.18 \mu m$ CMOS. In addition the poor control of psuedo resistive characteristics does not allow this to be convincing solution [^126]. The feasibility may be more favourable in more advanced technology nodes. Considering a value of \\(1 pF\\) for \\(C_{I1}\\) we expect slightly over \\(20 M\Omega\\) without positive feedback and approximately \\(200 M\Omega\\) with \\(10%\\) matching. This may be acceptable in either cases depending which type of electrode is used but generally any thing above \\(100 M\Omega\\) is satisfactory for most scenarios. + + +## 22 Bandwidth Limited Amplifiers + + + +Biomedical instrumentation has the advantage that the slowly varying signals prevent most implementations from facing problems due to limited bandwidth. The exception however lies with the stage that drives the input capacitance of the ADC and the settling time during sampling can be quite challenging[^127]. Particularly when multiple channels are multiplexed to the same data converter. In some sense there is an similarity when we look at NEF and bandwidth efficiency because they are strongly dependent on maximizing transconductance efficiency. + +$$ FOM \left[ \frac{MHz \: pF}{mA} \right] = \frac{f_{UGF} \cdot C_{L}}{I_{tot}} \text{for diff. pair} FOM = \frac{10^{3}}{4 \pi \eta U_{T}} $$ + +{{< figure src="technical_1/MCAmp.pdf" title="Figure 25: " width="500" >}} + + +Strictly stated in Equation 11, a bandwidth constrained circuit should minimize the total current consumption \\(I_{tot}\\) for a given unity gain bandwidth \\(f_{UGF}\\) and capacitive load \\(C_L\\). It is typical to find dedicated structures out side of the signal processing chain that drive the ADC input capacitance and focus specifically on maximizing the FOM by employing current recycling, adaptive biasing, and positive feedback techniques. The challenge here is efficiently introducing these techniques while also preserving the capability for full output swing, stability and particularly low distortion. The later is likely the most challenging and demands high loop gain that is generally not found in adaptive single pole structures if full output swing is also required. With that said, two stage Miller compensated topologies can provide an excellent solution to this problem because high gain in the second stage will suppress a number nonlinearities excited by the input stage. Further more the capacitive coupling of the output to the input of the second stage implies the settling speed is limited by bandwidth of the second stage. This allows the configuration to simultaneously provide filtering and settling while sharing many of the biasing and feedback elements. Using the model shown in Figure 25. We can show that sampling induced kick back from the ADC at \\(V_{out}\\) has negligible in pact on internal integration node as it is inversely proportional to the product $A_{cl}\cdot \frac{gm2}{gm1}$ where \\(gm1\\) and \\(gm2\\) are the transconductance of the first and second stage. This is derived from evaluating a step response due to discharging the output load \\(C_{L}\\) which has the Laplace domain response as Equation 12. + +$$ H_{step}(s) = \frac{s^2}{s^2 + (\omega_2 - \frac{\omega_1 C_{M}}{A_{cl} C_{L}} ) s + \frac{\omega_{1} \omega_{2}}{A_{cl}}} \text{where} \omega_{1} = \frac{gm_1}{C_{M}} \: \: , \: \: \omega_{2} = \frac{gm_2}{C_{L}} $$ + +{{< figure src="technical_1/T1_T2AMP.pdf" title="Figure 26: " width="500" >}} + + +Figure 26 shows the proposed circuit implementation of the two-stage amplifier used inside the second instrumentation stage in Figure 24. This structure has the advantage of providing very high loop gain across the Miller capacitor and allows full output swing due to the positive feed back structures in the current mirrors. The PMOS mirror provides high gain by cancelling the \\(1/gm\\) transresistance of from the diode connected pair leaving the high impedance node and the NMOS mirror provides positive feedback to speed up the transient behaviour on the PMOS side. When this structure provides closed loop gain larger than 20 dB it is sufficient to rely on the NMOS current mirror for stability. In fact this is equivalent to a feed-forward stabilization technique that by passes high frequency signal lag induced by the pole at the PMOS side. However when good phase margin is required at the unity gain frequency stability becomes more stringent. In this case we suggest introducing an additional capacitor across \\(V_n\\) & \\(V_p\\) to realize a zero that cancels the pole in the PMOS branch [^128]. The zero will in fact boost the effective \\(\omega_{2}\\) from $N M \frac{gm_{M5}}{C_{L}}$ to $\frac{N M + M }{2-N} \frac{gm_{M5}}{C_{L}}$. The factor M in this structure has a rather interesting implication with respect to NEF. If M is large enough this topology will have a NEF equivalent to the complementary structure. However in effect the biasing current of the intermediate branch is reduced when M is large which can move the parasitic poles in side the amplifier bandwidth. The apparent trade off between stability and NEF is unique to this structure but it is not challenging to have M=8 for low power applications. + +$$ FOM = \frac{10^3}{4\pi \eta U_{T}} \cdot \frac{2 C_L }{ C_M (1+M/K+1/K)} $$ + +The components that improve bandwidth efficiency are detailed in Equation 13. Referring this back to Equation 6 however implies the noise is dominated by the capacitor that introduces the dominant pole of the system. The observation made here is that unlike the single stage topologies, the two stage configuration can trade off input referred noise for a better speed FOM by adjusting the \\(\frac{C_M}{C_L}\\) ratio. The high level methodology applied here is replacing the \\(C_L\\) with a smaller capacitor that requires less power with the hope that stability can still be maintained by boosting transconductance power with positive feedback and current recycling. + +## 23 Circuit Implementation + + + +{{< figure src="technical_1/T1_T1AMP.pdf}" width="500" >}} +{{< figure src="technical_1/AMP_Feedback.pdf}" title="Figure 27: Schematic showing circuit implementation of the proposed compact neural amplifier. " width="500" >}} + + +Figure 27 shows the transistor level implementation of the topology used in Figure 24. The first gain stage is a highly compact complementary structure that exhibits exceptional noise performance. The second stage transistor implementation is the high gain two-stage topology discussed in Section 22. The variable gain configuration is facilitated by the digital controlled low leakage switches that connect a selected set of capacitors in feedback. This particular configuration provides more generic instrumentation of the 1 Hz to 6 kHz bandwidth. It is well known that the analogue filters introduce frequency dependent group delay near the pole locations which has been shown to degrade processing capabilities of spike sorting techniques [^129]. By placing the high pass pole well inside of the LFP band the spike wave-forms exhibit less distortion due to analogue filtering and is instead filtered using linear phase filters in the digital domain that do not suffer from such drawbacks. + +The reset mechanism on instrumentation amplifiers using pseudo-resistive elements is essential. Either during stimulation, start-up, or amplifier saturation the charge across the feedback capacitor must be neutralized before correct operation can begin. This mechanism allows the rejection of various distortion components that would other wise corrupt the latent signal integrity or digital signal processing. However there is an inherent problem with these reset switches due to the parasitic charge injection induced on the intermediate semi-floating nodes. Moreover if these elements are cascaded to increase resistance or dynamic range these sensitive floating nodes are also increased thereby building up more residue charge. A significant amount of charge can introduce a permanent reset artefact after reset as this charge redistributes internally inside the resistor. The proposed solution to this problem is by minimizing the floating nodes and guarding the floating N-Well from injected noise. This should allow a very large pseudo resistance for a sub-Hz high pass cut off frequency while maintaining exceptional reset characteristics. We minimize the resulting charge residue by absorbing the leaky diode currents and residues into the guarding amplifier. Now there will be some instantaneous off-set as the reset signal injects charge directly onto the feedback capacitor but this can be quite small when using small switches. The drawback here is that there may exist a very slow drift on the order of \\(V/sec\\) from the guarding amplifiers due to $V_{os} R_{diode}$. But simple digital assistance will suffice in eliminating this concern by periodically resetting the structure and cancelling the residue off-set. This re-introduces the high pass pole at a well defined location depending on the periodicity of the reset signal and reconstructing signal in the digital domain [^130]. + +{{< figure src="technical_1/AMP_Label.pdf}" width="500" >}} +{{< figure src="technical_1/AMP_Chip.pdf}" title="Figure 28: Physical implementation of amplifier using a 6-metal $0.18 \mu m$ CMOS process measuring $75 \times 82 \mu m^2$ in size. " width="500" >}} + + +The floor plan for this implementation is annotated in Figure 28. The typical focus for analogue layout is achieving good matching for the input transistors and capacitors to minimise off-set or undesirable signal coupling. In this case the chopper introduces a lot switching that is difficult isolate from the signal so instead we focused on minimising parasitics of the clocked nets. The common mode feedback on the second stage uses a switched capacitor and wide band amplifier to ensure accurate common mode settling without deteriorating linearity. This is important because the ADC can be quite sensitive to the sampled common mode resulting in a reduced precision if there is an unexpected offset on the sampled output. Simulated performance of the implemented topology is shown in Figure 29. This compact configuration can achieve an input referred noise of $5.6 \mu V_{rms}$ over the specified bandwidth with a noise corner frequency of 20 Hz. The performance is detailed with a clear reduction in size can be observed when compared to other chopper systems in Table 5. The total gain is \\(421 V/V\\) for this particular configuration which can be adjusted using the digital calibration bits integrated into the structure allowing different gain and power settings. The maximum available gain setting is shown in Figure 30. + +{{< figure src="technical_1/Noise_PLO.pdf}" width="500" >}} +{{< figure src="technical_1/Amp_Thd.pdf}" title="Figure 29: Post layout simulated results of the proposed instrumentation circuit. " width="500" >}} + + + +{{< figure src="technical_1/sim_gain.pdf" title="Figure 30: Post layout simulated results using periodic steady state analysis to evaluate the closed loop gain of the instrumentation circuit. " width="500" >}} + + +Table 5: Summary of performance specifications of the proposed instrumentation topology and other bio-signal chopper stabilized amplifiers found in the literature. +| Parameter | Units | This Work | Markovic [^125] | Makinwa [^123] | +|----|----|----|----|----| +| technology | [nm] | 180 | 40 | 65 | +| Supply Voltage | [V] | (1.2) | (1.2) | (1) | +| Total Current | [(\mu)A] | (1.05) | (1.67) | (2.1)| +| Bandwidth | [Hz] | (<1)-(6 k) | (1-5k) | (0.5-1k) | +| Filter Order \ Roll-off | [dB/Dec] | (20) | (20) | (20) | +| Noise Floor | [$nV / āˆš{Hz}$] | (55) | (101) | (60)| +| Noise Corner | [Hz] | $20 Hz$ | (100) | (<1)| +| Dynamic Range | [dB] | (58) | (69) | (64) | +| Area | [(\mu)m(^2)] | $6.2\cdot 10^3 $ | $7.2\cdot 10^4$| $2\cdot 10^5$ | +| Area-Power-Product | [(\mu)W (\mu)m(^2)] | (7.3 10^3) | (141 10^3) | (420 10^3) | +| NEF | | (1.08) | (2.5) | (1.66) | + + +Overall the proposed implementation performs well for supply voltages larger than \\(1.1 V\\) where the limiting factor is due to the current biased complimentary input stage. This configuration necessitates a voltage overhead requirement of \\(2V_{TH}+2V_{ov}\\). However both of the gain stages are class-A which at exhibit relatively well behaved current transients on the supplies. Class-AB alternatives do not share this feature and are more prone to disturb neighbouring recording circuits. Minimizing the dynamic current dissipation should lead to better LDO performance and lower supply induced sensor noise when many channels are integrated together. This also motivates another aspect for using a wide-band amplifier configuration for the first amplification stage because it usually implies that the common mode will also have wide band regulation. This leads to better common mode rejection in the signal band due to additional loop gain. + +# 24 Analogue Signal Conversion + + +\label{ch:T1_converter} + +Analogue to digital conversion remains to a crucial component instrumentation, particularly for full signal characterization. Even when considering the demanding constraints for integrated neural sensors, the prevalence of full spectrum signal characterization is ubiquitous in the literature. This is motivated by the efficiency and reliability of various digital processing methods that require very efficient signal conversion to discreet samples instead of processing recordings in the analogue domain. Typically the most valued performance criteria for such a system is the ADC power consumption. A Successive Approximation Register (SAR) ADC is commonly used for quantizing biomedical signals because it only dissipates switching energy that can be very small for slow sampling rates. The SAR topology is depicted in 31 and can be found extensively in BMI recording publications. + +{{< figure src="technical_1/Split_Cap_Schmtc.pdf" title="Figure 31: Schematic of a conventional N bit SAR ADC with the split capacitor at position M." width="500" >}} + + +## 25 Capacitive array miniaturization + + + +This discussion pays special attention to acquiring neural recordings that include LFPs while minimizing the required silicon area per sensor. This is motivated by wanting to integrate many sensors on chip for large arrays and secondly reducing any capacitive switching noise that can be quite difficult to reject in fully integrated systems. Recording LFPs and EAPs simultaneously will require increased ADC resolution so that the instrumentation dynamic range exceeds 60dB. Equivalently this means 10 to 14 bit precision is needed depending on the nonlinearity tolerances of the proceeding processing methods. This can be quite difficult it terms of the SAR specifications because the capacitor mismatch and sampling noise can prevent aggressive sizing on the unit capacitor. For a given ADC precision N, the SAR capacitor array will require $M \cdot 2^{N/M}+M$ unit capacitors \\(C_{unit}\\) where M is the number of equally split sections. By splitting the array into sections it should be obvious that the total capacitor requirement \\(C_{Total}\\) can be reduced to some extent. The quantization errors resulting from capacitor mismatch on the other hand is also closely related to these parameters. For given standard deviation \\(\sigma\\) and confidence interval CI we can use Equation 14 to make a simple estimate for the expected quantization error \\(E_Q\\) [^131]. + +$$ E_Q = V_{ref} \frac{\sum \Delta Ci}{2^N C_{unit} - \Delta C_{Total}} = V_{ref} \cdot \alpha(N) \frac{āˆš{2^N}-1}{āˆš{2}-1} $$ + +The above expression assumes no split configuration is used where \\(\alpha\\) represents a scaling factor that is dependent on the number control bits for each sub-DAC, $\alpha(x)= \frac{CI \sigma}{2^x - CI \sigma āˆš{2^x}}$. \\(V_{ref}\\) is the reference voltage by which the sampled input is normalized to arrive at the binary encoded result. Now extending this formulation to include the dependency of M and bounding $E_Q < LSB/2$ in accordance with the required ADC precision leads to the expression in Equation 15. + +$$ \frac{1}{2^{N+1}} \geq \alpha(N/M) \sum_{k=0}^{M} \left[ \sum_{i=0}^{M} āˆš{2^{i}} \right] \cdot \left( \frac{\alpha(N/M)}{2^{N/M}} \right)^k $$ + +There several higher order terms with respect \\(\sigma CI\\) not shown here because they have vanishing contribution as N is increased and require a numerical solution to the problem. Otherwise for M=2 and arbitrary placing the split capacitor K position in the array we can similarly reconstruct the equality from 14 in Equation 16. + +$$ \frac{1}{2^{N+1}} \geq \frac{CI\sigma(āˆš{2^{N-k}}-1)}{(2^{N-K} - CI \sigma 2^{\frac{N-K}{2}} )(āˆš{2}-1)} + \frac{(āˆš{2^{K}}-1) CI \sigma} {(āˆš{2}-1) 2^K (2^K -CI \sigma 2^{\frac{K}{2}})} $$ + +The standard deviation \\(\sigma\\) is closely related to the exact requirements for the whole capacitive DAC in terms of the total area and unit capacitor size. The dependency of \\(E_Q\\) is mainly subject to the variance due to the MSB capacitors and for each less significant bit (from MSB to LSB) the expected variance increases by \\(āˆš{2}\\) while its capacitive coupling decreases by 2. This is because $\sigma \propto 1/āˆš{A_C}$ where \\(A_C\\) is the area of the capacitor. Clearly there is a process related figure of merit here that relates to the quality of capacitors since small capacitors with excellent matching will result in the best characteristics ADCs such that we minimize the % deviation per \\(\mu m^2\\). + +{{< figure src="technical_1/Split_CAP.pdf" title="Figure 32: Numerical solution to Equation 16 relating the capacitive DAC area requirement with the DAC resolution (N) and the position of the split capacitor before capacitor K. " width="500" >}} + + +Figure 32 shows a numerical solution to the equality in Equation 16. This allows us to consider the effect of split capacitor positioning with respect to the optimal area allocation for the capacitor array. The visible plateau for small N represents the case when the design is bounded by the minimal unit capacitance. This is determined using the process documentation for the target 0.18 \\(\mu m\\) CMOS technology that gives its mismatch specifications and minimum sizing. Generally split capacitor configurations are more sensitive to parasitics they can lead to more pronounced nonlinearities. However in some cases that the unit capacitor size limits the array size such that splinting the array is an effective solution for improving power dissipation. We reiterate that this also indicates that the binary weighted configuration without splitting maximizes area efficiency if we are not limited by sampling noise or minimal capacitor sizing. In addition a fully differential DAC counter intuitively reduces the minimum size if the switching method first detects polarity before applying successive feedback [^132]. This is because the first quantization cycle does not depend on the capacitive division. This in turn means that the array can tolerate twice the mismatch error implying a 4 times smaller unit capacitance while only doubling the number of capacitors in the array. + +## 26 Model based topology selection + + + +From here there are multiple directions we can take in order to ensure efficient operation and simultaneously achieve a compact configuration. A common approach is to multiplex the SAR ADC to a large number of channels but this will also require the analogue stage driving the ADC to dissipate proportionally more power due to settling requirements on the sampling capacitance. From a high level perspective, distributing the quantization effort into a large array of ADCs with staggered operation should lead to much more systematic power dissipation due to their uncorrelated operation. Opposed to using a single high speed ADC that requires a much higher clock frequency with stronger tones in the generated supply noise. Another SAR based alternative using calibration for the capacitive array such that it can specifically be designed with the smallest possible unit capacitors. Then we could correct any nonlinearity or quantization errors that arise from capacitor mismatch if the array is characterized precisely enough. This does require either foreground or background calibration modules to extract the individual capacitor weights. Because we aim to perform a number of processing techniques in the digital domain for characterizing neural recording, it makes sense for us to consider effective means to perform calibration. + +{{< figure src="technical_1/SDADC.pdf" title="Figure 33: Schematic of the proposed $\Sigma \Delta$ assisted SAR ADC topology for achieving a more compact configuration." width="500" >}} + + +The structure illustrated in 33 represents a hybrid topology based on SAR and sigma delta structures. The motivation is driven by the efficiency of SAR quantization for large signals and the compactness of high resolution quantization from sigma delta loops. The digital control will perform fully differential bottom plate sampling of the input which is then rapidly quantized to \\(2^N\\) levels using the typical binary search. After the SAR operation the resulting residue left on the capacitive array is quantized using a sigma delta control loop that feedback on the nodes \\(V\Sigma\Delta\pm\\). + +There is a strict advantage over conventional sigma delta loops which is that the residue error that needs to be quantized is reduced to \\(\frac{V_{ref}}{2^{N}}\\) which can easily be designed to lie within the linear range of a differential pair. This negates having to use passive or active feedback to deal with transconductance nonlinearity and significantly improves the power efficiency by retaining a relatively simple control loop topology. Moreover as the feedback loop is typically responsible for small dynamic range of 30dB the requirements on clock jitter and decimation filtering is made more relaxed. + +The more desirable advantage over a high resolution SAR is that the capacitive DAC may designed in a highly optimal configuration with as few bits as possible. This allows sizing that primarily focuses on suppressing parasitic effects with minimal sampling capacitance. As will be demonstrated this topology does not require an axillary calibration DAC or a pseudo random dithering source for performing mismatch correction. This is due to the capability that the internal sigma delta structure is in the same signal loop as the SAR operation and can trade-off bandwidth for increased noise rejection simply by adjusting the sampling frequency \\(f_s\\). Naturally because this topology inherently needs a pre-amp stage for SAR conversion we should not expect the FOM to do better than low resolution SARs. + +Intuitively one can think that when combining the two topologies the individual sources for power dissipation now scale with \\(2^{\frac{N}{2}}\\). More specifically these sources come from the capacitive DAC and decimation filter. The components that do not have reduced scaling are related to the sampling noise and the thermal noise floor of the oversampling modulator. To demonstrate this quantitatively we will build an analytic model for the SAR and \\(\Delta\Sigma\\) SAR topologies to demonstrate some of the inherent characteristics. This will also reveal the techniques for optimizing of the proposed structure. + +$$ FOM_{ADC} = \frac{P_{sys}}{2^{N} f_s} $$ + +Maximizing the performance indicator from Equation 17 will represent our objective function which reflects the efficiency by which each sample is converted into a digital code. Through the simplicity of this relation, any comparison primarily requires an accurate expectation for power budget in terms of the required resolution or precision requirements. + +$$ P_{Ideal} = \underbrace{ E_{search} \cdot f_s C_{unit} V_{ref}^2 (2^{N-2}+2^2)}_{Capacitor Array} + \underbrace{2N (N+2) f_s E_{gate} }_{Register Logic} $$ + +Equation 18 Considers the primitive structure with an ideal comparator where \\(E_{search}\\) represents the average dissipation for binary search switching method and \\(E_{gate}\\) is the average gate dissipation per clock cycle. Both these parameters adjust to different core libraries or various switching methods that typically trade off efficiency for parasitic tolerance [^133]. This ideal structure is extended by the requirements of either a dynamic latch comparator or an analogue pre amplifier that allows negligible comparator requirements at the expense of consuming a static current. The classic pre-amplifier approach also tends to deal with mitigating kick back noise but in general the straightforward application of classic \\(kT/C\\) relations conveniently give; + +$$ P_{amp} = 32 \pi \ln(2) \cdot \underbrace{\frac{(U_T N 2^N)^2}{V_{ref} \cdot \eta q}}_{Noise} \cdot \underbrace{A_{ol} f_s NEF^2}_{Bandwidth} $$ + +Here \\(A_{ol}\\) represents the gain provided by the pre-amplifier. Notice the very typical inverse relationship with respect to \\(V_{ref}\\) which motivates the use of the more efficient dynamic comparator structure. However evaluating the equivalent input referred noise of a dynamic structure accurately requires the a piece wise evaluation for different phases of operation and the respective stochastic integrals [^134]. The contribution can be associated with two dominant sources, that of sampled noise; + + +$$ \sigma_{S} = \frac{4 kT}{3 C_x F} + \frac{ kT}{3 C_x F^2 H} + \frac{ kT}{12 C_x F^2 H^2} $$ + +And noise contributed from transconductive elements; + +$$ \sigma_{M} = \frac{kT}{C_x F^2} + \frac{kT}{2 C_x F^2 H} + \frac{kT}{8 C_x F^2 H^2} $$ + +$$ F = \frac{2 \rho V_{th}}{V_{ref} - V_{th} } \text{and} H = \frac{V_{ref}}{2 V_{ov}} \cdot {2 \rho }{1 + \rho} $$ + +As before, this must be bounded by the acceptable quantization noise, $ V_{ref} \cdot {2^{-N-2}} = āˆš{\sigma_M + \sigma_S } $, which give the values for \\(C_x\\). Strictly there is a strong dependence on the input signal in order to evaluate the dissipated power but on average it is reasonable to approximate this to the capacitive switching energy of $P_{Latch} \approx f_{s} C_x V^2$. + +Now consider the components of the \\(\Delta\Sigma\\) structure. Clearly it will follow closely to that of the pre-amplifier based relations with the exception that the primitive components from Equation 18. Instead this will scale with \\(N-K\\) where \\(K\\) is the number of bits resolved by the sigma delta loop. Here two additional components will be accounted for, the first is the integrator and the second is the digital FIR that decimates the modulated residue quantization. A second order feed forward integration topology is chosen for \\(H(s)\\) based on its efficacy of being applied to the configuration shown in Figure 33 and primarily minimizing the number of summing operators and coefficients prone to mismatch. For the sake of discussion we make the assertion that decimation noise rejection is bounded $K \leq (FIR)^{-1/2}$ in the case of a rectangular window for analytic clarity [^135]. Furthermore, note that as we increase the SAR quantization the first stage will proportionally see a reduction of the input signal that needs to be accounted for to achieve the correct integration constant. + +$$ P_{int} = 32 \pi \cdot \underbrace{\frac{(U_T 2^{N} NEF)^2 }{ q V_{ref}}}_{Noise} \cdot \underbrace{FIR f_s (1+2^{N-K}) }_{Bandwidth} $$ + +And similarly the digital decimation filter will scale in the form of; + +$$ P_{fir} = \underbrace{2^{K}}_{OSR} \underbrace{( K + \log_{2}(K))}_{Quantization} fs E_{gate} $$ + +Collecting these terms for each topology will equate to expressions that typically have scalar dependencies on technology or implementation which we must make a set of reasonable assumptions for. The literature will indicate numerous means by which each component can be reduced through specialized logic cells, adaptive comparator power allocation, or power saving switching methods. Our particular interest lies with the dependency on N that will imply the effectiveness of a certain topology for a given dynamic range requirement. In addition this familiarizes us with specific factors fundamental to power dissipation with respect to resolution. + +{{< figure src="technical_1/P_TOP_N.pdf}" width="500" >}} +{{< figure src="technical_1/P_TOP_A.pdf}" title="Figure 34: Summary of the FOM (\\(P_{sys}/2^{N} f_s\\)) for each topology with respect to different resolution requirements. " width="500" >}} + + +Figure 34 presents the expected merit for each topology as the target resolution is varied. Without consideration for area, there is a clear power advantage for the dynamic SAR structure mediated primarily by the fact that the comparator does not have settling associated tolerance. This is the main reason why the pre-amp topology requires a proportionally increased bandwidth/power as resolution is increased. What stands out is that the \\(\Delta\Sigma\\) structure has a power dependency $\propto 2^{3N}$ for achieving the required input referred noise in contrast to more conventional dependency of \\(2^{2N}\\). The mechanism behind this is due to the SAR quantization that reduces the signal input range which needs to be recovered to achieve the correct integration factors. Moreover the over sampling ratio increases simultaneously which has an overall multiplicative effect. Clearly the resolution of the SAR quantizer should only perform a few conversion that put the residue in the linear range of the loop filter and let the modulator perform most of the quantization effort. When all topologies are using the same unit capacitor, this result demonstrates that for \\(N < 5\\) & \\(N > 14\\) the \\(\Delta\Sigma\\) topology becomes strictly unfavourable in terms of power but performs comparably with respect to power efficiency for \\(N \approx 10\\). Taking the FOM area product by considering the capacitors in terms of \\(\Box\\) units the advantage of the \\(\Delta\Sigma\\) topology becomes more obvious. For the precision significant to neural recording, \\(8}} + + +Considering the design space of the \\(\Delta\Sigma\\)SAR structure in more detail will expose a more optimal strategy for increasing FOM. Figure 35 exemplifies how the FOM behaves as either the SAR of sigma delta accuracy is increased. After the optimal basin at N = 9 & K=4 the best strategy for improving ADC resolution is by increasing SAR quantization at half the rate of the sigma delta increase in resolution. For reference a conventional $\Delta \Sigma$ modulator [^136] is designed with the same target specifications and using the same design method to configure the OPAMP integrators and resistive input network. Such a configuration achieves 167 dB FOMs irrespective of target resolution when we consider just the analogue power dissipation. In fact this figure is commonly achieved by state of the art [^137]. As shown in Figure 36 the \\(\Delta\Sigma\\)SAR configuration can theoretically achieve more than 4X better performance than conventional \\(\Delta\Sigma\\) modulators for resolutions above 12 bits even when operating at lower supply voltages. This is because of the improved noise efficiency. Please refer to Section 58 for additional details regarding derivations and topology comparisons that are omitted here for clarity. + +{{< figure src="technical_1/AMD.pdf" title="Figure 36: Estimation on the expected figure of merit for a target resolution and varying SAR precision. The red star and blue circle indicate the target and measured performance respectively. " width="500" >}} + + +## 27 Circuit Implementation + + + +Extending the conventional SAR structure to perform sigma delta modulation is achieved with relatively little changes to the overall topology. The main difference is that during the last phase of SAR conversion a register must be toggled that switches in the integrators intermediate to the comparator. Simultaneously the \\(V\Sigma\Delta\pm\\) capacitors are directly connected to the comparator bipolar output instead of the common mode voltage \\(VCM\\) for differential feedback. This configuration is integrated on chip and performs 7 bits of differential SAR quantization with another 5 bits resolved by the noise shaping modulator with an over sampling rate of 32. At the system level, 4 analogue recording channels will be multiplexed to the input of the ADC which implies sampling rate of \\(100 kS/s\\) is required to sample each output at \\(25 kS/s\\). + +{{< figure src="technical_1/SAR_Arch.pdf}" width="500" >}} +{{< figure src="technical_1/SAR_Logic.pdf}" title="Figure 37: Schematic configuration of the top level control for the \\(\Delta\Sigma\\)SAR data converter." width="500" >}} + + +Figure 37 shows the top level configuration of this data converter. By using a specialized register logic slice a small reduction in complexity is achieved in addition to the mitigation of timing issues typical with the conventional self clocking register configuration. This topology uses a bottom plate sampling strategy to neutralize the effect of parasitics and common mode comparator nonlinearities while operating at 1.2V with a 10MHz clock frequency. Although there are only \\(N-K+OSR\\) active phases, settling the output of the recording amplifiers on to the capacitor array will require several cycles because of the band limited behaviour present in the driving stage. + +The implementation of the capacitive DAC and second order feed-forward integrator are shown in Figure 37. This configuration also opts to scale the voltage reference for the LSB in order to reduce the total number of capacitor required. As the capacitor array is implemented using CMIM devices the 7 bit differential structure with a split capacitor for \\(M=3\\) will grantee 10.1b for a confidence interval of \\(3\sigma\\) using Equation 16 and process documentation parameters that show a $8\times8 \mu m$ has \\(0.23 %\\) mismatch induced standard deviation. The reasoning for this configuration is that we are guaranteed \\(>9.5 bits\\) without calibration and will allow \\(>12 bits\\) with calibration. For either case the accuracy is sufficient for recording LFP and EAP signals simultaneously. This result was also confirmed with monte-carlo analysis using foundry supplied PSP models. + +{{< figure src="technical_1/T1_SDSAR_CDAC.pdf}" width="500" >}} +{{< figure src="technical_1/T1_SDSAR_INT.pdf}" title="Figure 38: Schematic implementation of the \\(\Delta\Sigma\\)SAR structure. " width="500" >}} + + +The integrator topology primarily deals with the contrasting bandwidth requirement of the SAR operation and the sigma delta integration for the first stage. Particularly when taking the SAR decisions at the oversampled clock the first stage can only provide wideband gain if the capacitor is switched out and a resistive element is used instead. The circuit complexity can be dramatically reduced by using triode region transistors that regulate the PMOS biasing current for a well defined common mode. Because these transistor can be large in area they could slow down the maximum SAR speed. To avoid this the CMFB circuit is semi open loop during the SAR quantization leading to an increase bandwidth by using the common mode voltage that preserved on the integration capacitor. Also by switching the biasing current of the analogue summing stage a constant common mode can be presented to the comparator input thereby reducing any off-set disparity between the two operation phases. + +{{< figure src="technical_1/ADC_Label.pdf}" width="500" >}} +{{< figure src="technical_1/ADC_Chip.pdf}" title="Figure 39: Physical implementation of ADC using a 6-metal $0.18 \mu m$ CMOS process measuring $93 \times 147 \mu m^2$ in size." width="500" >}} + + +Figure 39 shows the fabricated structure of the ADC. Since the capacitors are placed on top of the active circuits this floor plan distances the integrators and the MSB capacitors to physically isolate the digital switching noise sources. A number of shielding structures are employed to improve post layout performance. There include various guard rings and isolating N-wells but due to the proximity of the digital switching the most effective strategy is appropriately orienting fully differential structures in order to equalize the coupling components. Here metal layers 1-3 are used for transistor interconnect, layers 5-6 for the capacitive DAC, and layer 4 is interposed in order to shield the two sections while connected to the common mode voltage. This is because the transient fluctuations on \\(V_{cm}\\) are only due to mismatch and should be the most quiet reference in the system with large capacitive loading. + +In order to take advantage of this structure we reveal two distinguishing characteristics that can not be found in either conventional topologies or other hybrid topologies. When the capacitive DAC is considered as a set of weights that need to be determined we realize that the derivative for slow varying signals is predominantly quantized by the sigma delta loop. With the exception when the SAR bits switch the quantization is independent of the mismatch in these weights. As a result all the mismatch coefficients can be accounted for with respect to the $\Sigma \Delta C$ capacitor. + +{{< figure src="technical_1/adc_cloop.pdf" title="Figure 40: Control loop used to perform calibration with a slow test signal at the ADC input." width="500" >}} + + +The calibration technique discussed is abstractly represented by Figure 40 where there are two IIR control loops with the coefficients \\(a_1\\) and \\(b_1\\). In part this loop performs normal operation by evaluating the signal quantization \\(Q_{sig}\\). This is done adding the SAR quantization with calibrated weights and decimating the oversampled residue with a \\(32^{nd}\\) order FIR window quantized with 8 bit coefficients for each sample. Here \\(a_{1}\\) simply has to be small enough to track the signal and reject noisy components to determine $\Delta Q$. $\Delta Q$ represents DNL nonlinearities that are used to adjust the coefficients \\(K_{DAC}\\). The multiplication operator is in fact a bitwise evaluation that indicates if a coefficient needs to be adjusted due to a correlation between $\Delta Q$ and a change in that bit. Hence \\(b_{1}\\) needs to be small enough to prevent level dependent tuning and \\(V_{test}\\) should be a full range slow varying signal. + +{{< figure src="technical_1/adc_UC.pdf}" width="500" >}} +{{< figure src="technical_1/adc_CC.pdf}" title="Figure 41: INL Plots illustrating the mismatch artefact reduction due to calibration." width="500" >}} + + +The improvement in INL is evident in Figure 41 due to the calibration mechanism with \\(a_1=1/4\\) and \\(b_1=2^{-8}\\). The close interaction between INL & DNL errors over the full dynamic range for a capacitive array in addition to the sigma delta loop's capability of quantizing $\pm 2 LSB$ of the array allows this method to converge accurately. Here it is observed that the calibration improves the quantization accuracy by two additional bits. + +{{< figure src="technical_1/adc_thdsnr.pdf" title="Figure 42: Measured THD and SNR of the fabricated data converter." width="500" >}} + + +{{< figure src="technical_1/ADC_TEST.jpg}" width="500" >}} +{{< figure src="technical_1/adc_TI.pdf}" title="Figure 43: Testing setup used for characterizing the ADC." width="500" >}} + + +Figure 43 shows the test bench used during device characterization. The saleae logic device is a digital probe that offers 100 MS/s digital signal acquisition for measurements of up to 10 seconds. Here the raspberry pi module simply provides real time interaction with the device configuration using automated spi control and a graphical user interface that will indicate ADC precision based on the selected operation. This allows us to tweak the operating conditions and find which noise sources are disturbing the configuration. The analogue bias \\(I_{BIAS}\\) is generated by a 2602A Keithley system source meter and fed in using a guarded triax cable. The differential input signals are generated using a Agilent 33522A arbitrary waveform generator and fed to the ADC input using BNC cables. + +Table 6 outlines the characteristics of the implemented ADC configuration while comparing it to recent oversampling/noise shaping data converter publications. Figure 42 demonstrates the spectral characteristics of the quantization output for a input signal at half the full input range after calibration. In comparison to the analogue instrumentation, the resource related specifications are significantly larger. However note that there requirements are distributed over a number of channels as a result of multiplexing this structure. + +Table 6: Summary of performance specifications for the \\(\Delta\Sigma\\)SAR data converter and other oversampling/noise shaping data converter structures found in the literature. +| Parameter | Units | This Work | Lo [^138] | Roermund [^139] | +|----|----|----|----|----| +| Technology | [nm] | 180 | 65 | 65 | +| Supply Voltage | [V] | (1.2) | (1.2) | (0.8) | +| Total Current |[(\mu)A] | (12) | (13) | (1.7) | +| Sampling Frequency | [kS/s] | $200 $ | (8) | (16) | +| ENOB | [bits] | (11.3) | (17.5) | (14.5) | +| SFDR | [dB] | (86) | (105) | $ 87 $ | +| Area | [$\mu m^2$] | $93 \times 147$ | $400 \times 180$ | $600 \times 300$| +| Power-Area-Product | [$\mu W \mu m^2$] | $1.9 \cdot 10^5$ | $1.1 \cdot 10^6$ | $2.4 \cdot 10^5$| +| $P/(fs + 2^N)$ | [fJ/conv] | (10) | (29) | (6.6) | +| (SNDR+10log(BW/P)) | [dB] | (166) | (180) | (177) | + + +The trade off with respect to residue over sampling in Figure 44 demonstrates that there is some flexibility with respect to sampling rate and SINAD performance. In addition this also clarifies that post-fabrication adjustments do not exhibit significant resolution improvements beyond the design point. This is related to the sampling noise of the capacitor array and the noise floor of the analogue integrators that need to be programmable for different oversampling ratios. At which point the decimation also has more strenuous requirements that may result in an inefficient resource overhead. Strictly stated it is significantly more efficient to reject noise with digital bandpass filtering selected frequency components than having the ADC resolve the signal beyond the target precision. + +{{< figure src="technical_1/adc_fom.pdf" title="Figure 44: Measured Figure of Merit as a function of oversampling ratio." width="500" >}} + + +In the context of miniaturization the topology presented here follows closely to the expected improvement from the model for high resolution signal acquisition. We achieve nearly 12 bits of quantization with a 6 bit equivalent capacitive DAC which is reflected in the compact design foot print. When compared to similar compact ADC implementations found in recent publications we observe a competitive power budget with again significantly smaller area requirement. Some additional digital processing is required opposed to the simplicity of SAR converters to take full advantage of the topology. However such hardware is typically readily available in systems that also perform spike sorting and neural signal classification. + +# 28 System Level Abstraction + + +\label{ch:T1_model} + +Numerous specifications such as ADC resolution and input referred noise of the instrumentation amplifiers relate directly to signal specific parameters. Moreover a particular processing algorithm would favour certain filter configurations of others in terms of signal conditioning. In multi stage systems however there is a significant amount of flexibility related to choosing gain for individual stages or their filter parameters that is indifferent to the resulting transfer function. Here we consider such a primitive \\(N\\) stage analogue processing chain and discuss the allocation of resources to gain insight to some of the high level the optimization for selecting a specific configuration. Such a configuration is shown in Figure 45. + +{{< figure src="technical_1/ACS.pdf" title="Figure 45: Multistage amplifier configuration using the series G to adjust the allocation power and area. " width="500" >}} + + +$$ G[n] = A_{g} \left( \beta + \alpha^{n} \right) \text{where} A_{g} = āˆš[N]{\frac{G_{T}}{ \prod_{i=1}^{N} (\beta + \alpha^{n} )}} $$ + +Consider a geometric series for the gain of each stage as expressed in Equation 25. Here \\(G_{T}\\), \\(\alpha\\), \\(\beta\\) represent the total gain required, resource distribution factor, and a minimal contribution factor. The formulation is motivated by the fact that if \\(\alpha\\) is one resources are allocated equally. This means every stage has equal gain but it also implies that the sum of all gain factors is minimal leading to a minimum amount of area due to the feedback capacitors. More typically designs will choose a smaller \\(\alpha\\) such that most of the gain is situated at the first few stages. This allows some reduction in power in the proceeding stages because of the reduced noise requirement. \\(\beta\\) simply allows us to specify that a fraction of the total gain is uniformly distributed but is typically kept small in order to maximize the benefit from resource redistribution. This allows us to express the noise power requirement for a given set of parameters in Equation 26. + +$$ P_{Amplifiers} = P_{unit} \left( 1 + \sum_{k=1}^{N-1}\left[\prod_{i=1}^{k} \frac{1}{A_{g} \beta + A_{g} \alpha^{i} } \right] \right)^2 $$ + +$$ A_{Gain}= A_{unit}\left( \sum_{k=1}^{N} \left[1 + A_{g} \beta + A_{g} \alpha^{k} \right] \right) $$ + +Here \\(P_{unit}\\) is simply evaluated from Equation 6 and leads to an area requirement that is simply expressed using Equation 27. Now taking some typical parameters we can evaluate a possible configuration of gains and thereby the associated allocation of resources. This is shown in Figure 46. + +{{< figure src="technical_1/RDBG.pdf" title="Figure 46: Resource allocation for analogue power and area using the parameters \\(G_T=500\\), \\(\alpha=0.3\\), and \\(\beta=0.05\\). " width="500" >}} + + +Lets take \\(A_{unit}\\) as some unit capacitance size that allows the deviation of gain due to mismatch to fall inside the confidence interval. In order to realize Equation 26, each stage has its power and input referred noise reduced by accumulated gain for the preceding stages. This result presents us with the trend illustrated in Figure 47 where it appears that in many stage systems it is relatively beneficial to redistribute the resources to the front-end for a reduction in overall power. However when the number of stages is three or less we observe the increase in area can diminish this improvement for high gain system requirements. + +{{< figure src="technical_1/NM_NP.pdf}" width="500" >}} +{{< figure src="technical_1/NM_PAP.pdf}" title="Figure 47: Normalized resource improvements for \\(\alpha\\) with respect the case when \\(\alpha=1\\) for each configuration. " width="500" >}} + + +So far we have neglected some aspects to the design consideration. The first is the multiplicative increase standard deviation as N is increases and the sensitivity to variance being inversely proportional to closed loop gain. Here we can account for the increased variance by proportionally increasing \\(A_{unit}\\) in order to neutralize this increase according to Equation 28. + +$$ \Delta \sigma^2 =\frac{A_{\mu+\sigma}}{A_{Gain}} \approx \prod_{i=1}^{k} \left( 1 + \sigma CI \left[ 2 - \frac{2}{āˆš{ A_{g} \beta + A_{g} \alpha^i }} \right] \right) $$ + +Again \\(\sigma\\) represents the deviation for a chosen unit capacitance and \\(CI\\) is our confidence interval. For completeness in estimating area we will also introduce the capacitance required for performing filtering on the last \\(K\\) stages. Rearranging Equation 6 in terms of output referred noise according to Equation 29. + +$$ e^2_{out} = \frac{kT}{C} {NEF^2}{\eta} $$ + +Combining these terms lets us define a more accurate area requirement that is reformulated in Equation 30. + +$$ A_{filt} = A_{unit} \cdot \frac{kT}{C_{unit}} \frac{NEF^2 SNR^2}{Vdd^2 \eta} \cdot \left( 1 + \sum_{k=1}^{K-1} \prod_{i=1}^{k} \left[A_{g} \beta + A_{g} \alpha^{N-i} \right] \right) $$ + +It is important to point out that SNR here refers to the SNR of the data converter as we have fixed the input referred noise of the system for a systematic comparison and we adjust \\(G_T\\) to fill this dynamic range. And extending this result with the requirements for signal conversion we can estimate system level power \\(P_{Total}\\) and area \\(A_{Total}\\) requirements as a sum of individual components according to Equation 31. + +$$ A_{Total} = A_{filt} + A_{Gain} + A_{ADC} \text{and} P_{Total} = P_{Amplifiers} + P_{ADC} $$ + + +Taking an appropriate set of parameter values, the system of relations is exemplified in Figure 48 with respect to the dependency on the supply voltage, \\(Vdd\\). As illustrated there are two domains when considering the area requirement. For small \\(Vdd\\) the sampling & filtering noise requirements overwhelm the design particularly in this case if \\(\alpha\\) is not taken small enough and a second order roll off is needed. When there is more voltage overhead available we observe reliably matching in input dynamic range of the ADC is the dominating factor. + +{{< figure src="technical_1/NM_TSNA.pdf}" width="500" >}} +{{< figure src="technical_1/NM_TSNAP.pdf}" title="Figure 48: Analogue resource relations with respect to different supply voltages. " width="500" >}} + + +The area power product also tells an interesting story. When \\(Vdd\\) is larger than 1 V a clear proportional dependency on power is apparent that is mostly related to the total gain & noise requirements of the system because the ADC is not the limiting factor. However for small supply voltage the power dissipation requirement is more closely related to the lower noise quantization requirements presented by the SD-SAR topology. We should be careful because certain circuit topologies are simply not viable below specific supply voltages and as a result it would no be possible to achieve a NEF smaller than 2. Figure 48 also indicates when particular topologies are viable specific to the $0.18 \mu m$ CMOS process where $V_{th} \approx 350 mV$. That said it is likely a system can be designed with \\(0.6 V\\) supply in order to achieve significant power and area savings. The main challenge will be achieving acceptable total harmonic distortion as the supply will not easily allow cascoding transistors. Particularly sub-threshold transistors suffer from \\(Gm\\) nonlinearity as a function of \\(e^{\frac{-V_{DS}}{U_T}}\\) that can only be compensated by increased loop gain and multi-stage topologies. Since it is implementation dependent, it is difficult to quantify what this increase in area an power overhead this will result in. We can assert that \\(60 dB\\) precision with instrumentation has very significant diminishing returns when the conventional design approaches a \\(2 V_{th}\\) supply. The reader can find more details in regard to these comparisons in Section 60. + +The approach taken here can be exhaustively extended towards including more detail in the system level design in order to leverage the capability of numerical methods. Higher order Gm-C filtering structures can be accounted for as a single stage by introducing new parameters that reflect the increase in \\(NEF\\) and filtering capacitors. Transistor area per amplifier can arguably be assumed static if chopping techniques are employed or alternatively this can accounted for by considering the flicker noise relations for the input transistors. However these contributions have negligible effect on changing the optimal resource destitution and will be more influenced by strategic positioning of poles to reject certain noise components. The most critical parameters on the systems level is the supply voltage as well as the requirement for channel to channel gain matching. As the power area product has a inverse square dependency as either \\(V_{DD}\\) or gain variance tends to zero. There are only a select number of scenarios where gain matching is of significance which is primarily in the case of distributed LFP recording and multi electrode (i.e. tetrode) recordings where exact coupling of neural circuitry is in question. The supply voltage has significance with respect to the expected power dissipation of the on chip digital processing and it is understandably advantageous to aggressively dissipate more power on the analogue side if the power saving in the digital domain indicate a overall improvement. + +We note another aspect to technology selection in addition enabling voltage scaling is the increase in functional capacitor density. In fact we have shown that the dominant factor for area requirement in chopper stabilized structures is capacitance through the strong dependency on gain and filtering elements. More advanced processes have an increased number of metal layers and higher transistor gate capacitance. This ultimately leads to an increased capacitor density per square millimetre. In certain scenarios this should allow us to marginally shrink amplifier configurations while keeping the same filter characteristics. The main concern would be associated with capacitor nonlinearity that requires extra consideration or correction circuits. + +\fi + +# 29 Conclusion + + + +This chapter has demonstrated the capacity for conventional analogue instrumentation with state-of-the-art circuit techniques. This presents capacity for achieving very compact performance that is sufficient for the full characterization of neural recordings. The fabricated system uses 0.03 mm\\(^2\\) size silicon footprint for 4 recording channels that can characterize 5 mVpp neural signals with over 11 bits of precision. In addition proposed $\Delta\Sigma SAR$ ADC topology demonstrates how oversampling converters can achieve 10fJ/conversion efficiency with minimal circuit complexity. The techniques applied here suggests chopping and sigma-delta modulation are key components for achieving better performance particularly for size constrained systems. In association we suggest immediate digitization & coherent mixed signal processing to leverage a number of advantages. Moreover we expect modern system will allow more processing capabilities in the digital baseband for BMI systems that needs to be used effectively. + +The significance of minimizing the noise efficiency factor has been revealed in terms of having profound influence to power dissipation and area. In extension we have presented a number of topologies that excel at achieving excellent power and area efficiency in the case of single stage, two stage, and ADC structures. However we are left with little surprise when methodical optimization of various configurations is limited by the fundamental bounds in terms of noise and dynamic range. In fact various idealized configuration show little benefit with respect to one another if they have been optimized and exploited appropriately with the understanding presented. It is characteristic that improving resource efficiency for full bandwidth signal quantization is difficult because we simultaniously attempt to achieve lower supply voltages. + +Although digitization is crucial to most neural recording systems for extracting the signal characteristics used to train and improve signal postprocessing. It is clear that improvements at the system level will lie very much in the domain of specialized instrumentation and analogue to information converters. This notion is motivated by the desire for the system to be limited by the law of equipartition and less so by the quantization process of the data converter. The direct classification of recordings in the analogue domain has significant implications on the responsibilities of the accompanied DSP on chip and the reduction of associated processing bandwidth. + +# 53 Conclusion + +As brain machine interfaces continue to progress in establishing a better communication link between neural activity and our models for cognitive or behavioural dynamics. We can expect with certainty the design considerations of these systems will remain a very involved process. Using abstractions and resource models will play a pivotal role in realizing these complex systems. Particularly as these systems require operational efficiency far beyond current state-of-the-art to enable chronic and implantable neuro-prothetics for full limb replacement. The models discussed here not only guide the design process towards more optimal systems they also provide excellent insight to inherent design limitations at different stages of design though clarity in system level objectives. A considerable amount of effort was put into realizing highly efficient and ultra-low power amplification of signals which can naturally be extended towards improving on-chip voltage regulators or RF-telemetry circuits to advance the capabilities of these systems while operating with several hundred millivolts of supply head-room. + +There still remain many opportunities as emergent processing modalities that find them selves adapting to the current paradigm or platform of operation. Currently that paradigm is nanometre CMOS which suggests nothing other than ''there is plenty of room at the bottom'' [^201]. While the results presented here advocate for transitioning to smaller feature sizes to miniaturize recording and increase the in channel processing capabilities that accommodate the algorithms for extracting information from electrode recordings. We must also give way to software abstraction that deals with the increased complexity of these systems to retain long term utility and higher level adaptive function. Moreover we signify the resulting flexibility empowers electronic sensing systems to meet the broad set of challenges found in fabrication, implantation, and realization of chronic solutions. If we consider the maximal density of the proposed structures, by estimation for two-dimensional sensing arrays it is viable simultaneously record at a density of 400 locations different simultaneously per square millilitre of CMOS chip. That figure for some areas in the visual cortex implies a ratio on the order of 100 neurons per electrode [^202]. This encourages us that this direction is an important step forward towards high fidelity neural decoding systems and will allow precise studies of neural circuits in rodents for disease models. + +Putting our findings in perspective of the SAR limit to inducing power inside the body [^203] and state-of-the-art results in midfield powering of millilitre sized implants as coupling scenario for implants deeper than 5cm[^14]. This work suggests the power budget for a 2 mm\\(^2\\) CMOS chip and coil is around 200\\( \mu\\)W at 11% of the maximum safety threshold. This may be improved with near-field coupling of multi coil configurations but either solution is challenged in powering multiple devices without more active electronics. We can be confident that our micro-controller structure in 65 nm CMOS is compact enough that the main limitation is power related. Extrapolating the power requirements from the current 180 nm CMOS design gives us the impression that we can integrate at least 136 reconfigurable instrumentation channels dissipating \\(1.47 \mu\\)W by both analogue and digital domains. In fact integrating 64 channels can already be realized by our 180 nm CMOS implementation with power induction at 71% of the maximum safety threshold. While this seems unattainable by many systems presented in the literature today we argue that this approach will even allow active telemetry with UWB data transmission from the chip because of the highly compressed data-rates [^204]. + +# 54 Original Contributions + +The technical contributions presented by this thesis are detailed in the list below of which some has already been published. These publications are outlined in Section 56. + +\begin{minipage}{0.9\textwidth} +\begin{itemize} + \item{**Chapter 16**} + \begin{enumerate} + \item[\\(-\\)]{A 1.26 \\(\mu\\)W instrumentation amplifier with 6 kHz bandwidth that provides 52 dB gain and exhibits a input referred noise figure of 5.6 $\mu V_{rms}$ with a flicker noise corer of 20 Hz.} + \item[\\(-\\)]{A 14.4 \\(\mu\\)W 11.4 ENOB \\(\Delta\Sigma\\)SAR ADC that can perform 200 kS/s with a 2.4 pF sampling capacitance that achieves a 10 fJ/conversion figure of merit.} + \item[\\(-\\)]{Fabricated fully integrated signal acquisition front end that uses 0.01 mm\\(^2\\) of silicon area to perform 5 mVpp signal quantization with a 58 dB dynamic range.} + \end{enumerate} +\end{itemize} +\end{minipage} + +\begin{minipage}{0.9\textwidth} +\begin{itemize} + \item{**Chapter 30**} + \begin{enumerate} + \item[\\(-\\)]{PCA & template matching spike sorting method for embedded systems that require 57 operations per sample and 680 bits of memory to perform fully unsupervised classification with \\(>\\)80% accuracy.} + \item[\\(-\\)]{A 1.52 GOPS/mW distributed processing architecture for neural recording applications that has a 0.02mm\\(^2\\) silicon foot print with fully reconfigurable 8 bit processing capabilities.} + \item[\\(-\\)]{Linux based development platform for developing decoding techniques with support for C/C++/Python and other functional languages.} + \end{enumerate} +\end{itemize} +\end{minipage} + +\begin{minipage}{0.9\textwidth} +\begin{itemize} + \item{**Chapter 43**} + \begin{enumerate} + \item[\\(-\\)]{A 0.6 V 58 dB SNDR time domain instrumentation architecture with a NEF of 1.18 that generates multiphase PWM encoded digital signals with a sub 0.01 mm\\(^2\\) footprint.} + \item[\\(-\\)]{A 4\\(^{th}\\) order oscillator based bandpass filter for conditioning the time domain signals with reconfigurable gain that dissipates 120 nW of power.} + \item[\\(-\\)]{Unsupervised analogue classification technique that achieves over 72% accuracy without necessitating signal quantization or a large number of analogue components.} + \end{enumerate} +\end{itemize} +\end{minipage} + +# 55 Future Work + +We have presented some of the most compact high performance instrumentation structures that can be integrated in nano-meter CMOS for wide-band recording of neural activity. This shifts the focus towards careful system integration of electrodes, data processing, wireless communication, and power management in order to realize a truly implantable solution. The first core objective that extends on the work here is stream lining the design with industry standard synthesis for large scale integrated systems. This implies formal silicon verification for proof of concept from our latest developments and involve more conservative design choices associated with improving device lifetime and risk-factors. This is important in providing a more universally translatable platform to allow other components of the system to be integrated arbitrary to the technology node of fabrication. + +However we should also consider the long term goal for these systems. Our micro-controller approach dedicates a significant amount of resources just to perform spike sorting or signal characterization. While this is the focus in current systems to allow wireless solutions it is not the primary challenge for a neuro-prosthetic device which instead lies with decoding spike-train data or decomposing LFP activity. This implies that we need to adopt more resource efficient structures to extract features or spikes in neural activity equivalent to that proposed in Section 48. More concise signal acquisition allows us to focus on decoding the collection neural activity rather than single recordings and possibly increase the prevalence where we reconfigure what signal features are extracted based on what is most informative at the system level. Specifically we picture a hierarchical approach where without intervention the system tunes to relevant information to guarantee some level of performance which is then tuned incrementally with off-chip supervision to maximize performance with higher order statistics and better optimization methods to find the best configuration that selects electrodes, LFP/EAP features, denoising bandwidth, etc. Moreover some aspects in regard to the design of a medical grade device are not yet fully investigated. For instance can we make the analysis of spiking activity suitable for long term reliability? This is specifically the endeavour of current research where experimental platforms need to reflect the informed capabilities. + +We find it highly probable that integrating processing structures and other auxiliary circuit components will be one of the simpler aspects of realizing BMIs with better decoding performance and capacity. Primarily because the design tools allow directed and precise development following methods already presented in the literature. Innovation in electronics will likely allow the required performance improvement by scaling when it is needed. The principle challenge lies with compact system integration of these devices. Compatible fabrication of penetrating electrode structures with the right impedance characteristics for low noise and sustain unimpaired neural tissue interface for coupling activity may raise significantly more unexpected challenges. In addition we note importance of introducing miniaturized antenna structures that perform harvesting power as well as back-scattering recorded data. Both of these aspects are crucial to scaling integrated recording systems in a distributed fashion. That said, the effort towards developing computational modalities for high dimensional data analysis that specifically use analogue or time domain techniques still hold uncovered potential. Drawing from structures in the brain, bio-inspired ultra-low-power processing architectures for machine learning is an emergent challenge that can also find utility in brain machine interfaces [^205]. + +# 56 Publications + +The relevant conference and journals publications that have emerged from this thesis are summarized in the list below with reference to the corresponding technical chapter. + +\begin{itemize} +\item{**Chapter 16**} +\begin{enumerate} + \item[\\(-\\)]{ L. B. Leene and T. G. Constandinou, ''Ultra-low power design strategy for two-stage amplifier topologies," in Electronics Letters, vol. 50, no. 8, pp. 583-585, April 2014, \href{http://dx.doi.org/10.1049/el.2013.4196} {[Online] doi: 10.1049/el.2013.4196}. } + \item[\\(-\\)]{ L. B. Leene, Y. Liu and T. G. Constandinou, ''A compact recording array for neural interfaces," IEEE Proceedings of Biomedical Circuits and Systems Conference, pp. 97-100, May 2013, \href{http://dx.doi.org/10.1109/BioCAS.2013.6679648} {[Online] doi: 10.1109/BioCAS.2013.6679648}.} + \item[\\(-\\)]{ L. Zheng, L. B. Leene, Y. Liu and T. G. Constandinou, ''An adaptive 16/64 kHz, 9-bit SAR ADC with peak-aligned sampling for neural spike recording," IEEE Proceedings of International Symposium on Circuits and Systems, pp. 2385-2388, May 2014, \href{http://dx.doi.org/10.1109/ISCAS.2014.6865652} {[Online] doi: 10.1109/ISCAS.2014.6865652}.} +\end{enumerate} + +\item{**Chapter 30**} +\begin{enumerate} +\item[\\(-\\)]{ L. B. Leene and T. G. Constandinou, ''A 2.7\\( \mu\\)W/Mips, 0.88 GOPSmm\\(^2\\) Distributed Processor for Implantable Brain Machine Interfaces," IEEE Proceedings of Biomedical Circuits and Systems Conference, October 2016.} +\end{enumerate} + +\item{**Chapter 43**} +\begin{enumerate} + \item[\\(-\\)]{ L. B. Leene and T. G. Constandinou, ''A 0.45V Continuous Time-Domain Filter using Asynchronous Oscillator Structures," IEEE Proceedings of Electronics Circuits and Systems Conference, December 2016.} + \item[\\(-\\)]{ M. Elia, L. B. Leene and T. G. Constandinou, ''Continuous-time micropower interface for neural recording applications," IEEE Proceedings of International Symposium on Circuits and Systems, May 2016,\href{http://dx.doi.org/10.1109/ISCAS.2016.7527295} {[Online] doi: 10.1109/ISCAS.2016.7527295}.} + \item[\\(-\\)]{ K. Faliagkas, L. B. Leene and T. G. Constandinou, ''A novel neural recording system utilising continuous time energy based compression," IEEE Proceedings of International Symposium on Circuits and Systems, pp. 3000-3003, May 2015, \href{http://dx.doi.org/10.1109/ISCAS.2015.7169318} {[Online] doi: 10.1109/ISCAS.2015.7169318}.} +\end{enumerate} + +\end{itemize} + +# 58 Supplementary Results for the Resource Models + +This section will elaborate on some of the analytic findings in Chapter 16 by detailing the derivations and illustrating additional results that emerge from these relations. In particular we will demonstrate the impact of technology related factors to a larger extent that include quantitative measures for some of the more intuitive relations. + +# 59 Topology Selection + +We first introduced Eq. 18 as a base line for the figure of merit calculations. This reference SAR ADC only dissipates power though the capacitor array and the driving control logic without considering the comparator. We identified the power dissipation in the register logic as; + +$$ P_{Register} = 2N (N+2) f_s E_{gate} $$ + +Eq. 52 simply reflects that a typical SAR operation that resolves N bits requires \\((N+2)\\) per sample inferring the required clock frequency and the standard control logic uses \\(2N\\) gates to perform the binary search operation. + +$$ P_{Capacitor \: Array} = E_{search} \cdot f_s C_{unit} V_{ref}^2 (2^{N-2}+2^2) $$ + +Eq. 53 demonstrates the power dissipation for capacitive switching has three terms. The total amount of capacitance in the DAC is represented as $C_{unit} (2^{N-2}+2^2)$, the maximum input dynamic range as \\(V^2_{ref}\\), and the average search efficiency for quantization as \\(E_{search}\\). While this dependency is not surprising the term \\(E_{search}\\) needs to be evaluated under the proper assumptions. While we may be inclined to use sinusoidal test signals to extract this parameter if the sensor signals have similar structure but note that this will not reflect an even distribution with respect to the tested input ranges. In this respect triangular ramp test signals are representative to capture even-distribution of output quantization codes. + +To realize a model where an analogue pre-amplifier is employed we estimate the power requirements for achieving the required bandwidth for settling. The capacitance for which we evaluate this settling speed is found be considering the output referred noise the results from the capacitor value. These two relations are summarized as follows; + +$$ (N+2) f_s A_{op} \cdot (N+2) \ln(2) = \frac{I_{amp}}{2 \pi C_{out} \cdot \eta U_T} $$ + +The result in Eq. 54 is simply derived from the unity-gain frequency that needs to exceed the clock rate in excess related to the settling requirement that scales by $(N+2) \ln(2)$. + +$$ \frac{V_{ref}}{2^{N+2}} = āˆš{\frac{\zeta}{\eta} \cdot \frac{kT}{C_{amp}}} $$ + +Here we again refer to \\(\zeta\\) as the amplifier noise excess factor introduced in Eq. 7. After some simplification by taking the most significant terms we arrive at Eq. 19 but evaluated here in full as; + +$$ P_{amp} = 32 \pi \ln(2) \cdot \frac{ \left( U_T (N+2) 2^N \right)^2 }{V_{ref} q} \cdot A_{ol} f_s NEF^2 $$ + +Similarly we derive the power for the dynamic latch type comparator following closely the analysis of [^134]. The derivation for estimating the additional components for the hybrid data converter follows similarly to the pre-amp case where the bandwidth of the integrators is now also related to the order of oversampling but not that of settling. In particular we estimate the output referred noise of the first and most power intensive integrator as; + +$$ (1+2^{N-K}) FIR f_s = \frac{I_{int}}{2 \pi C_{int} \cdot \eta U_T} $$ + +Eq. 57 simply evaluates the integration factor required to achieve a consistent output swing irrespective of SAR resolution. This shows us that the input signal level heavily dictates the corresponding biasing current \\(I_{int}\\). + +$$ \frac{V_{ref}}{2^{N+2}} = āˆš{\frac{\zeta}{\eta} \cdot \frac{kT}{C_{int}}} $$ + +Similarly Eq. 58 relates the integration capacitance to the expected output referred noise. Summarizing these assertions gives us a direct relation between ADC resolution and power dissipation; + +$$ P_{amp} = 32 \pi \cdot \frac{ \left( U_T 2^N , NEF\right)^2 }{q V_{ref}} \cdot FIR f_s (1+2^{N-K}) $$ + +For the sake of clarity in the discussion we estimate the \\(FIR\\) order based on the expected variance from a rectangular window operator. Because this digital filter is estimating a DC component such that any up-modulated white noise power will scale as \\(āˆš{FIR}\\) for such a case and the dependency of a specific window operator will follow this upper bound. This result follows from the maximal dynamic range of real signals for window functions and assert that if we require another \\(K\\) bits to be resolved by the oversampling loop the will need a filter order of \\((K+1)^2\\) to grantee that when using a more effective noise shaping window operator we will achieve the desired noise requirement. Applying a similar estimation on digital power dissipation as before such that; + +$$ P_{fir} = \left[(N-K)+ K+\log_2(K-1) \right] \cdot \left(FIR + N-K \right) \cdot f_s E_{gate} $$ + +Eq. 60 states that the required clock frequency is \\(FIR+N-K\\) and the total number of gates being clocked is \\((N-K)\\) for the SAR operation and \\(K+\log_2(K)\\) for the $\Sigma \Delta$ decimation. For completeness we also note the dissipation of the capacitive DAC is estimated as; + +$$ P_{\Sigma \Delta \: Array} = E_{search} \cdot f_s C_{unit} V_{ref}^2 (2^{N-K-2}+2^2+ FIR) $$ + + +While we have extracted many of the empirical parameters that are associated with the implementation presented in Sec 27. Let us consider the impact of parameter variation and reflect on the expectations. This will allow us to evaluate the sensitivity of these parameters with regard to performance measures. + +{{< figure src="appendix/C32_V12_a.png}" width="500" >}} +{{< figure src="appendix/C32_V12_b.png}" title="Figure 94: Summary of the performance merit for each topology." width="500" >}} + + +First we introduce Fig. 94 which is the normalized case that we presented earlier however here we apply a different scaling with regard to increasing resolution. Here the resolution of the SAR and \\(\Sigma\Delta\\) loop are increased simultaneously which again demonstrates that this topology can provide compact quantization for from 8-10 bits. However because we are using vertical Metal-Insulator-Metal Capacitors provided by the technology that exhibit minimal variance per unit area the unit capacitance \\(C_{unit}\\) is \\(32 fF\\). This is relatively big when compared to very aggressive SAR designs presented in the literature that use unit capacitors of several femto-farad. + +{{< figure src="appendix/C4_V12_a.png}" width="500" >}} +{{< figure src="appendix/C4_V12_b.png}" title="Figure 95: Summary of the performance merit for each topology with a \\(4\times\\) reduction in unit capacitance. " width="500" >}} + + +{{< figure src="appendix/C4_V06_a.png}" width="500" >}} +{{< figure src="appendix/C4_V06_b.png}" title="Figure 96: Summary of the performance merit for each topology with a \\(2\times\\) reduction in reference voltage and a \\(4\times\\) reduction in unit Capacitance. " width="500" >}} + + +This leads into results presented by Fig. 95 where the unit capacitance is reduced to \\(4 fF\\). This illustrates that the hybrid topology has difficulty scaling its power budget because there are significantly more analogue components that the simple structures. In fact if we reduce the power supply from \\(1.2 V\\) to \\(0.6 V\\) the inhibitory analogue scaling that the integrators have exacerbates this effect. Particularly the dynamic comparator structure which has good digital scaling characteristics will allow significantly smaller power dissipation. However in all cases we note that for precision that exceeds \\(60 dB\\) the hybrid data converter topology will allow for a more compact designs. + +# 60 System Level Abstraction + + + +As most of the relations presented in Sec. \ref{ch:T1_model} follow naturally from Eq. 25. Here we will provide some additional details regarding our assertions and observations. To show that Eq. 28 represents the expected increase in variance, let us consider the typical gain sensitivity to the variance of our normalized unit capacitor. + +$$ \frac{\sigma^2_A}{A_{cl}^2} = \frac{\Delta^2_A - A_{cl}^2}{A_{cl}^2} \text{where} \Delta_A = \frac{A + āˆš{A_{cl}} CI \sigma }{1 + CI \sigma} $$ + +This expression is similar to that used in estimating the variance of a capacitive DAC in Eq. 16. \\(\Delta_A\\) represents the expected gain deviation from the mean that relates to our confidence interval \\(CI\\). Strictly there are only two components that attribute to gain variance which are the input and the feedback capacitors. These contributions have exactly a ratio of \\(āˆš{A_{cl}}\\) for their respective variances. Expanding this result will reveal; + +$$ \frac{\sigma^2_A}{A_{cl}^2} = \sigma CI \cdot \frac{2 ( A_{cl} - āˆš{ A_{cl} } ) + \sigma CI ( 1 - A_{cl} ) } {A_{cl} \left( \sigma CI + 1 \right)^2 } \approx \sigma CI \cdot \left( 2 - \frac{2}{āˆš{A_{cl}}} \right) $$ + +For exceedingly larger \\(A_{cl}\\) it makes sense to take the higher order terms however instead we chose include the \\(āˆš{A_{cl}}\\) term to considering the design of low-gain multi-stage configurations. Since the typical deviation of $\sigma CI$ is on the order of several percent it is conceivable that these higher order terms have vanishing contribution irrespective of gain. In order to compensate the increased variance the capacitor sizes need to be adjusted proportionally to that of the change standard deviation. This results in the penalty factor accumulated from every stage as Eq. 28. + +{{< figure src="appendix/LG-NP.png}" width="500" >}} +{{< figure src="appendix/LG-PAP.png}" title="Figure 97: Normalized resource redistribution dependency in low gain settings \\(G_T=200\\). " width="500" >}} + + +The results in Fig. 97 show that particularly in low gain settings that relate to smaller \\(V_{DD}\\) configurations the resource distribution becomes more important. This is because the individual gain of each stage is low resulting in very poor noise figures for minimal area configurations. With conventional structures we see that multi-state topologies can benefit greatly from this factor primarily because the baseline performance is much worse than single or two-stage structures. + +{{< figure src="appendix/area-R21-B32-sigma.png}" width="500" >}} +{{< figure src="appendix/area-R21-B32-snr.png}" title="Figure 98: System area requirement for two-Stage/single-Pole (red) and three-stage/double-pole (green) amplifier/filter structures. " width="500" >}} + + +Fig. 98 reveals some of the more intuitive details associated with gain matching and ADC SNR performance with quantitative measures. In a) we observe the general inverse proportionality that gain matching exhibits with regard to capacitor are requirement. We point out that it can be marginally reduced by reducing \\(G_T\\) or equivalently the supply voltage. On the other hand in b) we see that reducing \\(G_T\\) by increasing the ADC dynamic range is more effective of a solution when we do not consider the associated increase in power dissipation. + +{{< figure src="appendix/PAP-AIRN.png" title="Figure 99: Detailed dependency with regard to system supply voltage and the precision of the two-stage/single-pole (red) and three-stage/double-Pole (green) amplifier/filter structures. " width="500" >}} + + +Fig. 99 demonstrates a more generic result when the amplifier power budget and gain configuration is actively matching the dynamic range of the ADC. Neglecting linearity we observe that there is an interesting strategy for selecting the appropriate supply voltage in accordance to the targeted ADC resolution. Similarly we make the assertion that there is gain-varience, quantization limited, and linearity limited regimes in each extrema of this graph that will bound viable implementations. + +# 61 Transistor level implementation + +For clarity the transistor level implementation is detailed here in terms of the transistor sizing. + +{{< figure src="appendix/SIZE1.pdf" title="Figure 100: Transistor sizing for the two stage operational amplifier with bandwidth boosting implemented in 0.18\\(\mu\\)m CMOS. Sizing units shown are in microns.}\label{fig:A1_S1" width="500" >}} + + +{{< figure src="appendix/SIZE2.pdf" title="Figure 101: Transistor sizing for the fully differential $\Delta\Sigma SAR$ switched loop filter implemented in 0.18\\(\mu\\)m CMOS. Sizing units shown are in microns.}\label{fig:A1_S2" width="500" >}} + + +{{< figure src="appendix/SIZE3.pdf" title="Figure 102: Transistor sizing for the differential low noise complementary instrumentation amplifier implemented in 0.18\\(\mu\\)m CMOS. Sizing units shown are in microns.}\label{fig:A1_S3" width="500" >}} + + +{{< figure src="appendix/SIZE4.pdf" title="Figure 103: Transistor sizing for the fully differential time domain instrumentation amplifier implemented in 0.18\\(\mu\\)m CMOS. Sizing units shown are in microns.}\label{fig:A1_S4" width="500" >}} + + +{{< figure src="appendix/SIZE5.pdf" title="Figure 104: Transistor sizing for the time domain instrumentation high pass filter structure implemented in 0.18\\(\mu\\)m CMOS. Sizing units shown are in microns.}\label{fig:A1_S5" width="500" >}} + + +{{< figure src="appendix/SIZE6.pdf" title="Figure 105: Transistor sizing for the differential time domain filter implemented in 0.18\\(\mu\\)m CMOS. Sizing units shown are in microns.}\label{fig:A1_S6" width="500" >}} + +# 62 Supplementary Results for Classification Methods + +This section will detail the signal characteristics found in the data sets used extensively for validating the methods proposed here. We will exemplify some of the signal features and demonstrate the implementation of the proposed methods with Matlab code. + +# 63 Signal Characteristics + +As was mentioned used evaluation recordings contains different sets of synthetically generated spike trains for three classes of neurons each with different spike morphologies. The spike shapes are based on recordings with background noise of similar spikes randomly distributed in time at lower amplitudes. While the these datasets provide time stamp data for when the individual spike wave forms can be found in the recording they do not introduce the low-frequency content that is expected from typical recording. Here we have extracted these low frequency variations from real recordings with a high order FIR filter and added them to the synthetic data. While this will not greatly effect the classification results it assures us that the proposed methods are not inadvertently sensitive to low-frequency components. + +{{< figure src="appendix/synthetic_rawa.pdf}" width="500" >}} +{{< figure src="appendix/synthetic_rawb.pdf}" title="Figure 106: Example of synthetic data derived from typical neural recordings." width="500" >}} + + +Fig. 106 depicts the typical recordings that are used before preprocessing. Whether we extract the finer signal components in the digital domain or in the analogue domain it is necessary to carefully consider the possible dynamic range. Particularly as buffer overflows are not explicitly modelled unless hardware specific data types are used. + +{{< figure src="appendix/synthetic_filta.pdf}" width="500" >}} +{{< figure src="appendix/synthetic_filtb.pdf}" title="Figure 107: Filtered components of spiking activity and detection operator output." width="500" >}} + + +Once the spiking activity is extracted it may appear like that in Fig. 107. Because spikes have a board bandwidth relative to the sampling rate, the white noise is typically more evident than what is presented. Alongside the spiking waveform we present the energy operator. Here there is a clear difference in how apparent the noise is in contrast to the spike amplitude. This disparity improves the more energy each spike had in the high-frequency bands. + +{{< figure src="appendix/spike_analoga.pdf}" width="500" >}} +{{< figure src="appendix/spike_digitala.pdf}" title="Figure 108: Comparison of digital and analogue pre-filtering methods. " width="500" >}} + + +Fig. 108 compares the characteristic difference between analogue and digital filtering strategies. While we typically expect the group delay is well controlled in digital systems the analogue implementation exhibits more systematic rejection of out of band components. Low order FIR structures in particular suffer from limited leaking these components but allow finer adjustments that accentuate separating features in the signal. + +{{< figure src="appendix/spike_analogb.pdf}" width="500" >}} +{{< figure src="appendix/spike_digitalb.pdf}" title="Figure 109: Comparison of digital and analogue detection methods." width="500" >}} + + +Similarly Fig. 109 compares the digital and analogue realizations of the detection operators. Since we only use linear blocks to realize the analogue operator we lose the suppression of white noise. Moreover the digital operator can fine tune delay used to correlate derivative with amplitude components allowing for a very explicit single maximum in each waveform. + +{{< figure src="appendix/synthetic_spikes.pdf" title="Figure 110: Colour coded spike-waveforms for 16-sample spike windows where the three classes of neurons are coloured (ref,blue,green) and the false positives labelled (black)." width="500" >}} + + +Finally we illustrate a sub-set of aggregate waveforms captured by the digital methods in Fig. 110. This data is used in the RVD and template-matching methods. + +# 64 Implementation structure + +Here we will detail the Matlab code implementation for the proposed methods which were used for validation in association with the data. Note alpha represent the smallest representable value which reflects the depth of the registers. + +## 65 Introducing noise and LFP content + +This code section exemplifies the method by which noise is systematically added to each recording in addition to LFP content. We note that the synthetic spike trains have well defined average rates and consistent amplitudes which allows the additive noise to remain consistent across all tests. + +\begin{lstlisting}[language=Matlab] +load(LFP_content) +LFP.Time=LFP.Time-min(LFP.Time); +load(SpikeTrain_dataset) + +scale=3; +lpflt = designfilt('lowpassiir', 'FilterOrder', 1, ... +'HalfPowerFrequency', 6500, 'SampleRate', ... +scale*10^(3)/samplingInterval, 'DesignMethod', 'butter'); + +AT=resample(LFP,[1:size(data,2)].*(samplingInterval*10^(-3))); +rdata=awgn(resample(data(1:size(data,2))',scale,2),snr); +rdata=rdata+resample(AT.Data,scale,2); + +rdata=filter(lpflt,rdata); +\end{lstlisting} + +## 66 Analogue detection operator + + + +The analogue detection operator simply operated on the bandpass filtered sub-components of the original signal and tracks a means threshold at three times that of the average. Because we specifically upsample the waveform sectioning it make sense that the adaptive threshold updates close or below the Nyquist frequency in order to capture slowly varying changed in spiking intensity. + +\begin{lstlisting}[language=Matlab] +i=34; +while(imei) + mei=mei+alpha; + else + mei=mei-alpha; + end + %Set treshold at 3x rms with minimum at 0.01 + drms=3*mei+1/64; + end + %Upon peak-detection above threshold process data + if(made(i)>drms && made(i)>made(i+1)) + G(1:200,k)=rdata(i-32:i+167); + IDX(k)=i*2/scale; + k=k+1; + i=i+180; + end +end +\end{lstlisting} + +## 67 Digital detection operator + + + +The digital operator is slightly more sophisticated as it is not sensitive to the rate or spiking when estimating its threshold. While we similarly remove low-frequency content equivalent to the analogue filters. The threshold updates are only performed upon detecting peaks in the energy operator. + +\begin{lstlisting}[language=Matlab] +while(ilm) + lm=DO(i); + thv = thv + (a1*nest+DO(i)-a1*thv)/512; + F(k,1:8)=G(i+[-10:2:-4 -3:0]); + cnt=1; + else + F(k,8+cnt)=G(i); + cnt=cnt+1; + end + elseif(cnt thv ) + %upon detecting threshold crossing initialize buffers + lm=DO(i); + k=k+1; + thv = thv + (a1*nest+DO(i-2)-a1*thv)/512; + F(k,1:8)=G(i+[-10:2:-4 -3:0]); + cnt=1; + end +end +\end{lstlisting} + +## 68 \\(\Omega_3\\) optimization + + + +The mixed signal optimization that selected the best sections in the aggregate waveforms is performed iteratively. Here we simply introduce normalization factors K and section pointers T. + +\begin{lstlisting}[language=Matlab] +for i = repmat(1:size(G,2),1,1) + % for each \\(\Omega\\) feature find the best section + for j = 1:3 + %offset with reference point + ref=3.*sum(G(RP(j),i)); + %integrate current section current section + rng=round(K(j)*10)+1; + acc=sum(G([-rng:rng]+round(T(j)),i)); + %nomalize the integration to reference + if(ref < acc && K(j) > 0.1) + K(j)=K(j) - alpha; + elseif(K(j)<1) + K(j)=K(j) + alpha; + end + %Compare signal deviation and increment on sections + G1=abs(ref-sum(G([-rng:rng]+round(T(j)+2),i))); + G2=abs(ref-sum(G([-rng:rng]+round(T(j)-2),i))); + if(T(j)>70 && G2>G1) + T(j)=T(j)-alpha; + elseif(T(j)<90 && G1>G2) + T(j)=T(j)+alpha; + end + end +end +\end{lstlisting} + +## 69 K-means with centroid splitting + + + +Here we present the means by which we explicitly multiplex active clusters and the iterative splitting of each centroid. + +\begin{lstlisting}[language=Matlab] +seed=randi(size(F,1)-5,1); +U(1:4,:)=F(seed+[1:4],:); +for NM=[1, 2, 4] + %if new iteration duplicate new centroid from previous + switch NM + case 2 + U(2,:)=U(1,:)-ones(1,size(U,2)).*alpha; + case 4 + U(3,:)=U(1,:)-ones(1,size(U,2)).*alpha; + U(4,:)=U(2,:)-ones(1,size(U,2)).*alpha; + end + % Track centroids using data in F + for i = repmat(1:size(F,1),1,1) + %multiplex centroid adjustment + if(CS==0) + CA=mod(CA,NM)+1; + end + CS=mod(CS+1,4); + [dist, mc]=min(sum(abs(repmat(F(i,:),NM,1)'-U(1:NM,:)'))); + %if current centroid is minimum then adjust + if(CA==mc) + U(mc,:)=U(mc,:)+sign(F(i,:)-U(mc,:) ).*alpha; + end + end +end +\end{lstlisting} + +## 70 Recursive variance decomposition + + + +Similarly this implementation realizes the estimation of loading vectors that provide a basis for the spikes in F. + +\begin{lstlisting}[language=Matlab] +for i = repmat(1:size(F,1),1,1) + %First track mean xu and first loading vetor s1 + for j = 1:size(F,2) + d(j) = F(i,j)-xu(j); + xu(j) = xu(j) + sign(d(j)-xu(j))*alpha; + ad(j) = abs(d(j)); + s1(j) = s1(j) + sign(ad(j).*g1-s1(j))*alpha*2; + end + %get dot product s and project on it-self to check gain g1 + s=ad*s1; + if( (ad'-s1.*(s))'*s1 > 0 )g1=g1+alpha; + else g1=g1-alpha; + end + %using varience residues esitimate second loading vector s2 + for j = 1:size(F,2) + ad(j) = ad(j)-s1(j).*s; + s2(j) = s2(j) + sign(ad(j).*g2-s2(j))*alpha*2; + end + %get dot product of s2 and project to normalize with g2 + s=ad*s2; + if( (ad'-s2.*(s))'*s2 > 0 ) + g2=g2+alpha; + else + g2=g2-alpha; + end +end +\end{lstlisting} + + + + + +# References: + +[^1]: R.Q. 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[Online]: http://www.darpa.mil/program/unconventional-processing-of-signals-for-intelligent-data-exploitation diff --git a/content/publications/2016/brain-machine-interfaces-neural-recording-front-end-design.md b/content/publications/2016/brain-machine-interfaces-neural-recording-front-end-design.md new file mode 100644 index 0000000..0c6abf4 --- /dev/null +++ b/content/publications/2016/brain-machine-interfaces-neural-recording-front-end-design.md @@ -0,0 +1,663 @@ +--- +title: "Brain machine interfaces: Neural Recording Front End Design" +date: 2016-08-08T15:26:46+01:00 +draft: false +toc: true +math: true +type: posts +tags: + - chapter + - thesis + - CMOS + - biomedical +--- + +Lieuwe B. Leene, Yan Liu, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +This chapter focuses on the multitude of questions associated with the mixed signal design for multi channel integrated neural recording systems. As a result, a significant section will be directed at developing an abstract understanding of how design parameters influence the various design challenges. This discussion will clarify the key limitations for these systems and propose how they can be mitigated or efficiently designed for. In the scope of integrating a large number of recording channels together, clearly understanding how each resource trades for another is crucial for optimizing a complex system. Optimization methods found in the literature typically assume a certain configuration which limits to what extent improvements can be made [^109]. However here we specifically identify abstractions that allow us to consider the impact of different topologies and filter structures simultaneously. This should enable a much boarder sense of optimization that will reflect in the improved performance characteristics demonstrated here. + +We will focus on elaborately evaluating the dominant resource requirements with respect to noise, mismatch, quantization, and functional aspects for signal conditioning together that is mostly implementation independent. In addition we propose several circuit implementations based on this analysis that present highly efficient and compact instrumentation. The corresponding abstractions that we use attempt to realize clarity respect to underlying dependencies. This should allow better analytic models that make the limiting factors appear obvious and reveal means to circumvent specific constraints with alternative techniques. For example we may be interested to know when it is worthwhile to put certain functions in the digital domain in terms of the CMOS technology parameters. Approaching the ideal instrumentation structure in such a scenario remains highly desirable for constrained applications. Thus conforming to the technology parameters could reveal that conventional methods do not deliver the most effective solution. + +The chapter is organized as follows; Section 17 describes the general problem statement related to the analogue front end which is followed by the associated amplifier design considerations in Section 19. The method for improving the analogue to digital conversion is outlined in Section \ref{ch:T1_converter}. These results are then collected in Section \ref{ch:T1_model} to evaluate the impact of system level parameters as a function of resource requirements. + +# 17 Architecture for Neural instrumentation + +The analogue dimension of neural recording system can be broken down into two objectives for signal conditioning that will maximize the performance of the proceeding digital signal processing. The first is related to getting adequate signal quantization by amplifying the signals to full input range of the data converter without corrupting the signal of interest. The second objective is performing some kind of filtering that removes noisy or irrelevant components in the recording and only captures the relevant signals of interest. + +{{< figure src="technical_1/T1_SIG_Spectrum.pdf" title="Figure 20: Illustration of the spectral power density characteristic for a typical neural recording with the associated frequency bins. " width="500" >}} + + +As depicted in Figure 20, the input spectrum of a typical \text{in-vivo} electrode recording can be classified using a few frequency bands. The energy from extracellular spiking activity is primarily concentrated around \\(300 Hz\\) to \\(6 kHz\\) and is characteristically intermittent resulting in a distinct difference between the average and instantaneous spectral power [^110]. This characteristic is also present in the LFP band to a lesser extent. From an electrical standpoint the design constraints are derived from the tolerated noise levels in each frequency band to maintain a proper signal to noise ratio. As a consequence it important to specify the signal to noise ratio in terms of noise density opposed to integrated noise figures as digital processing accuracy is not limited by the later term. Here we should also note that the electrode spectral noise power $N^2_{electrode} = 4 kT R_{en} \Delta f$ depends on the resistive component of the electrode impedance. This is typically matched by that of the amplifier noise characteristic \\(N_{amp}\\) so that no excess power is wasted and is expressed in terms of the electrode resistance \\(R_{en}\\), Boltzmann energy \\(kT\\), and the frequencies of interest $\Delta f$. + + +## 18 Instrumentation Requirements + + + +This kind of electrical sensing can be broken down in the a number of system blocks each of which perform an essential operation to this process. These are shown in Figure 21 and consist of an amplifier, a filter, a sampler, and a quantizer. Occasionally one circuit can combine multiple of these operations together depending on the construction. Table 3 presents the overall performance requirements that should be demonstrated when these components are integrated together. These are also the specifications that we will target as the design is being considered in the following discussion. The reasoning behind these specific requirements are mainly related to conventional signal acquisition given the bandwidth and noise requirements. Moreover these seem to be sufficient for most decoding/characterization methods hence similar figures can be found in most BMI publications. + +{{< figure src="technical_1/ISYS.pdf" title="Figure 21: " width="500" >}} + + +Table 3: Summary of the target specifications for the analogue instrumentation system. +| Parameter | Symbol | Specification | +|----|----|----| +| Integrated Channels | | 64 | +| Supply Voltage | (V_{DD})| (<)1.8V | +| Power Dissipation | (P_{SYS}) | (<)5 (\mu)W | +| Diff. Signal | | 5 (\mu) - 5 mVpp | +| Common Signal | | 50 mVpp | +| CMRR/PSRR | | (>)80 dB | +| Input Referred Noise | (e^2_{in}) | (<)5 (\mu)Vrms | +| Total Gain | (A_T) | (>)40 dB | +| THD at max input | | (>)40 dB | +| 3dB Bandwidth | (f_{3dB}) | 6 kHz | +| High pass frequency | (f_{hp}) | (<)1 Hz | +| Sampling rate | (f_{smp}) | 25 kS/s | +| Input Impedance | (R_{IN}) | (>)50$ M \Omega$ @( 1 )kHz | +| ADC Resolution | (ENOB) | 12 bits | +| Active Area | | 0.01 mm(^2) | + + +# 19 Amplifier Principles for Miniaturization + + + + +{{< figure src="technical_1/Harrison.pdf" title="Figure 22: " width="500" >}} + + +The principle design considerations for neural instrumentation have been well established particularly with regard to the Harrison topology [^111] that been widely adopted in many systems and shown in Figure 22. Objectively the optimization techniques have become both more specialized and specific for maximizing the average signal to noise ratio in the LFP or EAP bandwidth with the absolute minimum power budget. Interestingly due to the use of more advanced CMOS technologies there is a persistent trend towards sub-threshold operation. This is motivated by trading in the excess transistor bandwidth for improved current efficiency that measured in terms of the achieved transconductance per dissipated ampere of current. In fact this is purely a result of maximizing the individual transistor performance with respect to the speed efficiency product [^112]. This is expressed in Eq 4 using \\(f_T\\), \\(U_T\\), \\(v_sat\\), \\(\mu\\) as the transition frequency, thermal voltage, velocity saturation voltage, and carrier mobility respectively. + +$$ \max\limits_{IC} \left\lbrace f_{T} \frac{gm}{I_{DS}} \right\rbrace = \frac{v_{sat}^2}{4\pi \mu \eta U_{T}^2} \: \frac{1}{IC_{max}} \approx \frac{22}{IC_{max}} \left[ \frac{THz}{V} \right] Where IC_{max} = \left( \frac{L_{sat}}{L_{tech}} \right)^2 $$ + +Here \\(L_{sat}\\) is a technology independent BSIM6 parameter that reflects the impact of ballistic carrier transport during velocity saturation and normalizes the minimum feature length \\(L_{tech}\\) for a specific technology as an effective length. The implication of Equation 4 is that the transistors for optimized low frequency instrumentation amplifiers are exclusively in the sub-threshold regime because \\(f_T\\) is always in excess with respect to the signals of interest. The subthreshold operation results in each transistor's transconductance being defined as $gm = \frac{I_{DS}}{\eta U_{T}}$ which only depends on drain current. Instead of noise optimization though the overdrive voltage, \\(V_{ov}\\), the topology can only reduce noise by removing non-amplifying transistors or biasing them with reduced drain current when compared to the input transistor(s). This reflects the need for a different design methodology as the input referred contribution is dominated by how the total amplifier current distributed to all the transistors. At least in the small signal sense the key requirement is that the amplifying transistors dissipate all the current while biasing/non-amplifying transistors dissipate relatively very little. + +In principle due to the under-determined nature of transistor level design the optimization methodology is initially constrained by one of the most important objective characteristics. This could be low noise, wide bandwidth, good linearity, etc. Hence this discussion will digress by distinguishing the design considerations for noise or bandwidth limited amplifiers as separate cases. This should reveal some key relations with respect how power efficiency is achieved. For each case we evaluate the implications with respect to different resource requirements. + +## 20 Noise limited Amplifiers + + + +This discussion is guided by the leading challenge for instrumentation systems which is maximizing efficiency while maintaining good linearity. For this reason a noise efficiency factor (NEF) was first introduced in [^113] and is expressed in Equation 5. + +$$ NEF^2 = e^2_{in} \frac{I_{tot}}{ U_T 4kT \omega_{3db}} $$ + +This figure represents a normalized efficiency or in other words it evaluates how much extra current is dissipated by a particular circuit when compared to an ideal bipolar junction transistor for the same noise performance. Here \\(e^2_{in}\\), \\(I_{tot}\\) and \\(\omega_{3db}\\) represent the input referred noise power, the total current dissipation and the -3dB bandwidth in radians respectively. NEF reflects how well a particular topology achieves efficient amplification for a particular noise floor and thus it inherently trades off with a multitude of other parameters. Here we shall use it as design parameter that reflects the chosen transistor level topology. With this in mind, we propose the following reformulation from Equation 5: + +$$ e^2_{in} = \frac{kT}{C} \frac{NEF^2}{\eta A_{cl}} \frac{I_{in}}{I_{tot}} \text{where} C = \frac{gm}{\omega_{3db} A_{cl}} \text{and} gm=\frac{I_{in}}{\eta U_T} $$ + +This result leads to: + +$$ gm = \omega_{3db} \frac{kT}{e^2_{in}} \frac{\zeta}{\eta} Equivalently I_{in} = \omega_{3db} \frac{q U_T^2}{e^2_{in}} \zeta \text{where} \zeta = NEF^2 \frac{I_{in}}{I_{tot}} $$ + +Note that this relation is exclusive to noise limited characteristics and implies nothing with regard to the output load or linearity conditions. Moreover there is a fundamental requirement for transconductance with respect to noise and an implementation related factor \\(\zeta\\). This factor represents the noise efficiency of the topology and the slope factor \\(\eta\\) that tells us about the transistor performance as a fundamental process parameter. Numerous techniques for improving NEF can be found in the literature. As a generalization these can be put into two categories. The first reducing the transconductance of non-signal amplifying transistors using degeneration such that their input referred noise is minimized [^114]. The second approach is AC coupling the amplifier's input signal to biasing transistors such that the total transconductance is increased and the current efficiency is improved. Interestingly because this factor relates to current efficiency the NEF can be smaller than 1 or exceed the efficiency of a BJT using a stacked mixer structure that reuses the same biasing current for multiple amplifiers [^115]. This hints at the fact that NEF should be normalized to the voltage supply but in some sense these structures trade off dynamic range for power efficiency. Theoretical NEF figures for some of the primitive low noise topologies are listed in Table 4 assuming biasing transistors have negligible contribution and taking \\(V_{th}\\) as the NMOS & PMOS threshold voltage. + +Table 4: Theoretical figures for NEF for various amplifier topologies. \\(^\star\\) N is the number of stages sharing the structure. +| Topology | NEF | Minimum (Vdd) | Reference | +|----|----|----|----| +| Single Transistor | $\eta $ | (V_{th}) | - | +| Differential Pair | $\eta āˆš{2}$ | $V_{ds} + V_{th}$ | [^116] | +| Complementary Pair | $\eta $ | $2 V_{th}+2 V_{ds}$ | [^117] | +| Common Reference(^\star) | $ \eta āˆš{\frac{1+N}{N}}$ | $V_{ds} + V_{th}$ | [^118] | +| Common Bias(^\star) | $ \eta āˆš{\frac{2}{N}}$ | $(1+N) V_{ds} + V_{th}$ | [^115] | + + +These relations highlight the fact NEF primarily dependent on the chosen topology and less sensitive to the actual transistor design after optimization. Choosing a topology for the instrumentation amplifier with respect to its ideal NEF performance is significantly more effective than starting with a particular structure and introducing resistive degeneration on transistors that should not contribute noise. + +Also notice that the expression for noise in Equation 6 only has one degree of freedom and that is the ratio between the closed loop gain and capacitive load of the amplifier. This implies the 3dB bandwidth of the amplifier is fixed but its unity gain frequency is arbitrary. In fact by satisfying the relation for Equation 7 it is automatically the case the the equivalent noise density requirement is also satisfied. This is significant because we could allow the first stage to provide wide band gain and rely on a second stage to perform filtering. The second stage will have a capacitor gain product that is \\(A_1^2\\) times smaller than if the fist stage had to perform filtering. This can has a large impact on analogue circuit area that is typically dominated by capacitors used for filtering and setting closed loop gain. + +{{< figure src="technical_1/flickker.png" title="Figure 23: " width="500" >}} + + +So far we have only considered the implication thermal noise requirements on the design. We must also address the flicker noise sources because neural signals have a lot of low frequency content. Moreover because flicker noise sources concentrate the noise power at the lower frequencies, the total noise profile inside the LFP frequency band can be dominated by this type of noise. The nature of flicker noise from transistor physics can be due to a number of phenomena; mobility fluctuation $\Delta \mu$, carrier density fluctuation $\Delta N$, and changes in access resistances $\Delta R$. Each of these phenomena will exhibit a \\(1/f\\) frequency dependence when computing the input referred power spectrum. Typically for a given inversion coefficient IC only one of these phenomena will dominate the overall noise characteristic of a transistor. This is illustrated in Figure 23 which shows that $\Delta N$ is typically the leading cause for flicker noise generated additively to the drain current. IC is a factor that indicates to what extent a transistor is operating in the subthreshold region by using the definition IC=ID/($2\mu C_{ox} W/L U^2_T$). This uses The more general parameters \\(q\\), \\(W\\), \\(L\\), \\(C_{ox}\\) that represent electron charge, transistor width, transistor length, and gate oxide sheet capacitance respectively. The region of interest for biomedical circuits is typically when \\(IC<1\\) which exhibits good current efficiency and subthreshold operation. The phenomenological model corresponding to carrier density fluctuation $\Delta N$ component is expressed in Equation 8 after being referred to the transistor gate as an equivalent voltage noise density [^119]. + +$$ e^2_{fl} \Delta f = \frac{q^2 kT \lambda N_T}{W L C^2_{ox} f} \cdot K_{G} \text{where} K_{G} \approx (1 + \frac{\alpha \mu}{2})^2 \text{for} IC < 1 $$ + +Here \\(\alpha\\) and \\(\lambda\\) represent the coulomb scattering coefficient and tunnelling attenuation distance respectively. Notice that this expression has relatively weak biasing dependency in weak inversion contrast to the strong inversion region as shown in Figure 23. This trend follows very closely to the \\((gm/I_D)^2\\) characteristic which implies a fixed SNR for varying IC. The parameter \\(N_T\\) reflects the density of trapped charges at the oxide interface inside the transistor's conducting channel. Whether this parameter is consistent across various technology nodes is naturally put into question [^120] but similarly there is evidence supporting that indeed this factor is process independent [^121]. Now we should keep in mind that increasing the input transistor size will accommodate lower flicker noise but also result in increased noise. This is because of the signal loss when coupling \\(C_{in}\\) to \\(C_{fb}\\) that is loaded by the parasitic input capacitance of the amplifier \\(C_{g}\\) (see Figure 22). Keeping the ratio \\(C_{g}/C_{fb}\\) fixed as a \\(\delta\\), we can express the required input capacitance in Equation 9 in terms of general amplifier requirements using \\(A_{cl}\\), \\(K_F\\), \\(f_{cor}\\) as the closed loop gain, flicker charge density, corner frequency respectively. + +$$ C_{in} = \delta A_{cl} C_{g} = \frac{3}{4} \delta A_{cl} C_{ox} W L = \frac{3}{4} \frac{K_F A_{cl} \delta }{C_{ox} e^2_{in} f_{cor}} \text{where} K_F = q^2 kT \lambda N_T K_G $$ + +This expression indicates that attempting to achieve all desirable characteristics; small \\(e^2_{in}\\), small \\(f_{cor}\\), large \\(A_{cl}\\) simultaneously in a single amplifier structure comes at the cost of a very large input capacitance that scales proportionally to all factors. This representation suggests the Harrison topology has limited flexibility for improving input capacitance as the only solution appears to be minimising \\(\frac{KF}{C_{ox}}\\) through CMOS process selection. Moreover \\(\delta\\) cannot be made arability small as it will more typically be bounded by the minimum feedback capacitor \\(C_{fb}\\). This need to be large enough to set the high pass pole location at sufficiently small frequency to prevent the resistor \\(R_{fb}\\) from introducing noise inside the signal band which has a integrated power of \\(\frac{kT}{C_{fb}}\\) [^111]. Not to mention that the resulting size of the input transistors can be very large for this particular topology. + +## 21 Chopper Stabilized Amplifiers + + + +Alternatively we can apply chopping techniques to deal with these noise requirements which is used extensively in bio-signal instrumentation systems [^69]. By up modulating the signal to a higher frequency before amplification, the flicker noise is added to the usual near-DC band which no longer coincides with out input signal. The output is then demodulated to recover the input. The difference is that the flicker components now lie at the chopper frequency \\(f_{chp}\\) which is typically out of band and can be rejected easily. This eliminates the requirements from Eq 9 on the input capacitance and shifts the focus to rejecting up modulated aggressors at higher frequencies. We suggest using keeping the sampling and chopper frequency coherent because it allows low order FIR filter reject all up modulated harmonics. For instance by chopping at the half the Nyquist frequency (\\(f_s/2\\)) or odd multiples of it (i.e. \\([2n+1] f_s/2\\) $|$ $n \in \mathbb{Z}$) will fold chopper harmonics onto \\(f_s/2\\). The resulting filter are quite relaxed because of the large fractional bandwidth in the transition band that separates our signal bandwidth \\(f_{3dB}\\) from \\(f_{chop}\\). In this particular case we employ a sampling frequency of \\(25 kS/s\\) and use a chopping frequency at \\(37.5 kHz\\) to achieve this functionality [^122]. Conveniently any common mode signals from the sensor or analogue supplies are also rejected using this configuration because they will appear at the chopper frequency. + +In addition to basic chopping functionality, the performance can be further improved by providing closed loop feedback to actively cancel aggressors on top of filtering the resulting up modulated aggressors. This can be achieved in multiple ways and in some cases could improve linearity. One possible technique is using a DC-servo loop and another is performing ripple rejection both of which remove different components [^123]. Here we will consider the implementation of three such techniques that improve chopping performance that specifically have negligible power and area requirements. The considerations made here will be similar to that of [^124] [^125] but with explicit focus on area reduction. + +{{< figure src="technical_1/T1_CAMP.pdf}" width="500" >}} +{{< figure src="technical_1/T1_CAMP_T.pdf}" title="Figure 24: Proposed compact chopper stabilized neural amplifier topology. " width="500" >}} + + +Figure 24 shows the proposed configuration that promises a significant reduction in input capacitance and the required silicon area. This configuration has two gain stages where the first stage A1 is a wideband low noise stage and the second provides A2 low pass filtering as motivated by Section 20. This enables the rejection of flicker noise from the first stage completely and effectively shifts the corner frequency of the second stage by gain of first stage squared. Moreover this the configuration does not require auxiliary integrators provide feedback on the capacitive feedback network around A1 that would lead to increased complexity. + +The pseudo resistor across A1 in this configuration provides closed loop rejection of low frequency noise below the high pass pole with the time constant $\tau_{HP} = C_{F1} R_{HP}$. The noise components in the band from \\(f_{HP}\\) to \\(f_{CHP}\\) will be a mixture of flicker and thermal noise that are up-modulated by the chopper proceeding A1. This is because A1's corner frequency will lie inside of this band after sizing the input transistors such that \\(C_G\\) is about 5% of \\(C_{IN}\\) which usually leads to a target area of about 100 $\mu m^2$. + +It is important that the gains of A1 and A2 are carefully selected because this configuration only provides a first order role off in terms of analogue filtering. It could be that \\(f_{CHP}\\) is not sufficiently outside of the \\(6kHz\\) filter bandwidth resulting in some aggressors to appear on the output of A2. For this reason we require an aggressive high pass pole location to minimize this total up modulated power. More specifically we can say that the total noise contribution below the \\(f_{HP}\\) is mainly from \\(R_{HP}\\) which has a noise power of $\frac{kT}{A1^2 C_{F1}}$ when referred to the input of A1. The main concern here is that we have to sacrifice a small amount of dynamic range on A2 to prevent distortion. Although this power is quite limited, we need make sure the FIR filter can reject up-modulated noise components effectively. + +In addition we take advantage of the reduced output referred sampling noise a the input of the second stage that scales by \\(f_{3dB}/f_{CHP}\\). This is because most of the sampling noise will lie outside of the filter bandwidth. The size of \\(C_{I2}\\) can be reduced to alleviate the slewing errors due to the band limited behaviour of A1. In addition the parasitics at the output of A1 will pre-charge before \\(C_{I2}\\) is connected reducing the settling error due to the active nodes switching at the input and output. + +A common concern for chopper stabilized circuits is the resistive element of each chopper which in this case is seen at the input of the amplifier. This resistance is due to the switching capacitor \\(C_{I1}\\) that is continuously dissipating dynamic current. This can partially be compensated for by performing positive feedback from the output to assist in cancelling the dynamic current through \\(C_{PF}\\) [^123]. However this will rely on the matching of the capacitor ratios $\frac{C_{I1}}{C_{F1}} \frac{C_{I2}}{C_{F2}}$ to be equal to \\(\frac{C_{I1}}{C_{PF}}\\). This can be quite challenging if small configurations are desired that do not need exhaustive calibration. The use of a high precision ADC makes this somewhat easier because the total gain A1\\(\cdot\\)A2 does not need to be as large implies smaller ratios and better matching. Evaluating this resistance in terms of the switching capacitance will result in the expression in Equation 10. + +$$ R_{in} = \frac{1}{2 f_{CHP} \cdot (C_{I1} + C_{par} - \frac{C_{I1}}{C_{F1}} \frac{C_{I2}}{C_{F2}} C_{PF})} $$ + +This dependency should indicate that if the dynamic switching current cannot be well matched due to parasitics or variability the next objective would be to reduce the total switching capacitance. From our discussion however it appears that reducing the input capacitance is limited by the psuedo resistive noise that induces aggressors at the chopper frequency. This constraint can be mitigated using a distributed amplifier structure that splits A1 into two identical sections. This should be configured such that the second stage has its high pass pole and corner frequency proportionally larger than the first stage but scaled the gain of the prior stage. However such a topology is more constrained by parasitics that worsen the settling errors in $0.18 \mu m$ CMOS. In addition the poor control of psuedo resistive characteristics does not allow this to be convincing solution [^126]. The feasibility may be more favourable in more advanced technology nodes. Considering a value of \\(1 pF\\) for \\(C_{I1}\\) we expect slightly over \\(20 M\Omega\\) without positive feedback and approximately \\(200 M\Omega\\) with \\(10%\\) matching. This may be acceptable in either cases depending which type of electrode is used but generally any thing above \\(100 M\Omega\\) is satisfactory for most scenarios. + + +## 22 Bandwidth Limited Amplifiers + + + +Biomedical instrumentation has the advantage that the slowly varying signals prevent most implementations from facing problems due to limited bandwidth. The exception however lies with the stage that drives the input capacitance of the ADC and the settling time during sampling can be quite challenging[^127]. Particularly when multiple channels are multiplexed to the same data converter. In some sense there is an similarity when we look at NEF and bandwidth efficiency because they are strongly dependent on maximizing transconductance efficiency. + +$$ FOM \left[ \frac{MHz \: pF}{mA} \right] = \frac{f_{UGF} \cdot C_{L}}{I_{tot}} \text{for diff. pair} FOM = \frac{10^{3}}{4 \pi \eta U_{T}} $$ + +{{< figure src="technical_1/MCAmp.pdf" title="Figure 25: " width="500" >}} + + +Strictly stated in Equation 11, a bandwidth constrained circuit should minimize the total current consumption \\(I_{tot}\\) for a given unity gain bandwidth \\(f_{UGF}\\) and capacitive load \\(C_L\\). It is typical to find dedicated structures out side of the signal processing chain that drive the ADC input capacitance and focus specifically on maximizing the FOM by employing current recycling, adaptive biasing, and positive feedback techniques. The challenge here is efficiently introducing these techniques while also preserving the capability for full output swing, stability and particularly low distortion. The later is likely the most challenging and demands high loop gain that is generally not found in adaptive single pole structures if full output swing is also required. With that said, two stage Miller compensated topologies can provide an excellent solution to this problem because high gain in the second stage will suppress a number nonlinearities excited by the input stage. Further more the capacitive coupling of the output to the input of the second stage implies the settling speed is limited by bandwidth of the second stage. This allows the configuration to simultaneously provide filtering and settling while sharing many of the biasing and feedback elements. Using the model shown in Figure 25. We can show that sampling induced kick back from the ADC at \\(V_{out}\\) has negligible in pact on internal integration node as it is inversely proportional to the product $A_{cl}\cdot \frac{gm2}{gm1}$ where \\(gm1\\) and \\(gm2\\) are the transconductance of the first and second stage. This is derived from evaluating a step response due to discharging the output load \\(C_{L}\\) which has the Laplace domain response as Equation 12. + +$$ H_{step}(s) = \frac{s^2}{s^2 + (\omega_2 - \frac{\omega_1 C_{M}}{A_{cl} C_{L}} ) s + \frac{\omega_{1} \omega_{2}}{A_{cl}}} \text{where} \omega_{1} = \frac{gm_1}{C_{M}} \: \: , \: \: \omega_{2} = \frac{gm_2}{C_{L}} $$ + +{{< figure src="technical_1/T1_T2AMP.pdf" title="Figure 26: " width="500" >}} + + +Figure 26 shows the proposed circuit implementation of the two-stage amplifier used inside the second instrumentation stage in Figure 24. This structure has the advantage of providing very high loop gain across the Miller capacitor and allows full output swing due to the positive feed back structures in the current mirrors. The PMOS mirror provides high gain by cancelling the \\(1/gm\\) transresistance of from the diode connected pair leaving the high impedance node and the NMOS mirror provides positive feedback to speed up the transient behaviour on the PMOS side. When this structure provides closed loop gain larger than 20 dB it is sufficient to rely on the NMOS current mirror for stability. In fact this is equivalent to a feed-forward stabilization technique that by passes high frequency signal lag induced by the pole at the PMOS side. However when good phase margin is required at the unity gain frequency stability becomes more stringent. In this case we suggest introducing an additional capacitor across \\(V_n\\) & \\(V_p\\) to realize a zero that cancels the pole in the PMOS branch [^128]. The zero will in fact boost the effective \\(\omega_{2}\\) from $N M \frac{gm_{M5}}{C_{L}}$ to $\frac{N M + M }{2-N} \frac{gm_{M5}}{C_{L}}$. The factor M in this structure has a rather interesting implication with respect to NEF. If M is large enough this topology will have a NEF equivalent to the complementary structure. However in effect the biasing current of the intermediate branch is reduced when M is large which can move the parasitic poles in side the amplifier bandwidth. The apparent trade off between stability and NEF is unique to this structure but it is not challenging to have M=8 for low power applications. + +$$ FOM = \frac{10^3}{4\pi \eta U_{T}} \cdot \frac{2 C_L }{ C_M (1+M/K+1/K)} $$ + +The components that improve bandwidth efficiency are detailed in Equation 13. Referring this back to Equation 6 however implies the noise is dominated by the capacitor that introduces the dominant pole of the system. The observation made here is that unlike the single stage topologies, the two stage configuration can trade off input referred noise for a better speed FOM by adjusting the \\(\frac{C_M}{C_L}\\) ratio. The high level methodology applied here is replacing the \\(C_L\\) with a smaller capacitor that requires less power with the hope that stability can still be maintained by boosting transconductance power with positive feedback and current recycling. + +## 23 Circuit Implementation + + + +{{< figure src="technical_1/T1_T1AMP.pdf}" width="500" >}} +{{< figure src="technical_1/AMP_Feedback.pdf}" title="Figure 27: Schematic showing circuit implementation of the proposed compact neural amplifier. " width="500" >}} + + +Figure 27 shows the transistor level implementation of the topology used in Figure 24. The first gain stage is a highly compact complementary structure that exhibits exceptional noise performance. The second stage transistor implementation is the high gain two-stage topology discussed in Section 22. The variable gain configuration is facilitated by the digital controlled low leakage switches that connect a selected set of capacitors in feedback. This particular configuration provides more generic instrumentation of the 1 Hz to 6 kHz bandwidth. It is well known that the analogue filters introduce frequency dependent group delay near the pole locations which has been shown to degrade processing capabilities of spike sorting techniques [^129]. By placing the high pass pole well inside of the LFP band the spike wave-forms exhibit less distortion due to analogue filtering and is instead filtered using linear phase filters in the digital domain that do not suffer from such drawbacks. + +The reset mechanism on instrumentation amplifiers using pseudo-resistive elements is essential. Either during stimulation, start-up, or amplifier saturation the charge across the feedback capacitor must be neutralized before correct operation can begin. This mechanism allows the rejection of various distortion components that would other wise corrupt the latent signal integrity or digital signal processing. However there is an inherent problem with these reset switches due to the parasitic charge injection induced on the intermediate semi-floating nodes. Moreover if these elements are cascaded to increase resistance or dynamic range these sensitive floating nodes are also increased thereby building up more residue charge. A significant amount of charge can introduce a permanent reset artefact after reset as this charge redistributes internally inside the resistor. The proposed solution to this problem is by minimizing the floating nodes and guarding the floating N-Well from injected noise. This should allow a very large pseudo resistance for a sub-Hz high pass cut off frequency while maintaining exceptional reset characteristics. We minimize the resulting charge residue by absorbing the leaky diode currents and residues into the guarding amplifier. Now there will be some instantaneous off-set as the reset signal injects charge directly onto the feedback capacitor but this can be quite small when using small switches. The drawback here is that there may exist a very slow drift on the order of \\(V/sec\\) from the guarding amplifiers due to $V_{os} R_{diode}$. But simple digital assistance will suffice in eliminating this concern by periodically resetting the structure and cancelling the residue off-set. This re-introduces the high pass pole at a well defined location depending on the periodicity of the reset signal and reconstructing signal in the digital domain [^130]. + +{{< figure src="technical_1/AMP_Label.pdf}" width="500" >}} +{{< figure src="technical_1/AMP_Chip.pdf}" title="Figure 28: Physical implementation of amplifier using a 6-metal $0.18 \mu m$ CMOS process measuring $75 \times 82 \mu m^2$ in size. " width="500" >}} + + +The floor plan for this implementation is annotated in Figure 28. The typical focus for analogue layout is achieving good matching for the input transistors and capacitors to minimise off-set or undesirable signal coupling. In this case the chopper introduces a lot switching that is difficult isolate from the signal so instead we focused on minimising parasitics of the clocked nets. The common mode feedback on the second stage uses a switched capacitor and wide band amplifier to ensure accurate common mode settling without deteriorating linearity. This is important because the ADC can be quite sensitive to the sampled common mode resulting in a reduced precision if there is an unexpected offset on the sampled output. Simulated performance of the implemented topology is shown in Figure 29. This compact configuration can achieve an input referred noise of $5.6 \mu V_{rms}$ over the specified bandwidth with a noise corner frequency of 20 Hz. The performance is detailed with a clear reduction in size can be observed when compared to other chopper systems in Table 5. The total gain is \\(421 V/V\\) for this particular configuration which can be adjusted using the digital calibration bits integrated into the structure allowing different gain and power settings. The maximum available gain setting is shown in Figure 30. + +{{< figure src="technical_1/Noise_PLO.pdf}" width="500" >}} +{{< figure src="technical_1/Amp_Thd.pdf}" title="Figure 29: Post layout simulated results of the proposed instrumentation circuit. " width="500" >}} + + + +{{< figure src="technical_1/sim_gain.pdf" title="Figure 30: Post layout simulated results using periodic steady state analysis to evaluate the closed loop gain of the instrumentation circuit. " width="500" >}} + + +Table 5: Summary of performance specifications of the proposed instrumentation topology and other bio-signal chopper stabilized amplifiers found in the literature. +| Parameter | Units | This Work | Markovic [^125] | Makinwa [^123] | +|----|----|----|----|----| +| technology | [nm] | 180 | 40 | 65 | +| Supply Voltage | [V] | (1.2) | (1.2) | (1) | +| Total Current | [(\mu)A] | (1.05) | (1.67) | (2.1)| +| Bandwidth | [Hz] | (<1)-(6 k) | (1-5k) | (0.5-1k) | +| Filter Order \ Roll-off | [dB/Dec] | (20) | (20) | (20) | +| Noise Floor | [$nV / āˆš{Hz}$] | (55) | (101) | (60)| +| Noise Corner | [Hz] | $20 Hz$ | (100) | (<1)| +| Dynamic Range | [dB] | (58) | (69) | (64) | +| Area | [(\mu)m(^2)] | $6.2\cdot 10^3 $ | $7.2\cdot 10^4$| $2\cdot 10^5$ | +| Area-Power-Product | [(\mu)W (\mu)m(^2)] | (7.3 10^3) | (141 10^3) | (420 10^3) | +| NEF | | (1.08) | (2.5) | (1.66) | + + +Overall the proposed implementation performs well for supply voltages larger than \\(1.1 V\\) where the limiting factor is due to the current biased complimentary input stage. This configuration necessitates a voltage overhead requirement of \\(2V_{TH}+2V_{ov}\\). However both of the gain stages are class-A which at exhibit relatively well behaved current transients on the supplies. Class-AB alternatives do not share this feature and are more prone to disturb neighbouring recording circuits. Minimizing the dynamic current dissipation should lead to better LDO performance and lower supply induced sensor noise when many channels are integrated together. This also motivates another aspect for using a wide-band amplifier configuration for the first amplification stage because it usually implies that the common mode will also have wide band regulation. This leads to better common mode rejection in the signal band due to additional loop gain. + +# 24 Analogue Signal Conversion + + +\label{ch:T1_converter} + +Analogue to digital conversion remains to a crucial component instrumentation, particularly for full signal characterization. Even when considering the demanding constraints for integrated neural sensors, the prevalence of full spectrum signal characterization is ubiquitous in the literature. This is motivated by the efficiency and reliability of various digital processing methods that require very efficient signal conversion to discreet samples instead of processing recordings in the analogue domain. Typically the most valued performance criteria for such a system is the ADC power consumption. A Successive Approximation Register (SAR) ADC is commonly used for quantizing biomedical signals because it only dissipates switching energy that can be very small for slow sampling rates. The SAR topology is depicted in 31 and can be found extensively in BMI recording publications. + +{{< figure src="technical_1/Split_Cap_Schmtc.pdf" title="Figure 31: Schematic of a conventional N bit SAR ADC with the split capacitor at position M." width="500" >}} + + +## 25 Capacitive array miniaturization + + + +This discussion pays special attention to acquiring neural recordings that include LFPs while minimizing the required silicon area per sensor. This is motivated by wanting to integrate many sensors on chip for large arrays and secondly reducing any capacitive switching noise that can be quite difficult to reject in fully integrated systems. Recording LFPs and EAPs simultaneously will require increased ADC resolution so that the instrumentation dynamic range exceeds 60dB. Equivalently this means 10 to 14 bit precision is needed depending on the nonlinearity tolerances of the proceeding processing methods. This can be quite difficult it terms of the SAR specifications because the capacitor mismatch and sampling noise can prevent aggressive sizing on the unit capacitor. For a given ADC precision N, the SAR capacitor array will require $M \cdot 2^{N/M}+M$ unit capacitors \\(C_{unit}\\) where M is the number of equally split sections. By splitting the array into sections it should be obvious that the total capacitor requirement \\(C_{Total}\\) can be reduced to some extent. The quantization errors resulting from capacitor mismatch on the other hand is also closely related to these parameters. For given standard deviation \\(\sigma\\) and confidence interval CI we can use Equation 14 to make a simple estimate for the expected quantization error \\(E_Q\\) [^131]. + +$$ E_Q = V_{ref} \frac{\sum \Delta Ci}{2^N C_{unit} - \Delta C_{Total}} = V_{ref} \cdot \alpha(N) \frac{āˆš{2^N}-1}{āˆš{2}-1} $$ + +The above expression assumes no split configuration is used where \\(\alpha\\) represents a scaling factor that is dependent on the number control bits for each sub-DAC, $\alpha(x)= \frac{CI \sigma}{2^x - CI \sigma āˆš{2^x}}$. \\(V_{ref}\\) is the reference voltage by which the sampled input is normalized to arrive at the binary encoded result. Now extending this formulation to include the dependency of M and bounding $E_Q < LSB/2$ in accordance with the required ADC precision leads to the expression in Equation 15. + +$$ \frac{1}{2^{N+1}} \geq \alpha(N/M) \sum_{k=0}^{M} \left[ \sum_{i=0}^{M} āˆš{2^{i}} \right] \cdot \left( \frac{\alpha(N/M)}{2^{N/M}} \right)^k $$ + +There several higher order terms with respect \\(\sigma CI\\) not shown here because they have vanishing contribution as N is increased and require a numerical solution to the problem. Otherwise for M=2 and arbitrary placing the split capacitor K position in the array we can similarly reconstruct the equality from 14 in Equation 16. + +$$ \frac{1}{2^{N+1}} \geq \frac{CI\sigma(āˆš{2^{N-k}}-1)}{(2^{N-K} - CI \sigma 2^{\frac{N-K}{2}} )(āˆš{2}-1)} + \frac{(āˆš{2^{K}}-1) CI \sigma} {(āˆš{2}-1) 2^K (2^K -CI \sigma 2^{\frac{K}{2}})} $$ + +The standard deviation \\(\sigma\\) is closely related to the exact requirements for the whole capacitive DAC in terms of the total area and unit capacitor size. The dependency of \\(E_Q\\) is mainly subject to the variance due to the MSB capacitors and for each less significant bit (from MSB to LSB) the expected variance increases by \\(āˆš{2}\\) while its capacitive coupling decreases by 2. This is because $\sigma \propto 1/āˆš{A_C}$ where \\(A_C\\) is the area of the capacitor. Clearly there is a process related figure of merit here that relates to the quality of capacitors since small capacitors with excellent matching will result in the best characteristics ADCs such that we minimize the % deviation per \\(\mu m^2\\). + +{{< figure src="technical_1/Split_CAP.pdf" title="Figure 32: Numerical solution to Equation 16 relating the capacitive DAC area requirement with the DAC resolution (N) and the position of the split capacitor before capacitor K. " width="500" >}} + + +Figure 32 shows a numerical solution to the equality in Equation 16. This allows us to consider the effect of split capacitor positioning with respect to the optimal area allocation for the capacitor array. The visible plateau for small N represents the case when the design is bounded by the minimal unit capacitance. This is determined using the process documentation for the target 0.18 \\(\mu m\\) CMOS technology that gives its mismatch specifications and minimum sizing. Generally split capacitor configurations are more sensitive to parasitics they can lead to more pronounced nonlinearities. However in some cases that the unit capacitor size limits the array size such that splinting the array is an effective solution for improving power dissipation. We reiterate that this also indicates that the binary weighted configuration without splitting maximizes area efficiency if we are not limited by sampling noise or minimal capacitor sizing. In addition a fully differential DAC counter intuitively reduces the minimum size if the switching method first detects polarity before applying successive feedback [^132]. This is because the first quantization cycle does not depend on the capacitive division. This in turn means that the array can tolerate twice the mismatch error implying a 4 times smaller unit capacitance while only doubling the number of capacitors in the array. + +## 26 Model based topology selection + + + +From here there are multiple directions we can take in order to ensure efficient operation and simultaneously achieve a compact configuration. A common approach is to multiplex the SAR ADC to a large number of channels but this will also require the analogue stage driving the ADC to dissipate proportionally more power due to settling requirements on the sampling capacitance. From a high level perspective, distributing the quantization effort into a large array of ADCs with staggered operation should lead to much more systematic power dissipation due to their uncorrelated operation. Opposed to using a single high speed ADC that requires a much higher clock frequency with stronger tones in the generated supply noise. Another SAR based alternative using calibration for the capacitive array such that it can specifically be designed with the smallest possible unit capacitors. Then we could correct any nonlinearity or quantization errors that arise from capacitor mismatch if the array is characterized precisely enough. This does require either foreground or background calibration modules to extract the individual capacitor weights. Because we aim to perform a number of processing techniques in the digital domain for characterizing neural recording, it makes sense for us to consider effective means to perform calibration. + +{{< figure src="technical_1/SDADC.pdf" title="Figure 33: Schematic of the proposed $\Sigma \Delta$ assisted SAR ADC topology for achieving a more compact configuration." width="500" >}} + + +The structure illustrated in 33 represents a hybrid topology based on SAR and sigma delta structures. The motivation is driven by the efficiency of SAR quantization for large signals and the compactness of high resolution quantization from sigma delta loops. The digital control will perform fully differential bottom plate sampling of the input which is then rapidly quantized to \\(2^N\\) levels using the typical binary search. After the SAR operation the resulting residue left on the capacitive array is quantized using a sigma delta control loop that feedback on the nodes \\(V\Sigma\Delta\pm\\). + +There is a strict advantage over conventional sigma delta loops which is that the residue error that needs to be quantized is reduced to \\(\frac{V_{ref}}{2^{N}}\\) which can easily be designed to lie within the linear range of a differential pair. This negates having to use passive or active feedback to deal with transconductance nonlinearity and significantly improves the power efficiency by retaining a relatively simple control loop topology. Moreover as the feedback loop is typically responsible for small dynamic range of 30dB the requirements on clock jitter and decimation filtering is made more relaxed. + +The more desirable advantage over a high resolution SAR is that the capacitive DAC may designed in a highly optimal configuration with as few bits as possible. This allows sizing that primarily focuses on suppressing parasitic effects with minimal sampling capacitance. As will be demonstrated this topology does not require an axillary calibration DAC or a pseudo random dithering source for performing mismatch correction. This is due to the capability that the internal sigma delta structure is in the same signal loop as the SAR operation and can trade-off bandwidth for increased noise rejection simply by adjusting the sampling frequency \\(f_s\\). Naturally because this topology inherently needs a pre-amp stage for SAR conversion we should not expect the FOM to do better than low resolution SARs. + +Intuitively one can think that when combining the two topologies the individual sources for power dissipation now scale with \\(2^{\frac{N}{2}}\\). More specifically these sources come from the capacitive DAC and decimation filter. The components that do not have reduced scaling are related to the sampling noise and the thermal noise floor of the oversampling modulator. To demonstrate this quantitatively we will build an analytic model for the SAR and \\(\Delta\Sigma\\) SAR topologies to demonstrate some of the inherent characteristics. This will also reveal the techniques for optimizing of the proposed structure. + +$$ FOM_{ADC} = \frac{P_{sys}}{2^{N} f_s} $$ + +Maximizing the performance indicator from Equation 17 will represent our objective function which reflects the efficiency by which each sample is converted into a digital code. Through the simplicity of this relation, any comparison primarily requires an accurate expectation for power budget in terms of the required resolution or precision requirements. + +$$ P_{Ideal} = \underbrace{ E_{search} \cdot f_s C_{unit} V_{ref}^2 (2^{N-2}+2^2)}_{Capacitor Array} + \underbrace{2N (N+2) f_s E_{gate} }_{Register Logic} $$ + +Equation 18 Considers the primitive structure with an ideal comparator where \\(E_{search}\\) represents the average dissipation for binary search switching method and \\(E_{gate}\\) is the average gate dissipation per clock cycle. Both these parameters adjust to different core libraries or various switching methods that typically trade off efficiency for parasitic tolerance [^133]. This ideal structure is extended by the requirements of either a dynamic latch comparator or an analogue pre amplifier that allows negligible comparator requirements at the expense of consuming a static current. The classic pre-amplifier approach also tends to deal with mitigating kick back noise but in general the straightforward application of classic \\(kT/C\\) relations conveniently give; + +$$ P_{amp} = 32 \pi \ln(2) \cdot \underbrace{\frac{(U_T N 2^N)^2}{V_{ref} \cdot \eta q}}_{Noise} \cdot \underbrace{A_{ol} f_s NEF^2}_{Bandwidth} $$ + +Here \\(A_{ol}\\) represents the gain provided by the pre-amplifier. Notice the very typical inverse relationship with respect to \\(V_{ref}\\) which motivates the use of the more efficient dynamic comparator structure. However evaluating the equivalent input referred noise of a dynamic structure accurately requires the a piece wise evaluation for different phases of operation and the respective stochastic integrals [^134]. The contribution can be associated with two dominant sources, that of sampled noise; + + +$$ \sigma_{S} = \frac{4 kT}{3 C_x F} + \frac{ kT}{3 C_x F^2 H} + \frac{ kT}{12 C_x F^2 H^2} $$ + +And noise contributed from transconductive elements; + +$$ \sigma_{M} = \frac{kT}{C_x F^2} + \frac{kT}{2 C_x F^2 H} + \frac{kT}{8 C_x F^2 H^2} $$ + +$$ F = \frac{2 \rho V_{th}}{V_{ref} - V_{th} } \text{and} H = \frac{V_{ref}}{2 V_{ov}} \cdot {2 \rho }{1 + \rho} $$ + +As before, this must be bounded by the acceptable quantization noise, $ V_{ref} \cdot {2^{-N-2}} = āˆš{\sigma_M + \sigma_S } $, which give the values for \\(C_x\\). Strictly there is a strong dependence on the input signal in order to evaluate the dissipated power but on average it is reasonable to approximate this to the capacitive switching energy of $P_{Latch} \approx f_{s} C_x V^2$. + +Now consider the components of the \\(\Delta\Sigma\\) structure. Clearly it will follow closely to that of the pre-amplifier based relations with the exception that the primitive components from Equation 18. Instead this will scale with \\(N-K\\) where \\(K\\) is the number of bits resolved by the sigma delta loop. Here two additional components will be accounted for, the first is the integrator and the second is the digital FIR that decimates the modulated residue quantization. A second order feed forward integration topology is chosen for \\(H(s)\\) based on its efficacy of being applied to the configuration shown in Figure 33 and primarily minimizing the number of summing operators and coefficients prone to mismatch. For the sake of discussion we make the assertion that decimation noise rejection is bounded $K \leq (FIR)^{-1/2}$ in the case of a rectangular window for analytic clarity [^135]. Furthermore, note that as we increase the SAR quantization the first stage will proportionally see a reduction of the input signal that needs to be accounted for to achieve the correct integration constant. + +$$ P_{int} = 32 \pi \cdot \underbrace{\frac{(U_T 2^{N} NEF)^2 }{ q V_{ref}}}_{Noise} \cdot \underbrace{FIR f_s (1+2^{N-K}) }_{Bandwidth} $$ + +And similarly the digital decimation filter will scale in the form of; + +$$ P_{fir} = \underbrace{2^{K}}_{OSR} \underbrace{( K + \log_{2}(K))}_{Quantization} fs E_{gate} $$ + +Collecting these terms for each topology will equate to expressions that typically have scalar dependencies on technology or implementation which we must make a set of reasonable assumptions for. The literature will indicate numerous means by which each component can be reduced through specialized logic cells, adaptive comparator power allocation, or power saving switching methods. Our particular interest lies with the dependency on N that will imply the effectiveness of a certain topology for a given dynamic range requirement. In addition this familiarizes us with specific factors fundamental to power dissipation with respect to resolution. + +{{< figure src="technical_1/P_TOP_N.pdf}" width="500" >}} +{{< figure src="technical_1/P_TOP_A.pdf}" title="Figure 34: Summary of the FOM (\\(P_{sys}/2^{N} f_s\\)) for each topology with respect to different resolution requirements. " width="500" >}} + + +Figure 34 presents the expected merit for each topology as the target resolution is varied. Without consideration for area, there is a clear power advantage for the dynamic SAR structure mediated primarily by the fact that the comparator does not have settling associated tolerance. This is the main reason why the pre-amp topology requires a proportionally increased bandwidth/power as resolution is increased. What stands out is that the \\(\Delta\Sigma\\) structure has a power dependency $\propto 2^{3N}$ for achieving the required input referred noise in contrast to more conventional dependency of \\(2^{2N}\\). The mechanism behind this is due to the SAR quantization that reduces the signal input range which needs to be recovered to achieve the correct integration factors. Moreover the over sampling ratio increases simultaneously which has an overall multiplicative effect. Clearly the resolution of the SAR quantizer should only perform a few conversion that put the residue in the linear range of the loop filter and let the modulator perform most of the quantization effort. When all topologies are using the same unit capacitor, this result demonstrates that for \\(N < 5\\) & \\(N > 14\\) the \\(\Delta\Sigma\\) topology becomes strictly unfavourable in terms of power but performs comparably with respect to power efficiency for \\(N \approx 10\\). Taking the FOM area product by considering the capacitors in terms of \\(\Box\\) units the advantage of the \\(\Delta\Sigma\\) topology becomes more obvious. For the precision significant to neural recording, \\(8}} + + +Considering the design space of the \\(\Delta\Sigma\\)SAR structure in more detail will expose a more optimal strategy for increasing FOM. Figure 35 exemplifies how the FOM behaves as either the SAR of sigma delta accuracy is increased. After the optimal basin at N = 9 & K=4 the best strategy for improving ADC resolution is by increasing SAR quantization at half the rate of the sigma delta increase in resolution. For reference a conventional $\Delta \Sigma$ modulator [^136] is designed with the same target specifications and using the same design method to configure the OPAMP integrators and resistive input network. Such a configuration achieves 167 dB FOMs irrespective of target resolution when we consider just the analogue power dissipation. In fact this figure is commonly achieved by state of the art [^137]. As shown in Figure 36 the \\(\Delta\Sigma\\)SAR configuration can theoretically achieve more than 4X better performance than conventional \\(\Delta\Sigma\\) modulators for resolutions above 12 bits even when operating at lower supply voltages. This is because of the improved noise efficiency. Please refer to Section 58 for additional details regarding derivations and topology comparisons that are omitted here for clarity. + +{{< figure src="technical_1/AMD.pdf" title="Figure 36: Estimation on the expected figure of merit for a target resolution and varying SAR precision. The red star and blue circle indicate the target and measured performance respectively. " width="500" >}} + + +## 27 Circuit Implementation + + + +Extending the conventional SAR structure to perform sigma delta modulation is achieved with relatively little changes to the overall topology. The main difference is that during the last phase of SAR conversion a register must be toggled that switches in the integrators intermediate to the comparator. Simultaneously the \\(V\Sigma\Delta\pm\\) capacitors are directly connected to the comparator bipolar output instead of the common mode voltage \\(VCM\\) for differential feedback. This configuration is integrated on chip and performs 7 bits of differential SAR quantization with another 5 bits resolved by the noise shaping modulator with an over sampling rate of 32. At the system level, 4 analogue recording channels will be multiplexed to the input of the ADC which implies sampling rate of \\(100 kS/s\\) is required to sample each output at \\(25 kS/s\\). + +{{< figure src="technical_1/SAR_Arch.pdf}" width="500" >}} +{{< figure src="technical_1/SAR_Logic.pdf}" title="Figure 37: Schematic configuration of the top level control for the \\(\Delta\Sigma\\)SAR data converter." width="500" >}} + + +Figure 37 shows the top level configuration of this data converter. By using a specialized register logic slice a small reduction in complexity is achieved in addition to the mitigation of timing issues typical with the conventional self clocking register configuration. This topology uses a bottom plate sampling strategy to neutralize the effect of parasitics and common mode comparator nonlinearities while operating at 1.2V with a 10MHz clock frequency. Although there are only \\(N-K+OSR\\) active phases, settling the output of the recording amplifiers on to the capacitor array will require several cycles because of the band limited behaviour present in the driving stage. + +The implementation of the capacitive DAC and second order feed-forward integrator are shown in Figure 37. This configuration also opts to scale the voltage reference for the LSB in order to reduce the total number of capacitor required. As the capacitor array is implemented using CMIM devices the 7 bit differential structure with a split capacitor for \\(M=3\\) will grantee 10.1b for a confidence interval of \\(3\sigma\\) using Equation 16 and process documentation parameters that show a $8\times8 \mu m$ has \\(0.23 %\\) mismatch induced standard deviation. The reasoning for this configuration is that we are guaranteed \\(>9.5 bits\\) without calibration and will allow \\(>12 bits\\) with calibration. For either case the accuracy is sufficient for recording LFP and EAP signals simultaneously. This result was also confirmed with monte-carlo analysis using foundry supplied PSP models. + +{{< figure src="technical_1/T1_SDSAR_CDAC.pdf}" width="500" >}} +{{< figure src="technical_1/T1_SDSAR_INT.pdf}" title="Figure 38: Schematic implementation of the \\(\Delta\Sigma\\)SAR structure. " width="500" >}} + + +The integrator topology primarily deals with the contrasting bandwidth requirement of the SAR operation and the sigma delta integration for the first stage. Particularly when taking the SAR decisions at the oversampled clock the first stage can only provide wideband gain if the capacitor is switched out and a resistive element is used instead. The circuit complexity can be dramatically reduced by using triode region transistors that regulate the PMOS biasing current for a well defined common mode. Because these transistor can be large in area they could slow down the maximum SAR speed. To avoid this the CMFB circuit is semi open loop during the SAR quantization leading to an increase bandwidth by using the common mode voltage that preserved on the integration capacitor. Also by switching the biasing current of the analogue summing stage a constant common mode can be presented to the comparator input thereby reducing any off-set disparity between the two operation phases. + +{{< figure src="technical_1/ADC_Label.pdf}" width="500" >}} +{{< figure src="technical_1/ADC_Chip.pdf}" title="Figure 39: Physical implementation of ADC using a 6-metal $0.18 \mu m$ CMOS process measuring $93 \times 147 \mu m^2$ in size." width="500" >}} + + +Figure 39 shows the fabricated structure of the ADC. Since the capacitors are placed on top of the active circuits this floor plan distances the integrators and the MSB capacitors to physically isolate the digital switching noise sources. A number of shielding structures are employed to improve post layout performance. There include various guard rings and isolating N-wells but due to the proximity of the digital switching the most effective strategy is appropriately orienting fully differential structures in order to equalize the coupling components. Here metal layers 1-3 are used for transistor interconnect, layers 5-6 for the capacitive DAC, and layer 4 is interposed in order to shield the two sections while connected to the common mode voltage. This is because the transient fluctuations on \\(V_{cm}\\) are only due to mismatch and should be the most quiet reference in the system with large capacitive loading. + +In order to take advantage of this structure we reveal two distinguishing characteristics that can not be found in either conventional topologies or other hybrid topologies. When the capacitive DAC is considered as a set of weights that need to be determined we realize that the derivative for slow varying signals is predominantly quantized by the sigma delta loop. With the exception when the SAR bits switch the quantization is independent of the mismatch in these weights. As a result all the mismatch coefficients can be accounted for with respect to the $\Sigma \Delta C$ capacitor. + +{{< figure src="technical_1/adc_cloop.pdf" title="Figure 40: Control loop used to perform calibration with a slow test signal at the ADC input." width="500" >}} + + +The calibration technique discussed is abstractly represented by Figure 40 where there are two IIR control loops with the coefficients \\(a_1\\) and \\(b_1\\). In part this loop performs normal operation by evaluating the signal quantization \\(Q_{sig}\\). This is done adding the SAR quantization with calibrated weights and decimating the oversampled residue with a \\(32^{nd}\\) order FIR window quantized with 8 bit coefficients for each sample. Here \\(a_{1}\\) simply has to be small enough to track the signal and reject noisy components to determine $\Delta Q$. $\Delta Q$ represents DNL nonlinearities that are used to adjust the coefficients \\(K_{DAC}\\). The multiplication operator is in fact a bitwise evaluation that indicates if a coefficient needs to be adjusted due to a correlation between $\Delta Q$ and a change in that bit. Hence \\(b_{1}\\) needs to be small enough to prevent level dependent tuning and \\(V_{test}\\) should be a full range slow varying signal. + +{{< figure src="technical_1/adc_UC.pdf}" width="500" >}} +{{< figure src="technical_1/adc_CC.pdf}" title="Figure 41: INL Plots illustrating the mismatch artefact reduction due to calibration." width="500" >}} + + +The improvement in INL is evident in Figure 41 due to the calibration mechanism with \\(a_1=1/4\\) and \\(b_1=2^{-8}\\). The close interaction between INL & DNL errors over the full dynamic range for a capacitive array in addition to the sigma delta loop's capability of quantizing $\pm 2 LSB$ of the array allows this method to converge accurately. Here it is observed that the calibration improves the quantization accuracy by two additional bits. + +{{< figure src="technical_1/adc_thdsnr.pdf" title="Figure 42: Measured THD and SNR of the fabricated data converter." width="500" >}} + + +{{< figure src="technical_1/ADC_TEST.jpg}" width="500" >}} +{{< figure src="technical_1/adc_TI.pdf}" title="Figure 43: Testing setup used for characterizing the ADC." width="500" >}} + + +Figure 43 shows the test bench used during device characterization. The saleae logic device is a digital probe that offers 100 MS/s digital signal acquisition for measurements of up to 10 seconds. Here the raspberry pi module simply provides real time interaction with the device configuration using automated spi control and a graphical user interface that will indicate ADC precision based on the selected operation. This allows us to tweak the operating conditions and find which noise sources are disturbing the configuration. The analogue bias \\(I_{BIAS}\\) is generated by a 2602A Keithley system source meter and fed in using a guarded triax cable. The differential input signals are generated using a Agilent 33522A arbitrary waveform generator and fed to the ADC input using BNC cables. + +Table 6 outlines the characteristics of the implemented ADC configuration while comparing it to recent oversampling/noise shaping data converter publications. Figure 42 demonstrates the spectral characteristics of the quantization output for a input signal at half the full input range after calibration. In comparison to the analogue instrumentation, the resource related specifications are significantly larger. However note that there requirements are distributed over a number of channels as a result of multiplexing this structure. + +Table 6: Summary of performance specifications for the \\(\Delta\Sigma\\)SAR data converter and other oversampling/noise shaping data converter structures found in the literature. +| Parameter | Units | This Work | Lo [^138] | Roermund [^139] | +|----|----|----|----|----| +| Technology | [nm] | 180 | 65 | 65 | +| Supply Voltage | [V] | (1.2) | (1.2) | (0.8) | +| Total Current |[(\mu)A] | (12) | (13) | (1.7) | +| Sampling Frequency | [kS/s] | $200 $ | (8) | (16) | +| ENOB | [bits] | (11.3) | (17.5) | (14.5) | +| SFDR | [dB] | (86) | (105) | $ 87 $ | +| Area | [$\mu m^2$] | $93 \times 147$ | $400 \times 180$ | $600 \times 300$| +| Power-Area-Product | [$\mu W \mu m^2$] | $1.9 \cdot 10^5$ | $1.1 \cdot 10^6$ | $2.4 \cdot 10^5$| +| $P/(fs + 2^N)$ | [fJ/conv] | (10) | (29) | (6.6) | +| (SNDR+10log(BW/P)) | [dB] | (166) | (180) | (177) | + + +The trade off with respect to residue over sampling in Figure 44 demonstrates that there is some flexibility with respect to sampling rate and SINAD performance. In addition this also clarifies that post-fabrication adjustments do not exhibit significant resolution improvements beyond the design point. This is related to the sampling noise of the capacitor array and the noise floor of the analogue integrators that need to be programmable for different oversampling ratios. At which point the decimation also has more strenuous requirements that may result in an inefficient resource overhead. Strictly stated it is significantly more efficient to reject noise with digital bandpass filtering selected frequency components than having the ADC resolve the signal beyond the target precision. + +{{< figure src="technical_1/adc_fom.pdf" title="Figure 44: Measured Figure of Merit as a function of oversampling ratio." width="500" >}} + + +In the context of miniaturization the topology presented here follows closely to the expected improvement from the model for high resolution signal acquisition. We achieve nearly 12 bits of quantization with a 6 bit equivalent capacitive DAC which is reflected in the compact design foot print. When compared to similar compact ADC implementations found in recent publications we observe a competitive power budget with again significantly smaller area requirement. Some additional digital processing is required opposed to the simplicity of SAR converters to take full advantage of the topology. However such hardware is typically readily available in systems that also perform spike sorting and neural signal classification. + +# 28 System Level Abstraction + + +\label{ch:T1_model} + +Numerous specifications such as ADC resolution and input referred noise of the instrumentation amplifiers relate directly to signal specific parameters. Moreover a particular processing algorithm would favour certain filter configurations of others in terms of signal conditioning. In multi stage systems however there is a significant amount of flexibility related to choosing gain for individual stages or their filter parameters that is indifferent to the resulting transfer function. Here we consider such a primitive \\(N\\) stage analogue processing chain and discuss the allocation of resources to gain insight to some of the high level the optimization for selecting a specific configuration. Such a configuration is shown in Figure 45. + +{{< figure src="technical_1/ACS.pdf" title="Figure 45: Multistage amplifier configuration using the series G to adjust the allocation power and area. " width="500" >}} + + +$$ G[n] = A_{g} \left( \beta + \alpha^{n} \right) \text{where} A_{g} = āˆš[N]{\frac{G_{T}}{ \prod_{i=1}^{N} (\beta + \alpha^{n} )}} $$ + +Consider a geometric series for the gain of each stage as expressed in Equation 25. Here \\(G_{T}\\), \\(\alpha\\), \\(\beta\\) represent the total gain required, resource distribution factor, and a minimal contribution factor. The formulation is motivated by the fact that if \\(\alpha\\) is one resources are allocated equally. This means every stage has equal gain but it also implies that the sum of all gain factors is minimal leading to a minimum amount of area due to the feedback capacitors. More typically designs will choose a smaller \\(\alpha\\) such that most of the gain is situated at the first few stages. This allows some reduction in power in the proceeding stages because of the reduced noise requirement. \\(\beta\\) simply allows us to specify that a fraction of the total gain is uniformly distributed but is typically kept small in order to maximize the benefit from resource redistribution. This allows us to express the noise power requirement for a given set of parameters in Equation 26. + +$$ P_{Amplifiers} = P_{unit} \left( 1 + \sum_{k=1}^{N-1}\left[\prod_{i=1}^{k} \frac{1}{A_{g} \beta + A_{g} \alpha^{i} } \right] \right)^2 $$ + +$$ A_{Gain}= A_{unit}\left( \sum_{k=1}^{N} \left[1 + A_{g} \beta + A_{g} \alpha^{k} \right] \right) $$ + +Here \\(P_{unit}\\) is simply evaluated from Equation 6 and leads to an area requirement that is simply expressed using Equation 27. Now taking some typical parameters we can evaluate a possible configuration of gains and thereby the associated allocation of resources. This is shown in Figure 46. + +{{< figure src="technical_1/RDBG.pdf" title="Figure 46: Resource allocation for analogue power and area using the parameters \\(G_T=500\\), \\(\alpha=0.3\\), and \\(\beta=0.05\\). " width="500" >}} + + +Lets take \\(A_{unit}\\) as some unit capacitance size that allows the deviation of gain due to mismatch to fall inside the confidence interval. In order to realize Equation 26, each stage has its power and input referred noise reduced by accumulated gain for the preceding stages. This result presents us with the trend illustrated in Figure 47 where it appears that in many stage systems it is relatively beneficial to redistribute the resources to the front-end for a reduction in overall power. However when the number of stages is three or less we observe the increase in area can diminish this improvement for high gain system requirements. + +{{< figure src="technical_1/NM_NP.pdf}" width="500" >}} +{{< figure src="technical_1/NM_PAP.pdf}" title="Figure 47: Normalized resource improvements for \\(\alpha\\) with respect the case when \\(\alpha=1\\) for each configuration. " width="500" >}} + + +So far we have neglected some aspects to the design consideration. The first is the multiplicative increase standard deviation as N is increases and the sensitivity to variance being inversely proportional to closed loop gain. Here we can account for the increased variance by proportionally increasing \\(A_{unit}\\) in order to neutralize this increase according to Equation 28. + +$$ \Delta \sigma^2 =\frac{A_{\mu+\sigma}}{A_{Gain}} \approx \prod_{i=1}^{k} \left( 1 + \sigma CI \left[ 2 - \frac{2}{āˆš{ A_{g} \beta + A_{g} \alpha^i }} \right] \right) $$ + +Again \\(\sigma\\) represents the deviation for a chosen unit capacitance and \\(CI\\) is our confidence interval. For completeness in estimating area we will also introduce the capacitance required for performing filtering on the last \\(K\\) stages. Rearranging Equation 6 in terms of output referred noise according to Equation 29. + +$$ e^2_{out} = \frac{kT}{C} {NEF^2}{\eta} $$ + +Combining these terms lets us define a more accurate area requirement that is reformulated in Equation 30. + +$$ A_{filt} = A_{unit} \cdot \frac{kT}{C_{unit}} \frac{NEF^2 SNR^2}{Vdd^2 \eta} \cdot \left( 1 + \sum_{k=1}^{K-1} \prod_{i=1}^{k} \left[A_{g} \beta + A_{g} \alpha^{N-i} \right] \right) $$ + +It is important to point out that SNR here refers to the SNR of the data converter as we have fixed the input referred noise of the system for a systematic comparison and we adjust \\(G_T\\) to fill this dynamic range. And extending this result with the requirements for signal conversion we can estimate system level power \\(P_{Total}\\) and area \\(A_{Total}\\) requirements as a sum of individual components according to Equation 31. + +$$ A_{Total} = A_{filt} + A_{Gain} + A_{ADC} \text{and} P_{Total} = P_{Amplifiers} + P_{ADC} $$ + + +Taking an appropriate set of parameter values, the system of relations is exemplified in Figure 48 with respect to the dependency on the supply voltage, \\(Vdd\\). As illustrated there are two domains when considering the area requirement. For small \\(Vdd\\) the sampling & filtering noise requirements overwhelm the design particularly in this case if \\(\alpha\\) is not taken small enough and a second order roll off is needed. When there is more voltage overhead available we observe reliably matching in input dynamic range of the ADC is the dominating factor. + +{{< figure src="technical_1/NM_TSNA.pdf}" width="500" >}} +{{< figure src="technical_1/NM_TSNAP.pdf}" title="Figure 48: Analogue resource relations with respect to different supply voltages. " width="500" >}} + + +The area power product also tells an interesting story. When \\(Vdd\\) is larger than 1 V a clear proportional dependency on power is apparent that is mostly related to the total gain & noise requirements of the system because the ADC is not the limiting factor. However for small supply voltage the power dissipation requirement is more closely related to the lower noise quantization requirements presented by the SD-SAR topology. We should be careful because certain circuit topologies are simply not viable below specific supply voltages and as a result it would no be possible to achieve a NEF smaller than 2. Figure 48 also indicates when particular topologies are viable specific to the $0.18 \mu m$ CMOS process where $V_{th} \approx 350 mV$. That said it is likely a system can be designed with \\(0.6 V\\) supply in order to achieve significant power and area savings. The main challenge will be achieving acceptable total harmonic distortion as the supply will not easily allow cascoding transistors. Particularly sub-threshold transistors suffer from \\(Gm\\) nonlinearity as a function of \\(e^{\frac{-V_{DS}}{U_T}}\\) that can only be compensated by increased loop gain and multi-stage topologies. Since it is implementation dependent, it is difficult to quantify what this increase in area an power overhead this will result in. We can assert that \\(60 dB\\) precision with instrumentation has very significant diminishing returns when the conventional design approaches a \\(2 V_{th}\\) supply. The reader can find more details in regard to these comparisons in Section 60. + +The approach taken here can be exhaustively extended towards including more detail in the system level design in order to leverage the capability of numerical methods. Higher order Gm-C filtering structures can be accounted for as a single stage by introducing new parameters that reflect the increase in \\(NEF\\) and filtering capacitors. Transistor area per amplifier can arguably be assumed static if chopping techniques are employed or alternatively this can accounted for by considering the flicker noise relations for the input transistors. However these contributions have negligible effect on changing the optimal resource destitution and will be more influenced by strategic positioning of poles to reject certain noise components. The most critical parameters on the systems level is the supply voltage as well as the requirement for channel to channel gain matching. As the power area product has a inverse square dependency as either \\(V_{DD}\\) or gain variance tends to zero. There are only a select number of scenarios where gain matching is of significance which is primarily in the case of distributed LFP recording and multi electrode (i.e. tetrode) recordings where exact coupling of neural circuitry is in question. The supply voltage has significance with respect to the expected power dissipation of the on chip digital processing and it is understandably advantageous to aggressively dissipate more power on the analogue side if the power saving in the digital domain indicate a overall improvement. + +We note another aspect to technology selection in addition enabling voltage scaling is the increase in functional capacitor density. In fact we have shown that the dominant factor for area requirement in chopper stabilized structures is capacitance through the strong dependency on gain and filtering elements. More advanced processes have an increased number of metal layers and higher transistor gate capacitance. This ultimately leads to an increased capacitor density per square millimetre. In certain scenarios this should allow us to marginally shrink amplifier configurations while keeping the same filter characteristics. The main concern would be associated with capacitor nonlinearity that requires extra consideration or correction circuits. + +# 29 Conclusion + +This chapter has demonstrated the capacity for conventional analogue instrumentation with state-of-the-art circuit techniques. This presents capacity for achieving very compact performance that is sufficient for the full characterization of neural recordings. The fabricated system uses 0.03 mm\\(^2\\) size silicon footprint for 4 recording channels that can characterize 5 mVpp neural signals with over 11 bits of precision. In addition proposed $\Delta\Sigma SAR$ ADC topology demonstrates how oversampling converters can achieve 10fJ/conversion efficiency with minimal circuit complexity. The techniques applied here suggests chopping and sigma-delta modulation are key components for achieving better performance particularly for size constrained systems. In association we suggest immediate digitization & coherent mixed signal processing to leverage a number of advantages. Moreover we expect modern system will allow more processing capabilities in the digital baseband for BMI systems that needs to be used effectively. + +The significance of minimizing the noise efficiency factor has been revealed in terms of having profound influence to power dissipation and area. In extension we have presented a number of topologies that excel at achieving excellent power and area efficiency in the case of single stage, two stage, and ADC structures. However we are left with little surprise when methodical optimization of various configurations is limited by the fundamental bounds in terms of noise and dynamic range. In fact various idealized configuration show little benefit with respect to one another if they have been optimized and exploited appropriately with the understanding presented. It is characteristic that improving resource efficiency for full bandwidth signal quantization is difficult because we simultaniously attempt to achieve lower supply voltages. + +Although digitization is crucial to most neural recording systems for extracting the signal characteristics used to train and improve signal postprocessing. It is clear that improvements at the system level will lie very much in the domain of specialized instrumentation and analogue to information converters. This notion is motivated by the desire for the system to be limited by the law of equipartition and less so by the quantization process of the data converter. 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[Online]: http://www.darpa.mil/program/unconventional-processing-of-signals-for-intelligent-data-exploitation diff --git a/content/publications/2016/brain-machine-interfaces-neural-recording-neuron-processor-interface.md b/content/publications/2016/brain-machine-interfaces-neural-recording-neuron-processor-interface.md new file mode 100644 index 0000000..dc6d152 --- /dev/null +++ b/content/publications/2016/brain-machine-interfaces-neural-recording-neuron-processor-interface.md @@ -0,0 +1,651 @@ +--- +title: "Brain machine interfaces: Neuron Processor Interface" +date: 2016-08-08T15:26:46+01:00 +draft: false +toc: true +math: true +type: posts +tags: + - chapter + - thesis + - CMOS + - biomedical +--- + +Lieuwe B. Leene, Yan Liu, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +A core aspect of emerging neuroscience is quintessentially performing real-time data analysis at a massive scale. However when we observe its manifestation in state-of-the-art neural interfaces we find the hardware is very limited to specific methods that can be objectively short-sighted. This chapter aims to direct our attention to a different point of view with respect to how these sensor systems can be structured. In particular we are guided by the concept where an implant is capable of performing software defined instrumentation. This is associated with a focus that lies with enabling real time & in-vivo testing of a more diverse set of signal characterization methods. More importantly we will demonstrate that this can be made feasible for large scale distributed systems. + +This particular approach is motivated by a number of factors that aim to increase performance and enable research opportunities. The first is that many aspects with regard to the signal quality of an implant cannot be predicted beforehand. As a result implementing a specific algorithm for specific signal characteristics may lead to failure or an overly conservative design because the environment can potentially be excessively noisy. By introducing the capacity to dynamically execute different processing methods on neural data the implanted system to use either LFP and EAP activity in real-time. This may be a significant element to improving the success for chronic BMI implants. Moreover the prolific development in characterization methods used for decoding neural data inhibits a general consensus for DSP techniques. This prevents a single method and corresponding architecture to be applicable in most scenarios. The second factor is that this approach conceptually enables the development of real-time resource constrained algorithms which are virtues often neglected when working with data sets. Currently most BMI development platforms have limited capabilities to allow algorithms to use external or multi-modal features to inform local operation and simultaneously provide recordings from hundreds of electrodes. This construction may be a key factor to allowing high level algorithms to directly manipulate machine learning parameters local to each implant. This hierarchical fashion should improve the efficiency of distributed BMIs for decoding information. In contrast we question the feasibility for scaling the current supervised methods that require fine measurements of each electrode's recording to approach a optimal decoding strategy. Typically the computational efficiency of this approach remains exhaustive when reconfiguring sensor parameters because it use a centralized unit that recalibrates all recording channels in an elaborate fashion. + +This chapter is organized as follows; Section 31 motivates localized processing for increased efficiency and estimates to what extent we can perform on-chip processing. This is followed by Section 32 where typical methods used for neural signal analysis are introduced and the respective hardware complexity is demonstrated in Section 33. This leads into the proposed distributed processing architecture in Section 38 where the design is discussed with respect to the implementation. Section 41 demonstrates the realization of this platform. Finally Section 42 draws conclusions with respect to the digital approach to neural instrumentation. + +# 31 Processing at the interface + +Ideally a neural interface device is tasked with recording from a large ensemble of electrodes and transmitting information with the lowest bandwidth because the harvested power is a scarce resource for implants inside the body. However over the course of an implant's life time most signal characteristics are dynamically changing which implies that there should be an involved learning process that similarly adapts to these changes. This can also mean that the output bandwidth is constrained by the total amount of mutual information that can be retained within the device. Such a device will predict the expected recording from one time interval to the next and differentiate any new information that needs to be transmitted. Hence we should be convinced that the processing capacity or complexity for a closed or memory limited system should reflect in its fundamental ability to store information [^140]. + +In order to capture some high level trends with respect to processing requirements let us normalise memory capacity in terms of state variables that is independent of modality. This is particularly useful because the number of state variables in a dynamic process is a good indicator for complexity whether is a digital classifier or an analogue filter. Here we will exclusively focus on processing by assuming the signal being operated on is idealized with respect amplitude and its representation. This extends from our analysis in Section\ref{ch:T1_model} by elaborating specifically on comparing digital and analogue resource allocation associated with processing. + +$$ R_{A} = \underbrace{\frac{2\pi BW kT SNR^2 U_T}{V_{DD} L}}_{power} \cdot \underbrace{\left( \frac{A_{min}}{L} +\frac{kT SNR^2}{L Vdd^2 C_{dens}} \right)}_{Area} $$ + +If we represent the resource required as the power area product for a state variable then in the analogue domain it would be represented by Equation 32. Here \\(BW\\), \\(V_{DD}\\), \\(C_{dense}\\), \\(A_{min}\\) reflect the signal bandwidth, supply voltage, capacitor density, and typical transconductance area overhead for a particular technology respectively. \\(L\\) is a normalized feature size that allows us to evaluate parameters for a particular technology and extrapolate them based on constant field scaling factors. + +$$ R_{D} = \underbrace{ 2BW \alpha \log_2(SNR) C_{gate} V_{dd}^2 L^2 }_{power} \cdot\underbrace{ \alpha \log_2(SNR) A_{gate} L^2}_{Area} $$ + +Similarly Equation 33 represents the power area product for a digital state variable. \\(C_{gate}\\), \\(A_{gate}\\), \\(\alpha\\) parametrise typical gate capacitance, area, and overhead for each register respectively. Generally the dependency of both parameters \\(R_A\\) and \\(R_D\\) are well understood and guide maximizing system efficiency in an abstract sense [^141]. + +{{< figure src="technical_2/impact.png" title="Figure 49: Impact of technology on \\(R_A\\) analogue (green) and \\(R_D\\) digital (blue) processing resource requirements extrapolated from a \\(180 nm\\) CMOS technology under constant field scaling." width="500" >}} + + +For neural instrumentation however both power and area requirements must be highly constrained in order to realize a device that can accommodate a large number of recording channels and remain implantable. Figure 49 shows the resource requirements for processing in the analogue and digital domain with respect to signal fidelity and CMOS technology. Either approach can present an advantage over the other under specific conditions. Digital systems appear favourable beyond \\(65 nm\\) CMOS where analogue will do better at lower SNR conditions given a technology with a larger feature size. The discussion in Section \ref{ch:T1_model} suggested the analogue preconditioning requires a resource allocation of $10^{-15} Wm^2$ with a weak dependence on technology. Moreover if quantization is not considered then power can be entirely determined by the noise specification and the area requirements are dependent on the gain configuration. Comparing this figure with the estimate on \\(R_D\\) indicates that we should be able to integrate a considerable amount of processing capabilities before the DSP uses a comparable amount of resources. This is important because improving on-chip processing capacity ideally results in requiring less supervision and a lower wireless communication bandwidth. + +While we may expect other sources of over-head and extra power dissipation components, we should instead take a moment to consider the implications of this result. Particularly when considering the claim that electronic sensing of brain activity on larger scales is not viable due to the excessive data rates derived from the principle entropy relations and the associated communication bandwidth [^142]. Clearly any degree of on-chip processing undermines this limitation because it enables us to achieve data rates far lower than that of the electrical signals by finding a more appropriate basis of encoding information. On the other hand it does raise an important point regarding the relationship of the generated output data rate and the recorded signal to noise ratio. In some sense we are simply faced with the challenge of best consolidating the recorded information towards high level indicators for specific objective functions. This allows us to approach data rates extracted from current BMI studies which are negligible in comparison to the Nyquist rates. In this light we argue that electronic methods for recording activity are the closest to realizing a viable neuroprosthetic solution in the near future when comparing optical, magnetic and less invasive BMI architectures. + +Now we can make the assertion that there should be two approaches to solving the system level challenge of integrating wireless neural instrumentation systems. The first approach would be a mixed signal topology that extensively uses analogue processing such that technology has a weak impact on improving efficiency. Instead the critical component lies with the effectiveness of analogue dimensionality reduction. In such a case we need to adopt a well established algorithm that can accommodate analogue variability an still deliver exceptional signal characterization. The second approach is to rely on digital methods that deliver robust and reconfigurable compute resources that scale well with technology. This should grantee the capacity for a variety of fully adaptive algorithms capable of extracting multi-modal characteristics from recordings. This could much more valuable for experimental neuroscience at this point in time. Unfortunately not all forms of algorithms can use the low power characteristics of processing in the analogue domain. Moreover they are typically limited by underlying assumptions regarding noisy perturbations. When we introduce different contexts of operation reconfiguring the analogue is not done as arbitrarily as a digital structure would. For this reason we will adopt the digital approach in order to leverage robust reconfigurable capabilities and reconsider the analogue approach in Section 48. + +The significance here is that these trends allow us to roughly estimate the complexity of algorithms for different technologies if their resource requirements made to be equivalent to that of the instrumentation circuits. We show in Figure 50 that using a $0.18 \mu m$ CMOS process should give way to approximately 100 state variables or equivalently perform about 100 operations per sample taken. In fact looking at image processors that similarly rely extensively on data intensive post processing we can see an identical dependency on technology scaling as we have predicted for various levels of digital performance at different technology nodes. It is important to note that the normalized efficiency evaluated here is in fact independent of signal bandwidth and only depends on signal to noise ratio and its relation to the supply voltage. + +{{< figure src="./technical_2/Operations.pdf}" title="Figure 50: Analytic number of digital operations available with respect to different technologies (red) with references to the normalized performance of image processors (blue)." width="500" >}} + + +$$ P_{system} = \underbrace{ N_{channel} \cdot \left( P_{Algo} + P_{Transmit} \right) }_{In \: Channel} + \underbrace{ P_{Control} + P_{Comms} }_{System \: Level} $$ + +System level design of a embedded processing system for BMIs should be guided entirely by the optimization of compute power efficiency. As shown by Equation 34 we expect are two primary components in the system power breakdown. The over all objective should lie with minimizing the channel level power dissipation of the algorithm \\(P_{algo}\\) by increasing that of the system level control \\(P_{Control}\\) such that the component that scales with channel count is reduced. Secondly we should keep in mind that reducing in processed output data alleviates the dissipation of the on-chip communication \\(P_{Transmit}\\) and the external telemetry power consumption \\(P_{Comms}\\). + +## 32 Methods for Neural Signals + + + +A key component to developing this platform is a discussion on the diverse set of signal processing methods performed on neural data and their computational requirements in order to determine our system's specifications. More importantly we want to judge what is the expected complexity for some of these operators and how many variables are allocated during each process. There are in principle four different categories for the methods that are applied to process neural signals which are listed below. In practice, a single integrated system will utilize a multitude of different techniques to achieve denoising and feature extraction. + +\textbf{Pre-Processing} is the filtering and conditioning of each ADC output sample using FIR, IIR, or non-linear filters. Here the objective is simply to de-noise the features or signal components. The resulting signal allows for better detection or more precise evaluation of the signal characteristics and is often closely related to the characteristics of the instrumentation circuits. This output may be considered as the raw signal recording that is used to bench mark any post processing methods or other instrumentation systems. + +**Detection** is associated particularly with capturing the intermittent spike events. There is no quantitative evaluation made with regard to the nature of the detected spike but any detection may trigger the process that records contiguous samples around the detection event that are then subsequently characterized. These events are commonly triggered upon simple threshold crossings of the signal or its integral power over several samples. In some systems the interest lies only with the accurate detection of spike events which is sufficient to perform closed loop therapeutic treatment or control actuators external to the body. +**Data reduction** can be interpreted either as representing a spike waveform in terms of defining features or with a reduced basis to allow approximate reconstruction by using spike amplitude or wavelet decomposition. Representing waveforms in terms of their quintessential components allows for more efficient post processing and reduces data rates in the case of wireless telecommunication. In its primitive sense this is simply dimensionality reduction of the recorded data and is usually followed by supervised or unsupervised signal classification. + + +**Classification** is the predominant objective for BMIs and is the main difficulty to realize inside a embedded recording system. Such a task in spike based systems primarily performs a generalization of the detected spike shape in terms the previously detected neurons. This reflects the fact that in most cases multiple neurons can be detected by a single electrode and by distinguishing these events the integrity of information can be preserved. The objective here lies with having an equivalent spike event output as simple detection to perform actuation but with better fidelity. + +It should also be clear that the above operations primarily focus on reducing the recorded signal to its primitive components in terms of spike events at the rate of \\(100 b/s\\) instead of the \\(256 Kb/s\\) data stream typically generated by the ADC. The processing layer on top of this elementary function will either aim to evaluate neural connectivity or use collections spike rates to perform inference of high-level dynamics. This application specific processing of these systems will not be considered here primarily because the nature of such a problem is very different from the more generic information extraction from recordings. As a result that system architecture should revolve specifically around multichannel trained dimensionality reduction. Even when such a task can adjoin to what is presented here it will be out side the scope of this discussion which targets more generic signal instrumentation. + +{{< figure src="technical_2/Survay_I.pdf}" title="Figure 51: Estimated resource requirements for different classes of algorithms use for processing neural recordings found in literature." width="500" >}} + + +When we survey the various algorithms found in recent literature and estimate the expected memory/computational requirements we might observe a distribution like that shown in Figure 51. For fair comparison we have adopted these methods to operate on a window size of 32 samples with three types of dectected spike waveforms when applicable and only accounted for memory allocation that cannot be shared across channels. This should give a good normalized indication of the limiting components for each method which we could then further optimize in a more specialized manner. Notice that there is a strong correlation in the memory usage and the required number of operations for most embedded systems. + +Some of the most efficient spike detection and feature extraction is associated with using temporal characteristics of the spiking waveforms. Common examples include using the time interval between minimum and maximum peaks or the duration of threshold crossing for detected spikes. The defining characteristic here is that alignment buffers are not needed which leads to using very few operations per sample. Inherently the drawback is the increased sensitivity to noise which implies a very limited capacity to distinguish and classify different spike shapes. Unless more filtering is performed. There are other methods that also operate with reduced signal buffers. For instance using compressed sensing where signals a continuously re-projected with a sensing matrix. This requires a few accumulators for each coefficient being extracted but this is strictly data compression. Ultimately This may not help directly with classification or signal characterization that must now be performed off-chip before any benefit can be realized. + +Many other classes of algorithms operate on a windowed basis that exploit learned mean spike shapes that are expected in the recording. Here a convolution or distance operator will indicate which class of spike is detected. For terminology let each convolution of the signal result in a feature that is used for detection and/or classification. The adaptive component of these methods leverage a significant amount of noise shaping and separation depending on what the objective function entails when the basis for convolution is being determined. The most prevalent approach is convolving with principle components which simply maximizes the signal variance in the projected space. In contrast to using temporal feature that struggle with sample limited denoising, the windowed operators should be more robust towards noise. Instead there is some difficulty in systematic alignment of the window with the spike. This aspect often motivates increased sampling rates or interpolation in order to perform accurate alignment. + +The objective function for determining the convolution kernels can be oriented towards maximising sparsity[^154], signal to noise[^155], cluster separation[^49], or expectation maximization[^156] each reflecting different signal modalities and analysis methods. Although the complexity for training can be varied extensively the local operations for classification after adaptation is almost equivalent. This operation is the \\(F\\) linear projections using \\(W\\) samples onto the feature space where \\(F\\) and \\(W\\) are the number of features used and the number of samples in the window respectively. There may be some deviation from this operation if we also consider the different confidence intervals for each class is taken into account. This can be done by evaluating centroid distances in terms of the variance for each respective centroid. Conversely to such training, generalized templates averaged over a number of recording channels may also be used for feature extraction in order to share the memory requirements at the loss of not achieving maximally separated clusters for each individual channel. + +Naturally it is challenging to objectively judge feature extraction and classification methods. We could always reduce the dimensionality of the search space or by simplifying the convergence strategies to reduce memory and computational requirements. For this reason the details in Figure 51 should be considered in relative terms due to the generalizations made with regard to system specifications. As many methods in the literature are not performed at the sensor interface they typically will not take advantage of processing on a sample to sample basis and opt for a batched or sequenced processing methodology. + +We claim however that the segregation between methods primarily lies with whether the classification features are based on sample space characteristics or alternatively use windowed convolution operators. The former is the less rigorously justified as the features relating to amplitude and spike width have weak physiological significance but are aggressively more efficient than other methods. The characteristic requirement of the later later approach is typically related to the window size that is indirectly associated with the sampling speed in order to fit the relevant spike shape into the window. One important objective of current decoding research is related to introducing adaptive techniques that iteratively improve classification without supervision. Particularly without excessive memory requirements in order to keep track of long term statistics. To demonstrate why this can be particularly challenging, consider a simplified example of using K-means to directly cluster the sample space adaptively where we are fortunate to know the number of classes is three. + +Clearly for each detected spike we would need to evaluate the distance between our data the centroids having a memory and complexity requirement of \\((1+F) W\\) variables and \\(2 F W\\) operations respectively. Then once the class is determined an additional \\(2W\\) operations are needed to adjust the centroid with the new data. This may include keeping track of the additional \\(F W\\) truncation residues that allow using a small enough adjustment weight for convergence when our quantization is limited by an 8 bit system. Now for completion, assume our window is 32 samples and we come to the conclusion that for each recording channel we to actively need to allocate nearly \\(2 K bits\\). + +Typically this primitive aspect of a generic classification algorithm is intensive enough warrant not performing it locally in contrast to the complexity of the aforementioned temporal features. It also raises the challenge of trained dimensionality reduction without supervision which exclusively relies on evaluating the covariance matrix in order to minimize the correlation of non-signal components with our new basis. The above algorithm may be representative in terms of complexity with the exception that basis pursuit relies heavily on inner products. There is some relief from the fact these optimal basis change very slowly and actively adapting is only needed once few hours as the electrode recording changes slowly with respect to the neural activity. As will be demonstrated the feasibility of these more involved methods rely very much on the careful construction and memory allocation of the algorithm with respect to the processing architecture. Operations like k-means and PCA decomposition can be performed to a certain extent if the operations are broken down into a incremental procedures. + +# 33 Resource Constrained Classification + + + +Primarily to substantiate our expectations for performing processing at the sensor interface and evaluate where the system level requirements should lie. Ultimately such a system needs to encompass a significant variety of different application requirements. We will consider the implementation of two well known methods that process neural recording and generate classified events. This will be applied to the equivalent scenario where the proposed instrumentation front-end is used from Section 17 such that the digitized signal will have considerable dynamic range but lacks analogue filtering. In particular this implies the recorded signal is filtered by a first order butterworth low pass filter in addition to near-DC rejection while being sampled at \\(25 KS/s\\). We will address the rejection of low frequency aggressors in addition to the computational requirement of typical processing algorithms. + +Many of the filter and processing considerations are guided by evaluating accuracy empirically and justified though constrained parametric optimization [^157]. The particular algorithms implemented here are structured in such a way they perform specific considerations for the underlying hardware. On numerous occasions we will employ single bit accumulators as approximations to the IIR equivalent feedback structures in order to improve our effective register depth through feedback. This is a primary advantage of in-channel processing where we may exhaustively make use of recorded data without having concern for the communication of these components. + +Empirical validation is demonstrated by using of synthetic data sets that are publicly available online. This data is based on characterized extracellular recording where both background activity and spike morphologies are extracted from a human neocortex and basal ganglia. The synthesized recording was originally used to evaluate the performance of super-paramagnetic clustering with wavelet decomposition at different background noise levels in [^1]. Synthetic data specifically allows the inference of the ground truth resulting in unbiased performance indicators. For fair comparison of analogue and digital techniques we additionally include low frequency content from \\(1-300 Hz\\) at \\(10\times\\) of the largest peak to peak amplitude of the extracellular action potentials found in the recordings. + +## 34 Spike Detection & Filtering + + + +Arguably the most influential aspect to neural detection and classification algorithms is the signal preconditioning for systematic and accurate detection of spike events. The importance lies with the fact that detection behaviour has the significant influence on how the feature space appears when the spike is characterized with various methods. Although amplitude noise can usually be accounted for in terms of filtering. Any misalignment in the time domain due to noisy aggressors in the detection operator can up modulate low frequency components. The tendency to perform detection in the digital domain is entirely related to the instantaneous characteristic of discreet time processing which is superior to the group delay inherent to analogue implementations. Minimizing this factor will minimize additional memory for capturing any signal before the detection event. + +The method proposed here tracks both the mean spike amplitude and back ground noise levels in order to assert the detection level of spike events. Motivated by using physiological characteristics to specify the underlying operation parameter \\(k_3\\) is introduced to represent the relative amplitude of background activity to that the maximum spike waveform that is intended to be detected. Or in other words if we are only interested in the closest neurons to the electrode \\(k_3\\) should be close to 1, otherwise if we also want to detect background activity with an amplitude at \\(25%\\) of the largest spiking events \\(k_3\\) should approach \\(4\\). In actuality this term should also be related to how well our classification can separate noisy detection or actual spike events. + +\begin{algorithm} + \DontPrintSemicolon + \KwData{Sample from ADC \\(X[n]\\)} + \KwResult{Detection events & spike window \\(W_1\\)} + \Begin{ + \ShowLn + Update \\(V_{LFP}\\) with $k_1 \cdot (X[n]-V_{LFP})$ \tcp*{ Track low frequency content} + Set \\(S[n]\\) with $X[n] - V_{LFP} + k_2 \cdot S[n-1]$ \tcp*{ IIR bandpass filter} + Set \\(G[n]\\) as $\sum S[n]\cdot FIR(2*R) $ \tcp*{ FIR bandpass filter } + Set \\(ES[n]\\) as $S[n] \cdot G[n-R]$ \tcp*{ Energy Estimate from IIR & FIR product } + Update \\(V_{noise}\\) with $k_1 \cdot (|ES[n]|-V_{noise})$ \tcp*{ Estimate variance on energy estimate } + + \uIf{$ES[n] > V_{th}$ **and** $ES[n] > max_{local}$ \tcp*{ Find threshold crossing or new local max } }{ + Update \\(V_{th}\\) with $k_1 (ES[n-1]+2V_{noise} - k_3 \cdot V_{th})$ \tcp*{ Adapt peaks and varience} + Initiate Spike Alignment \; + Set \\(max_{local}\\) to \\(ES[n]\\) \tcp*{Set local maximum} + Set \\(index\\) to \\(0\\) \tcp*{Initiate data pointer} + } + + \uElseIf{Currently alligning spike (\\(index<16\\)) }{ + Set \\(W_1[index]\\) to \\(G[n-10]\\) \tcp*{Store spike waveform with delayed samples} + Set \\(index\\) to \\(index+1\\) \tcp*{Increment data pointer} + } + + \uElseIf{Idle state (\\(index>31\\))}{ + Set \\(max_{local}\\) to \\(0\\) \tcp*{Finish classification & find next local maximum} + } + \uElse{ + Accumulate \\(index\\) with \\(1\\) \tcp*{Increment data pointer} + %Perform Classification on \\(W_1[index]\\)\; + } + + } + \BlankLine + \caption{Spike Detection and Alignment} + \label{aglo:T2_Detection} +\end{algorithm} + +The specifics of this operation is reflected in Alg. \ref{aglo:T2_Detection}. Here the term Update, Set, and Accumulate represent recurrence, instantaneous, and integrated relations respectively. The state variable \\(V_{LFP}\\) primarily removes low frequency drift that is not associated with individual spiking events and \\(S[n]\\) is as a result a bandpass equivalent of our sampled signal \\(X[n]\\). The signal's instantaneous energy is represented by \\(ED[n]\\) which is a product of \\(S[n]\\) and the delayed derivative computed by the FIR of even order \\(2R\\) with the coefficients $a_n= -a_{2R-n} = 1-2/R \cdot(n-1)$ for \\(n\\) from \\(1\\) to \\(R\\). The factor \\(R\\) is in association with the ratio of sampling interval to spike polarization interval, equivalently as $R=f_{nyquist} / 5KHz$. At the maximum of \\(ED[n]\\) operation on line 5 essentially measures the product of the maximum spike intensity with the maximum derivative that proceeds it by \\(R\\) samples. This method primarily depends on the fact that spike detection looks for highly correlated narrow band energy which rejects a substantial amount of white noise. Moreover the operator compresses uncorrelated components in amplitude as it exhibits a square dependency in terms of $ED[n] \propto S[n]^2$ making variation in the threshold less sensitive to detection. The fact that the operator is narrow band limits the detection of slower spike waveforms that do not contain large derivative components but on the other hand this grantees more systematic alignment. In this case alignment is done simply with respect to where the peak value of \\(ES[n]\\) is detected. + +{{< figure src="technical_2/freq_pfd.pdf}" width="500" >}} +{{< figure src="technical_2/phase_pfd.pdf}" title="Figure 52: Extracted frequency characteristics of digital filter used in Algorithm \ref{aglo:T2_Detection}." width="500" >}} + + +The overall filtering characteristic of \\(S[n]\\) and \\(G[n]\\) is shown in Figure 52. The IIR bandpass is a result of \\(k_2\\) being \\(0.5\\) such that both filters suppress components around the Nyquist frequency. The group delay should be equivalent to a single high pass pole at $250 Hz$ but the FIR assists in further suppressing high and low frequency components. We should not expect significant contribution from group delay induced distortion as the features of interest will predominantly have $1 KHz - 5 KHz$ components. Besides \\(R\\) and \\(k_1\\) can always be adjusted to reposition the high-pass poles closer to DC. Note that \\(V_{LFP}\\) will represent the \\(DC-250 Hz\\) signal components that can be used to infer characteristics about the background activity. + +{{< figure src="technical_2/C05.pdf}" width="500" >}} +{{< figure src="technical_2/C01.pdf}" width="500" >}} +{{< figure src="technical_2/C02.pdf}" title="Figure 53: False alarm rates normalized by true positives for data sets with different background activity." width="500" >}} + + +The overall performance shown in Figure 53 reflects how spike detection is systematically accurate until the noise level approached \\(50%\\) of the signal intensity irrespective of the data set with the default case where \\(k_3=3\\). Note that the white noise is additive to the background activity implying \\(-14dB\\) of white noise and \\(-14dB\\) of background activity should evaluate to around \\(-8dB\\) accumulated SNR. When the noise level exceeds the anticipated background activity for \\(K_3\\) we observe a strong increase in the number of detected false positives. The rate of erroneously detected false negatives presents a more gradual increase but at this point classification is much more challenging. As expected background has a considerably bigger impact on false alarm rate because spectral content and signal structure is equivalent to that of the foreground activity. + +We can observe that the main component for computational complexity in this detection operator arises from the FIR & IIR high-pass filters where the order is closely related to the sampling frequency. In fact if we ignore the buffer used to capture features before the alignment event then this filter accounts for 70% of the memory utilization and 53% of the elementary operations while the rest is used for evaluating the instantaneous energy and performing overhead control. Note that the classification operator should be introduced in line 19 with a sample basis using the index as referenced pointer. This implies that we will be classifying while repolarization occurs at the electrode and our detection trigger is blanked out during this interval. This implies that we lose the capacity to detect any over lapping spikes. Such events have limited occurrences and missing such events can be acceptable because proper classification will likely fail as well. + +## 35 Recursive Variance Decomposition + + + +Another commonly used technique is that of principle component analysis (PCA) which extracts the largest loading vectors \\(\nu_n\\) of the covariance matrix. This predominantly negates the systematic components of the captured signal and reduces the dimensionality of the spike window to a sub-set of maximally varying features by linear transformation. These components are particularly useful as indication for spiking activity in the signal due to structure in \\(\nu_n\\) but typically also suffice for providing a basis for classification in low noise conditions and reducing complexity once these vectors are found. The challenge specifically lies with the fact that determining this is basis requires both the computation of the covariance matrix that evolves over time as well as finding the transformation that diagonalizes that matrix. The implication is that in order to extract the first two principle components we need to track a total of \\(W(W+3)\\) state variables where \\(W\\) is the number of samples in the spike window. + + +The iterative method employed here referred to as recursive variance decomposition (RVD) and is an approximation to standard PCA by recursively tracking the largest two loading vectors reducing the minimum number of state variables to $3W + 3$. Similarly to PCA estimators like hebbian eigenfilters [^155], every iteration incrementally updates the the learned basis without requiring extensive computation. The methodology is based on recursive extraction of the largest loading vector $|\nu_1|$ that is normalized by \\(g_1\\) by checking the condition $(x - x \cdot \nu)\cdot \nu = 0 $. This condition checks if there is any residue in the direction of \\(\nu_1\\) after removing its component to see if it is appropriately scaled. Moreover due to the strong correlation between the mean and first principle component we approximate that $sign(\mu) \approx sign(\nu_1)$ completing the extraction of \\(\nu_1\\). In fact these two statements allow a significant reduction in complexity as normalization is achieved through feedback. The noise shaping and orthogonality properties associated with PCA is preserved using this extraction which is the most important aspect. + +\begin{algorithm} + \DontPrintSemicolon + \KwData{Spike window \\(W_1\\)} + \KwResult{First two aggregate loading vectors \\(\nu_1\\) & \\(\nu_2\\)} + \Begin{ + \ForEach{Sample **n** in window \tcp*{ Projection phase } }{ + $D_1[n] = W_1[n] - \mu[n]$ \tcp*{ Get distance from mean spike } + Accumulate \\(p_1\\) with $D_1[n] \cdot \nu_1 \cdot sign(\mu[n])$ \tcp*{ Project spike with \\(\nu_1\\) } + Accumulate \\(p_2\\) with $D_1[n] \cdot \nu_2 $ \tcp*{ Project spike with \\(\nu_2\\) } + } + \; + \ForEach{Sample **n** in window \tcp*{ Training phase } }{ + Update \\(\mu[n]\\) with $ k_1 \cdot sign(W_1[n] - \mu[n])$ \tcp*{ Track mean spike } + Accumulate \\(\nu_{1}[n]\\) with $k_1 \cdot sign(| D_1[n]\cdot g_1 | - \nu_{1}[n])$ \tcp*{ Move \\(\nu_1\\) towards \\(D_1[n]\\) } + Accumulate \\(\nu_{2}[n]\\) with $k_1 \cdot sign( (D_1[n] - \nu_{1}[n] \cdot p_1)\cdot g_2 - \nu_{2}[n])$ \; \tcp*{ Move \\(\nu_2\\) towards \\(D_1[n]-p_1\cdot\nu_1\\) } + Accumulate \\(p_3\\) with $(|D_1[n]| - \nu_{1}[n]\cdot p_1) \cdot \nu_{1}[n]$ \tcp*{ Get gain error } + Accumulate \\(p_4\\) with $(|D_1[n]| - \nu_{2}[n]\cdot p_2) \cdot \nu_{2}[n]$ \tcp*{ Get gain error } + } + Accumulate \\(g_1\\) with $k_1 \cdot sign(p_3)$ \tcp*{ Adjust gain on \\(\nu_1\\) } + Accumulate \\(g_2\\) with $k_1 \cdot sign(p_4)$ \tcp*{ Adjust gain on \\(\nu_2\\) } + + } + \BlankLine + \caption{Recursive variance decomposition} + \label{aglo:T2_PC_l1min} +\end{algorithm} + +Algorithm \ref{aglo:T2_PC_l1min} shows the operation for estimating the first two PCA components. Here \\(D[n]\\) is the new data point off set by the mean spike waveform $\mu [n]$ which allows the long term estimation of aggregate variance. Similarly parameter \\(k_1\\) specifies how the state variables are exponentially averaged over the preceding data points. Because the projection of the first loading vector must be evaluated before the second vector these operations must be sequenced in time or with memory buffers. The evaluation of \\(p_4\\) is strictly for illustrating the iterative method at which other components are evaluated while \\(g_2\\) can also be adjusted to normalize the values of \\(p_2\\) to prevent overflow without needing \\(p_4\\). + +## 36 Template Matching using K-means + + + +Finally we consider the implementation of template matching in channel. This can be seen as simply a K-means clustering method without dimensionality reduction on the input vector. The implication is that it is characteristically more memory intensive but requires less computationally intensive operators. + +\begin{algorithm} + \DontPrintSemicolon + \KwData{Spike window \\(W_1\\)} + \KwResult{Classification with respect to aggregate clusters} + \Begin{ + Accumulate $Spike \: Count$ with \\(1\\) \tcp*{track accumulated statistics} + \ForEach{Sample **n** in window \tcp*{Projection Phase} } { + \ForEach{Template **k** in memory} { + Accumulate \\(p_k\\) with $W_1[n] - T_k[n] $ \tcp*{Get \\(l_1\\) distance for each spike class} + } + } + Find $p_{min}=min{[|p_1|, \: |p_2|, \: |p_3|, \: |p_4|]}$ and Set \\(c\\) to index \tcp*{Find most similar} + \ForEach{Sample **n** in window \tcp*{Training phase} }{ + Accumulate \\(K_c[n]\\) with $k_1 \cdot sign(W_1[n] - T_c[n])$ \tcp*{ Adjust most similar class} + \If{ Not all templates generated **and** $Spike \: Count > k_2$ } { + Duplicate exiting templates \; + Set $Spike \: Count$ to 0 \; + } + } + } + \BlankLine + \caption{Incremental K-Means classification} + \label{algo:T2_Kmean} +\end{algorithm} + +The implementation considered in Algorithm \ref{algo:T2_Kmean} is relatively straightforward where one section evaluates the generation of new templates and the other adjust existing templates with new data. The template approach in general has good noise performance due to the redundancy in correlated features that average out white noise. There is some usually some concern with respect to the convergence of k-means centroids. Typically due the the fact that noisy sample points may be initialized as new clusters and thereby wasting memory. The method used here is iteratively duplicating centroids after convergence. This minimizes the impact of noisy data in the feature space. As illustrated in Figure 54 during each iteration the centroids converge to mean positions. Due to the morphology that these centroids may be in we generally need more centroids than there are clusters but this approach works well when there are few spike classes. The assumption here is that we are clustering features that are characteristically Gaussian mixtures. + +{{< figure src="technical_2/Cdup.pdf" title="Figure 54: Illustration of centroid evolution over several iterations." width="500" >}} + + +## 37 Complexity Evaluation + + + +Generally the application of these methods should reflect a system level objective. For the configuration used here the memory and algorithmic operations are estimated in Table 7. Multiplications are equivalent to eight elementary operations and the memory calls are not considered as a computation but as load/store cycles. The impression made here is that template matching is strictly very efficient if the the memory allows large allocation of active spike waveforms. Similarly RVD could show a considerable reduction in operations if a dedicated multiplier is introduced but that depends on how much we value compactness over execution speed. The disparity in memory requirement will dramatically worsen when the number of centroids is increased which is not the case for the computational complexity in RVD. + +Table 7: Estimation on memory and computational resource requirements for each algorithm. +| **Algorithm** | **Memory** | **Operations** | **cycles per sample** | +|----|----|----|----| +| NEO Peak Detection | 20 Elements | 30 | 56 | +| RVD / training | 63 Elements | 29 / 88 | 57 / 116 | +| Template / training | 85 Elements | 9 / 16 | 27 / 34 | + + +{{< figure src="technical_2/P05.pdf}" width="500" >}} +{{< figure src="technical_2/D05.pdf}" title="Figure 55: RVD and template based classification for data sets with \\(-26 dB\\) background activity." width="500" >}} + + +{{< figure src="technical_2/P01.pdf}" width="500" >}} +{{< figure src="technical_2/D01.pdf}" title="Figure 56: RVD and template based classification for data sets with \\(-20 dB\\) background activity." width="500" >}} + + +{{< figure src="technical_2/P02.pdf}" width="500" >}} +{{< figure src="technical_2/D02.pdf}" title="Figure 57: RVD and Template based classification for data sets with \\(-16 dB\\) background activity." width="500" >}} + + +The empirical results in Figure 56 generally show that in moderate noise conditions our classification accuracy is typically better than $85 %$ which is calculated in terms of the aggregate probability of correct classification multiplied with the probability of missing a spike event. Unsurprisingly RVD is not very effective in noisy conditions where the variance accentuates irrelevant components. The classification accuracy from template matching is also shown in Figure 57. These results should primarily show an improved noise rejection characteristic but more generally this approach is more resilient at dealing with false positives. In principle a new cluster will be assigned to a zero mean template representing the false positives while maintaining the other templates intact. Strictly the detection circuit should be readjusted to favour increased detection of false positives as long as the rate of false negatives remains low. But instead exactly the same parameters are used for every test. + +We should be careful to judge the effectiveness of these implementations particularly with respect to efficiency. While we can generally increase performance by allocating more memory or introducing additional computation we need to quantitatively evaluate the objective. We suggest normalizing the resource allocation with respect to increased information extracted from the signal by classifying. That is how much more processing are we allocating for classification by proportionally increasing the signal to noise ratio of our output. In the optimistic case when the three classes neurons being detected are uncorrelated our base-line accuracy would be \\(33%\\) while needing \\(56\\) cycle of operation for spike detection. In fact this leads us to believe both algorithms in this respect decrease resource efficiency by a factor around \\(2\\) accounting for an increased memory, processing requirement compensated with increased accuracy. While this claim is very sceptical with respect to the motivation for classifying spike events it also reasons the aggressive reduction in algorithmic complexity through approximations presented here. There is genuine benefit in classification that assists the convergence of further processing algorithms. In addition we simply argue that excessive dedication of resources that exceed that needed for signal conditioning may not be worth while. They key point demonstrated here is that these methods appear very much attainable in terms of on-chip processing capacity. Here we considered the case without supervision specifically in consideration for scalability. It is likely that further reductions or optimizations can be made in that regard to the structure of these methods to improve accuracy and noise tolerance. + +# 38 System Architecture + + + +The conceptual architecture of the system proposed here is foremost based on the opportunity for software defined real-time instrumentation that has not yet be exploited in chronic implantable systems at this scale. Currently it is common place to see synthesized logic that performs all processing and data handling procedures in such a way that they have very limited high-level reconfigurability. This is strictly in order to save power and reduce complexity at the system level. It is important to note that for any recording device there are a multitude of phases during its operation where this flexibility can be highly advantageous once sensor characteristics are learned. Like discussed in Section 32 many classification algorithms benefit from training or characterizing the recording conditions. + +The approach to specialized DSP in the literature reflects two problems in this field. The first is signal extraction from recordings that relates to what we have discussed in terms of spike detection to extract compressed spike train data. The other is associated with accelerating adaptive filters that map these spike trains on to estimates for cognitive dynamics or invoked limb movement. Typical examples for spike sorting are fully synthesized cores [^49] [^158] that can be integrated and are capable in achieving respectable processing capacity for specific algorithms. In contrast to spike train decoding that is predominantly performed by FPGAs as integration make less sense for the development high dimensional adaptive filters like [^159] that do not need to be embedded within body. Interestingly the work in [^40] proposes a application specific instruction set processor (ASIP) that similarly argues for high performance computation for these structures with a high degree of flexibility that reflects the different models used for spike encoding. Additionally we see the advantage of using off-chip microcontrollers like MSP430 that interface with a highly reconfigurable instrumentation front-end to leverage both adaptive and involved noise shaping to perform more intricate operations such as seizure detection or artefact removal [^160]. While these works may not be viable for high channel count implantable devices it does highlight the considerations for designing fully integrated prosthetics that is in-line with this work. + +Here we will consider a particular type of microcontroller topology that can support reconfigurable functionality and reflects the fact that although multichannel BMIs are highly parallel in nature the associated processing can also be algorithmically intensive. The feasibility of this notion has been estimated to an extent but many components are subject to implementation. In essence we optimistically approach this design problem with a strategy that exploits both the homogeneity in processing and the information locality in order to realize a feasible solution. This lets us focus on the in-channel operation where efficiency is maximized through the topology of the execution unit. Regardless of the end result this proposed system will be one step towards the goal for more effective chronic neural implants. + +## 39 Distributed System + + + +The system illustrated in Figure 58 represents the distributed microcontroller architecture. The primary mechanism of operation is the program memory that continuously feeds the stored instructions into the pipelined array of processors that operate locally on the recorded data. The execution of these instructions is handled with what is essentially a instruction decoder, memory module and an arithmetic unit that is interfaced with four analogue recording channels. This approach guarantees that the absolute minimum amount of energy is required for the communication of recorded data as the information is processed and consolidated to its elementary component at the quantization interface. + +{{< figure src="technical_2/Sys_sH.pdf" title="Figure 58: Illustration of the proposed distributed \\(\mu\\)C array for homogeneous program execution at the sensor interface." width="500" >}} + + +Inherently this implementation will sacrifice the availability of more intricate functionality found in DSPs since the data is not funnelled into one processing unit that can be very elaborate in complexity. The distributed structure is rationalized by the fact that the intensive operations such as clustering methods operate at a much lower speed due to the sporadic spiking activity that make statistical convergence slow. Furthermore these adaptations need to be performed on the order of minutes by which such functions may also be implemented through the redundancy of elementary operations. Moreover multiplexing loses effectiveness in memory intensive applications as it does mitigate the power & area scaling associated with memory allocation. + +Also consider that the program control that gives this implementation its capability for generic computation does not scale with the number of processing units. This is an important distinction when addressing a hundreds of channels on chip that will allow this implementation to outperform any other architecture and leverage the fully integrated form factor. We also note that whether this architecture is realized by synthesized logic, FPGA fabric, or more custom logic cells is insignificant to the extent that the memory structure plays a more profound role. This claim is based on the algorithms in Section32 that allocate significantly more resources to memory than algorithmic operators. In particular memory density and efficiency is a critical component to the success of this type of large scale sensor system. Here 3-T eDRAM is employed which is more effective than alternative solutions memory solution and can still be realized on a standard CMOS process [^161]. When compared to an SRAM equivalent we find it can readily achieve a factor 8 improvement in density [^162]. + + +{{< figure src="technical_2/NPI_TLT2.pdf" title="Figure 59: System architecture for NPI sensing platform with digital interfaces annotated." width="500" >}} + + +The high-level interfaces are illustrated in Figure 59. There are multiple layers with respect to how internal resources are accessed for reconfiguration. This is primarily for robustness where each layer increases in complexity and chance of failure. The low-speed interface is the simplest element which acquires commands from an external device with very relaxed requirements on input timing. These commands allow us to reconfigure the high level sub-blocks like tuning the generated reference voltages provided by the power management, control reset/power of individual sub-blocks and selecting which digital test signals should be monitored. In particular the processor array and program memory layers almost operate in isolation to the peripherals. These blocks are timed by the internal PLL structure that drives significantly higher data rates that do not need to propagate to the pad level in order to save power. The back-end of the system similarly communicates data uni-directionally between two different clock domains to send data packets off-chip using a number of handshaking protocols. + +The implementation of the analogue circuitry has been discussed in Section 23 where we additionally constrain all algorithms to a maximum of 1024 cycles per sample while maximally allocating \\(128\\) words of memory. With respect to our previous discussion this amount of hardware should allow a large set algorithms that are resource efficient. If not the topology will promote the construction of processing with more aggressive memory efficiency and using feedback dynamics to implement more complex operators such as division. It should be noted that these specifications have flexibility by sampling multiple times per program cycle or reducing the system clock using the configurable phase locked loop in order to reduce power. + +{{< figure src="technical_2/Lay_sH.pdf}" width="500" >}} +{{< figure src="technical_2/Lay_sH.png}" title="Figure 60: Physical implementation of NPI system using a 6-metal $0.18 \mu m$ CMOS process. " width="500" >}} + + +Figure 60 presents the fabricated prototype device. It can be seen that integrating many peripheral blocks such as a phase locked loop, voltage supply regulators, and program memory on chip minimizes the pad count required for the digital and power domains. However even for a 64 channels system the number of analogue pads required for the sensor interface play a significant role on top level organization. In addition careful consideration has to be made with respect to how the digital signals propagate where minimizing track length not only reduces digital noise coupled to the substrate but more significantly the associated power dissipation. The number of processing elements can in fact quite easily be scaled up by extending the instruction pipeline where the system level timing constraint for speed and fanout lies with the program memory which has an internal pipeline that needs to connect the program memory together. + +## 40 Processing Core + + + +In order to allow the hardware to provides generic processing capabilities in a distributed fashion a number of considerations have to be made. In particular we need to reflect the typical operations with certain modalities of operation. It is clear that although all recording channels should execute the same algorithm they will typically not share the same state of operation. This state dependency is exemplified with respect to intermittent processing during bursting neural activity and idling during quiet periods. This is an inherent limitation to sharing the program memory as the dynamic execution of the code where each core has its own program counter or a top level scheduler is not feasible for an arbitrary number of channels. The quasi-out-of-order execution makes it challenging for us to adopt scalable tile structures found in image processing [^105] that excel in maximizing area and power efficiency in a scalable sense. + +Lead by maximizing the locality of data execution [^163] where this aspect of branch control or conditional execution is mediated by skipping a section of the incoming instructions if a condition is not met. The approach of skipping sections of code up on branching is relatively in-efficient with respect to throughput. This approach is optimal at the system level when individual cores may need to execute any section code and branching will only be limited by the dissipation related to the registers pipe-lining the instructions across the chip. + +{{< figure src="technical_2/Sys_uC.pdf" title="Figure 61: Organization of the distributed execution unit detailing components and the interconnect." width="500" >}} + + +The individual components of the execution unit are shown in Figure 61 and details the main data buses used for exchanging data. The majority operations revolve around manipulating data in the registers R1-R16 as A operand in association with any other data sources that can be used as B operand. The operation performed by the arithmetic logic unit (ALU) will always overwrite the result to the location of the A operand but can in extension also be used to to write to other locations (i.e. memory, periphery, etc.). This implies that in terms of instructions there are always two components where the first is simply the operation executed by the ALU in addition to the two memory sources. The second component optionally extends this simple functionality by writing these intermediate values to multiple other locations or arbitrary branching operations that will take the unit out of sleep. + +On that note we mention that the local execution controller consists of three registers that assist in branching operations or conditional execution. When either of these registers have logic one the instruction is gated by a null operation before execution. One of these registers will self reset allowing for if-else functionality by skipping a single instruction. The two other registers need to be cleared actively but in combination this will allow for nested conditioning of up to three levels. While in idle state no internal registers are clocked with the exception of the instruction pipeline and the branch controller saving a significant amount of power as the instruction does not need to be decoded. + +The digital data interface provides the means for communicating data either off chip or to adjacent execution units. This functionality allows granular consolidation of features or signal structure and correlate measurements with system level parameters. For example consider each execution unit is listening to the most informative analogue instrumentation channel, it is conceivable that comparing its spike train with that of an adjacent units to evaluate neural interconnect level features. The Asynchronous data bus on the other hand is a key feature that allows this system to appear as a slave at the network level that does not need to be coherent with the system or off-chip clock. This bus is in essence a large buffer distributed across many channels utilising asynchronous hand-shake protocols to funnel the data to a SPI module that is clocked either externally or internally [^164]. This solves a number of coherence problems that mitigates the need of having a FPGA to drive this system as the SPI module is not timing critical. Furthermore this alleviates clock distribution as the timing constraints are always local to each execution unit and not the data bus that is distributed across the chip which may either be very restricting or power intensive. + +The dynamic control with respect to the analogue channel is enabled by one designated 8 bit register per analogue channel. In this particular case 4 bits are used to specify gain, 2 bits for configuring the biasing current as 0x,1x,2x,3x, and 1 bit of the reset function. In particular the reset phase will temporarily boost the transconductance on the band-limited filtering stage to allow sub-microsecond auto-zero for active noise shaping. For both the ADC and the amplifiers there is one bit that controls a multiplexer at the input that can switch in the sensor or a global differential test net for calibration or verification. Similarly the ADC has 2 bits to select which analogue channel another bit to clock at the full rate or half the rate of ad joint micro-controller. In addition there are 3 bits to control the how the chopper frequency is divided from the sampling signal which is the final control bit. Understandably the analogue configuration will remain static after the appropriately being set. The ADC configuration register is considerably more dynamic as the multiplexer needs to be reconfigured and sampling needs to toggle persistently. + +There are two modes of getting quantized data from the ADC depending on the desired functionality. The first is simply reading the 8 bit quantization register that shadows the 7bits quantized by successive approximation and the LSB from the first integration result. In order to utilize the higher resolution capability the comparator output is used to integrate coefficients from the instruction onto a local register where the comparators will decrement or increment the register accordingly. If no calibration data is locally stored this operation first integrates binary weights on one register during the SAR cycles and then integrates the FIR window onto another register. This is large investment of cycles to perform high resolution quantization but this can be optimized for specific applications when it is necessary. If the calibration data is available for the 7 SAR weights then the ADC must be configured to run at half the system speed and before quantization these weights are loaded from the memory onto registers R2-R7. Followed by the usual process of SAR quantization while these weights as simultaneously also integrated on a second register. Then after the integration phase three registers will contain quantized data. The scaling of coefficients is key and should be such that the $\Sigma \Delta$ result simply copies the sign bit of the SAR operation and can concatenate the lower 7 bits with the SAR result. Then the calibration data is scaled appropriately and added to the 14bit signed double with carry logic. Clearly there a number of conventions suggested here that will best exploit the capabilities of the design. + +The memory module local to each execution unit hold 128 words of data which can be shared across the analogue channels with 32 locations each. Particularly when the DSP is mainly performing filtering the recorded data can be buffered for FIR filtering or keep its high precision filter state variables for IIR structures. These filter and program coefficients are stored in the shared program memory such that the execution unit does not experience an overhead in memory requirement. However for other memory intensive algorithms such as template matching, serving the most informative of the four analogue channels will have to suffice because the memory requirement is beyond the capabilities of this configuration. The DRAM architecture has a refresh-up-on-read mechanism which implies that the used memory locations will have to systematically be read to keep the data stored valid. Fortunately this requirement is self fulfilling as the program recycles itself every $100 \mu s$ and the DRAM retention time is on the order of $1 m s$ implying that as long as there is a guaranteed read on the memory location it will stay valid. The physical read mechanism however does require a minimum of two cycles. The first is in the background which simply prepares the internal registers of the module while a different execution is taking place and the second is in the foreground where the location is read and the data bus is driven by the DRAM. + +{{< figure src="./technical_2/Lay_uC.pdf}" width="500" >}} +{{< figure src="./technical_2/uCm.png}" title="Figure 62: Physical implementation of execution unit using a 6-metal $0.18 \mu m$ CMOS process " width="500" >}} + + +As the illustration in Figure 62 shows, keeping the 8 bit structure in terms of parallel operations maintains a very compact floor plan. This is typical of data flow intensive designs where the digital logic should be placed underneath the associated data buses. This is difficult to replicate by automated synthesis tool where signal congestion is the most stringent aspect. The digital signals for the two operands and the data line span horizontally where sub-blocks extensively take advantage of the gated output buffers for each sub-block that is controlled by the decoders. The full custom approach taken here sacrifices design effort for additional performance in terms of reduced parasitics and more aggressive power gating. + +$$ \mbox{\textbf{\textless C\textgreater,[\textless CE\textgreater],\textless A\textgreater,\textless B\textgreater,[\textless OE\textgreater*]}} $$ + +The syntax for constructing instructions needs to be in the Backus Normal Form [^165] as formatted in Equation35 with reference to Table 8 which summarises all possible compositions. A parser is implemented that will translate an ordered set of these instructions directly into hardware specific machine code that needs to fed into the instruction pipeline any violations or exceptions will be caught by this script automatically. Although there is no dedicated multiplication hardware there are specialized registers that allow shift add based multiplication over eight cycles. Any other primitive logical or arithmetic function can be realized with this instruction set as it is turning-complete. This assertion is made by noting that it can evaluate the operation; subtract and branch if less than or equal to zero, which is sufficient for a one instruction set computer [^166]. + +Table 8: Overview of instruction sub-components. +| **Index** | **Operation Subset** | **Summary of Possible Entries** | +|----|----|----| +| C | Logic Operation: | Logical Shift Left/Right, Arithmetic Shift Left/Right, XOR, XNOR, AND, OR, MOVE-A, MOVE-B | +| C | Arith. Operation: | Compare, Add, Carry Add, Multiply, Complete Multiply | +| CE | Compare Option: | \textgreater, =, \textless, Overflow | +| CE | Add Option: | Subtract, Absolute Value, Increment Overflow Bit | +| CE | Mov Option: | Mem. Address is from Data line. Default is from Instruction | +| A | Operand A: | R1-R8, R9-R13, ID, Count, Memory | +| B | Operand B: | R1-R8, Left uC, Right uC, Instruction, ADC, Memory, Null | +| OE | IO Extension: | Write to Left uC, Write to Right uC, ADC Sample enable, Write Output Buffer | +| OE | Branch Extension: | Write to Branch Register BR1-BR3, Invert Branch Result | +| OE | Memory Extension: | Write Address, Write Data, Read Data | + + +It should be mentioned that there a number of hardware specific details with respect to how certain instructions behave that need careful consideration towards the implementation details. For example if no comparison is made but a branch register is accessed the output of the comparator will be treated as false no matter what logic the overflow bit is. This allows us to clear or set branch registers while simultaneously performing an operation. Another example is that by default the instruction data is ready at the input of the memory address to prepare a read in the background. In most cases it is intuitive and we simply strive to maximize the cycle efficiency. At all times the execution unit is capable of dealing with the compute aspects while performing branching and memory access simultaneously. + +This work also provides an elaborate set of test tools that allows compilation of instruction code and the generation of piece-wise-linear 'csv' files for test sources that can be used in the circuit simulators. This can be used in association with the transistor or verilog implementation of the processing core. The behavioural models in particular are important for the translation of this architecture to other implementations. + +{{< figure src="./technical_2/uC_PS.pdf" title="Figure 63: Power dissipation with respect to specific operations for the same operand A=113 & B=114 in randomized order." width="500" >}} + + +The results in Figure 63 exemplifies the dependency of power dissipation with respect to different operators for the same operand A and B. It should be expected that the is a strong operand dependency with respect to power consumption but these results follow our expectations closely. Generally the simpler the operation the lower the current dissipation is because less complexity is involved with the switching losses. Here again we observe that when the unit is in a sleep or branching state the power dissipation is mainly associated with the instruction pipeline. As this 32bit pipeline transverses the entire execution unite it plays a significant contribution towards the baseline power consumption. The typical power consumption for full activity will lie around $45 \mu A$ it should be noted that sporadic spiking activity will gate the majority of operations and it is likely that running at half the designed rate with 512 cycles is more than sufficient. Note the typical figure of power is \\(2.7 pJ/Cycle\\) or $2.7 \mu W/MIPS$ which is several orders of magnitude better than 16-bit microcontrollers such as the MSP-430[^167]. + + +Table 9: Summary of performance specifications for the NPI system and state-of-the-art specialized integrated processing architectures. \\(^\star\\) Reconfigurable topology. +| Parameter | Unit | This Work | Markovic [^168] | Arimoto [^105]| +|----|----|----|----|----| +| Architecture | | Distributed (\mu)C Array | Multi-Grain FPGA | Dedicated Tile Array| +| Technology | [nm] | 180 | 40 | 65 | +| Supply Voltage | [V] | (1.2) | (1) | (1.2)| +| Parallel Units | | (64) | (16^\star) | (2048)| +| Instruction Size | [bits] | (32) | - | (32) | +| Operational Frequency | [MHz] | (20) | (400) | (300) | +| Sampling Frequency | [S/s] | (32k) | (100M) | - | +| Operations per Sample | [Cycles] | $256 $ | (4) | - | +| (P_{Digital}) per Channel | [(\mu)A] | (44) | - | -| +| (P_{Analogue}) per Channel | [(\mu)A] | (16) | - | - | +| System Power | [mA] | (1.42) | $ 11.6 $ | (300)| +| Program Memory Capacity | [kb] | (32) | - | - | +| Processor Memory Capacity | [kb] | (1) | (36) | (1) | +| Processor Array Area | [mm(^2)] | $1.04 \times 1.32$ | $3.8 \times 5.4$ | $1.60 \times 3.19$ | +| Power Efficiency | [GOPS/mW] | (1.52) | $ 0.86 $ | (0.31) | +| Area Efficiency | [GOPS/mm(^2)] | (0.88) | $ 2.34$ | (36.1)| + + +The specifications given in Table 9 summarize the main features associated with this system on chip for processing neural data at the sensor interface. As the total power consumption is on the order of \\(1.5 mW\\) there is some concern with respect to the power density associated with the system in full operation that in this particular case is \\(26 mW/cm^2\\). In fact if the number of channels is scaled up beyond 64 channels this power density will tend to \\(29 mW/cm^2\\) but will not exceed it. Either figure will likely be smaller subject to the physical & software implementations but more importantly will not result in a thermal agitation or the heating of cortical tissue that exceeds \\(2^{\circ}C\\) [^68]. More generally we have the advantage of tuning processing capabilities to the heat-capacity of the implanted package. In fact comparing this work to state of the art FPGA topologies[^168] and highly parallel ASIC structures[^105] that follow the same design methodology we find that power and area efficiency that exceeds that of stand-alone microprocessors by orders of magnitude. These figures also reflect the expectation that technology scaling should lead to even more compact configurations. In addition Gate leakage may introduces some diminishing returns with respect to power efficiency. We mention that these figures are extrapolated based on the performance of a single execution unit and we expect more overhead from other components that is not accounted for in this comparison. + +$$ R_{D} = \frac{P_{\mu C} \cdot A_{\mu C}}{N^{2}_{chan} \cdot Cycles} = \frac{44 \mu W \cdot 196 \times 158 \mu m^2} {4^2 \cdot 256}\approx 3.3 \cdot 10^{-16} \: \left[W mm^2 \: per \: OP \right] $$ + +Re-evaluating our power/area figure of merit in Figure 49 with Equation 36 we observe that practically we lose a factor of ten in efficiency when compared to a dedicated ASIC implementation because resource utilization inside the execution unit can not be maximized. This was expected given that instead we attain high-level reconfigurability. However this does achieve a very good understanding with regard to where the system scales from this point both with respect to area and power requirements. + +## 41 Testing Platform + + + +As this system is directed at generic use for the neuroscience community where high level programming and interfaces are essential for end user adoption. The testing platform presented here is aligned in such a fashion that its fundamental components can be extended upon greatly to serve a multitude of needs. This ambitious design criteria is primarily provided by the real-time platform illustrated in Figure 64 that supports a standard Linux operating system. The thee components compromise of the custom NPI system on chip, the Raspberry Pi platform, and networked resources. + +{{< figure src="technical_2/Sys_iP.pdf" title="Figure 64: Block diagram of the instrumentation platform developed as framework for real-time applications." width="500" >}} + + +The software stack running on the Raspberry Pi primarily handles the high speed SPI link that fetches data from the NPI system at \\(10 Mb/s\\) and stores it to a local buffer for some of the data visualization. This data stream is then forwarded to a network routine that is connected to a server over the local area network via a UDP protocol to allow large quantities of data to be stored in a scalable fashion. The graphical user interface is built on top of this process in order to give a means to both configure the device actively and provide some form of interactive interrogation with respect to the recorded data and the algorithm being executed. + +The application of a generic internet of things platform plays a important role with respect to long term development objectives. It signifies that the ASIC is there to provide a specialized interface with the sensor and a generic digital interface with the external control to allow rapid adoption of new techniques or other components as software extensions. This substantiates the modular approach where design effort is explicitly focused towards specialized hardware for the sensor and software development at the system level. This is important given the complexity of these systems where overspecialisation limits the versatility of existing designs thereby limiting the utility of other commercially available tools/devices. + +The advantage here is that a multitude of procedures can be run on the real-time platform without supervision that are detailed in high-level programming code that have fast development and turn-around capabilities. In this case it significantly improved test procedures by enabling automated exhaustive characterization of logical integrity. In fact the standalone module of the microcontroller structure can run 1 MIPS of on the fly randomly generated operations. This can be seen in Figure 65 where the Saleae logic analyser is used to probe the internal data bus of one particular core. + +{{< figure src="technical_2/Scope.png" title="Figure 65: Digital waveform of the internal data bus BIT 1-8 as new instructions are being loaded into the device using the clocked Latch and Configure signals." width="500" >}} + + +Table 10: Section of Instructions and recorded outputs from $\mu C$ structure with the associated machine code. +| **BITLINE**| **INSTRUCTION** | **Machine Code** | +|----|----|----| +| 00011010 | MOVB R5 DINST 26 |0011111100000000011000000011010| +| 11101111 | MOVA R3 DINST -17 |0011011000000000011010011101111| +| 00001010 | AND R5 R3 |1110111100000000000000000000000| +| 00011010 | MOVB R5 DINST 26 |0011111100000000011000000011010| +| 11101111 | MOVA R3 DINST -17 |0011011000000000011010011101111| +| 11111111 | OR R5 R3 |1110111100000000000010000000000| +| 00011010 | MOVB R5 DINST 26 |0011111100000000011000000011010| +| 11101111 | MOVA R3 DINST -17 |0011011000000000011010011101111| +| 11110101 | XOR R5 R3 |1110111100000000000100000000000| + + +This is partly shown in Table 10 where the internal bit-line of one such execution unit could be directly accessed. Because it is not viable for us to exhaustively simulate the hardware in various conditions we use a physical test bench in order to record the performance tolerance with respect to voltage supply and operating frequency. Moreover what the user sees is reduced to latent frames of data over several milliseconds and the corresponding instruction code executed by the platform. The physical interfacing protocols are very much transparent. By construction each core has a hard wired ID that will allow the active supervision of internal variables for development and debugging of single units. Due to the specialized hardware the instrumentation programs currently still require careful tailoring of the instruction code but this can be extended towards compiling directly from C++ code that is also used to construct the rest of the platform. + +{{< figure src="technical_2/TPlat.pdf" title="Figure 66: Graphical user interface used for configuring the NPI system showing test data." width="500" >}} + + +Figure 66 depicts the GPU accelerated graphical set-up used for testing the device where the functionality is mainly associated with reconfiguration and powering different system sub-blocks for validation. From a engineering point of view it is more of a convenience to have automated reconfiguration of the device as one interacts with the various settings. Particularly in associated with probing the supply voltages or analogue reference signals generated on chip. It would be more typical that during experimentation this functionality can be reduced to simply selecting from a set of predetermined programs. + +{{< figure src="technical_2/TPhw.pdf" title="Figure 67: Test bed used for characterization with various components illustrated." width="500" >}} + + +In order to move towards fully isolated operation which will be the case for a implanted device the system on chip architecture relies on a minimum amount of off-chip components in order to bring the resource requirements of the topology into scope. This is shown in Figure 67. These feasibility considerations are generally with respect to reasonable assumptions associated with a wireless implant that is hermetically sealed. In this particular case we will allow a number of off-chip decoupling capacitors, a reference resistor and a reference voltage which may very well be integrated on chip in one way or another if necessary. The system also uses a \\(1 MHz\\) external clock reference which may be realized at the wireless power carrier frequency and is locked onto with a phase locked loop to generate the internal \\(20 MHz\\) system clock. Three linear LDOs were integrated to provide a \\(1.2 V\\) supply to the digital,analogue, and memory separately. Where the analogue supply voltage used to derive internal ADC voltages references of \\(1.2 V,0.9 V,0.6 V,0.3 V\\) from the unregulated supply using high speed buffers. + +# 42 Conclusion + +This chapter substantiates a scalable and long-term approach for the development of programmable neural interfaces. In particular we discuss why moving away from the fixed purpose DSP architectures seen in many conventional systems is of significance with respect to performance and reliability. In addition we provide indicators that show the majority of modern CMOS technologies using dedicated on-chip processing hardware is viable to perform local signal analysis. Furthermore we highlight the importance of efficient algorithm construction were operators should revolve around execution per sample and processing structures that improve scalability for systems with many recording channels in association with the near-data-processing paradigm. PCA & template maching methods are proposed for embedded systems that require 57 operations per sample and 680 bits of memory with entirely unsupervised operation that can achieve over 80% accuracy during spike detection & classification. + +A distributed micro-controller structure is proposed in effort to realize these characteristics and reveal underlying constraints. The topology reflects the nature of processing neural data in the context of achieving generic computational capacity. This discussion details both low-level and system level considerations that address the software stack. The impact of memory requirement that results from being able to execute arbitrary algorithms in isolation is evident both in-channel and chip level. In the proposed configuration the amount of resources allocated for this function is comparable to that of the signal processing but depends very much on the number of channels that are integrated together. We point out that if the number of channels is increased this component does not change and allows this topology to become more effective. The distributed processing architecture operates with an efficiency of 1.52 GOPS/mW and each core only requires a 0.02mm\\(^2\\) silicon foot print with fully reconfigurable 8 bit processing capabilities. + +The foregoing discussion has depicted the intricate complexity associated with these sensing systems and revealed the diversity of aspects that should be taken into consideration. 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[Online]: http://www.darpa.mil/program/unconventional-processing-of-signals-for-intelligent-data-exploitation diff --git a/content/publications/2016/brain-machine-interfaces-neural-recording-time-domain-techniques.md b/content/publications/2016/brain-machine-interfaces-neural-recording-time-domain-techniques.md new file mode 100644 index 0000000..423c429 --- /dev/null +++ b/content/publications/2016/brain-machine-interfaces-neural-recording-time-domain-techniques.md @@ -0,0 +1,561 @@ +--- +title: "Brain machine interfaces: Time Domain Techniques" +date: 2016-08-08T15:26:46+01:00 +draft: false +toc: true +math: true +type: posts +tags: + - chapter + - thesis + - CMOS + - biomedical +--- + +Lieuwe B. Leene, Yan Liu, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 43 Time Domain Techniques + +Thus far our work has detailed numerous design techniques that extend on contemporary work where the classical analogue approach with digital processing has demonstrated its capabilities. However we have also analytically shown that although we can still strive to improve area and efficiency, there are a number of factors that prevent making significant progress in terms of improving system characteristics. Moreover there is a strict need for more efficient computational processing that appears overwhelming if it is made robust and adaptive. If we keep the current processing methodology this component can only be made viable with smaller technologies and voltage scaling that can substantially diminish the performance of analogue operations. Here we will attempt to address the two factors that have the most significant impact on improving sensing electronics based on the observations made in the foregoing discussions to consolidate this work. The first is introducing all-digital instrumentation that is not diminished by technology related scaling and the characteristics of nano-meter transistors. The second objective is developing a mixed signal topology for analogue to information conversion where feature extraction is performed adaptively in the analogue domain. + +This chapter will focus on exploring the emerging time domain processing modality in order leverage increased digital performance associated with modern CMOS processes. In fact this motivation is carefully addressed in the literature[^169] where logic-gate based topologies demonstrate better scalability with respect to linearity and bandwidth. Here we will demonstrate how the fundamental limits of noise efficiency can be approached by proposing several topologies and design techniques. Further we will elaborate on the characteristic relations between analogue performance and resource requirements that enable these structures. The organization of this chapter is as follows. Section 44 will introduce the essential design considerations for continuous time-domain circuits by considering the phase characteristics of oscillators in relation to driving transistors that are used for analogue feedback. This structure will be used to implement both amplifying and filtering structures to compose the instrumentation front end. This is followed by Section 48 where we propose a mixed signal topology for analogue domain classification. + +# 44 Principles for time domain processing + +There are two driving factors to approaching time domain concepts where signals are represented in terms of delays between pulse edges or phase components in oscillators. The first benifit is the inherent digital operation where continuous valued signals are represented by digital events with respect to a global or local reference [^170]. This implies that the typical analogue processing has the same power scaling and advantages as the digital processing in terms of technology parameters. This allows oscillator structures to approach very efficient operation irrespective of the oscillation frequency or supply voltage [^171]. The second is that many operations are not restrained by non-linearity from individual transistors giving way to ideal integrators and other operators [^172]. The overall result is that even with limited power budgets the topologies have an overwhelming excess in bandwidth where performance can scale with digital gate delay or its switching energy. The abundance of digital operations for such systems allows these topologies have the potential for digital synthesis using standard cells and a digital design flow to directly process analogue signals [^173]. Moreover event based representation of continuous valued signals allows for often a surprisingly efficient implementation with reduced complexity for a variety of elementary operations. For example [^174] presents a clock-less PVT invariant true random number generator based on the collapse of a ring oscillator structure. + +{{< figure src="technical_3/BW-VDD.pdf}}" width="500" >}} + +{{< figure src="technical_3/mLP.pdf}}" title="Figure 68: Voltage supply relationship with respect to the bandwidth and linearity requirements with respect to different technologies " width="500" >}} + + +Let us elaborate on the notion of scaling analogue with digital characteristics quantitatively. Figure 68 illustrates the drawback of conventional analogue techniques from first principles by looking more closely at the voltage scaling characteristics. Here transitioning to nanometre technologies gives us the capability of reducing our voltage supply because the desired bandwidth can be achieved with a smaller inversion coefficient or equivalent gate voltage. However the transconductance and consequently linearity and noise efficiency can degrade as the drain voltage is reduced. This dependency is because transistor gain requires a large channel resistance which is a function of \\((1-e^{-V_{DS}/U_T})\\) in addition to any DIBL which introduce a asymptotic limit where the former is in fact not process dependent [^176]. This limits the output swing \\(V_{max}\\) with a overhead that is \\(5 U_T\\) [^119]. Figure 68 b) demonstrates the resulting the class-A power efficiency measured as \\(V_{max}/V_{DD}\\) to reflect how efficiently we can use the provided voltage supply. This is evaluated in terms of \\(P_{out}/P_{vdd}\\) where \\(P_{out}\\) and \\(P_{vdd}\\) are the output signal power and the power dissipated by the voltage supply respectively. We can conclude that conventional low noise amplification structures can no longer benefit from technology scaling unless we adopt topologies that do not rely on amplification in the voltage domain. Because the input referred noise of a circuit relies only on its current dissipation scaling supply voltages remains a viable means to reduce power if time-domain structures can mitigate the need for voltage gain. + +## 45 Sub-threshold Ring Oscillators + +The understanding and the interpretation of principle elements for a given modality has the most influential impact on how well it can be utilised. Moreover encoding signals in the time domain will influence how flexibly certain objectives are approached either using digital operations or analogue feedback. Here we will review some basic understanding for ring oscillator structures that are biased in weak inversion. This component will provide a fundamental basis for the topologies proposed here because it connects analogue signals at the input to phase and time domain signals at its output. The interest here specifically lies with using current controlled oscillators that have a well defined linear relationship associated with any injected charge and the resulting shift in output phase. This will lead to the small signal transfer function that relates to the biasing current of the oscillator. Moreover we must be able to evaluate the different components of phase noise and refer it back to the input of transconductive element because we will apply this structure to instrumentation. + +$$ V_{out} (t) = A(t) \cdot f\left[ \omega_0 t + \phi(t) \right] $$ + +A generalized time dependent model for an oscillator is represented by Equation 37 where \\(A\\) and \\(\phi\\) represent the amplitude and phase state variables of the system. \\(f\\) describes the limit cycle of the oscillator over time that maps the steady state output voltage \\(V_{out}\\) as function of phase. The challenge for sub-threshold current biased ring oscillators is that the non-linearity in \\(f\\) is difficult to analytically predict without well informed priori. This is of significance as it will determine how noise sources perturb coupled to the output phase state. + +{{< figure src="technical_3/impulse.png" title="Figure 69: " width="500" >}} + +Many principle aspects of phase dependencies in oscillators have been well described in a generalized form using numerical methods [^178] and by approximation [^177]. The underlying characteristics however are illustrated in Figure 69 where charge perturbations integrate on to the phase of state the oscillator with respect to the impulse sensitivity function (ISF) \\(\Gamma(x)\\). This factor is a cyclo stationary function that describes how the coupling changes as a function of the phase state \\(\phi\\) subject to the source of perturbation. Moreover this allows us to predict the accumulated phase noise due to a time varying process according to Equation 38. + +$$ \phi (t) = \int_{-\infty}^{\infty} h_{\phi}(t,\tau) i(\tau) \: d\tau = \int_{-\infty}^{t} \Gamma(\omega_0 \tau) i(\tau) \: d\tau $$ + +The integral dependency on accumulated phase is what leads to the infinite open loop gain for oscillator based amplifiers. This also implies that any white noise source that is incoherent with the oscillator fundamental frequency will translate to the output phase as \\(\Gamma_{rms}\\). This depends on the assertion that incoherence implies uncorrelated which is subject to the beat frequencies of the two sources. In practical cases this is a fair approximation not only because the oscillator frequency drifts freely but also because we explicitly consider closed loop implementations that aggressively shape in band perturbations. The utility of Equation 38 lies with its ability to predict the single-side band output noise spectrum due to a white noise current source with spectral density $i_n^2 / \Delta f$ with carrier off-set frequency \\(f_{off}\\) according to Equation 39 [^179]. + +$$ L(f_{off}) = \left( \frac{\Gamma_{rms}}{2\pi f_{off}} \right)^2 \cdot \frac{i_n^2 / \Delta f}{2} $$ + +The \\(N\\) stage ring oscillator structure of interest is illustrated in Figure 70. Opposed to voltage controlled structures this configuration is current biased and the oscillating ring is isolated from the supplies. Here the oscillating frequency in sub-threshold operation can be approximated as $f_0 = I_B / (N C_{gate} V_{RS})$ where \\(I_B\\) is the biasing current and \\(C_{gate}\\) is the input capacitance of the delay element. \\(V_{RS}\\) is the voltage across the oscillating structure and is evaluated using Equation 40 where \\(V_{th}\\) is the transistor threshold voltage. In this case \\(M_2\\) provides a biasing current from the PMOS side and \\(M_1\\) if designed appropriately will allow isolation from the ground supply. This is particularly useful in differential configurations where capacitance on a common \\(V_R\\) or \\(V_S\\) can minimize high frequency noise from coupling directly to the differential phase component through the common mode feedback. + +$$ V_{RS} = V_{th} + \eta U_T \ln \left( \frac{2 I_B}{2\eta U_T^2 \mu C_{ox}} \frac{L}{W} \right) $$% + +{{< figure src="technical_3/schematic_RO.pdf" title="Figure 70: Schematic of current regulated ring oscillator with capacitively couple noise source. " width="500" >}} + +The defining characteristic of the current biased oscillator is that the conduction of the NMOS and PMOS devices in each delay element is strictly non-overlapping. This is different when compared to oscillators biased in strong inversion and implies maximum current efficiency in a large signal sense. In addition it leads to the respective NMOS and PMOS ISF being non-negative. Thus the focus should lie with optimizing its rms value by balancing pull-up pull-down conductance. In fact we can empirically demonstrate that despite the intricacies of non-linear phenomena a current starved ring oscillator presents a significantly superior noise excess factor when compared to that of a transistor biased with the same weak inversion conditions due to change being retained in the high impedance nodes. + +{{< figure src="technical_3/state_variables.pdf}" width="500" >}} + +{{< figure src="technical_3/ISF_bias_nmos_pmos.pdf}" title="Figure 71: Simulation results outlining the dependency of parameter dynamics as a function of oscillator phase" width="500" >}} + +Figure 71 exemplifies the challenge of being able to predict internal parameter dependency analytically. Specifically in \textbf{a)} where the NMOS and PMOS of a single delay slice is evaluated both the saturation and linear conduction phases contribute towards accumulated phase noise. It is indicative to note that the bias transistor has a near uniform ISF equal to \\(2\pi/q_{max}\\) independent of phase state as expected from the linear phase to charge relation. Here \\(q_{max}\\) simply represents the total charge dissipated by the ring oscilator each cycle which is \\(2N V_{RS} C_{gate}\\). In particular this phase independent sensitivity is surprisingly independent of oscillator configuration in terms of number of stages and delay cell input capacitance. Instead the characteristic relies on the capacitance and channel resistance seen at the drain of M2 such that increasing impedance improves linearity. + +When the aggregate contribution of all delay elements is taken into account as well as the increased noise excess factor in the linear region the ISF in \textbf{b)} appears predictable when normalized to that of M2. One may expect that the aggregate ISF of the ring oscillator to exceed the sensitivity to that of M2 as its contribution should have a similar profile and more noisy elements are involved. However the soft-switching of each delay element filters out a significant component of injected noise in addition to the fact that the nodes \\(V_R\\) and \\(V_S\\) retain accumulated current noise that feedback on the following stage. + +Insight to optimizing the oscillator consideration is drawn from considering the lossy integration phases on \\(V_X\\). Specifically as the transistors M1 and M2 present high impedance when considering the injection of charge or integration of a noisy current. We can infer that resulting voltage fluctuations are either one of two cases; coupled to \\(V_R\\) or \\(V_S\\) through a transistor in the linear region, or coupled to the switching capacitance during a transition. Rejection of the former will rely on increasing \\(q_{max}\\) and minimizing coupling factors as the ISF is equivalent to that of the bias current. + +{{< figure src="technical_3/ISF_M2_compensate.pdf}" width="500" >}} + +{{< figure src="technical_3/ISF_M2_injct.pdf}" title="Figure 72: The compensation effect of M1 on the ISF for capacitively couple noise sources with reference to Figure 70" width="500" >}} + +It is well known that the dominant factor of noise in ring oscillators comes from supply variations that are capacitively coupled as illustrated in Figure 70. This represents the coupling expected from substrate noise and supply noise that is not generated by the transistors them selves. The impact of introducing M1 opposed to grounding \\(V_T\\) is shown by Figure 72 with a dramatic improvement in ISF characteristics. Moreover large drain resistance of M1 allows the peak to peak ISF to be adjusted by exploiting the dynamics previously discussed. On that note it is important to realize that unlike Gm-C differential implementations the rejection of common mode signals is not present due to the coupling dependency of on phase. The matching/minimization of these factors can still allow a considerable improvement towards performance in practice but the process of optimization is challenging due to the fact that these components can not be well predicted as a priori. More generally incoherent perturbations in differential implementations will scale with \\((\Gamma_{rms}-\Gamma_{dc})^2\\). + +It may be obvious that there no high impedance analogue nodes in this configuration that could introduce undesirable poles. But more importantly we do not need to provide extra voltage headroom or a second gain stage to let our output signal vary with maximum amplitude. In this case the oscillator mostly reuses the VSR voltage headroom. This raises an interesting question; what limits the required voltage headroom for this circuit? Typically the complementary structure necessitates that the source drain voltage of the current bias transistors and differential pairs is sufficient to provide good channel resistance. However there is another component with regard to the noise generated by the oscillator that should be considered in terms of the oscillator voltage overhead VRS. This leads us to evaluate the dependency on sampling noise with respect to the loading capacitor of each delay cell. Considering that the scaling the technology can result in a higher oscillator frequencies and equivalently using a small loading capacitance for the same power budget. It is important to realize that it is a charge induced as sampling noise on each capacitor before each up/down transition as residue from the previous cycle. This sampling noise can be referred to the input of M2 which leads to the expression in Equation 41. + +$$ v^2_{smp} = \frac{1}{Gm^2_{M2}} \cdot \underbrace{2N f^2_{osc} kT C_{gate}}_{Noise \: power} $$ + +As Equation 41 suggests this noisy charge injection occurs for every transition in a delay element which is \\(2N\\) times per period. When we expand this expression in terms of the oscillator power dissipation we can show its underlying dependency in Equation 42. + +$$ v^2_{smp} = \frac{4kT}{P_{osc}} \cdot \left( \eta U_T \right)^2 $$ + +Now it should be clear from Equation 42 that this contribution only depends on the total power dissipation of the oscillator \\(P_{osc}\\). This profound result confirms that without considering band-limiting factors all transistor generated noise densities are in fact independent of the frequency or total capacitance when referred to the gate of the biasing transistor. Following our expectation is that the dominant factor for noise is the total biasing current of the structure which is fundamentally identical to that of an conventional amplifier. + +## 46 Time Domain Sensor interface + +A principle element to these systems is associated with achieving effective conversion from continuous analogue signals to time encoded binary signals without distortion or excess signal corruption. It is typical to see the removal of VCO non-linearity though LMS post-processing[^180] however this level of in-channel DSP can also be avoided through feedback utilizing the linearity of passive components. Our endeavour here lies with applying the discussion and topology selection in Section 23 to VCO based structures that follow closely to our optimization methodology. We suggest thinking of the oscillator's phase as an analogue memory that represents the state variable of the system which we can freely adjust by injecting charge. + +This approach is different from that currently seen in the literature for time-domain based instrumentation of low frequency signals. The time domain encoding concept is predominantly used in asynchronous ADCs that aim to avoid quantization noise from being introduced [^181][^182]. There is some motivation here to approach a neuromorphic amplifier topology that generates tokens with time-domain events that encode the input signal intensity [^183]. Many of these structures leverage signal dependent power dissipation that reduces as the input signal varies more slowly. However they are typically open-loop topologies to avoid a complicated feedback DAC where events are generated upon asynchronous level crossings that reset internal integration nodes or toggle the reference voltages. Linearity and dynamic range can become difficult to achieve while maintaining aggressive power efficiency because resetting integrators or changing references are large signal discontinuities. + +{{< figure src="technical_3/LNTI.pdf}" width="500" >}} + +{{< figure src="technical_3/TDFB.pdf}" title="Figure 73: Time domain instrumentation topology for low noise voltage to time-domain conversion." width="500" >}} + +The proposed implementation shown in Figure 73. This structure opts for a direct conversion of analogue to phase domain signals by relying on the integration to filter out oscillator harmonics present in the feedback signal. Abstractly the topology is seen as a ideal integrator with integration factor \\(\frac{Gm}{q_{max}}\\) proceeded with a non-linear element that introduces spurs around N times the oscillator frequency when feeding back. Here N is the number of taps in the ring oscillator used to simultaneously evaluate the phase difference of the differential structure. This allows us to freely adjust N for improving \\(\Gamma\\) through increasing \\(q_{max}\\) without sacrificing the ability to suppress the harmonics. Since the signals at the output of the phase frequency detector represent the phase difference between the two oscillators is full scale. The capacitive network need to scale down by a relatively large factor to assure \\(V_{x}\\) does not exceed the linear range of the transconductor and is implemented using a capacitance area reduction technique [^184]. When the closed loop gain is large however this concern can be dismissed since the quantization levels scale with $\frac{V_{DD}}{A_{cl} N}$ which will typically be the same order of magnitude as the input signal. + +While we are free to adjust the transconductance for noise requirements there is a limitation to the increase the complexity resulting from the capacitive feedback DAC and parallel digital phase processing. Because digital power dissipation scales with $N f_{osc}$ which is bounded by \\(I_B\\) it is independent of \\(N\\) for a fixed capacitive load in the oscillator delay cell. In fact increasing \\(N\\) reduces the total power of the oscillator harmonics as we effectively increase the number of quantization levels. This can be seen at the output of the capacitive DAC but this aspect will not be evident with respect to the processing performed in the time domain. + +Note that when using ring oscillators with large number of stages in order to reduce leakage and non-linearities in the limit cycle to some extent we can retain a small factor of \\(N\\) by sub-sampling the output taps of the structure. This does require an integer ratio between the total number of stages and \\(N\\) in order to position the harmonics beyond \\(N f_{osc}\\). Also consider that relation between the phases of the oscillator will imply a specific frequency shaping and harmonic modulation at high frequencies [^185]. + +The primary design criteria for the phase detector structure and it respective time domain encoding should be related to maximizing power-bandwidth efficiency of digital cells. This is because the time-domain characteristics of the detector could introduce a inverse relation with regard to signal level and required logic gate bandwidth. Using conventional \\(1.5 b\\) encoding with up/down signals for example would give rise to this unwanted discontinuity. This is because the encoding scheme will generate narrower pulses for smaller signals that require exceedingly more bandwidth to process and feed into the time domain memory. It is conceivable that if this bandwidth is insufficient a dead-zone is introduced that is characteristically similar to class-B amplifiers. + +Using a single bit representation that results from a XOR phase detector inverts this problem such that for small error the minimum bandwidth is required that successively increases as the loop error increases. In extension any asymmetric switching & delays in driving the capacitive feedback that is expected from process variation exacerbates any capacitive mismatch in the different phases of the feedback additively. These components primarily excite distortion on the output depending on the ratio of gate delay to oscillation period. Here Chopping the input will remove off-set and mismatch related components to a certain extent by up modulating them. + +The motivation for using the single stage structure or allocating all the gain to the first stage is also associated with how the supply noise couples to the signal. In this respect we suggest that this structure should be thought of equivalent to that of a ADC. Particularly with respect to the digital feedback where providing asymmetric feedback implies that supply noise coupling can not be cancelled out. In addition capacitive mismatch between the positive and negative branches will also contribute to supply noise coupling. As since supply noise sources couple to the output of the amplifier while providing the maximum closed loop gain minimizes the input referred component. It should be noted that this type of supply sensitivity and capacitive mismatch is equivalent to that found in analogue to digital converters hence this drawback is only with reference to an all analogue solution. Further more once our signal has been encoded in the time domain which we expect to exhibit improved resilience to supply noise because its influence is proportional to the gate delay of the technology used. + +{{< figure src="technical_3/schematic_TDI.pdf}" width="500" >}} + +{{< figure src="technical_3/schematic_PR.pdf}" title="Figure 74: Transistor level implementation of the phase domain integrator structure with phase detector feedback." width="500" >}} + +The schematic implementation of the VCO is show in Figure 74 which is derived from the complementary amplifier structure used in prior work. The fact that both ring oscillators are isolated from the supplies and floating in the middle of the rails presents an improved ISF as well as assuring the buffer that amplifies the clock phases to the full scale is guaranteed to be centred around the switching point of a balanced inverter. The most crucial component for effective operation however lies with the sizing of the input NMOS M2 with respect to loading ring oscillator. The DC operating point M2 and R1 will present an load equivalent to that of a diode connected transistor. If the delay element is balanced the current bias of the oscillator is evaluated with \\(K_{M2}\\) and \\(K_{N}\\) representing the \\(W/L\\) ratio of transistors M2 and the NMOS in the delay cell respectively. + +{{< figure src="technical_3/DIG2.pdf" title="Figure 75: Simulated transient behaviour of the differential oscillator and the generated digital output. " width="500" >}} + +Figure 75 clarifies the principle operation of this topology. We can see that as two currents are being integrated on the differential oscillator a phase shift will start to emerge when the two waveforms are compared. This phase difference on node $\Delta \phi$ represents our system output where the signal is encoded in the pulse width of the digital signal. This signal is applied to the capacitor array for feedback. + +$$ f_{osc} \approx \frac{\alpha I_{M1}}{N C_{gate} V_{th}} \text{where} \alpha = \frac{K_{M2}}{2 K_{N}} $$ + +The factor \\(\alpha\\) in Equation 43 dominates the noise performance when referred to the input which would ideally approach the \\(NEF\\) of that without the oscillator. Similarly the corner frequency of the oscillator flicker noise which is not rejected by the chopper scales with this factor. It follows that the transistor length of the oscillator has a strong relation with respect to $f_{cor} \propto 1/L^{2}$. Fortunately it is easy to diminish this contribution as only a small bias is needed to result in a oscillation frequency several orders outside the signal bandwidth. + +$$ H_{sys}(s) \approx \frac{\eta f_{osc} }{s U_T} \cdot \frac{2-\alpha}{\alpha} N and f \approx \frac{C_I}{C_D} \cdot (N+2) $$ + +The overall open loop system characteristics \\(H_{sys}\\) evaluated in Equation 44. This reflects the single pole nature of the topology that scales with the oscillator frequency and the number of phases taped out as one may expect. Notably the capacitive feedback structure used can represent a very small feedback factor \\(1/f\\) without excess input capacitance that accommodates a large number of oscillator taps [^186]. Evaluating the low pass 3dB point of the system which reveals a dependency as shown in Equation 45. + +$$ f_{3dB} = \frac{\eta f_{osc} }{\alpha U_T} \cdot \frac{N}{N+2} \cdot \frac{C_D}{C_I} $$ + +This expression is primarily dominated by the oscillator frequency which even for a small bias current can result in a considerable bandwidth. Although this is partially expected due to the fact there is no explicit load capacitance it also illustrates the benefits in FOM that can be achieved with this configuration of current-mode time domain architecture. There is a instinctive concern for the stability of the system as a result of the excessive bandwidth driven by maximizing efficiency. The non dominant poles introduced in the voltage domain is due to the parasitic capacitance on node \\(V_Q\\) typicall will not compromise stability due to coupling to the input of the transconductance at higher frequencies. The non-dominant pole on the time domain is introduced by any delay \\(t_d\\) from the VCO to the output buffers of the PFD as $e^{-j\omega t_d}$. This component can be more restrictive for small loop gain as it does not scale with the power of the input stage but with the supply voltage. + +The voltage requirement of this structure is improved by biasing the NWell of the PMOS peudo differential pair to \\(V_{XN}\\) & \\(V_{XP}\\) in a cross coupled fashion to reject the differential lading component. The forward biasing reduces the threshold voltage of the devices allowing a supply voltage down to \\(0.6 V\\) without any considerable impact from leakage currents. This configuration also implies that the common mode at \\(V_X\\) is well regulated by the body transconductance of M4 & M5 rejecting common mode input fluctuation. The main voltage requirement actually comes from the switches of the chopper that feeds the ring oscillator that need good on-resistance to prevent noise injection which implies a minimum voltage of approximately \\(2V_{th}+V_{ov}\\). Back-gate biasing will allow us to reduce the impact of \\(V_{th}\\). + +The psuedo-resistive feedback structure in Figure 74 b) extracts the signal component from up modulated aggressors using a current DAC which is resistively coupled to the input to close the loop. This allows us to feed back the full swing digital signals to cancel a DC off-set and sets the input common mode by matching the cross coupled transistor with the input pair. This primarily prevents having to use a cascaded resistor structure in order to deal with the large voltage swing on the output that can significantly degrade performance. While stability is trivialized by the capacitive feed forward signal that grantees stability [^187], it is important to note the design choice associated with the two poles in this feedback loop. One pole lies at the input of the complementary pair associated with \\(C_{fb}\\) and the other is at the gate of the cross-coupled pair \\(C_{x}\\). + +$$ \tau_{hp1}(s) \approx C_{fb} \cdot R_{psudo} \text{and} \tau_{hp2}(s) \approx C_{x} \cdot \frac{\eta U_{T}}{I_{M1}} \cdot \frac{W_{M6} + W_{M7}}{W_{M6} - W_{M7}} $$ + +Equation 46 described the dependency of the two time constants in addition to the capacitive feedback. The reduction in capacitance of the feedback network implies that the high pass filter needs careful design in terms of the resulting pole location as the noise expected from the psuedo resistor will appear increasingly wider band as we try to reduce the total capacitance. Here we allow the second pole of \\(C_{x}\\) to approach DC by having $W_{M6} \approx W_{M7}$ resulting in a integration node. This means that the noise around the chopper frequency is strongly related to amount of capacitance we can allocate to \\(C_{x}\\) and the 1/f agressors are now shaped by the VCO integrator and this capacitance. The bias of \\(I_{M1}\\) in the current DAC should be adjusted to set the pole location close to but smaller than the chopper fundamental similar to the conventional design approach. + +When we compare this structure to the conventional topology we realize a number of significant advantages. Primarily the inversion coefficient of the transistors is not bound like in a complementary input stage where the \\(V_{GS}\\) voltage for both the NMOS and PMOS has to be sufficiently large to allow the drain voltage to fluctuate by several \\(100 mV\\). This is particularly significant because the minimum feature size is inverse proportional to the optimal inversion coefficient confirming again that conventional means to not work at nano meter technologies. Here the threshold voltage can be arbitrarily small and we still retain a topology that is independent of supply voltage in the sense that it is strictly current biased. This will lead to improving the tolerance towards wafer level variations of the threshold voltage and carrier mobility which many sub \\(1 V\\) structures do not have. Similarly this implies class-A type power dissipation that minimizes switching current seen at the analogue supplies. + +The excess in bandwidth from the VCO despite operating with a very small inversion coefficient has enabled us to achieve both \\(40-50 dB\\) closed loop gain while still retaining excess loop gain that easily exceeds \\(30 dB\\). This excess loop gain in the signal band is facilitated by the near ideal VCO integration of this topology that shapes a number of external noise sources and nonidealities. In particular technology scaling allows us to minimizes the noise gain due to the input capacitance \\(C_g\\) according to the expression $1 + C_{g}/C_{in}+ N/A_{cl}$ [^63]. Hence the VCO topology can allow a reduction for the input capacitance by a very significant factor relating to an impedance enhancement that scales with technology. + +{{< figure src="technical_3/Sim_Inband.pdf}" width="500" >}} + +{{< figure src="technical_3/Sim_Outband.pdf}" title="Figure 76: Transient noise simulation result of the 180nm CMOS time domain instrumentation topology with a \\(6 mV\\) peak to peak sine input at \\(1 kHz\\)." width="500" >}} + +A Transient noise simulation performance is shown in Figure 76. This demonstrates that the dependency on nonlinearity is mainly due DAC mismatch components which are modulated the oscillator frequency spurs. Secondly the noise-floor and corner frequency characteristics follow closely to analytic predictions. In addition for the same current bias as a conventional implementation the structure can achieve an equivalent noise floor but at a reduced voltage overhead. Noticeably in the full spectrum there is a considerable amount of harmonics out side of the band induced by the chopped and oscillator aggressors. These components will need to be filtered out in order to approach a \\(60 dB\\) signal to noise ratio. Interestingly there is an observable gain in noise floor as we approach the point where there is no excess loop gain. Note that the spurious free dynamic range of this structure almost exceeds that of the structure used in Section 23 by a factor of 10 for the same power budget due to the increase input range. + +## 47 Time Domain analogue filter + +Now that we have addressed the aspects of achieving low noise and linear instrumentation we must proceed to address the mechanisms for filtering to implement a band limiting characteristic necessary for the processing algorithms. There is some diversity in the number of approaches used to filter time domain signals. Most notably the continuous-time FIR based structure that represents a number low power characteristics that scales well with technology without sampling or clocking [^188][^189]. However similarly to conventional FIR structures it is limited to signals where the frequency dynamic range is small in order to keep the filter order small. Other examples are found in PLL structures that lock using coherent phase domain signals which is inherently second order due to the analogue integration node which result in a loss of noise efficiency at low frequencies [^190]. We do mention that VCO-based ADCs have been very successful in achieving efficient high-order noise shaping [^191][^192]. + +It is important to realize that our proposed instrumentation topology converges on incoherent phase domain signals and neglects the modulation products through construction similar to that of asynchronous \\(\Delta\Sigma\\) modulators[^193]. Here we will take a similar approach to construct a first order phase domain integrator where the time-domain signals are also incoherent. Through simplicity the structure achieves a significantly better dynamic range and voltage scaling capability than its analogue domain counterpart. The premise will lie with our assumption that the intermodulation products of the incoherent frequencies are sufficiently out of band to allow construction of higher order filter structures. + +{{< figure src="technical_3/TD_ABST.pdf" title="Figure 77: Closed loop time-domain analogue filtering structure" width="500" >}} + +The topology used for analogue filtering of time-domain signals is illustrated in Figure 77. This is based similarly on the phase difference of two ring oscillators that integrate a switched current which is generated by evaluating the difference in duty cycle with respect to the input and feedback. The logic simply advances or recedes the phase difference of the oscillator when there is an excess or lack pulse width when comparing the two inputs respectively. This behaviour is shown in Figure 78. The use of logic gates over avoids any drawback that arise from limited linearity and mismatch in the case of approaching this design with current mixing techniques. More over the efficiency of these operations allows miniaturized reconfiguration in the digital domain with a minimal analogue structure. + +{{< figure src="technical_3/DIG1.pdf" title="Figure 78: Simulated transient behaviour of the differential oscillator and the time encoded digital signals internal to the feedback loop." width="500" >}} + +Most design considerations here are similar to that of conventional filters. We expect the analogue in-band noise components will scale with the biasing current \\(I_b\\) which will determine its input referred noise relative to the transconductance element $\Delta I$. This however does represent a fundamental drawback since the charge pump transconductance element does not benefit from the sub-threshold slope gain factor. $\Delta I$ will typically be larger for the same bandwidth requirements by a factor of \\(1/U_T\\). Although this factor is essential for achieving smaller cut off frequencies while maintaining large oscillation frequencies. The decreased noise efficiency is the fundamental drawback of using a digital logic instead the capacitive feedback network. However in this scenario the processed signal will already be at full dynamic range with reduced noise requirements. + +{{< figure src="technical_3/TD_SUB.pdf}" width="500" >}} + +{{< figure src="technical_3/TD_FLT.pdf}" title="Figure 79: Schematic sub-blocks for first-order time domain analogue filter " width="500" >}} + +The gate level implementation is elaborated in Figure 79. The charge pump structure here uses a cascaded current source and dummy load for bandwidth improvement. This configuration is important because this operator precedes the integration and consequently has a substantial influence on off-set or distortion near the cut-off. The self referenced bias of the charge pump through M11-M14 should allow to good matching independent of the configuration in biasing transistors M2-M3. Similarly the noise figure is improved by sharing the drain voltage of M12-M13 as its noise is coupled to the common mode. + +{{< figure src="technical_3/gmc_eqv.pdf}" width="500" >}} + +{{< figure src="technical_3/TD_FLT2.pdf}" title="Figure 80: Bandpass time-domain analogue filter which is cascaded to realize a 4\\(^{th}\\) order TD-BPF." width="500" >}} + +The two digital components in Figure 79(a) represent the subtraction for feedback and a gain factor \\(G\\) when the phases of \\(Q\\) are mapped to the output. The subtraction logic is determined by considering the XOR-PWM waveform as a two state input of $\pm 1$ and similarly the DAC input states which in this case is \\(+1/0/-1\\). The configuration of both components should compliment each other. This is exemplified when we consider the summing node for another case when two integrators are cascaded with both outputs fed back to achieve a bandpass response. This configuration is shown in Figure 80. The boolean operation required is shown in Figure \ref{fig:T3_logic} where four levels are needed to include carry signals. Here we compromise with two DAC structures with input states \\(\pm 1\\) and \\(+2/0/-2\\). + +\begin{karnaughmap} + \centering + \karnaughmap{3}{\\(\boldmath{F}=D-(Q+X)\\) }{D Q X}{{1}{-1}{3}{1}{-1}{-3}{1}{-1}}{} + \caption{ Karnaugh map associated with the subtracting XOR type PWM signals \\(Q\\) & \\(X\\) from \\(D\\) } + \label{fig:T3_logic} +\end{karnaughmap} + +The logic that sums the different phases relies on the coherence of it input. Because we know the different taps of the ring oscillator will not over lap with respect to certain signal range at the output we may isolate the components with the \\(AND\\) operation of two different phases to isolate small variations in pulse width and combine them. Analogous to a variable gain amplifier, if the signal variations exceed the section where the two phases overlap the output will saturate. The significance here is that gain achieved with this operation has arbitrary gain bandwidth product with negligible power dissipation. Once blocking or interfering signals have been removed we may give the signal reconfigurable gain by only using a handful of gates. It simply relies on increasing the number of oscillator taps from the previous stage while maintaining its feedback configuration which is independent of noise & linearity performance. In fact for a gain \\(G\\) on the PWM signal \\(D\\) we require \\(2G\\) taps that are summed according to Equation 47. + +$$ Q = \bigcup_{k=0}^{G-1} \{ D_{R k} \cap D_{R k+N/2-R/2} \} Where R= \floor{\frac{N}{G}} $$ + +While \\(AND\\) & \\(OR\\) will perform equivalent operations that retain the oscillator phase difference \\(\Phi\\) but subtract a signal independent component which the gate delay between the two phases being operated on from the pulse width. Here \\(\Phi\\) is normalized such that it represents \\(1\\) and \\(0\\) when the oscillator phase difference is \\(\pi\\) and \\(0\\) respectively. This implies that for a positive gate delay number of $\Delta T$ we will have an output off set by $Q=\Phi - \frac{\Delta T}{N}$. If an \\(XOR\\) gate is used we extract a signal independent component as $Q=2 \cdot \frac{\Delta T}{N}$. Both statements will hold true as long as $\Phi < 1-2\Delta T$ which implies that the pulse section used for computation is signal independent. Using this rather simple construction of logic one may sum phases that are one radian apart with a \\(XNOR\\) gate to realize the absolute value operator which exemplifies the rich utility of this time domain processing. + +$$ H_{sys}(s) = \frac{ G }{1 + s/p_1} \text{where} p_1 = \frac{N }{q_{tot}} \cdot \Delta I = \frac{ N \omega_{osc} }{ K } $$ + +When the primitive topology in Figure 77 is analysed in the Laplace domain we can derive the Equation 48. This demonstrates a first order characteristic similar to the amplifier and has is a close relationship with the oscillation frequency and the filter bandwidth with the addition of the gain factor \\(G\\). + +This filter configuration here specifically designed for a $0.18 \mu m$ process. Considering that digital filters will become more viable as the technology node decreases it should be acknowledged that the proposed time-domain filter structure will only be advantageous when frequency dynamic range is large and memory is limited. This is primarily because the \\(kT/C\\) relations inhibit very aggressive sizing in the oscillator structure particularly if no excess loop gain is available. We still require a large amount of energy storage \\(q_{max}\\) to prevent external noise sources from perturbing the output. We point out the proposed topology discussed here provides the means by which instrumentation can successfully scale with technology characteristics. Particularly as it is robust towards transistor non-linearity and imperfections. A large component for performance enhancement will rely on calibration components that improve the resilience of the capacitive feedback structure and filter parameters to allow miniaturization. While this specific time-domain topology will not allow the absolute minimum supply voltage this configuration does take advantage of transistor sub-threshold slope which implies a fundamentally superior noise performance that can also circumvent supply noise. + +{{< figure src="technical_3/TD_sys_sim.pdf" title="Figure 81: Transient noise simulation of proposed instrumentation amplifier with time-domain filter structure with a \\(6 mV\\) peak to peak sine input at \\(1 kHz\\)}\label{fig:T3_sys_sim" width="500" >}} + +{{< figure src="technical_3/65nQ.pdf" title="Figure 82: Transient noise simulation result of the proposed instrumentation topology in 65nm CMOS with \\(2 mV\\) peak to peak sine input at \\(2 kHz\\)}\label{fig:T3_65nm" width="500" >}} + +As shown in Figure 81 both a low noise floor and band limiting behaviour is achieved. In particular we see a \\(40 dB\\) roll off in the noise floor at the \\(6 KHz\\) cut-off frequency from the \\(4^{th}\\) order bandpass filter. While Table 11 reveals some similar performance characteristics as the conventional implementation in Section 23 which is the result of using the same optimization strategy. However this work is the first to consider NEF maximization for the design of time-domain circuits. As a result we are much more confident about the power efficiency for this implementation. As a reference this topology was also implemented using a 65nm CMOS process without filtering structure to confirm the scalability of this structure with the noise transient simulation shown in Figure82. The compact capacitive feedback may not allow linearity beyond 60dB but given the scalability and efficiency of this design there is a significant advantage over current state-of-the-art. + +Table 11: +| Parameter | Units | \multicolumn{2}{c}{This work} | Chandrakasan [^194] | Tsividis [^195] | Markovic [^180]| +|----|----|----|----|----|----| +| Modality | | Time | Time | Voltage | Time | Time | +| Technology | [nm] | 180 | 65 | 180 | 28 | 40| +| Supply Voltage | [V] | (0.6) | (0.5) | $0.2 \| 0.8$ | (0.65) | (1.2)| +| Total Current | [(\mu)A] | (0.8) | (1.5) | (1.8) | (36.92) | (5.8) | +| Bandwidth | [Hz] | (375)-(6k) | (1)-(6k) | (1)-(1k) | (40M) | (3-1.5k) | +| Filter Order | | IIR (4^{th}) | - | IIR (2^{nd}) | FIR (8^{th}) | - | +| Noise Floor | [(nV/āˆš{Hz}) ] | (69.4) | (57.5) | (36) | (514) | (427) | +| Noise Corner | [Hz] | (<10) | (<10) | (0.5) | - | (<1)| +| SFDR | [dB] | (58) | (54) | (50.4) | (30) | (78) | +| Area | [mm(^2)]| $115 \times 100 ^\star$ | $64 \times 69 ^\star$ | $800 \times 775$ | $72 \times 45$ | $280 \times 360$ | +| NEF | | (1.18) | (1.22) | (2.1) | (8.13) | (12.9) | +| Chopped Input Capacitance | [pF] | 0.04 | 0.03 | 21.5 | 0.01(^\dagger) | - | + + +This brings us finally to finding a satisfactory answer to how the area-power product figure of merit limited or bounded in some sense. Section \ref{ch:T1_model} argued that linearity and quantization was crucial constraint in the conventional structures which is not the case for the proposed structures. Instead we observe from Equation 41 we must dissipate a certain power level in the oscillator which we know is biased by a fractional current related to the input referred noise through \\(\alpha\\). As a result the current of the oscillator is fixed and thus when the voltage \\(V_T\\) is scaled down this sampling contribution will progressively become larger to the point that is it comparable to that of the thermal noise. This equality reveals the oscillator voltage should not approach $\alpha \cdot 2U_T$ or the NEF efficiency factor will degrade. We can assert that although at first it appeared that the sampling noise limited the minimum size of the instrumentation circuit here is limits the minimum power of the circuit in a much more explicit manner. The area requirement is more simply proportional to \\(K_F/\alpha\\) reflecting the location of the flicker noise corner and the target oscillator frequency. There are some details remain with regard to choosing \\(\alpha\\) which represents one degree of freedom for trading off oscillator area for minimum voltage but is also strongly depedent on the system bandwidth. + +# 48 Analogue Signal Classification + +Now our interests will be redirected towards the methods and hardware implementation of neural spike analogue classification in order to faithfully demonstrate that continuous time instrumentation can provide a substantial improvement over the conventional approach at the system level. In particular we demonstrate an unsupervised method that will allow the classification of spikes without requiring signal quantization at any stage of the adaptive process with empirical results. + +{{< figure src="technical_3/Nsample.pdf}" width="500" >}} + +{{< figure src="technical_3/Fsample.pdf}" title="Figure 83: Illustration of Nyquist rate feature extraction and using feature enhancement in order to operate at sub-Nyquist rates. " width="500" >}} + +The abstract motivation here is illustrated in Figure 83. Utilizing digitized recordings as basis for feature extraction implies the necessity of operating with excessive data rates in order to capture the full bandwidth of features in the signal such that $f_s > 2 f_{BW}$. By using mechanisms that enhance & extract prominent features directly in the analogue domain this sampling constraint is eliminated [^141]. Instead we may sample at the rate of spikes present in the recording. Even by approximation we can assert that $f_n << f_s$. In some sense this motivation inspired by that of adaptive compressed sensing or sparse representation methods [^196]. Here we will introduce a perspective based on realizing a less generalized method that can be integrated effortlessly which has not yet been attempted in the literature. The challenge for this approach is finding efficient analogue operators that allow direct feature extraction and more importantly feedback mechanisms that adaptively improve the feature extraction process without substantial resource requirements or supervision. + +The notion that motivated this specific classification structure is that in order to improve alignment and thereby reducing how noise couples to features relatively high sampling rates are needed. This implies high temporal resolution for these spread-spectrum signals is desirable such an approach but has unavoidable implications on larger memory and power requirements. As we shall see analysing \\(K\\) features for \\(M\\) centroids with mixed signal methods will require \\(KM+K\\) registers and \\(max(K,M)\\) integrators where register depth has logarithmic dependency on temporal resolution. In contrast to PCA, template matching, and many all-digital methods where temporal resolution or window size is linearly proportional to register count. While it is still vital to align the analogue operators with the spike waveform, increased clock rate does not influence the analogue power dissipation since signal quantization is not performed. + +It is relatively rare to see analogue or mixed signal implementations for machine learning classifiers due to the convoluted impact circuit imperfections has of learning dynamics [^197]. This makes it difficult to successfully realize more complex architectures but the methodology can significantly increase the information storage density at very low power budgets. This is exemplified by the system in [^198] that not only achieve 1.04 GOPS/mW but also an area efficiency of 0.03 GOPS/mm\\(^2\\) using a 130 nm technology. Here the continuous valued charge on floating gates was used to preserve learned features without quantization of errors. + +## 49 Feature Selection + +It should be expected that when a spike event it sampled at a relatively high rate we typically only need a select few samples once it is aligned in side a window in order to tell different classes apart. Only when noise becomes a considerable component must we consider multiple samples before we can make an accurate distinction. In such a scenario we would like to use the samples that maximally distinguish classes. That is, we would like to maximize the quality of our feature \\(Q_F\\) by maximizing for instance a simple sum of \\(N\\) maximally separating samples \\(c\\) in the window \\(W\\) with the linear distance operator \\(D\\). + +$$ Q_F = \frac{\sum_{i=1}^{N} D(W[c_i]) }{N} + \frac{en_{rms}}{āˆš{N}} + \frac{BG(t)}{N} $$ + +The expression in Equation 49 primarily tells us that in the presence of white noise \\(en_{rms}\\) and background activity \\(BG\\). Increasing the number of samples reduces the contribution of white noise by \\(āˆš{N}\\). However if the new samples have negligible signal quality our aggregate distance will decrease fractionally by \\(1/(N+1)\\). This suggests that we should avoid using on a large ensemble of samples because it avoids complexity and may very well improve classification accuracy. Implementing an effective analogue solution requires the evaluation of optimal section in the spike window. To analyse this problem let us define a distance to noise ratio \\((DNR)\\) with respect to the mean spikes of \\(M\\) classes and their standard deviation for each sample in the spike window as; + +$$ DNR[n] = \frac{\sum_{i=2}^{M} |\mu_{0}[n] - \mu_{i}[n]|}{āˆš{\sum_{k=1}^{M}\sigma_k^2[n]}} $$ + +Where \\(\mu_0\\), \\(\mu_k\\),\\(\sigma_k\\) are the mean of all spike waveforms, mean of spike waveforms in class \\(k\\) and the aggregate standard deviation of class \\(k\\) respectively. In a more general form of choosing samples that maximize Equation 50 can be seen as classification by expectation maximization[^199]. In Figure 84 we exemplify this quality factor for a number of training data sets along side the first principle component of each set respectively. + +{{< figure src="technical_3/S2PcorA.pdf}" width="500" >}} + +{{< figure src="technical_3/S2PcorB.pdf}" width="500" >}} + +{{< figure src="technical_3/S2PcorC.pdf}" title="Figure 84: Illustration of feature dependency for windowed neural spikes for data sets from \cite[roman]{} with \\(-16/,dB\\) background noise and \\(-20 dB\\) added white Gaussian noise." width="500" >}} + +A number of observations can be made. In particular for a variety of spike shapes show PCA peaks in the first moment which are convex with respect the depolarizing and repolarization sections. In contrast to the DNR plot shows multiple local minima and thus optimization in this space is not considered trivial. What should be pointed out is that the peaks in the PCA curve will typically correspond to good DNR points as they will relate to sections of high variance due to maximum class separation on top of the noise variance. It should also be clear that our interest does not lie in the refractory period as the slow-wave component is small in magnitude and typically corrupted by high-pass filters that reject environmental interference. Hence we inherently expect poor DNR in the latent refractory period of the recorded action potential. One of the more significant implications of not quantizing the signal is related to the fact that features can generally not be extracted before the detection event. This implies that the operator used for detection should avoid introducing group delay that could result in completely missing the most energetic features in the spiking event. + +In actuality this hints at the contradictory advantage of analogue filter detection over an FIR filter equivalent. That is this group delay exclusive to IIR filters is highly dependent on the frequency content of the spike waveform. This can to some extent be observed in Figure 84 where class 2 is deliberately delayed with respect to the alignment point since it has a smaller derivative or equivalently less high frequency content. Here the alignment is a achieved by conditioning the signal with a narrow bandpass filter and looking for a peak above the threshold. While a relatively simple in implementation, if designed to maximize output signal to noise power it can be quite effective. + +The approach to self mixing spike classes to with the sampling or alignment strategy is effective at improving features of already very similar spike shapes. In fact this alignment in some sense captures the features existent before the detection event and is mixed with latent features. As a result although analogue techniques are less effective at demonstrating resilience towards background noise they can efficiently mix different features to improve discrimination between spike shapes. + +## 50 Mixed Signal Implementation + + + +The adaptive method employed here is to section the spike waveform depending on the redundancy in the number of features required. Noting that features in the same polarizing phase will correlate strongly since they emerge from the same phenomena. Each section after the detection event is bounded as priori to grantee non-overlapping features (i.e. $0-150 \mu s , 170-310 \mu s$) and the maximum variance is found in each section respectively. These are assumed as optimal DNR features referred to as \\(\Omega\\)s. Our classification will integrate around these points and perform k-means clustering in the resulting space. + +{{< figure src="technical_3/TD_SYS.pdf" title="Figure 85: System abstraction showing the configuration for pre-filtering detection and reconfigurable integrators. " width="500" >}} + + +The topology is summarized in Figure 85 where the predominant active component lies with the state machine reconfiguring the integrators to optimize the classification. The noise rejection performed by three bandpass filters primarily removes out of band aggressors that prevent accurate classification. Notice the feedback loop for detection relies on a long term average of a narrow band component in addition to a indication of a localized peak above the threshold. Filters \\(F1\\) & \\(F2\\) are band pass filters with first order roll-off and a \\(0.4-7 kHz\\) bandwidth where as \\(F3\\) is a narrow band of $2.5-4.5 kHz$ to maximize group delay sensitivity. There is an additional advantage of pre-sectioning the waveform which is that these optimal points can be found independently in sequence. During initialization we seed the starting point in the middle of the section. + +{{< figure src="technical_3/TD_VM.pdf" title="Figure 86: Illustration of closed loop control for finding point of maximum variance. " width="500" >}} + + +The control loop for implementing this method is shown in Figure 86. Here \\(\Omega_{1/2}\\) represents the temporal off-set separated by $20 \mu s$ with respect to the detection event around which the signal is integrated in the analogue domain. The digital integrators primarily average the aggregate statistics to assist long term convergence by tracking the mean value of both integration results. This allows us to compare the deviation from the mean for each spike event and evaluate which has a larger variance. Note a key characteristic is that signal being analysed is band limited to such an extent that we do not expect local minima within each separate section. Since the digital integrators are accumulating boolean results to reject the uncorrelated noise the factor \\(a_{1}\\) represents the register depth of the counter. To be more precise the \\(\Omega\\)s are taken as a first order difference between the detection event and an off-set. + +$$ X(t) = \underbrace{\int_{t0+\Omega}^{t0+\Omega+\Delta +MA} Q_{out}(t) dt}_{Integrated \: Signal} - \underbrace{ 2 \cdot \int_{t0}^{t0+\Delta} Q_{out}(t) dt}_{Off-set} $$ + +This first order difference operation is shown in Equation 51 where \\(t_0\\), \\(\Delta\\), and \\(Q_{out}\\) are the time where the spike even is aligned, static integration time of $20 \mu s$, and analogue signal containing the spike. This clarifies that the moving average \\(MA\\) is mixed with the signal when it evaluates the mean of the \\(\Omega_{1}\\) section. This approach primarily helps with a self referenced gain that allows smaller register depth. + +{{< figure src="technical_3/TD_CC.pdf" title="Figure 87: Illustration of closed loop control for tracking two-centroids with the \\(\Omega_{1}\\) feature. " width="500" >}} + + +After several seconds of training data or equivalent spike count we can assume that the sections that maximize variance have been approached. At this point the \\(\Omega\\)s are fixed and the centroids need to be generated to complete the adaptive process for classification. As illustrated in Figure 87 a similar feedback mechanism is used to adjust the mean centroids based on boolean results. This particular configuration is the adjustment of two centroids based on one feature in the \\(\Omega_1\\) section. By adjusting the centroids \\(MA_{\mu}\\) when it is the closest to the new data point we realize a k-means clustering method with a \\(l_0\\) norm distance operator. + +Since we bound the \\(\Omega\\) sections to be strictly non-overlapping the same analogue integrator can be used to evaluate the accumulated error of all features to each centroid. Moreover for a small \\(a_1\\) the centroid adjustment can be time multiplexed leaving a reduced requirement on the total number of integrators required. This implies that \\(K\\) integrators are needed to iterative adjust all the centroids and \\(M\\) integrators are needed to evaluate the distance from each centroid. Because this adaptive process is performed in isolation we may perform the training in phases that updates clusters and features separately we will only need \\(M\\) or \\(K\\) integrators concurrently which ever is more demanding. However \\(KM\\) registers are needed to specify the location of each centroid which should be converted to a time-domain signal by using reconfigurable delay lines. + +{{< figure src="technical_3/TD_ADR.pdf" title="Figure 88: Delay line configuration for evaluating the absolute difference between the asynchronous time domain signal \\(D\\) and the registered centroid position \\(X\\). " width="500" >}} + + +Such a configuration is illustrated in Figure 88 where there is course control by selecting different phases of \\(D\\) and fine control with a conventional multiplexed delay structure. Again the reduction in complexity and rejection of quantization noise by performing time domain computation opposed to the equivalent \\(8b\\) full adder is typical of this processing modality. Finally the question should remain is that how are centroids initialized without requiring quantization. This requirement is avoided by using an iterative method with respect to centroid generation. After having a single centroid converge to the mean of the feature space we iteratively split centroids in two while training similar to that discussed in Section36. We presume redundant clusters will be generated that are removed if supervision is allowed to intervene or in the case that high level control is used to analyse which clusters are significant after several iterations. The results presented here however do not consider this supervision. + +## 51 Validation + + + +In order to demonstrate the viability of this approach we will simulate a linearised model that is constructed using Matlab. Here we aim show to what extent unsupervised methods are constrained with respect to classification performance. Original data sets used in Section 33 have been up sampled from \\(24 kS/s\\) to \\(240 kS/s\\) after the band limiting filters to emulate the continuous time logic that will operate at a high clock rate. + +{{< figure src="technical_3/feature_clean.pdf}" width="500" >}} +{{< figure src="technical_3/feature_noisy.pdf}" title="Figure 89: comparing PCA and \\(\Omega\\) feature distribution for the Difficult2 data set. Ground truth for spike classes annotated as cyan, maroon, yellow and blue for false positives." width="500" >}} + + +The feature space resulting from this method is exemplified in Figure 89. Here we compare it to that of the two component PCA feature space since the \\(\Omega\\) represents its approximation. It is typical to see multiple additional clusters form either due to the detection of false positives or miss alignment of a spike class in the presence of noise. Initializing extra clusters can typically retain classification accuracy in noisy environment but degrade precision in pristine conditions. + +{{< figure src="technical_3/A05.pdf}" width="500" >}} +{{< figure src="technical_3/B05.pdf}" title="Figure 90: \\(\Omega_2\\) and \\(\Omega_3\\) classification for data sets with \\(-26 dB\\) background activity." width="500" >}} + + +{{< figure src="technical_3/A01.pdf}" width="500" >}} +{{< figure src="technical_3/B01.pdf}" title="Figure 91: \\(\Omega_2\\) and \\(\Omega_3\\) classification for data sets with \\(-20 dB\\) background activity." width="500" >}} + + +{{< figure src="technical_3/A02.pdf}" width="500" >}} +{{< figure src="technical_3/B02.pdf}" title="Figure 92: \\(\Omega_2\\) and \\(\Omega_3\\) classification for data sets with \\(-16 dB\\) background activity." width="500" >}} + + +The results in Figure 91 demonstrate classification accuracy in terms of the percentage of all correctly classified events with respect to the ground truth including false positives and false negatives. This indicates that when a signal to noise ratio exceeds \\(20dB\\) the conditions are quite forgiving towards the simplicity of the algorithm. The two features used here require very little effort to adapt and classify activity. It is important to mention that a fixed filtering configuration is maintained for all test points in order to demonstrate adaptive characteristics. + +The results in Figure 92 shows improvement in noisy conditions if the number of sections is increased to 3 implying a three dimensional feature space to improve centroid distance. Using the same algorithm for feature selection the configuration can deal with twice the amount of background noise without supervision. In some sense the fact that the signal is not quantized does not have a significant impact on classification accuracy. This highlights the importance of closed loop algorithms whether resources are constrained or not. As such constructing a convex search space or extracting well reasoned features from underlying phenomena is crucial to reducing in complexity. + +{{< figure src="technical_3/CA01.pdf" title="Figure 93: False alarm rates normalized by true positives for the analogue detection." width="500" >}} + + +Figure 93 shows that these noise levels detection is relatively consistent but not as adaptive as the digital approach. The threshold for detection will favour generating false positives over false negatives. The main point of failure for noise levels beyond that point lies with the inability to perform feature selection based on localized variance maximization. This is partially expected as PCA will similarly perform poorly when noise levels become comparable to the signal. + +In a practical case it may be difficult to ascertain if signal to noise level is adequate to trust classification unless there is confidence to do so in the sense that there may be redundancy in the recording taken. However it is significantly more viable for realizing sub $1 \mu W$ neural spike classification for large scale recordings considering the resource requirements for adaptive classification. Given that each integrator consumes less that \\(50 nW\\) in $0.18 \mu m$ CMOS and each structure needs minimal supervision. + + +Table 12: Overview of Detection & Classification performance in green for data sets from [^1] for different methods. \\(\star\\) Requires off-chip Supervision. \\(\dagger\\) White noise is also added at -20dB of the signal power. +| Method | Analogue | Digital Registers | Cycles / Sample | Data Set | \small{Background} @ -16dB (^\dagger) | \small{Background} @ -20dB (^\dagger) | +|----|----|----|----|----|----|----| +| \multirow{3}{2.5cm}{RVD} | \multirow{3}{2.5cm}{1(\times)ADC} | \multirow{3}{2cm}{83} | \multirow{3}{2.5cm}{172} | Easy 2 | \flcl{0.734} | \flcl{0.842} | +| | | | | Diff. 1 | \flcl{0.729} | \flcl{0.871} | +| | | | | Diff. 2 | \flcl{0.748} | \flcl{0.848} | +| \multirow{3}{2.5cm}{Template} | \multirow{3}{2.5cm}{1(\times)ADC} | \multirow{3}{2cm}{105} | \multirow{3}{2.5cm}{90} | Easy 2 | \flcl{0.820} | \flcl{0.876} | +| | | | | Diff.1 | \flcl{0.860} | \flcl{0.835} | +| | | | | Diff. 2 | \flcl{0.803} | \flcl{0.875} | +| \multirow{3}{2.5cm}{WDF [^200] } | \multirow{3}{2.5cm}{2(\times)BP-Filter 1(\times)ADC} | \multirow{3}{2cm}{41} | \multirow{3}{2.5cm}{104(^\star)} | Easy 2 | \flcl{0.951} | \flcl{0.991} | +| | | | | Diff. 1 | \flcl{0.850} | \flcl{0.929} | +| | | | | Diff. 2 | \flcl{0.846} | \flcl{0.916} | +| \multirow{3}{2.5cm}{(\Omega_3) Features} | \multirow{3}{2.5cm}{3(\times)BP-Filter 4(\times)Integrator 4(\times)DAC} | \multirow{3}{2cm}{16} | \multirow{3}{2.5cm}{1} | Easy 2 | \flcl{0.800} | \flcl{0.946} | +| | | | | Diff. 1 | \flcl{0.723} | \flcl{0.931} | +| | | | | Diff. 2 | \flcl{0.798} | \flcl{0.886} | + + +A number of methods are shown in Table 12 where we see classification accuracy and the corresponding hardware requirements in both the analogue and digital domain. The RVD and template methods presented in Section 33 represent the digital approach where little analogue components are needed beside the quantizer. Allocating more processing power or memory resources would imply choosing one over the other. As expected supervised intervention allows methods like WDF [^200] to leverage a substantial improvement with respect to resource efficient classification. In this perspective we see using \\(\Omega_3\\) features as distributing our resources in the analogue domain while still maintaining comparable classification accuracy but require less reliance on digital scaling factors. We provide more comparison details in Section 62 for the proposed digital and analogue methods proposed by this work as well as the equivalent Matlab implementation used for evaluation. + +# 52 Conclusion + +This chapter has proposed a number of time-domain constructs that encourage mixed signal design for instrumentation. Where we derived underlying concepts from the phase state of a ring oscillator in order to represent continuous valued time domain memory as the equivalent of a clocked filp-flop or sampled capacitor. In addition we have discussed the means to analytically evaluate and optimize the characteristics of these topologies. Overall we present are clear benefits over conventional implementations such as instrumentation and the functional manipulation of continuous valued signals. Moreover these structures will scale performance with technology due to the extensive use of digital gates. The instrumentation structure in particular gives way to fully synthesized platforms. Performing processing and filtering in the digital domain remains to be critical for robust sensing of LFPs and EAPs in very poor signal to noise conditions. A 0.6 V 58 dB SNDR time domain instrumentation architecture is demonstrated with a NEF of 1.18 that generates multiphase PWM encoded digital signals using sub 0.01 mm\\(^2\\) footprint and employing bandpass filtering with 40 dB/Dec roll off. + +In extension we demonstrated the capacity for mixed signal analogue to information conversion with respect to unsupervised classification that uses adaptive techniques to converge towards specific signal characteristics. Using reconfigurable integration of selected temporal sections in the spike shape lets us effectively focus resources on feature and cluster evaluation without open loop quantization. This mitigates the trade off associated with resolution and digital complexity. The main challenge as pointed out is establishing what dynamics will allow convergence to optimal feature extraction with reduced hardware requirements. Here we exploit certain phenomena in the principle components of spike shapes and the sensitivity of group delay of analogue detection to frequency content in spike waveforms to achieve direct classification. + +It is typical that techniques behind instrumentation and signal acquisition are more mature in development and direction when compared to different processing modalities. Especially when realizing mixed signal methods for machine learning where a multitude of convoluted factors impact performance. There is much still to addressed when adaptive techniques are evaluated with respect to their resource efficiency and this will likely be a important aspect that will emerge in many intelligent sensor systems. + +# References: + +[^1]: R.Q. Quiroga, Z.Nadasdy, and Y.Ben-Shaul, ''Unsupervised spike detection and sorting with wavelets and superparamagnetic clustering,'' Neural Computation, vol.16, pp. 1661--1687, April 2004. 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[Online]: http://www.darpa.mil/program/unconventional-processing-of-signals-for-intelligent-data-exploitation diff --git a/content/publications/2017/a-0-016-tsqrd-12-b-rds-sar-with-14-fj-conv-for-ultra-low-power-biosensor-arrays.md b/content/publications/2017/a-0-016-tsqrd-12-b-rds-sar-with-14-fj-conv-for-ultra-low-power-biosensor-arrays.md new file mode 100644 index 0000000..8be58d7 --- /dev/null +++ b/content/publications/2017/a-0-016-tsqrd-12-b-rds-sar-with-14-fj-conv-for-ultra-low-power-biosensor-arrays.md @@ -0,0 +1,259 @@ +--- +title: "A 0.016 mmĀ² 12 b Ī”Ī£SAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays" +date: 2017-06-15T15:26:46+01:00 +draft: false +toc: true +math: true +type: posts +tags: + - publication + - instrumentation + - CMOS + - biomedical + - data-converter +--- + +Lieuwe B. Leene, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +The instrumentation systems for implantable brain machine interfaces represent one of the most demanding applications for ultra low power analogue-to-digital-converters (ADC) to date. To address this challenge this paper proposes a \\(\Delta\Sigma\\)SAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0-2 MASH topology. This configuration uses a specialized FIR window to decimate the \\(\Delta\Sigma\\) modulator output and reject mismatch errors from the SAR quantizer which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision.} A fully differential prototype was fabricated using \cmostech to demonstrate 10.8 ENOB precision with a 0.016 mmĀ² silicon footprint. Moreover a 14 fJ/conv figure-of-merit (FOM) can be achieved while resolving signals with the maximum input amplitude of \\(\pm\\)1.2 Vpp sampled at 200 kS/s.} The ADC topology exhibits a number of promising characteristics for both high speed and ultra low power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio which are critical parameters for many sensor applications. + +# 2 Introduction + +The emergent market for wearable electronics and implantable devices for personalized health care has resulted in a growing demand for miniaturized battery powered systems that wirelessly connect a network of sensors[^1]. These systems rely extensively on high precision analogue to digital conversion to leverage digital processing techniques and accommodate stringent diagnostic requirements[^2]. As a result the ADC power, area, and precision can have a profound impact on a system's overall capabilities. For this reason oversampling techniques using \\(\Delta\Sigma\\) ADCs have already been used extensively to accommodate the niche characteristics of biomedical devices and acquire low frequency bio-signals [^3].} + +More recent developments allow these techniques to be more applicable to large sensor arrays using an incremental analogue to digital converter (IADC) topology [^4]. This is in contrast to the conventional use where a single oversampling ADC continuously converts the signal from a single sensing unit with exceptional efficiency. IADC designs are unique in the sense that they periodically reset the loop filter which enables a single ADC to process multiple analogue inputs with reduced latency. This periodic reset associates a particular conversion time for each result and enables pipelined [^4], two-step [^5], or multi-step operation [^6]}. The resulting modulator can exhibit reduced mismatch sensitivity and require a smaller oversampling ratio while achieving equivalent performance to that of higher order modulators[^7]. This is crucial for larger sensor arrays because reduced circuit complexity leads to more compact designs and faster signal conversion. These earlier publications realize an IADC structure that explicitly transfers the quantization residue from one quantizer to the next using a sample and hold mechanism which is not necessarily required. For instance the zoom technique used in [^8] reuses the capacitive DAC during conversion thereby reducing complexity and power consumption. The resulting system achieves exceptional precision by combining a SAR with a second order switched capacitor (SC) \\(\Delta\Sigma\\) modulator. A common problem however is that the SAR INL/DNL errors are not shaped by the loop filter and end up limiting the overall precision unless dynamic element matching techniques (DEM) are used. This can lead to exhaustive digital overhead for DEM control and necessitate additional redundancy in the capacitive digital to analogue converter (DAC) to remove the SAR nonlinearity[^9].} + +{{< figure src="/images/tcas2017/block_sys.svg" title="Figure 1: Block level implementation of the proposed ADC array structure for sensor arrays using SAR and \\(\Delta\Sigma\\) quantizers where a digital filter is applied to the comparator bit stream to perform decimation and mismatch correction." width="500" >}} + +The system proposed by this paper is illustrated in Fig. 1 which uses a SAR and CT-\\(\Delta\Sigma\\) together to convert the signal from four analogue inputs. This configuration is then tiled 16 times in parallel to record from 64 channels simultaneously for neural recording applications. The topology is introduced as a $\Delta \Sigma$SAR because it emerged from introducing higher order CT-\\(\Delta\Sigma\\) type noise shaping to the SAR by processing the residue charge left after the SAR conversion. Using SC techniques with a similar motivation also lead to the noise shaping SAR (NSSAR) topology from [^10] which has been used extensively to achieve very high resolution SARs [^11] and higher order modulators with reduced active filter structures [^12]. In fact the fully-passive NSSAR technique can increase the SAR precision by several bits while immune to PVT variation [^13]. The distinction here is that the NSSAR will shape the quantization noise over multiple samples by introducing 1 to 3 extra cycles per sample where as the $\Delta \Sigma$SAR will allow one-shot conversions but introduce considerably more cycles corresponding to the oversampling ratio of the modulator. The later is characteristic of IADC operation. Additionally the CT approach leads to an inherent reduction in size because the loop filter is not subject to extra sources of sampling noise typical in CS circuits.} The IADC 0-2 multi-stage noise shaping (MASH) quantization scheme used by the \\(\Delta\Sigma\\)SAR can be interpreted as first resolving the sampled input using a conventional SAR and then applying a \\(\Delta\Sigma\\) feedback loop to resolve the remaining quantization residue left on the capacitor array equivalent to the zoom technique. The resulting bit stream from the comparator output consists of both SAR and oversampled quantization results. The advantage this topology presents is that it can be configured without the need for DEM or analogue dithering techniques because SAR INL/DNL errors can instead be cancelled by calibrating the FIR filter that processes this bit stream in the digital domain. This minimises capacitive switching during signal conversion and reduces overall complexity. Moreover by virtue of resolving a small SAR residue, the CT loop filter can maximize its noise efficiency without much concern for distortion or modulator nonlinearity.} + +This paper presents an analytic design method for evaluating which condition allows the zoom type IADCs to exhibit high performance and which two-step configuration will lead to the best efficiency or size. Preliminary efforts to realize the system in Fig. 1 are presented in [^14] and the circuits proposed here are improved to achieve better power efficiency as part of a larger reconfigurable neural recording system [^15]. This system uses an array of miniaturised ADCs that distributes the digital processing over many parallel segments leading to lower clock frequencies and better efficiency opposed to demanding a single high frequency ADC and digital core.} To present the design characteristics of the \\(\Delta\Sigma\\)SAR, this paper is organized as follows. Section \ref{sec:design} introduces the principle design relations of this ADC structure with regard to system efficiency and size. This is followed by the proposed mismatch compensation method in Section \ref{sec:cali}. The circuit level implementation is proposed in Section \ref{sec:circ} with design considerations for the loop filter, capacitive DAC and FIR filter. Finally measured results are presented in Section \ref{sec:mes} which are used to draw conclusions in Section \ref{sec:con}. + + +# 3 \\(\Delta\Sigma\\)SAR Architecture + +The \\(\Delta\Sigma\\)SAR topology closely resembles the SAR with an additional loop filter that can switch between amplifying \\(A(s)\\) and integrating \\(H(s)\\) behaviour following the last SAR conversion. This similarity is shown in Fig. 2 which represents a single ended equivalent of the fully differential implementation described here. The input signal is sampled on the bottom plate of the capacitive array such that conventional SAR feedback can be applied while the loop filter is initially providing wideband amplification of 10x. Once the first \\(N\\) bits are resolved the comparator output is connected directly to a unit element in the capacitive array for the \\(\Delta\Sigma\\) quantization phase. Simultaneously the loop filter is switched to introduce second order noise shaping and resolves another \\(M\\) bits using DC extra oversampling cycles. In theory this will result in \\(M+N\\) bits of precision but in practice the SAR conversion will need to evaluate \\(N+1\\) bits with 1 bit of redundancy. This redundancy implies that the residue will always be half of the modulator input range to prevent overloading the \\(\Delta\Sigma\\) ADC[^16]. If 1 cycle is used for sampling the ADC will need to be clocked at \\((N+DC+2)f_{smp}\\) for a sampling frequency \\(f_{smp}\\) with a modulator bandwidth \\(f_{bw}\\) at half this clock frequency. A typical conversion is illustrated by the timing diagram in Fig. 3 which shows the FSM using 1 cycle for sampling, \\(N+1\\) cycles for SAR, and DC cycles for \\(\Delta\Sigma\\) modulation. Meanwhile the comparator results will infer if the corresponding FIR coefficient provided by a shared controller is added or subtracted from a local accumulator thereby resolving the input signal. To provide insight to the design considerations we will first discuss the noise requirements needed for achieving a \\(N+M\\) ADC precision. This will reveal the dominant power requirements due to the filter and capacitive DAC and also give some indication about the size of each capacitor in Fig. 2 which can then be used to estimate area. Note however that the defining characteristic of this quantization process is that the SAR residue is bound to a well defined voltage range of $\pm V_{R}/2^{N+1}$ where \\(V_{R}\\) is the ADC reference voltage. The reduced input range implies that feedback may not be needed to linearise the Gm-C loop filter used during \\(\Delta\Sigma\\) conversion but it also indicates the filter coefficients have to be carefully adjusted to achieve second order noise shaping. } + +{{< figure src="/images/tcas2017/sch_adc.svg" title="Figure 2: Proposed topology that interoperates SAR and oversampling quantizers in the same signal loop using a capacitive DAC, switched loop filter, and single bit quantizer." width="500" >}} + +{{< figure src="/images/tcas2017/fsm.svg" title="Figure 3: Timing diagram of the sampling (SMP), SAR (S0-SN), and oversampling (\\(\Delta\Sigma\\)) modes of operation where \\(C_{0}\\) to \\(C_{N+DC}\\) correspond to the calibrated coefficients of the FIR filter. EOC is the end-of-conversion signal that is put low when the quantization process is finished. " width="500" >}} + +## 4 Topology Optimization + +The efficient operation of low speed ADCs primarily relies on the careful consideration of various noise sources to avoid dissipating excess power. However the two modes of operation have characteristically different requirements. Concisely stated the \\(\Delta\Sigma\\) modulator will focus on achieving a specific noise floor because out of band noise is removed after decimation while the SAR operation is sensitive to integrated noise over the entire circuit bandwidth. To illustrate the design relations quantitatively the following discussion will reiterate on several expressions from well established \\(\Delta\Sigma\\) theory [^17]. This will allow us to determine system constraints particularly with respect to the analogue filter that provides second order noise shaping and in this case consumes most of the power.} + +## 5 Filter Noise Constraints + +First recall that the oversampling ratio for a second order modulator is dictated by Eq. 1 in terms of resolving \\(M\\) bits. This will later be used in association with the expression in Eq. 2 to evaluate acceptable quantization noise power \\(S^2_{n}\\) for a \\(N+M\\) precision ADC.} + +$$ DC \geq \sqrt[5]{ \frac{2 \pi^4}{15 \cdot 2^{-2(M+1)}}} $$ + +$$ S^2_{n} =\frac{1}{12} \left( \frac{V_R}{2^{N+M+1}} \right)^2 $$ + +Now in order to capture the subjective performance of the circuit level implementation and its impact, this analysis uses the Noise Efficiency Factor (NEF). The expression for NEF in Eq. 3 normalizes the input referred noise \\(e^2_{in}\\) of a particular implementation to that of a bipolar transistor with a biasing current equivalent to that used by the filter \\(I_{filt}\\). As a result we can abstractly consider noise-power relations without considering a specific filter topology that will exhibit some particular NEF.} + +$$ NEF^2 \deff \frac{2 I_{filt} e^2_{in}}{\pi U_T 4kT f_{bw}} $$ + +In fact by combining this with the ADC noise requirement in Eq. 2, \\(I_{filt}\\) can be predicted as a function of circuit topology and its equivalent NEF. This is detailed in Eq. 4 under the condition that \\(e^2_{in} = S^2_{n}\\) where the relevant circuit noise bandwidth is reduced \\(f_{bw}/DC\\) due to oversampling.} + +$$ I_{filt} = \pi U_T 24kT \frac{ f_{bw} }{ DC } \left( \frac{ 2^{N+M+1} NEF }{V_R} \right)^2 $$ + +Similarly \\(I_{filt}\\) can be evaluated for just the SAR operation as a special case: $I_{SAR} \deff I_{filt}(DC=1,M=0)$. In the case that \\(I_{SAR}\\) is larger than the estimate in Eq. 4 we should adopt that value instead. This result is mainly relevant for SAR converters where an analogue amplifier is used to precede the comparator and thereby dominating the noise requirements[^18]. Here it will also be used to indicate the preliminary performance with respect to \\(N\\) & \\(M\\) with a fixed clock speed and the associated conversion time of \\(N+DC+2\\) cycles. The resulting conversion efficiency is proportional to \\(2^{N+M}/P_A(N+DC+2)\\) as conversion per Watt where total analogue power is estimated as $P_{A} \approx V_{R}I_{filt}$. In this case the filter supply voltage is simply equal to the reference voltage. Normalization allows the relative efficiency to be visualized in Fig. 4 which provides some evidence that the filter alone tends to be more efficient as \\(M\\) becomes larger than \\(N\\). However \\(N\\) can not be arbitrarily small if the residue need to be kept in the linear range of the modulator. This implies a direct relationship between the ADC reference voltage and the minimum SAR resolution.} The details of this requirement is strongly dependent on the full ADC precision and its sensitivity towards transistor nonlinearity. However as a priori the minimum SAR resolution \\(N\\) can be approximated by considering that the linear input range for a sub-threshold differential input pair is related to the thermal voltage $\pm U_{T}$[^19] which suggests that \\(N \geq\log_2(V_{R}/U_{T})\\) to keep the residue inside the linear range.} + +{{< figure src="/images/tcas2017/Cost.svg" title="Figure 4: Power efficiency as \\(2^{N+M}/P_A(N+DC+2)\\) in terms of conversions per Watt where \\(N+M\\) is the target precision of the analogue filter for different values of \\(N\\) & \\(M\\) normalised by the best case where \\(M=8\\) & \\(N=1\\).}" width="500" >}} + +## 6 Estimating System Power + +The previous result is relatively optimistic in the sense that it does not consider the decimation filter or DAC power dissipation. To warrant an accurate estimation of the ADC's efficiency and resource requirements the Digital \\(P_{D}\\), and capacitive switching \\(P_{C}\\) losses should also be estimated.} + +$$ P_C = C_{U} f_{smp} V^2_R \left(DC/2 + \sum_{i=1}^{N} (2^i-1) 2^{N-2i-2} \right) $$ + +Eq. 5 includes the SAR energy dissipation in terms of the capacitive switching using the analysis from [^20].} The \\(V_{cm}\\) based switching method employed here retains a stable common mode on \\(V_{DAC}\\) with good conversion efficiency. This will help to preserve the linearity of the modulator. Variation in common mode voltage changes the offset of the loop filter as well as the impact of top plate parasitics[^20]. Both will introduce nonlinearity that is convoluted by the SAR quantization process and can be challenging to compensate accurately. \\(P_{C}\\) is evaluated for \\(N+1\\) SAR cycles where the unit capacitor \\(C_{U}\\) size introduces some degree of freedom. Strictly the total capacitance is bounded such that the \\(kT/C\\) noise is smaller than noise requirement of Eq. 2. For instance we could let the sampling noise contribute half the allowable noise power which leads to a minimum capacitance according to Eq. 6 given a \\(2^{N+1}\\) unit binary DAC. + +$$ C_U = \frac{12 kT}{V_R^2} 2^{N+2M+1} $$ + +This unit element should be noticeably larger than what may be expected from SAR configurations due to the small number of elements in the capacitor array resulting in reduced matching and interconnect complexity. Generally such a configuration will favour high density vertical metal-insulator-metal (MIM) capacitors that have large minimum size requirements and can be placed over active circuitry to reduce silicon footprint. In fact by using a split capacitor configuration the size of \\(C_{U}\\) can be even larger with less elements in the array for the same sampling capacitance leading to very efficient utilization of MIM capacitor area[^21]. It may still be the case that \\(C_{U}\\) is smaller than the minimum capacitance \\(C_{min}\\) for intermediate precision of 6-10 bits. In such a case this model will simply adopt \\(C_{min}\\). This will also apply to the load capacitance \\(C_{L1}\\) when it is calculated with respect to the modulator bandwidth as \\(f_{bw}=gm_{1}/C_{L1}\\). However this should carefully consider the reduced input swing of \\(V_{R}/2^{N+1}\\) which means the transconductance for a conventional fully-differential input in sub-threshold operation would be $gm_{1}=V_{R} I_{filt}/(\eta U_{T} 2^{N})$ where \\(\eta\\) is the transistor slope factor. + +In order to estimate the digital losses this model extrapolates the energy dissipation per clock cycle extracted from a 1 bit accumulator taken as \\(E_{reg}\\). The associated register depth \\(R_{D}=N+M+log_{2}(DC)\\) bits is derived by considering the accumulated rounding errors from DC additions during FIR decimation}. This leads to Eq. 7 which is expected to be insignificant at higher resolutions because decimation filter has reduced requirements when compared to the full precision of the integrator. + +$$ P_D = R_D E_{reg} f_{smp} \underbrace{(DC+N+2)}_{Cycles/Sample} $$ + +## 7 FOM Dependence + +The above relations should provide a good indication for the power requirements even though some system components such as the comparator and auxiliary circuits have been ignored. The Walden \\(FOM_{W}\\) and Schreier \\(FOM_{S}\\) are presented in Eq. 8 & 9. These performance metrics are plotted in Fig. 5 by assuming typical values from the \cmostech process. \\(V_{R}\\) is adjusted to \\(0.6/1.2/2.4 V\\) which keeps the linear input range of the \\(\Delta\Sigma\\) modulator consistent while resolving different SAR resolutions for fair comparison. Other constants are assumed as follows; \\(\eta=1.2\\), \\(NEF=1.4\\), \\(E_{reg}=1\\) fJ, \\(C_{min}=10\\) fF, \\(f_{smp}=10^5\\) Hz, \\(f_{bw}=10^5 (N+DC+2)/2\\) Hz. The general trend presented here is that the topology operates at maximal performance when the most of the power is dissipated by the oversampling loop and the lowest energy per conversion is dissipated when the capacitive switching and modulator power become comparable. It is not surprising that reducing the supply voltage makes it more difficult to achieve a good FOM because the absolute noise performance becomes more difficult to achieve. For reference a conventional $\Delta \Sigma$ modulator [^22] is designed with the same target specifications and using the same analysis method to configure the OPAMP integrators and resistive input network. Such a configuration achieves 167 dB \\(FOM_{S}\\) irrespective of target resolution when we consider just the filter power dissipation. In fact this figure is commonly achieved by state of the art [^8]. This highlights how the \\(\Delta\Sigma\\)SAR configuration can theoretically achieve more than 2X better performance for resolutions above 12 bits even when operating at lower supply voltages. + +$$ FOM_W = \frac{P_C + P_D + P_A}{f_{smp} 2^{N+M}} $$ + +$$ FOM_S = 6.02 (N+M) + 10 \log_{10}\left( \frac{f_{smp}/2}{P_C + P_D + P_A}\right) $$ + +{{< figure src="/images/tcas2017/AMD.svg" title="Figure 5: Estimation on the expected \\(FOM_{S}\\) and \\(FOM_{W}\\) for a resolution and varying SAR precision. The red star and blue circle indicate the target and measured performance respectively. The blue stars correspond to \\(FOM_{W}\\) achieved by other works." width="500" >}} + +{{< figure src="/images/tcas2017/APM.svg" title="Figure 6: Estimated area requirements with respect to ADC resolution for various SAR resolutions. The red star and blue circle indicate the target and measured performance respectively. The blue stars correspond to area achieved by other works." width="500" >}} + +{{< figure src="/images/tcas2017/FOMS_EA.svg" title="Figure 7: The estimated DOP with respect to the target ENOB and the \\(\Delta\Sigma\\) modulator resolution. This normalised by the best configuration where \\(M=5.8\\) & \\(ENOB=10.9\\) (i.e. \\(N=5.1\\)). \\(V_{R}\\) is assumed to be 1.2 V and the red star indicates the target performance for this implementation.}" width="500" >}} + +$$ EA = \left( 2 C_{L1} + C_{U} 2^{N+2} \right) / C_{dens} $$ + +The required area for this configuration is estimated by Eq. 10 which uses the MIM capacitor density \\(C_{dens}\\) of 2fF/\mmu mĀ². As shown in Fig. 6 high resolution configurations will tend towards noise limited requirements that are closely related to the integration and sampling capacitors. Lower resolutions are largely dependent on technology and how the SAR DAC is configured to address mismatch. Fig. 7 shows the impact of \\(M\\) on overall ADC efficiency in combination with the area requirement. This is characterised using the density of performance $DOP = FOM_{S}-10 log_{10}(EA)$ which peaks for an ENOB of 11.4 bits with \\(M\\) being 5.8 bits.} The overall quantitative results show exceptional figures of merit with highly compact configurations for 10-16 bit designs from first principles. The design described above only focuses on achieving an optimal noise performance because it dominates the low frequency FOM metrics.} Naturally a number of extra considerations need to be made for achieving the desired ENOB. Finding the requirements for open loop gain, parasitics, nonlinearity, and digital filtering is done by using numerical optimization on simplified models guided by analytic results from prior work [^22][^24]. However we can observe some agreement with this simplified model and the performance achieved in other works.} + +# 8 Foreground Calibration for the $\Delta \Sigma$SAR + +{{< figure src="/images/tcas2017/cal_tran.svg" title="Figure 8: Simplified model of the ADC structure quantization process illustrating how capacitor weight estimation \\(W_{SAR}\\) and actual capacitor weights \\(W_{DAC}\\) propagate to the output.}" width="500" >}} + +The foregoing analysis suggests that the resources dedicated to SAR operation should be kept small in order to achieve the peak performance of the oversampling modulator. As a result the DAC linearity may be much worse than the target precision. Ideally before instrumentation the system should perform a calibration procedure that determines the actual capacitor weights \\(\mathbf{W}_{DAC}\\) and recovers any lost accuracy due to mismatch in the digital domain[^26][^25]. Digital calibration techniques are extensively used for SAR converters because they enable more aggressive capacitor sizing without introducing extra analogue complexity that does not benefit from technology scaling[^27]. A simplified model of the quantization process is shown in Fig. 8 where the SAR result is fed back according to the 7 capacitor weights \\(\mathbf{W}_{DAC}\\) to produce a residue that is oversampled by the modulator and decimated by the FIR filter. The mismatch errors arise when the coefficients \\(\mathbf{W}_{SAR}\\) do not correctly calculate the exact charge offset by the capacitors (i.e. $\mathbf{W}_{DAC} \neq \mathbf{W}_{SAR}$). The structural advantage here is that all mismatch induced errors are accurately evaluated by the oversampling loop which can operate with extra noise shaping during calibration without needing a more precise reference ADC. First note that the DNL errors due to DAC mismatch are only observed upon changes in the SAR codes. Secondly the single bit \\(\Delta\Sigma\\) modulator can present significantly better linearity without calibration if SAR codes remain unchanged. Moreover if the weights are correctly estimated we should expect no discontinuities in the DNL characteristic for slowly varying inputs. The proposed calibration method takes advantage of these observations by correlating the first order difference of the ADC output and the SAR codes to find the correct coefficients for \\(\mathbf{W}_{SAR}\\). In addition by using a triangular test signal to perform calibration this procedure does not need full precision multipliers. This is because the triangular waveform distributes the occurrences of each SAR code evenly when at least one sample is taken per SAR code. Therefore the number of toggles on each SAR bit is exactly distributed as powers of two. Now if each SAR coefficient is adjusted when the respective SAR bit toggles then the rate of adjustment for each capacitor weight will be uniform if the adjustments are proportionally scaled by powers of two.} + +$$ \mathbf{W}_{SAR}[n+1] = \mathbf{W}_{SAR}[n] + \boldsymbol{\alpha} \underbrace{ sign(\dot{Q_{out}}[n] \dot{\mathbf{Q}_{SAR}}[n])}_{\text{ternary result (+1/0/-1) } } $$ + +Eq. 11 introduces the proposed method for iteratively updating \\(\mathbf{W}_{SAR}\\) for the n\textsuperscript{th} sample using \\(\alpha\\) as fixed adjustment factor. \\(\dot{Q_{out}}\\) is the first order difference of the quantized output which is a function of the SAR \\(Q_{SAR}\\) and modulator \\(Q_{\Sigma\Delta}\\) outputs. The exact relation is expressed in Eq. 12. No multiplication is required here because whether a SAR bit has toggled is strictly Boolean and represented by \\(\dot{\mathbf{Q}_{SAR}}[n]\\). This leads to a ternary result with respect to the adjustment rule for incrementing or decrementing the estimated weights that can be implemented using 7 up/down counters of varying depth. In this case the MSB counter has a logical depth of 16 bits while the LSB uses 22 bits.} + +$$ Q_{out}[n] = \mathbf{Q}_{SAR}[n] \cdot \mathbf{W}_{SAR}[n] + 2^{-N} \mathbf{Q}_{\Sigma\Delta} \cdot\mathbf{W}_{FIR} $$ + +If we presume our \\(\Delta\Sigma\\) converter has ideal performance then $2^{-N} \mathbf{Q}_{\Sigma\Delta} \cdot\mathbf{W}_{FIR} = V_{IN}[n] - \mathbf{W}_{DAC}[n]$ which leads to \\(\dot{Q_{out}}\\) as:} + +$$ \dot{Q_{out}}[n] = \dot{V_{IN}[n]} + \dot{\mathbf{W}_{SAR}[n]} - \dot{\mathbf{W}_{DAC}[n]} $$ + +Eq. 13 reveals that during calibration the output will consist of two components. The first is due to the input as the ramp's rate of change \\(\dot{V_{IN}}\\) that is either increasing or decreasing. The second term results from an incorrect weight estimate on whichever SAR bit changed.} In fact depending on the sign of this error we know if the estimated weight needs to be larger or smaller. In essence Eq. 11 uniformly averages over all DNL errors to approach the correct weights. + +# 9 Circuit Implementation + +Using the foregoing results, the presented implementation targets a 12 bit resolution using \\(N=6\\) & \\(M=6\\) which should lie just on the inflection point of estimated area requirement curve. In particular we will present the configuration for a fully differential sensor array using analogue and digital supplies at 1.2 V and a commercially available 6-Metal \cmostech technology (AMS/IBM C18A6/7SF).} + +## 10 Loop Filter + +The loop filter topology used here is a second order feed forward architecture that is used extensively in CT modulators due to its reduced complexity and low distortion[^29][^28]. This particular structure reduces the number of summation nodes and digital feedback elements to minimise power consumption. The signal and noise transfer functions due the loop filter \\(H(s)=2^N (s^2+2 \omega_{bw} s)/\omega^2_{bw}\\) and the feedback factor $f\approx 2^{-N}$ are summarised in Eq. 14 & 15 where \\(\omega_{bw}\\) is the filter bandwidth in radians. The feedback \\(f\\) is determined by evaluating the capacitive coupling from \\(C_{\Delta\Sigma}\\) onto \\(V_{DAC}\\). Since \\(f\\) is quite small there is an apparent gain in the STF but not in the NTF. This gain is provided by increasing the bandwidth of the first stage by \\(2^{N}\\) which substantially diminishes the input referred noise from the second integrator and comparator.} Then using the requirements from Sec. 5 will allow the capacitors to be specified for this implementation as $f_{smp} (N+DC+2)/2=4V_{R} I_{B1}/(\eta U_{T} 2^{N} C_{L1})=2V_{R} I_{B2}/(\eta U_{T} C_{L2})$.} + +$$ NTF(s) = \frac{s^2}{s^2 + 2 \omega_{bw} s + \omega^2_{bw}} $$ + +$$ STF(s) = 2^{N}\frac{2 \omega_{bw} s + \omega^2_{bw}}{s^2 + 2 \omega_{bw} s + \omega^2_{bw}} $$ + +{{< figure src="/images/tcas2017/sch_lf.svg" title="Figure 9: Schematic level implementation of the switched loop filter using noise efficient complementary transconductors and a current mode summation circuit." width="500" >}} + +The transistor level implementation is shown in Fig. 9 where the switches \\(S_{\Delta\Sigma}\\) allow the filter to change its operation. The first stage uses a fully differential complementary or inverter-based transconductor that can tolerate small variations in input common mode fluctuation by \\(\pm\\)100 mV and this specific configuration exhibits an \\(NEF\approx1.6\\). The sizing of this complementary pair requires some attention regarding the capacitive loading on \\(V_{DAC}\\) due to the gate to drain capacitance of the transistors. In fact \\(C_{u}\\) needs to be considerably larger than this parasitic such that the open loop gain of the first integrator is not reduced and thereby diminishing filter performance.} The circuit is segmented into three sections; two analogue integrators and one summation stage. The first integrator will switch between resistive and capacitive loads. This stage will have the most demanding bandwidth requirement when providing pre-amplification during SAR quantization. Both integration capacitors are reset outside of the $\Delta \Sigma$ phase and the last two stages should achieve -40 dB HD3 for a \\(\pm\\)100 mV input signal which is derived from simulations [^24]. The common mode feedback on the two integrators uses linear mode devices that reference \\(V_{DD}/2\\). These transistors can be quite large and introduce considerable parasitics because of the large current dissipated in the first stage. To avoid a reduction in bandwidth, a sub-set of these gates are connected to the loading capacitor \\(C_{L1}\\) that is switched out during SAR conversion which retains the steady state common mode voltage.} The 1-bit quantization is realized using a dynamic latch where offset associated concerns should follow conventional wisdom for accurate SAR conversion. The diode connected load in the summing stage places the input common mode of the comparator close to \\(V_{DD}\\). This improves both the bandwidth and noise performance of the latch[^30].} + +## 11 Capacitive DAC + +A 7-bit fully differential binary weighted capacitive DAC is used to perform the SAR quantization. The single ended structure is shown in Fig. 10. The voltage scaling on the last conversion cycle reduces the number of capacitors needed and takes advantage of the reduced reference sensitivity for the last SAR conversion. Because calibration is performed with respect to \\(C_{\Delta\Sigma}\\) that references \\(V_{R}\\) the mismatch in the last SAR coefficient will also accommodate the mismatch in voltage reference.} The array is realized by precision top metal-on-metal capacitor devices which utilize M5-M6. A M4 \\(V_{CM}\\) shield is introduced to isolate this array from active analogue and digital circuitry placed below. While bottom plate sampling diminishes the effect of parasitics on \\(V_{DAC}\\), the split capacitor needs tuning according to the extracted parasitics on the LSB section particularly with respect to the shielding layer. The unit capacitor is 71 fF with 6\\(\times\\)6 \mmu m\\(^2\\) dimensions yielding 0.2% deviation of capacitor mismatch for a \\(3\sigma\\) confidence interval. This should allow a precision of 9 ENOB without calibration [^31] and will utilise all the top metal area needed for the sub-blocks placed below. + +{{< figure src="/images/tcas2017/sch_dac.svg" title="Figure 10: Single ended equivalent of the 7-bit split-capacitive SAR DAC using voltage scaling on the smallest weight. " width="500" >}} + +During sampling each input will be loaded by a total of 768 fF for an equivalent 52 \mmu Vrms sampling noise. This should indicate that the upper bound of maximum signal to noise and distortion ratio (SNDR) for this DAC is 78 dB. Also note that the INL characteristic of the SAR and comparator noise will inevitably lead to additional sources of quantization error which implies the \\(\Delta\Sigma\\) input range will correspondingly increase from its expected value. Moreover resolving a sampled input with a \\(\Delta\Sigma\\) modulator can lead to increased distortion due to idle tones. This is why the modulator should be designed such that signals that are -3 dB of the maximum \\(\Delta\Sigma\\) input range can still be adequately resolved. Fortunately comparing single bit modulators reveals second order feed-forward structures are substantially more capable of processing signals close to the full range input due to improved stability dynamics [^16]. This means the DAC mismatch requirements are less stringent and will not need a sub-binary weighting or additional calibration capacitors to minimize the sources of excess residue.} The simpler binary weighted structure will allow good baseline matching for the unit capacitors with the minimum number of elements in the DAC. Moreover introducing the split capacitor in addition to the \\(V_{cm}\\) switching method dramatically reduces the total switching energy to the extent that it is dominated by the oversampling phase. Particularly when multiple data converters are operated in parallel the excessive capacitive switching raises a concern for high frequency supply noise of the reference voltage that is outside the LDO bandwidth. The anti-aliasing provided by the loop filter will partly reject this component as a result of opting for a CT implementation. The \\(\Delta\Sigma\\) feedback will dissipate at most 77 fC every cycle which needs to be partly absorbed by decoupling capacitors local to the ADC. High density MOS capacitors are therefore introduced to load the reference voltage by 20 pF per ADC. The reduced switching noise should represent a clear advantage over switched capacitor modulators. An improvement over the conventional SAR may only be expected when calibration overhead is unavoidable because the sampling noise constraint makes energy dissipation in SAR switching mostly indifferent to its resolution. + +## 12 FIR Filtering + +Decimation of the \\(\Delta\Sigma\\) bit stream of incremental topologies finds the application of FIR filters particularly suitable. This is in part because resetting the integrators for each sample and discards residual components from the previous conversion and the corresponding group delay requirement can limit the IIR filter design.} Moreover sharing FIR filter coefficients with multiple ADCs reduces the hardware requirements to a shared lookup table with individual accumulators for each modulator. Using an \\(OSR\\) of 24 implies \\(N+DC+1=31\\) additions are needed per sample where a second order CIC filter would need at least \\(N+2DC+3=57\\) additions per sample for a full evaluation and four times the number of registers[^32]. From Sec. \ref{sec:model} we know that the register depth \\(R_{D}\\) should be 16 bits while the FIR coefficient precision needs to be 8 bits.} The application of a symmetric FIR window also assists with a number of circuit considerations for rejecting noisy aggressors near \\(f_{bw}\\)[^8]. Supply noise is a typical culprit but it may be less obvious that the FIR also reduces the sensitivity due to the second integrator's offset when the quantization mode switched.} Hanning or raised cosine FIR windows are known to provide exceptional aliasing particularly when applied to sample limited \\(\Delta\Sigma\\) decimation [^33]. Using a general family of raised cosine windows[^34] a configuration is proposed here that matches the noise shaping of the loop filter order (\\(L\\)) with that of the FIR side-lobe roll-off by defining its coefficients as:} + +$$ FIR[n] = cos^{K}\left(\frac{\pi n}{OSR+1}-\frac{\pi}{2}\right) $$ + +The factor \\(K\\) in Eq. 16 determines the spectral characteristics of the filter similar to that of the kaiser windows. The rapid side-lobe roll-off is related to \\(K\\) as \\(30K \\)dB/Dec with the first zero location at \\(\pi(1+K/2) f_{smp}\\). Because the quantization noise is shaped in relation to \\(L\\) at \\(20L \\)dB/Dec[^5], \\(K\\) can be defined as \\(K=2/3 L\\). This leads to a near uniform quantization noise profile with a reduced transition band from better pole placement. The \\(K\\)-factor dependent frequency characteristics are shown in Fig. 11 for an \\(OSR=16\\) applied to the output of a second order modulator. Note that when \\(K=2\\) the FIR is equivalent to that of a Hanning window. The overall system transfer function \\(Sys(z)\\) can be analysed in the z-domain using a bilinear transform of the loop filter \\(H(s)\\) and convolving it with that of the FIR response. To see how well decimation is achieved we compare the decimation performance to that of an ideal filter .} + +{{< figure src="/images/tcas2017/QFIR.svg" title="Figure 11: Overall noise shaping profile of the modulator and FIR in cascade for \\(K=2\\) and \\(K=1.33\\)." width="500" >}} + +$$ S_Q^2 = \frac{ 2\pi^{2L} }{3(2L+1)(OSR)^{2L+1} } $$ + +Eq. 17 introduces the expected in-band quantization noise power \\(S_Q^2\\) from analytic relations[^35] which assume an ideal brick-wall filter with a cut off frequency at \\(f_{smp}/2\\) that is not limited in any way.} Similarly integrating over the resulting power densities in \\(Sys(z)\\) will indicate the expected quantization noise from the proposed configuration. Comparing these two results will indicate how effectively the quantization noise is rejected by the FIR filter.} The noise excess is shown in Fig. 12 as a function of OSR and filter order. This shows that using the proposed window results in loss smaller than 0.5 bits.} Also notice that we do not pay special attention to how the \\(\Delta\Sigma\\) quantization noise folds onto the signal band. After the signal is convolved by the SAR quantization process the residue no longer shares the same structure as the input signal and therefore better in band decimation performance will not lead to better in band SNR.} + +{{< figure src="/images/tcas2017/OBT.svg" title="Figure 12: Quantization noise suppression based on numerical simulations and Eq. 17 and the respective precision loss for varying \\(OSR\\)." width="500" >}} + +# 13 Measured Results + +{{< figure src="/images/tcas2017/chip_micro.svg" title="Figure 13: Microphotograph of the 64 channel neural recording system showing two 32 channel macros used in parallel with integrated power management and digital processing.}" width="500" >}} + +{{< figure src="/images/tcas2017/fab_exhibit.svg" title="Figure 14: Fabricated \\(\Delta\Sigma\\)SAR prototype showing a) an isolated test ADC structure used for characterization b) a close up micrograph showing the capacitive DAC and top metal c) the ADC layout with annotated sub-blocks. The SAR capacitors are highlighted in blue and numbered in term of which SAR bit they represent. The analogue MOS and MIM capacitors are highlighted in red showing the filter capacitors L1 & L2 and the decoupling capacitors.}" width="500" >}} + +A chip micrograph is shown in Fig. 13 depicting the 64 channel instrumentation system with die size of 6.2 mm2. This configuration uses two macros each of which integrates eight ADCs together with the DSP in a tiled fashion to post-process the recordings from 32 instrumentation amplifiers. In fact the architecture may be scaled to accommodate more channels by virtue of the pipelined architecture that distributes the processing capacity. The measured results presented here are taken from an isolated test structure that allows detailed characterization without overhead from the whole system.} The physical implementation of the \\(\Delta\Sigma\\)SAR sub-block is shown in Fig. 14 which is 96\mmu m\\(\times\\) 164\mmu m in size. Because the DSP is assisted by a specialized execution unit that also performs neural signal decomposition only the digital accumulator is included in this figure. The active components inside the modulator contribute to a small portion to the overall system. Instead the most demanding layout consideration is with regard to the switches driving the capacitive DAC. Even though the capacitance is not too large, the switch resistance in \\(\Delta\Sigma\\) mode can introduce a pole leading to excess loop delay that could result in performance degradation [^36]. + +{{< figure src="/images/tcas2017/INL2.svg" title="Figure 15: Measured INL of the ADC before and after calibration with 2.4 V differential amplitude. " width="500" >}} + + +{{< figure src="/images/tcas2017/CALC.svg" title="Figure 16: Convergence of DNL rms and peak to peak values during calibration subject to a 90 Hz triangular waveform." width="500" >}} + +Initial ADC characterization used a low-frequency 180 Hz tone at half to the full input range where the comparator bit stream was directly acquired off-chip for post-processing. This allowed the proposed calibration mechanism to be compared with more robust methods. In fact when using more elaborate numerical optimization methods to adjust \\(\mathbf{W}_{SAR}\\) the THD only showed 2 dB improvement although convergence is typically much faster. Both testing and calibration waveforms were generated off-chip using an Agilent 33120a with additional bandpass filtering. The measured INL characteristics are shown in Fig. 15. The calibration method decreases the SAR nonlinearity by a factor of 10. As shown in Fig. 16 the main drawback of this method is that in order to reject noisy perturbations the \\(\alpha\\) rate must be small amounting to slow convergence on the order of 106 quantization cycles or around 10 seconds. The DAC used for generating the ramp signal will need to be more accurate than the ADC precision to allow correct calibration. On the other hand instead of using a more powerful centralized DSP unit to perform tuning, this system allows all channels to calibrate simultaneously resulting in a speed up for multichannel systems that can share a single high resolution DAC.} The discontinuities visible in this trend result from the fitting method used to calculate DNL as a function of time which is not very consistent. + +{{< figure src="/images/tcas2017/Spectrum2.svg" title="Figure 17: Measured ADC performance showing the spectral characteristics of a) SAR residue at the output of the \\(\Delta\Sigma\\) and b) the full precision output which has a SNDR of 66.8 dB. This recording was taken using a 2.35 Vpp 95 kHz input tone sampled at 200 kHz .}" width="500" >}} + +{{< figure src="/images/tcas2017/QRES.svg" title="Figure 18: FIR output over time due to a 1.2 Vpp 180 Hz input tone showing the quantized residue after SAR conversion. " width="500" >}} + +{{< figure src="/images/tcas2017/MMO.svg" title="Figure 19: Measured quantization noise spectrum of the second order \\(\Delta\Sigma\\) modulator that is clocked at 7 MHz averaged over 103 conversions with an OSR of 24.}" width="500" >}} + +Fig. 17 shows the spectral characteristics of the ADC after the capacitor weights have been estimated with 16 bit precision together with the SAR residue that can be obtained by only taking the decimated modulator output. This illustrates that SAR residue has its spectral power distributed over the entire bandwidth at multiple tones. This wideband quantization 'noise' will in effect present dithering on modulator's nonlinearity before appearing at the output.} Fig. 18 shows the signal resolved by the modulator as a function of time. Interestingly the polarity in residue will directly correspond to the polarity of the sampled input signal because swapping the reference voltage on the capacitive DAC will imply a successive approximation while maintaining correspondingly positive or negative residues. Then by performing a Fourier transform on the measured modulator output for each conversion separately we can evaluate the noise shaping characteristic of the loop filter. This result is shown in Fig. 19 which follows closely to the expected second order noise shaping.} + +{{< figure src="/images/tcas2017/SDOS.svg" title="Figure 20: Measured \\(FOM_{S}\\) dependency for varying OSRs but keeping a 7 MHz system clock frequency for a 10\\( kHz\\) 2.4 Vpp input tone." width="500" >}} + +{{< figure src="/images/tcas2017/FDP.svg" title="Figure 21: Measured SNDR dependency for varying input frequency for a 2.35 Vpp input tone." width="500" >}} + +Table 1: Comparison of State-of-The-Art ADC specifications +| **Parameter** | Unit | [^18] | [^23] | [^7] | [^13] | [^38] | [^39] | [^40] | [^41] | [^6] | **This Work** | +|----|----|----|----|----|----|----|----|----|----|----|----| +| **Year** | | 2007 | 2014 | 2015 | 2015 | 2016 | 2016 | 2016 | 2016 | 2017 | **2017** | +| **Tech.** | [nm]| 180 | 65 | 180 | 65 | 110 | 65 | 180 | 55 | 180 | **180** | +| **Topology** | | SAR | NSSAR | IADC | NSSAR | SAR | SAR | IADC | NSSAR | IADC | \textbf{(\Delta\Sigma)SAR} | +| **Supply-V** | [V] | 1 | 0.8 | 1.8 | 0.8 | 0.9 | 0.4 | 1.8 | 1.2 | 1.5 | **1.2** | +| **Supply-I** | [\mmu A] | 25 | 1.7 | 19 | 151 | 27 | 1.8 | 16.4 | 13.1 | 23 | **4.3** | +| **Speed** | [S/s] | 100 k | 32 k | 8 k | 6.25 M | 1 M | 1 k | 313 k | 4 k | 2 k | **200 k ** | +| **ENOB** | [bits] | 10.55 | 12.4 | 12.3 | 9.35 | 11.0} | 7.81 | 9.3 | 15.7 | 16.1 | **10.8**} | +| **SNDR** | [dB] | 65 | 76 | 75 | 58 | 67 | 49 | 57 | 96 | 97 | **67**} | +| **Area** | [mmĀ²] | 0.63 | 0.18 | 0.33 | 0.012 | 0.097 | 0.013 | 0.002 | 0.072 | 0.5 | **0.016 ** | +| **FOMW** | [fJ/conv] | 165 | 8 | 862 | 14.8 | 11.7 | 3.19 | 151 | 73.8 | 320 | **14**} | +| **FOMS** | [dB] | 156 | 177 | 159 | 163 | 170 | 137 | 154 | 180 | 175 | **170**} | + + +In Table 1 the performance is summarized and state-of-the-art noise shaping ADC structures are compared. This work achieves exceptional compactness for the 12 bit target resolution particularly in relation to the conversion efficiency [^37]}. The measured power dissipation is about 5 \mmu W of which simulations indicate 40% is dissipated in the loop filter and 23% in capacitive switching. Note that power dissipation from the look up table is not included in this figure. Fig. 20 presents the measured SNDR and \\(FOM_{W}\\) for varying oversampling ratios. During calibration the OSR was doubled to gain 3 dB in precision while the typical operation uses an \\(OSR\\) of 24.} The total conversion uses an additional 11 cycles for SAR and sampling phases to give the resulting 200 kS/s speed for a 7 MHz system clock. We also show the measured SNDR for varying input frequencies in Fig. 21. This shows that maximum precision is maintained for signals below 20 kHz but also shows some degradation at frequencies near the maximum input bandwidth. The main experimental difficulty resulting from the proposed configuration is that the filter characteristics are closely tied to the reference voltage in a practical setting. On occasion it is useful to give additional voltage overhead for aggressive digital and analogue systems to accommodate process voltage and temperature variance. However in this case the biasing circuit will need extra tuning parameters to keep the modulator's linearity consistent while adjusting the reference voltage. Multi channel systems can generally accommodate complex tuning for all ADCs to eliminate wafer/process level variations without substantial overhead since this functionality is already needed by instrumentation circuits to perform precise filtering. The power management block in Fig. 13 provides 12 bit digital trimming on the ADC reference voltages and bias currents such that most of the off-set can be accommodated although this is performed externally on the test structure.} + + +# 14 Conclusion + +A novel 12-bit analogue-to-digital data converter has been proposed that uses SAR & \\(\Sigma\Delta\\) quantization schemes to realize a compact and ultra low power data converter for a 64 channel neural sensor system. Using an efficient Gm-C filter, compact 7 bit binary DAC, and optimized FIR decimation this work aims to eliminate the circuit complexity from DEM and increase power efficiency which is highly desirable for biomedical sensors.} A prototype fabricated in \cmostech demonstrates 10.8 ENOB precision at the nyquist frequency with a state-of-the-art 0.016 mmĀ² silicon footprint and is capable of resolving full scale signals at 200 kS/s.} The proposed techniques are appropriate for a variety of sampling frequencies making this configuration applicable to numerous other applications that require aggressive ADC miniaturization. In addition a calibration technique suitable for large sensor arrays is presented that takes advantage of the two step quantization scheme to calibrate multiple ADCs simultaneously.} + +# 15 Acknowledgement + +The authors would like to thank Nicolas Moser and the reviewers for helpful comments and assistance with improving this manuscript. + +# Refernces: + +[^35]: B.E. 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Chandrakasan, ''An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes,'' IEEE Journal of Solid-State Circuits, vol.42, no.6, pp. 1196--1205, June 2007. +[^37]: K.Lee, Y.Yoon, and N.Sun, ''A scaling-friendly low-power small-area $\Delta\Sigma$ ADC with VCO-based integrator and intrinsic mismatch shaping capability,'' IEEE Transactions on Emerging and Selected Topics in Circuits and Systems, vol.5, no.4, pp. 561--573, Dec 2015. diff --git a/content/publications/2017/a-0-5-v-time-domain-instrumentation-circuit-with-clocked-and-unclocked-rds-operation.md b/content/publications/2017/a-0-5-v-time-domain-instrumentation-circuit-with-clocked-and-unclocked-rds-operation.md new file mode 100644 index 0000000..1fe7522 --- /dev/null +++ b/content/publications/2017/a-0-5-v-time-domain-instrumentation-circuit-with-clocked-and-unclocked-rds-operation.md @@ -0,0 +1,111 @@ +--- +title: "A 0.5 V time-domain instrumentation circuit with clocked and unclocked Ī”Ī£ operation" +date: 2017-05-28T15:26:46+01:00 +draft: false +toc: true +math: true +type: posts +tags: + - publication + - instrumentation + - CMOS + - time-domain + - circuit +--- + +Lieuwe B. Leene, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +This paper presents a time-domain instrumentation circuit with exceptional noise efficiency directed at using nano metre CMOS for next generation neural interfaces. Current efforts to realize closed loop neuromodulation and high fidelity BMI prosthetics rely extensively on digital processing which is not well integrated with conventional analogue instrumentation. The proposed time-domain topology employs a differential ring oscillator that is put into feedback using a chopper stabilized low noise transconductor and capacitive feedback. This realization promises better digital integration by extensively using time encoded digital signals and seamlessly allows both clocked & unclocked \\(\Delta\Sigma\\) behavior which is useful on-chip characterization and interfacing with synchronous systems. A 0.5 V instrumentation system is implemented using a 65 nm TSMC technology to realize a highly compact footprint that is 0.006 mmĀ² in size. Simulation results demonstrate an excess of 55 dB dynamic range with 3.5 \mmu Vrms input referred noise for the given 810 nW total system power budget corresponding to an NEF of 1.64. + +# 2 Introduction + +Recent efforts to realize brain machine interfaces (BMI) target fully integrated neural recording systems that use advanced CMOS technologies to enable real time diagnostics for hundreds of channels simultaneously. This emerging trend is predominately motivated by the extensive use of digital techniques applied to robust therapeutic feedback for closed-loop neuromodulation and signal compression/feature extraction in high channel count BMIs for prosthetic motor control[^1]. However there are a growing number of challenges associated with integrating analogue instrumentation for these digital systems due to the loss in analogue transistor characteristics which has motivated the use of time domain (TD) analogue [^2]. TD systems encode information with respect to the timing intervals of asynchronous digital signals to perform mixed signal processing while extensively using standard logic and oscillators that do not suffer from analogue complications. Many recent publications will indicate the potential for exceptional dynamic range like in the recording system of [^3] or highly compact instrumentation like the potentiostat in \cite{VCO_SENSE2}. We argue that a key advantage for these systems is that supply voltage is utilized more effectively from a fundamental aspect without being impeded by linearity. This allows an aggressive reduction in power dissipation. Furthermore realizing band limiting filters outside the instrumentation loop prevents KT/C relations from limiting the compactness of the system. + +{{< figure src="/images/iscas2017/TDI.svg" title="Figure 1: TD system architecture for BMI systems where both the instrumentation and processing sub-blocks manipulate time-encoded signals to perform feature extraction from bio-signal recordings. This paper will present the instrumentation sub-system." width="500" >}} + +This work presents a TD instrumentation topology for neural recording applications that targets ultra-low power operation and a highly compact implementation for miniaturized multichannel systems. Based on previous work in [^4], which uses a third order feedback loop to digitize the signal asynchronously, this realization exhibits only one dominant pole and thus reduces the resources spent on achieving stability. While [^4] can achieve a smaller footprint than the topology presented here the feed-forward structure cannot achieve high dynamic range as the high frequency quantization noise and out of band distortion from the counter cannot be suppressed without additional filtering. Our current efforts aim to realize the system architecture illustrated in Fig. 1. This approach aims to use the efficiency of TD processing techniques to extract features from neural recordings which promise an order of magnitude improvement over conventional implementations [^5]. In fact such a TD approach has already been applied to acquire wireless radio signals with a versatile activity dependent power dissipation [^6]. However there will be numerous scenarios where these asynchronous structures must interface with clocked systems to effectively perform calibration or other discrete time analysis. For this reason we specifically consider how the class of circuits presented here and in [^5] can seamlessly realize a more traditional clocked \\(\Delta\Sigma\\) oversampling loops. This is relevant because time encoded signals have a very broad bandwidth of several GHz making it unreasonable to characterize or communicate a large number of them off chip. Finding effective means to convert such time-encoded signals to a clocked and quantized equivalent is crucial for fully integrated systems. This paper is organized as follows; First the basic structure of the proposed circuit is introduced in Sec. \ref{Sec:architecture} which motivates the general topology chosen here. Then in Sec. \ref{Sec:circuit} we shall detail the circuit level implementation and identify important design considerations. Finally Sec. \ref{Sec:simulation} presents the preliminary simulation results which leads to the conclusions in Sec. \ref{Sec:conclusion}. + +# 3 Time-Domain Instrumentation Architecture + +The proposed configuration is shown in Fig. 2 as a single ended equivalent of the fully differential system implemented here. The neural signals picked up on VIN include local field potentials of several millivolt and extracellular action potential from nearby neural tissue with 100 microvolt amplitudes where the total bandwidth of interest here is from near DC to 6 kHz[^1]. Using a reference electrode these components are first chopped to a higher frequency fchp at 100 kHz. This is then passed into a capacitive network that allows the digital output signal Q to be directly feedback onto the input after using a XOR gate realize chopper modulation. The intermediate node VG is tapped off to a transconductive cell which advances/recedes the phase of a multi stage ring oscillator structure after the signal is chopped back to the base band. By referencing the phase of this oscillator to another oscillator we can realize the time-encoded digital signal that encodes the phase difference \pphi\dDelta as pulse width modulated information. Then we may either quantize this signal with a register in the time domain or simply buffer it onto Q to provide asynchronous feedback without time quantization. Now the near-DC aggressors such as off-set and flicker noise from the transconductor are neutralized using the feedback loop through Rp which presents a high pass response for signals below the chopper frequency on node VG. If we simply take the transconductor, oscillator, and digital logic to represent some kind of integrator then the high level instrumentation topology reduces to a relatively simple chopper stabilized circuit. Finally in the synchronous case where time is quantized, the output Q is passed into a second order cascaded integratorā€“comb (CIC) filter that decimates oversampled signals into discrete samples. Otherwise \pphi\dDelta is simply passed onto other TD processing structures which is outside the scope of this paper. + +{{< figure src="/images/iscas2017/TDA.svg" title="Figure 2: The proposed chopper stabilized instrumentation system that uses a ring oscillator to realize TD based first order integration with respect to the output phase difference which is then quantized in time and decimated using a CIC filter. " width="500" >}} + +We highlight the fact that the high pass feedback uses the output referred signal. This has a profound effect on how the noise profile of Rp appears at the chopper frequency when referred to the input. In fact if Rp was tied to a biasing voltage to set VG then resistor's noise will have a rms power of \\(āˆš{kT/C_{IN}}\\) at the input that is up modulated and will corrupt the linearity of the integrator. This can be very substantial because CIN is reduced to 100 fF in order to boost the input impedance that depends on the chopping frequency as RIN=1/(fchpCIN). This feedback configuration reduces this noise component as a function of closed loop gain Acl which is maximized as we realize all the necessary signal gain in a single analogue processing stage. Moreover the chopper stabilization allows an aggressive reduction on input transistor size which is important for reducing parasitics on the node VG. Any parasitic loading here can prevent further reduction in CIN because it would degrade the noise performance. + +The PWM signals \pphi\dDelta, Q, and X in Fig. 2 are illustrated in bold because they represent multiphase time-encoded signals by simultaneously taping off multiple phases inside the oscillator and using them in parallel. The capacitive feedback network sums these signals to acquire an analogue equivalent where the number of amplitude quantization levels is 1+N for N phases used in parallel. This is an important point because the error signal on VG is a function of the supply voltage as VDD/(N Acl) which must lie well within the linear range of the transconductor. Adding to the fact that supply noise is also inversely proportional to Acl reveals that although we can reduce power by reducing VDD, this parameter is tightly coupled to other performance requirements. In fact using the definition of noise efficiency factor NEF from [^7] one can derive the following expression to predict the system power Psys for noise limited systems: + +$$ P_{sys} = V_{DD} \omega_{3dB} \frac{kT U_T}{e^2_{in}} NEF^2 $$ + +Eq. 1 uses \\(\omega\\)3dB, kT, UT, and eĀ²in as the signal bandwidth in radians, Boltzmann energy, thermal voltage, and input referred noise power. This expression ignores any constraints due to sampling noise or capacitor sizing that could suffer as the supply voltage decreases. However it clearly illustrates our motivation for reducing power through VDD which is allowed in this fashion only if no band limiting behavior is required from the instrumentation loop. In fact an important contribution here is that a near ideal NEF is achieved for the TD structure using the proposed implementation. + +# 4 Circuit Implementation + +{{< figure src="/images/iscas2017/TDS.svg" title="Figure 3: Transistor level implementation of a) the low noise amplifier and b) high pass filter circuit that removes flicker noise and off-set. A legend is presented in gray showing how a) & b) relate to Fig. 2 and the chopper in a) is omitted for clarity." width="500" >}} + +The fully differential analogue part of this system is shown in Fig. 3. Here two analogue structures are shown, one for signal amplification that integrates on the differential phase \pphi\dDelta which we shall consider the amplifier. The second structure presents the pseudo resistor that rejects the low frequency aggressors that are being up modulated onto the output Q which we will refer to as the high pass filter. The amplifier is composed of a complementary transcondutor to boost the noise efficiency and is loaded by two ring oscillators that are biased with a current IX that is 16x smaller than IB such that the input referred noise from the oscillator to VG is greatly reduced. A XOR gate is used to compute the phase difference of the two oscillators because it does not have a discontinuity in its phase to PWM characteristic. The floating ground of both oscillators is tied together to reject common mode noise and minimize any coupling to the analogue power supplies. + +Actually, the high pass filter not only performs feedback but also determines the common mode input voltage on VG. This mechanism is used to set the common mode on VX to VCM using the transistors M5-M8. This is important because the oscillator needs to run in the middle of the rail to allow more efficient conversion from the small internal voltage oscillation of 300 mV to a digital signal with full swing. The reason a current DAC is used to drive the pseudo resistors is because the linearity of these devices is important and Rp can only handle \\(\pm\\)100 mV if simple diode connected devices are used. This is why CL is introduced to provide some filtering and minimize distortion from the high frequency PWM feedback. Note that because all transistors will use subthreshold operation the threshold voltage VTH difference between the input PMOS pair M3-M4 and the high VTH devices M9-M10 will represent voltage headroom of the PMOS current bias which should at least be 100 mV. + +Now there is quite a significant impact from using an oscillator as load for the amplifier structure in this particular fashion. It may be obvious that there are no high impedance analogue nodes in this configuration that could introduce undesirable poles. But more importantly we do not need to provide extra voltage headroom or a second gain stage to let our output signal vary with maximum amplitude. This proposed implementation allows both simplicity and high power efficiency. In this case the oscillator mostly reuses the VTH voltage headroom needed by the NMOS input transistors. This raises an interesting question; what limits the required voltage headroom for this circuit? Typically the complementary structure necessitates that the source drain voltage of the current bias transistors and differential pairs is sufficient to provide good channel resistance. However there is another component with regard to the noise generated by the oscillator that should be considered in terms of the oscillator voltage overhead VRO. Consider the noisy charge induced as sampling noise from one of the oscillators on each inverter gate capacitance Cgate before the up/down transition as residue from the previous cycle. This can be represented by an equivalent noisy current source **i**Ā²smp using the oscillator frequency fosc as formulated in Eq 2. + +$$ i^2_{smp} = 2N f^2_{osc} kT C_{gate} $$ + +Referring this component to VG as input referred voltage noise equivalent **v**Ā²smp requires fosc to be represented in terms of total charge dissipated each cycle fosc=IX/(2N VRO Cgate). Taking the transconductance of the amplifier approximately as Gm\\(\approx\\)2IB/(\\(\eta\\) UT) will resolve the expression as in Eq 3 using \\(\eta\\) and UT as slope factor and thermal voltage. + +$$ v^2_{smp} = \frac{i^2_{smp}}{Gm^2} = \frac{2 kT}{P_{osc}} \left( \eta U_T \frac{I_X}{2 I_B} \right)^2 $$ + +This result may be surprising in some sense because indicates the oscillator should dissipate a strict amount of energy to avoid this noise component from being significant. The only way to do this is by increasing the VRO because increasing its bias current IX will in fact degrade the input referred noise. Also notice that the actual capacitive load of the oscillator does not impact the thermal noise floor although it is directly related to the bandwidth of operation. In this particular case we configured the oscillation frequency to be around 300 kHz after optimization which implies that the effective frequency is around 1.5 MHz given the 5 phases. For this reason when the CIC filter is enabled we use a 3 MHz system clock for time quantization and an over sampling ratio of 128. This implies that the instrumentation bandwidth will be limited to 11 kHz sampled at exactly 22 kS/s. + +# 5 Simulation Results + +The presented implementation was fabricated using the commercially available TSMC 65 nm CMOS LP MS RF technology (1P9M 6X1Z1U RDL). This system can operate at 0.5 V by extensively using the different VTH process options for the standard transistor. Fig. 4 shows the floor plan and final fabricated device and the MIM capacitors covering the active area. A compact configuration was achieved with a 0.006mmĀ² footprint where future work could potentially share the biasing and digital filter resources. Our preliminary results consist of post layout noise simulations that should have a good degree of precision for predicting the expected bench top measurements. Fig 5 shows the ring oscillator output with 200 mV amplitude in the middle of the rail that is fed to the XOR gate to produce the full swing digital signal \pphi\dDelta. Fig 6 shows the output of the circuit in the frequency domain before & after decimation by the CIC filter. We can observe that linearity is quite easily achieved due to the exceptional loop gain from the TD integrator and because all analogue nodes exhibit a small signal swing. The performance summary in Table 1 compares this work to recently published instrumentation systems using the 65nm or 90nm technology node. Notice that a comparable noise performance is achieved for a similar if not better input dynamic range while the NEF & area characteristics are respectable given the extra capability that signal quantization is also performed. The input resistance due to chopping for this configuration is estimated to be 57 M\\(\Omega\\) which will be sufficient for most integrated neural recording electrodes. + +{{< figure src="/images/iscas2017/LAY.svg" title="Figure 4: The floor plan and micro photograph of the fabricated TD instrumentation prototype. " width="500" >}} + +{{< figure src="/images/iscas2017/DIG2.svg" title="Figure 5: Simulation results showing a) the two ring oscillator outputs & b) the respective phase difference signal due to a 5 mVpp sinusoidal signal at 2 kHz at the input of the instrumentation system." width="500" >}} + +{{< figure src="/images/iscas2017/SPC2.svg" width="500" >}} +{{< figure src="/images/iscas2017/SPC.svg" title="Figure 6: Spectral characteristics of a) the \\(\Delta\Sigma\\) modulator and b) the CIC filter output due to a 2 kHz 5 mVpp sinusoidal input showing a precision of 54.8 dB SINAD and no visible harmonics due to distortion." width="500" >}} + +Table 1: Performance summary and comparison with state of the art. +| Specification | This Work | [^8] | [^9] | [^10] | +|----|----|----|----|----| +| Modality | Time | Volt. | Volt. | Volt. | +| Technology | 65nm | 90nm | 65nm | 65nm | +| Supply [V] | 0.5 | 1 | 1 | 1 | +| Supply [A] | 2.65\mmu (\dagger) | 2.85\mmu | 1**n** | 3.28\mmu | +| Gain [dB] | 46 | 59 | 32 | 52 | +| Bandwidth [Hz] | 11 **k** | 10.5 **k** | 370 | 8.2 **k** | +| SINAD [dB] | 53 | (>)40 | 57 | (>)40 | +| IRN [Vrms] | 3.8\mmu | 3.04\mmu | 26\mmu | 4.13\mmu | +| NEF | 2.2 | 1.93 | 2.1 | 3.19 | +| Area [mmĀ²] | 0.006(\star) | 0.137 | 0.168(\star) | 0.042 | +\\(^\star\\) Includes ADC area. \\(^\dagger\\) Includes axillary and biasing circuits. + +# 6 Conclusion + +This work realizes a chopper stabilized \\(\Sigma\Delta\\) modulator right at the sensor interface using a time-domain topology for ultra low voltage operation. The proposed oscillator based instrumentation circuit addresses a number of the challenges associated with instrumentation using nano metre CMOS technologies. This system has a power budget of 810 nW and a compact silicon foot print of 0.006 mmĀ². Moreover this system can achieve a NEF of 1.64 while including the power dissipation due to quantizing the signal with 8.8 effective number of bits at 22 kS/s. + +# 7 Acknowledgment + +This work was supported by EPSRC grants EP/K015060/1 and EP/M020975/1. + +# Refernces: + +[^1]: H.Kassiri etal., ''Battery-less tri-band-radio neuro-monitor and responsive neurostimulator for diagnostics and treatment of neurological disorders,'' IEEE J. Solid-State Circuits, vol.51, no.5, pp. 1274--1289, May 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2528999 +[^3]: W.Jiang etal., ''A Ā±50mv linear-input-range vco-based neural-recording front-end with digital nonlinearity correction,'' in IEEE Proc. ISSCC, January 2016, pp. 484--485. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7418118 +[^2]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational amplifiers and their application to continuous-time filters in nanoscale cmos,'' IEEE J. Solid-State Circuits, vol.49, no.12, pp. 2758--2772, December 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2354641 +[^6]: M.Kurchuk etal., ''Event-driven ghz-range continuous-time digital signal processor with activity-dependent power dissipation,'' IEEE J. Solid-State Circuits, vol.47, no.9, pp. 2164--2173, September 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2203459 +[^10]: K.A. Ng and Y.P. Xu, ''A low-power, high cmrr neural amplifier system employing cmos inverter-based otas with cmfb through supply rails,'' IEEE J. Solid-State Circuits, vol.51, no.3, pp. 724--737, March 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2512935 +[^9]: P.Harpe etal., ''A 0.20$ $mm$^2$ 3$ $nw signal acquisition ic for miniature sensor nodes in 65 nm cmos,'' IEEE J. Solid-State Circuits, vol.51, no.1, pp. 240--248, Jan 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2487270 +[^8]: T.Yang and J.Holleman, ''An ultralow-power low-noise cmos biopotential amplifier for neural recording,'' IEEE Trans. Circuits Syst. II, vol.62, no.10, pp. 927--931, Oct 2015. [Online]: http://dx.doi.org/10.1109/TCSII.2015.2457811 +[^7]: M.S.J. Steyaert and W.M.C. Sansen, ''A micropower low-noise monolithic instrumentation amplifier for medical purposes,'' IEEE J. Solid-State Circuits, vol.22, no.6, pp. 1163--1168, December 1987. [Online]: http://dx.doi.org/10.1109/JSSC.1987.1052869 +[^4]: M.Elia, L.B. Leene, and T.G. Constandinou, ''Continuous-time micropower interface for neural recording applications,'' in IEEE Proc. ISCAS, May 2016. +[^5]: L.B. Leene and T.G. Constandinou, ''A 0.45v continuous time-domain filter using asynchronous oscillator structures,'' in IEEE Proc. ICECS, December 2016, pp. 49--52. [Online]: http://dx.doi.org/10.1109/ICECS.2016.7841129 diff --git a/content/publications/2017/circuit-design-considerations-for-implantable-devices.md b/content/publications/2017/circuit-design-considerations-for-implantable-devices.md new file mode 100644 index 0000000..427187d --- /dev/null +++ b/content/publications/2017/circuit-design-considerations-for-implantable-devices.md @@ -0,0 +1,14 @@ +--- +title: "Circuit Design Considerations for Implantable Devices" +date: 2017-11-15T15:26:46+01:00 +draft: true +toc: true +math: true +type: posts +tags: + - chapter + - instrumentation + - CMOS + - biomedical + - circuits +--- diff --git a/content/publications/2017/microwire-cmos-integration-of-mm-scale-neural-probes-for-chronic-local-field-potential-recording.md b/content/publications/2017/microwire-cmos-integration-of-mm-scale-neural-probes-for-chronic-local-field-potential-recording.md new file mode 100644 index 0000000..caa2da2 --- /dev/null +++ b/content/publications/2017/microwire-cmos-integration-of-mm-scale-neural-probes-for-chronic-local-field-potential-recording.md @@ -0,0 +1,13 @@ +--- +title: "Microwire-CMOS integration of mm-scale neural probes for chronic local field potential recording" +date: 2017-10-19T15:26:46+01:00 +draft: true +toc: true +math: true +type: posts +tags: + - publication + - instrumentation + - packaging + - biomedical +--- diff --git a/content/publications/2017/time-domain-processing-techniques-using-ring-oscillator-based-filter-structures.md b/content/publications/2017/time-domain-processing-techniques-using-ring-oscillator-based-filter-structures.md new file mode 100644 index 0000000..d5dffd1 --- /dev/null +++ b/content/publications/2017/time-domain-processing-techniques-using-ring-oscillator-based-filter-structures.md @@ -0,0 +1,252 @@ +--- +title: "Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures" +date: 2017-06-07T15:26:46+01:00 +draft: false +toc: true +math: true +type: posts +tags: + - publication + - CMOS + - circuits + - time-domain +--- + +Lieuwe B. Leene, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +The ability to process time-encoded signals with high fidelity is becoming increasingly important for time domain (TD) circuit techniques that are used at advanced nanometre technology nodes. This work proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation (PWM) encoded signals and makes extensive use of digital logic, enabling low voltage operation. First and second order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modelled precisely to realise more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65 nm CMOS technology to realise a 4\\(^{th}\\) order lowpass Butterworth filter. The system utilises a 0.5 V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73 nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio (SNDR) of 53 dB with a narrow 5 kHz bandwidth resulting in an figure-of-merit (FOM) of 8.2 fJ/pole. With this circuit occupying a compact 0.004 mmĀ² silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters whilst additionally offering direct integration with digital systems. + +# 2 Introduction + +Modern digital architectures and energy constrained devices are being increasingly challenged by device variability and probabilistic computation that are incompatible with today's digital paradigm [^1]. In contrast, many biological processes such as the human visual system are robust to such challenges. This has inspired research to explore alternative means for signal representation and computation based on phenomena observed in the natural world [^2]. This has led to the re-emergence of processing in the analogue domain as an 'accelerator' inside a digital framework[^3]. This is because the efficiency of analogue processing can be far superior to its digital equivalent for specific applications[^4][^5]. However there remain many challenges that in practice prevent such architectures from achieving a clear advantage. Current systems demand an integrated System on Chip (SoC) solution using digital CMOS technologies to realise cost effective performance. This substantially degrades analogue performance and ultimately leads to the use of time domain (TD) circuits to mitigate a number of these issues[^6]. Out of the different signal modalities that have been established: continuous-time continuous value (i.e. traditional analogue), discrete-time continuous value (i.e. switched cap analogue), discrete-time discrete value (i.e. traditional digital), these TD circuits represent the continuous-time discrete value (i.e. asynchronous digital) approach of representing information. + +TD systems rely on encoding signals in terms of the delay between instantaneous events such as clock edges or digital pulses that can be manipulated using asynchronous or synchronous digital logic with very high efficiency[^7]. The nature of digital provides immunity to supply noise and flexibility in signal representation that is less sensitive to operating conditions when compared to conventional voltage or current mode processing. In fact these techniques are becoming increasingly more widespread in recent years extending from the typical use in phase locked loops (PLL) towards sensing[^8] and processing applications[^9]. Moreover the ongoing trends in supply voltage reduction and technology scaling will lead to the time-based alternatives becoming increasingly more favourable for digital system integration[^10]. + +{{< figure src="/images/tcas2016/td_system.svg" title="Figure 1: Concept of processing multi-phase time-encoded signals using digital logic, in combination with oscillator-based memory elements for retaining system states." width="500" >}} + + +It is becoming increasingly important to establish which techniques can process time-encoded signals in a way that is robust towards noisy digital environments and the nonlinear characteristics of nanometre-scale CMOS. Several methods have already been developed for PLL subsystems such as using noise to linearise time quantisation[^11] or using two-dimensional vernier lines to perform noise shaping[^12]. One example of a TD processing system is the event-driven digital filter [^13] that uses a reconfigurable delay line to process TD signals asynchronously. This work applies different weights to the delay line outputs to realise finite impulse response (FIR) filtering without introducing clocked time quantization. + +Delay based techniques for amplification[^14], addition[^15], and subtraction[^15] have been particularly successful for MHz/GHz signals but tend to be incompatible with low frequency control or when dealing with signals of dissimilar bandwidths. This drawback is also characteristic of FIR techniques due to the fact that millisecond delay lines are easily prone to noisy aggressors and may require an exhaustive number of delay elements. Other systems use open loop voltage-controlled oscillator (VCO) structures for transducing low frequency signals with reduced complexity[^16][^17]. These tend to rely on the linearity of capacitive discharge or voltage-controlled frequency generation for precise processing. However this dependency is particularly vulnerable to process, voltage and temperature variations or device dependent nonlinearities if correction/compensation is not performed. Digital techniques have been proposed to reduce the overhead from correction logic[^8] but it would be desirable to reduce such sensitivities. + +This work proposes a ring oscillator based filter (ROF) structure that reduces the complexity of existing TD systems to realise a compact TD filter with closed loop operation for ultra-low-power computationally intensive applications[^18][^19]. The dynamics of this architecture are, in some way, similar to asynchronous delta sigma modulators[^20] or asynchronous delta modulators[^21][^22]. The difference is that the input and output are time-encoded signals such that the functionality is strictly focused on processing. This is illustrated in Fig. 1. This topology aims to exclusively use digital logic and asynchronous control loops to adjust the phase of an oscillator which is in turn used to generate digital feedback signals to realise a continuous-time dynamical system or infinite impulse response (IIR) in the digital domain. + +Similarly to the three prior works, the presented implementation also targets near-threshold voltage operation by reducing or in this case eliminating the analogue nodes that necessitate a large voltage swing. Instead the large signal components are encoded using an asynchronous digital representation. The presented technique rely on encoding phase using PWM signals and utilising current-controlled oscillators to achieve low distortion that do not require any overhead for calibration. This approach considers the oscillator as a TD memory element analogous to a capacitor in a Gm-C circuit. The resulting circuit is operated asynchronously but the concept of TD memory can also be found in clocked time to digital converters (TDC)[^23]. Furthermore, the auxiliary digital subsystem will feature additional functionality and flexibility in terms of event-driven/nonlinear outputs and gain control. + +The remainder of this paper is organised as follows: Section 3 describes the basic first/second order ROF structures and 'analogue' processing characteristics; Section 6 elaborates on digital processing techniques for manipulating TD signals; Section 9 details the transistor level implementation; Section 14 presents measured results and device characteristics; and Section 20 concludes this work with respect to the achieved performance. + + +# 3 Analogue Processing using ROFs + + + +The concept for the proposed topology that filters TD signals and allows local feedback without external clocking or control is shown in Fig. 1. + +This uses digital control to switch a transconductive element adjusting the oscillator phase according to the intended filter response. The feedback utilises the anti-aliasing properties provided by the current controlled phase modulation to reject high frequency errors in the digital computation thereby allowing the approximate computation presented in Sec. 6. + +{{< figure src="/images/tcas2016/TD_modes.svg" title="Figure 2: Analogy between conventional analogue circuits and TD circuits in relation to the four signal modalities." width="500" >}} + + +The different signal representations and associated processing domains are illustrated in Fig. 2. This shows how the oscillator-based processing concept presented herein relates to conventional analogue circuits, using phase information instead of magnitude to represent signals. Traditional analogue (continuous value and time) employs integration in voltage (or time) using a transconductive element that is loaded by a memory circuit. If the time however is discretized (i.e. sampled-time analogue), there is a requirement for a fast switch and large sampling capacitor. Alternatively, sampling the phase information of an oscillator can be achieved by simply using a clocked register (as the time encoded signal is inherently quantized). This implies that TD systems are able to utilize digital memories to significantly increase information capacity with minimal demand on resource. The analysis that follows develops expressions for this configuration by considering structures that are analogous to single and two-stage amplifiers[^24]. + +The oscillator's phase (Ļ†) is extracted using an XOR-based phase detector (PD). By using a differential structure, the phase output will not need an external reference since the XOR output will represent the phase difference (\\(\Delta\\)Ļ†) of two synchronized oscillators. In fact this phase measurement is a key feature that mitigates the need for external clocking or digital differentiation, as found in other realizations[^6][^10]. Moreover the XOR PD does not experience distortion from band-limiting digital gates such as the pulse swallowing seen in [^15]. Instead reducing the phase difference and equivalent PWM modulation depth leads to a smaller digital bandwidth requirement, which is not the case for the register based PD. + +## 4 Single-Stage ROF + +{{< figure src="/images/tcas2016/TD_L1.svg" title="Figure 3: Implementation of the single-stage ROF topology showing: (a) the switched current source driving an oscillator with closed loop feedback control of the TD signals D, Q, E; (b) the simplified s-domain equivalent model based on an ideal integrator in feedback." width="500" >}} + + +A block diagram of the single-stage ROF is shown in Fig. 3. The signals D & Q are PWM encoded TD signals that are compared and subsequently generate a third output that injects current into the differential oscillator such that the two pulse widths are matched. This control will either increase or decrease the relative phase and proportionally adjust the pulse width of Q in a closed loop fashion. The operation depends on the integral relationship that the output phase Ļ† has with respect to injecting a small signal current i\tss{\\(\Delta\\)}. This is characterised using an impulse sensitivity function (ISF) originally developed for analysing CMOS oscillators [^25]. + +$$ \phi (t) = \int_{-\infty}^{t} \Gamma_{i\Delta}(\omega_0 , \tau) i_{\Delta}(\tau) \: d\tau $$ + +Eq. 1 models the ISF due to i\tss{\\(\Delta\\)} as \\(\Gamma_{i\Delta}\\). This implies the simplified s-domain model yields an integration factor k1\\(\approx\\)I\tss{\\(\Delta\\)}\\(\Gamma_{i\Delta}\\). Strictly the ISF is a cyclostationary function implying that \\(\Gamma\\) may have phase dependent sensitivity with respect to i\tss{\\(\Delta\\)}. However because the current is injected into the virtual supply node VR, this sensitivity is small as seen from \\(\Gamma_{ig}\\) in Fig. 10 and instead will be assumed phase independent (for clarity). This allows for a relatively simple argument to be made to estimate \\(\Gamma_{i\Delta}\\) for low-power ring oscillators because the low-voltage operation implies that essentially all biasing current will be used to charge and discharge capacitors on each oscillator node. More specifically the contribution of short circuit current is negligible due to strictly non-overlapping conduction of the NMOS & PMOS transistors in the oscillator and similarly the transistor area will be sufficiently small to assume that the gate leakage component is much smaller than IB. + +Suppose qmax is the amount of charge dissipated by the oscillator each period. Then it should follow that qmax = IB/fosc by definition but this factor should also relate the total amount of capacitance switched every cycle as qmax = N VRG Cgate, where N, Cgate, VRG are the number of oscillator stages, total capacitive load at the output of every oscillator stage, and voltage across the oscillator respectively. More interestingly if we now consider injecting some excess charge every cycle then its impact is simply normalised by qmax leading to \\(\Gamma_{i\Delta}\\) = 2Ļ€/qmax. The final result is that if this integrator is configured for unity-gain feedback its bandwidth can be summarised in Eq. 2. +$$ f_{3dB} = \frac{I_{\Delta}}{q_{max}} = f_{osc} \frac{I_{\Delta}}{I_{B}} = \frac{I_{\Delta}}{N V_{RG} C_{gate} } $$ +These relations above are needed to point out a defining characteristic of the single-stage ROF which is that the oscillator frequency is directly related to the circuit bandwidth. Moreover in practice it would make sense that the ratio I\tss{\\(\Delta\\)}/IB is close to unity to maximise both bandwidth efficiency and minimise the input referred offset due to any difference in fosc between the two oscillators. A ratio larger than 1 inherently leads to nonlinearity as VRG will become strongly dependent on the dynamic current being switched and therefore vary f3dB as a function of input. Instead VRG should be well-defined in terms of the biasing current such that it can be estimated using sub-threshold device operation VRG = Vth+Ī· UT ln(2IB/Ispec) where Vth, Ī·, UT, and Ispec are the transistor model parameters for threshold voltage, slope factor, thermal voltage, device specific current respectively[^26]. This formulation allows the nonlinear signal compression to be estimated as \\(\epsilon\\) which is expanded in Eq. 3 to determine an appropriate ratio \\(\Delta\\)=I\tss{\\(\Delta\\)}/IB where IC=IB/Ispec. Finally note the desirable property that the open-loop gain is inherently infinite and independent of any operating conditions. Moreover the digital output can virtually drive any type of load without affecting the circuit bandwidth. + +$$ \epsilon = \frac{ V_{th} + \eta U_{T} \: ln[ 2 IC (1 + \Delta) ] }{ V_{th} + \eta U_{T} \: ln( 2 IC ) } - 1 $$ + +## 5 Two-Stage ROF + +{{< figure src="/images/tcas2016/TD_L2.svg" title="Figure 4: The compensated two-stage ROF topology which uses the first order structure and introduces a more explicit pole due to the switched current and load capacitor CL. Shown are: (a) implementation; and (b) the s-domain equivalent as two ideal integrators in feedback." width="500" >}} + +{{< figure src="/images/tcas2016/Bode-Plot.svg" title="Figure 5: Characteristic phase and magnitude response of the two-stage ROF structure with capacitive compensation." width="500" >}} + +The two-stage ROF structure is shown in Fig. 4. This provides more degrees of freedom in the design with a small increase in complexity over the single-stage ROF. The main difference here is that a more conventional charge pump now precedes the oscillator and is responsible for the filtering characteristics. By having the digital output drive the capacitor CL the TD integrator is both compensated and able to operate at maximum efficiency irrespective of oscillator frequency. The s-domain coefficients are therefore k1 = I\tss{\\(\Delta\\)}/CL and k2 = gmMB/qmax. The factor C in Fig. 4 accounts for the total capacitance CT on V\tss{P/N} that may attenuate the feedback by defining it as C = CL/CT and gmMB is the transconductance of the biasing transistor MB. This means that bandwidth efficiency of the VCO integrator is now boosted by the transistor's sub-threshold slope 1/Ī· UT. The requirement of fosc in fact becomes relaxed and may actually be smaller than the circuit's bandwidth if multiple phases are used to represent Q in parallel denoted as K. + +The impact of processing multiple taps from the ring oscillator is two-fold. First the stability requirement for the VCO pole location to lie outside the circuit bandwidth f3dB = k1 /2Ļ€ generally becomes negligible as it is easy to guarantee k1\textless C K k2. This condition implies that the loop has a phase-margin \textgreater 45\tps{\\(\circ\\)} when the two pole structure is put in unity-gain configuration. Secondly the combined value of Q will in effect have K+1 quantisation levels that due to the capacitive feedback onto V\tss{P/N} presents high frequency quantisation noise with an amplitude of VDD/K. Similarly to the previous linearity requirement regarding I\tss{\\(\Delta\\)}/IB, K should intentionally be large to obtain linear behaviour of MB and the oscillators. Fortunately K does not affect the efficiency or power dissipation of this circuit as the product of K fosc is a constant for a fixed current in IMB. Instead K influences circuit complexity to some extent. Another benefit of the two-stage configuration is that although the band-limiting capacitor needs to be broken up into K units to accommodate all phases it is an explicit capacitor and unlike the single-stage configuration it does not rely on the precise control/matching of parasitic capacitance to determine the pole location. Moreover charge pump circuits and the associated dynamics have been studied extensively in PLL circuits[^27] and can easily be applied here. That said, it can be concluded that the two-stage ROF should be used in scenarios when the output and bandwidth characteristics need to be precise and the single-stage ROF should be applied when focus lies with performing asynchronous computation with diminished requirements. + +$$ H(s) = \frac{k1 k2}{s^2+C k2 s} \cdot e^{-s t_d} $$ + +The open loop system response with capacitive compensation is characterised by Eq. 4. This is derived using the linearised model and introducing the impact of digital gate delay (td) for further processing Q to the frequency response[^10]. The corresponding Bode plot is shown in Fig. 5. The second order roll-off will assist in rejecting high frequency artefacts due to any approximations made in the digital processing system. It should also be evident from the linearised model that high pass behaviour can be realised with the same feedback but instead taking the output from the digital processing block which is driving the charge-pump circuit. + +# 6 Digital Processing using ROFs + +From the introduction it is clear that there is large variety of techniques being used to process time domain signals with asynchronous logic. This section will present specific techniques for manipulating the multi-phase PWM signals that can be obtained from the ROF without introducing delay lines. Applying Boolean functions to PWM signals can be divided into two scenarios: coherent and incoherent operation. This relates to the cases when the signals being operated on are the exact same frequency (e.g. different phases of the oscillator) or when they are different frequencies (e.g. when processing the signals D & Q). It will be shown that these two cases lead to significantly different behaviour. + +## 7 Coherent Operations + +{{< figure src="/images/tcas2016/TDC_1.svg" title="Figure 6: Average PWM output for simple Boolean functions with a coherent input. The output is evaluated with respect to the pulse width of A and the delay \\(\Delta\\)T." width="500" >}} + +{{< figure src="/images/tcas2016/TDC_2.svg" title="Figure 7: Average PWM output and the analytical result for a gain of 2x (blue), gain of 4x (green), and the complement of the absolute value for x-0.5 with the exact Boolean operator **B** annotated." width="500" >}} + +The coherent operations useful for manipulating the multiple phases output by a single ring oscillator because these delays are relatively well matched with respect to the oscillator period, thereby allowing predictable outputs irrespective of oscillator frequency. These simple operations are summarised in Fig. 6. This visualises the average PWM output Q subject to a PWM input A, the delay \\(\Delta\\)T and a Boolean function **B**. Here A is a periodic function with a normalised periodicity of one. As expected Q is linear with respect to the pulse width x of A. Let A be formally defined in terms of Eq. 5 such that Q can be evaluated as Eq. 6. This calculates the mean value of Q over the period of A denoted as T. + +$$ A(\tau,x) =\begin{cases} 1 & \tau (mod\: 1) \: < \:x 0 & \text{otherwise} \end{cases} $$ + +$$ E[Q(x,\Delta T)] = \int_{0}^{1} \mathbf{B}(A(\tau,x),A(\tau-\Delta T,x)) \: d\tau $$ + +However most of these operations can be visualised in terms of adding and removing pulses using delayed components of A. For instance using an OR gate with a delay of 0.5T will add an identical pulse at half the period and realise the equivalent 'gain' of 2x and effectively doubling the frequency of A. This example also illustrates that clipping will occur if x exceeds 0.5T as a natural consequence of overflow/saturation. Note that the output of **B** for the AND and OR gates have 3 regions that exhibit saturation, linear dependency, or gain. The interesting aspect here is that the point of clipping can be chosen freely by closely inspecting the region in Fig. 6 for which **B** is always 1. An underflow will occur for a pulse width smaller than c when using an AND gate with a delay of cT and an overflow will occur for a pulse width larger than (1-c) if an OR gate is used with a delay of cT. The clipping regions will not exceed 0.5 unless we combine more phases to realise larger 'gain' factors as illustrated in Fig. 7. + +## 8 Incoherent Operations + +{{< figure src="/images/tcas2016/TDG_1.svg" title="Figure 8: Average PWM output for simple Boolean functions with incoherent inputs A & B. The output is evaluated with respect to the pulse width of each input." width="500" >}} + +{{< figure src="/images/tcas2016/TDG_2.svg" title="Figure 9: The result from applying an AND gate(blue), OR gate (green), and XOR gate (red) to two PWM signals with equal pulse width but are modulated by different frequencies with the analytical polynomial annotated as a function of pulse width x." width="500" >}} + +Typically it will be the case that the signals of interest will not have the same frequency which requires us to consider how the two PWM signals A & B interact with one another. The primary interest will still lie with the average or near-DC behaviour of the Boolean function because the ROF is inherently lowpass in response. The main concern is associated with the beat frequency of the two PWM carrier frequencies fA-fB. This is because this spur needs to lie sufficiently outside of the f3dB bandwidth for us to make the approximation that B is uncorrelated with respect to A. This implies that the pulse B can be assumed uniformly distributed with respect to A. The circuit bandwidth will represent the averaging time constant and should ideally not be subject to carrier dependent tones such that a precise output is maintained. The oscillator frequencies are easily perturbed and subject to drift making this assertion quite reasonable in practice. As a result the average output Q due to two PWM signals with pulse width x & y can be calculated using the expression in Eq. 7. + +$$ E[Q(x,y)] \approx \int_{0}^{1} \int_{0}^{1} \mathbf{B}(A(\tau,x),B(t-\tau,y)) \: d\tau dt $$ + +This type of processing uses concepts from stochastic computation \cite{SDSP, sto_cmp} since the two digital signals interact with respect to a probability distribution that is shaped using the Boolean operator. The difference however is that these bitstreams themselves are not stochastic in the large signal sense and they are not clocked by some specific frequency. Instead the bitstreams are intentionally decorrelated by choosing different carrier frequencies. The primitive operations are summarised in Fig. 8 with respect to the PWM signals A and B. In some cases these operations will lead to nonlinear or polynomial behaviour which can be observed in Fig. 9. In addition the inverse of these functions can also be realised by manipulating the feedback and using **B**(Q,R) instead of Q directly where R is the output of a single-stage ROF in unit gain feedback with the input Q but the carrier frequency is doubled to decorrelate R from Q. + +# 9 Circuit Implementation + +\begin{figure*} + \centering + \includegraphics[width=18cm]{/images/tcas2016/System.svg} + \caption{Detailed transistor level implementation of the second-order ROF structure. Here the digital gates in: (a) implement a difference operator; (b) is the switched current DAC; (c) is the floating differential ring oscillator structure; (d) is the differential delay cell, and (e) is the corresponding buffer that amplifies the oscillator voltage to full swing. All device sizes are shown in (f). } + \label{Fig:TDSys} +\end{figure*} + +This particular implementation focuses on achieving robust low-voltage operation and minimising analogue complexity to enable larger multi-channel systems. A commercially available TSMC 65 nm CMOS LP MS RF technology (1P9M 6X1Z1U RDL) was used to develop a lowpass filter that processes the signals from the TD instrumentation circuit in [^30] and illustrates the basic performance characteristics of the ROF structure. The proposed circuit is detailed in Fig. \ref{Fig:TDSys} which can be divided into four sub-blocks: digital control (a), analogue integrator (b), TD integrator (c), and the oscillator stages (d & e). + +## 10 Charge Pump + +The switches S\tss{A/B/C} control how a reference current IB is pumped differentially into nodes V\tss{P/N}. Transistors M\tss{1-2} provide common mode regulation on V\tss{P/N} and mirrors the biasing current into the ring oscillators using M\tss{3-4}. This is extended for multi-phase inputs by operating several charge pumps in parallel. Any resulting voltage difference across V\tss{P/N} injects a differential current into the TD integrator as M\tss{3-4} represent a pseudo-differential pair. Although it is not shown M\tss{3-4} is split up into 5 devices of which two have their drain connected to the opposite polarity which allows us to manipulate the I\tss{\\(\Delta\\)}/IB ratio. This leads to a smaller VCO bandwidth and induces more filtering with better linearity. Using high Vth devices for M\tss{1-4} allows the common mode of V\tss{P/N} to be placed close to 250 mV which leaves enough voltage headroom for the switches and biasing transistors. + +{{< figure src="/images/tcas2016/ISF.svg" title="Figure 10: Post-layout simulation results showing to one of the oscillator outputs in a) for reference and the ISF \\(\Gamma_{ig}\\),\\(\Gamma_{io}\\),\\(\Gamma_{ir}\\) for injecting a small signal charge at the virtual ground, oscillator output, and virtual rail nodes." width="500" >}} + +## 11 Differential Oscillator + +Each oscillator consists of 7 differential delay stages each of which use a cross coupled load resulting in a total of 14 outputs. This structure is based on [^31] to achieve additional supply noise rejection when compared to the conventional ring oscillator. The 5 nA biasing current for each charge pump will lead to sub-threshold operation of all analogue devices which means the oscillator output that swings around VR & VG is only 100 mVpp with a transition time of 1/(14 fosc). Amplifying this output to improve signal transition time with high efficiency is achieved by a buffer that recovers the digital signal integrity and also uses positive feedback provided by M\tss{16-17}. This particular configuration requires some consideration with respect to the the optimal operating conditions of the buffer. + +The charge sensitivity for this oscillator is shown in Fig. 10. The ISF has been extracted using using post-layout simulation results. The sensitivities \\(\Gamma_{ig}\\), \\(\Gamma_{ix}\\), and \\(\Gamma_{ir}\\) are evaluated by injecting 1 fC of charge \\(\Delta\\)Q into the nodes VGP, VOP, VR and evaluating the change in phase with respect to having no charge injected. Then \\(\Gamma\\) is characterised by systematically injecting charge at some point in time (tq) with respect to the oscillator period and performing normalisation as \\(\Gamma\\)(tq)=2Ļ€ \\(\Delta\\)Ļ†(tq) fosc/\\(\Delta\\)Q to obtain the small signal equivalent. This illustrates the phase independent characteristic of \\(\Gamma_{ir}\\) as well as the 100 mV swing of the oscillator. Note that noisy aggressors coupled through \\(\Gamma_{ir}\\) are common to both phase outputs and rejected by the low impedance from M5. The behaviour of \\(\Gamma_{ix}\\) is also interesting because when the output is not transitioning the coupling is shorted to either virtual supply and therefore has equivalent sensitivity. However during a transition there is a brief doubling sensitivity as it is being injected into one node instead of being loaded by the differential structure. It should be noted that \\(\Gamma_{ix}\\) is not very representative for modelling how noise couples at the output since many sources will be psuedo-common to all stages (e.g. substrate noise) and the transistor noise is further affected by the operating point of the device itself. + +## 12 TDFA unit + +The PWM difference operator or time-domain full-adder (TDFA) unit is detailed more clearly in Fig. 11. This shows that a crucial aspect of computing with incoherent TD signals lies with carefully using different signal representations. In this case the nonlinearity that would have been expected from Sec. 8 is negated by using a 1.5 bit ternary encoding. Instead the output Q is linearly dependent on the difference in pulse width of D & Q without distortion. This is important because in-band distortion is not shaped by the filter and any nonlinearity from **B** will propagate to the output including down modulated PWM carrier spurs. + +{{< figure src="/images/tcas2016/TDFA.svg" width="500" >}} + +{{< figure src="/images/tcas2016/SUM.svg" title="Figure 11: Implementation of the linearised TDFA unit which calculates the difference with respect to the two PWM encoded signals D & Q." width="500" >}} + +## 13 Fabricated Prototype + +The fabricated device is shown in Fig. 12. This prototype integrates a number of TD sensing systems together where the TD ROF structure is located in the lower left section. This subsystem operates together with an asynchronous analogue to time converter (ATC) such that the measured characterisation reflects system-level performance. Moreover this mitigates any difficulty associated with precisely generating PWM encoded signals off-chip and transmitting them to the filter under low noise conditions. The entire system is 7200 Ī¼ mĀ² in size and one ROF is around 30\\(\times\\)40 Ī¼ mĀ². Excluding the ATC this filter structure has a 3600 Ī¼ mĀ² silicon footprint. There is also a reconfigurable asynchronous DSP block that realises several different coherent Boolean operations intermediate to the ATC and ROFs blocks. In particular there are variable-gain blocks that use the gain function from Sec. 7. + +{{< figure src="/images/tcas2016/chip_fab.svg" title="Figure 12: Microphotograph of the fabricated device showing the chip with annotated floor plan in (a) while the P1,M1,M2 layers of the ROF layout are highlighted in (b) (n.b. metal fill omitted for clarity)." width="500" >}} + +# 14 Measured Results + +{{< figure src="/images/tcas2016/setup.svg" title="Figure 13: Experimental setup used for characterising the ROF filters. Various off-chip instruments are used to supply power and analogue test signals to the device while a Saleae Logic digital acquisition tool samples the PWM output from the chip." width="500" >}} + +{{< figure src="/images/tcas2016/pcb.svg" title="Figure 14: Photograph of the custom printed circuit board used for testing the ASIC." width="500" >}} + +## 15 Experimental Setup + +A custom test platform was developed to characterise the fabricated ASIC using Raspberry Pi 3 development board to provide a graphical interface that automates the low level device control and test routines. This setup is illustrated in Fig. 13 with a photograph of the custom PCB in Fig. 14. The SPI interface allows the hardware to be reconfigured using a configuration register where 3 bits are used to fine tune the biasing current IB and another 10 bits are used for variable gain (VG) settings and output control. As shown the ROF signal chain consists of 6 blocks in the following order: ATC, VG, ROF, VG, MUX. The ATC will sense and amplify 5 mVpp differential signals and generate a PWM encoded signal with a 450 kHz carrier frequency. The VG blocks can select additional X1-X4 gain settings using only digital logic. The cascaded ROF provides a 4th order lowpass filter and the MUX gives control over which signals are sent off chip. Not all the TD phases will be sent off chip because of noise and overhead concerns. Instead the MUX will output one phase from the ATC or ROF for preliminary characterisation during asynchronous operation. The digital bit stream appearing at the output is then acquired at 100 MS/s over 1 second using a digital scope. + +{{< figure src="/images/tcas2016/spec.svg" title="Figure 15: Spectral power densities of the ROF PWM output with a 4 mVpp 1 kHz differential input signal where the distortion has been annotated in red and the oscillator harmonics are annotated in blue." width="500" >}} + +## 16 Filter Characteristics + +Taking the Fourier transform of the PWM output gives the spectrum shown in Fig. 15. Here the ROF oscillator frequency is observed at around 35 kHz with the corresponding higher harmonics. The bandwidth of this filter was designed to be 5 kHz which means these aggressors are sufficiently rejected for most applications. In fact the measured filter response in Fig. 16 shows the cascaded ROF will reject these harmonics by more than 50 dB. More practically, when the output of the ROF output needs to be sampled without the interference of such harmonics, this structure can easily be transformed into an oversampling TDC that decimates the PWM signal and filters out of band components [^17][^30]. This particular setup uses a 5.2 nA biasing current which leads to the charge-pump pole being precisely situated at the 5 kHz. Because the VCO pole location suffers from increased variability it is intentionally placed at twice the charge-pump cut-off frequency. It is evident from Fig. 16 that verifying the post-fabrication pole position and the corresponding variance remains challenging. If necessary this pole location can be calibrated using established techniques such as trimming M\tss{3-4} or introducing a digitally-switched capacitive load [^32] at the cost of increasing circuit complexity. + +## 17 Linearity + +Using a 1 kHz tone, the linearity characteristics are shown in Fig. 17. It is important to note that the use of an on-chip ATC implies that the distortion also includes nonlinearity from the amplifying ATC. The signal processing chain can accept a maximum input 4 mVpp under before the ATC feedback loop starts to overload the asynchronous \\(\Delta\Sigma\\) modulator. These measurements show that a maximum total harmonic distortion (THD) and spurious-free dynamic range SFDR of 53 dB is achievable for a 0.6 mVpp input amplitude. The noise floor is slightly higher than -80 dB and calculating the integrated noise over 10 kHz indicated that the maximum SNR is 55 dB for a 4 mVpp input signal that has a THD of 44 dB. In order to minimise the impact of ATC nonlinearity a 2x VG setting is used during this test such that the ATC output is at -4 dB of the full range but the ROF processes signals near the full input dynamic range. + +## 18 Supply Noise Sensitivity + +The PSRR has been tested using a 10 mVpp tone at different frequencies while the ATC input was shorted together. The result is presented in Fig. 18. This perturbation induces output tones at -55 dB of the full range which when referred to the 4 mV input range implies a PSRR of 63 dB. This level of supply coupling is difficult to improve because of this measurement setup and the ADC nature of the ATC. The implementation of the ATC uses VDD as reference voltage such that it is coupled asymmetrically to analogue nodes degrading supply rejection even in differential configurations. Although the impact of using the differential oscillator structure is not well represented, any further degradation in PSRR is prevented and the input referred noise-floor is not corrupted by supply noise coupled from the digital switching. Moreover this figure should be very representative for larger scale or multi channel systems as this implementation only uses a 2.5 pF decoupling capacitor for the shared 0.5 V supply. It can thus be expected that using more decoupling capacitance or separating the supplies will further improve this figure at the cost of allocating more resources. + +{{< figure src="/images/tcas2016/measure.svg" title="Figure 16: Measured filter response due to a 4 mVpp differential sinusoidal input at frequencies from 1 kHz to 100 kHz." width="500" >}} + +{{< figure src="/images/tcas2016/THD1.svg" title="Figure 17: Measured harmonics due to a 1 kHz differential input tone with increasing input amplitudes. The spectral power of the output tones are calculated with respect to the maximum output dynamic range." width="500" >}} + +{{< figure src="/images/tcas2016/PSRR.svg" title="Figure 18: Measured PSRR of the entire system due to a 10 mVpp sinusoidal signal on top of a 0.5 V bias driving the system's VDD at frequencies from 50 Hz to 60 kHz." width="500" >}} + +## 19 Performance Summary + +Table 1: System Characteristics and Comparison with State-of-the-Art +| Parameter [unit] |\textbf{\small{This Work}} | [^13](^\ddagger) | [^6] | [^10] | [^17]\cite{1} | [^20] | [^34] | +|----|----|----|----|----|----|----|----| +| Tech.[nm] | **65** | 130 | 90 | 65 | 40 | 130 | 180 | +| Modality | **Time** | Time | Time | Time | Time | Volt. | Volt. | +| Type | \textbf{TD-IIR} | TD-FIR | TD-IIR | TD-IIR | TD-(\Delta\Sigma) | GmC-(\Delta\Sigma) | GmC-IIR | +| Order | **4** | 16 | 4 | 4 | 2 | 1 | 5 | +| Supply-V[V] | **0.5** | 1 | 0.55 | 0.6 | 0.9 | 0.25 | 0.5 | +| Supply-I[A] | **146 n** | 0.46 m | 5.27 m | 43.7 m | 2.8 m | 72 n | 1.2 m | +| Bandwidth[Hz] | **5 k** | 70 k | 7 M | 70 M | 40 M | 1.9 k | 135 k | +| DR[dB] | \textbf{55(\dagger)} | 50 | 61 | 58 | 61 | 58 | 61 | +| Area[mmĀ²] | **0.004** | 5 | 0.29 | 0.38 | 0.017 | 0.08(^\star) | 0.29 | +| FOM[fJ/pole] | **8.17** | 1299 | 92 | 118 | 28 | 12 | 520 | + {\thanks{\\(\dagger\\) using a 10 kHz integrated noise figure, \\(^\ddagger\\) performance quote from full system asynchronous PWM operation, \\(^\star\\) uses external passive components.}} + +The filter performance is summarized in Table 1. The circuit power consumption has been measured to be 73 nW of which simulation results indicate 16 nW is dissipated in the charge pump plus oscillator circuits and 21 nW is dissipated by the biasing circuits. The remaining 36 nW is due to digital control and PWM switching. One of these contributions comes from applying digital feedback onto the capacitor CL which is 560 fF. This is expected to dissipate power according to foscCLVĀ²DD or in this particular case 3 nW. This later component can be become substantial if the supply voltage is not small enough or if very low-noise performance is required since in-band noise performance is directly dependent on CL. However when compared to other works the achieved performance is comparable and can operate with good energy efficiency. This is evaluated using the FOM from [^34] which is defined in Eq. 8 using the system power (Psys) and the number of poles (Npoles) to normalise performance. The most substantial gain from the ROF filter is that the reduced complexity leads to a very compact implementation that is not only considerably smaller than state-of-the-art but also more capable of reconfigurable functionality. Based on KT/C relations we may expect all-analogue processing to be more power efficient in a noise limited scenario because such systems can take advantage of the transistor sub-threshold slope. This drawback is similar to the noise performance from all-digital PLLs in comparison to sub-sampling PLLs. However the time-domain circuits will allow far superior linearity & dynamic range during ultra low voltage operation which the all-analogue systems cannot achieve. The 65 nm technology primarily influences the impact of excess digital switching from the asynchronous logic/overhead. Using an advanced CMOS technology allows most of the power to be dissipated in the oscillator and enables more efficient performance. + +$$ FOM = \frac{P_{sys}}{N_{poles} f_{3dB} DR} $$ + +# 20 Conclusion + +This work presents the first system to explicitly deliver IIR or analogue filtering for PWM encoded signals asynchronously using standard CMOS technology. The implementation and model of a low-complexity oscillator based filter is detailed to complement existing FIR and delay line based techniques for clockless processing of time-encoded signals. The proposed topology can deliver 53 dB SFDR with a maximum SNR of 55 dB while operating at 0.5 V. The extensive use of digital logic allows highly flexible and reconfigurable oscillator based computing for future ultra-low-power systems in nanometre CMOS. Measured results demonstrate 8.17 fJ/pole efficiency for the 5 kHz bandwidth and reports an area requirement of 0.004 mmĀ² . In fact unlike prior art this topology is substantially more efficient and compact at processing asynchronous TD signals that have reduced bandwidths or require low frequency filtering than state-of-the-art. Moreover the ROF primitives and digital processing techniques presented here can be directly applied to ultra-low-power \\(\Delta\Sigma\\) modulators and mixed signal systems due to its simplicity and affinity for low voltage mixed signal operation. + +# 21 Acknowledgement + +The authors would like to thank Dr. Pantelis Georgiou, and the Europractice Advanced Technology Stimulation programme for providing access to the TSMC 65nm technology. The authors additionally thank Michal Maslik for the helpful comments and assistance with improving this manuscript. + +# Refernces: + +[^1]: I.L. Markov, ''Limits on fundamental limits to computation,'' Nature, vol. 512, pp. 147--154, August 2014. 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[Online]: http://dx.doi.org/10.1109/JSSC.2012.2216708 diff --git a/content/publications/2018/a-0-006-mm-tsqrd-1-2-rmu-w-analogue-to-time-converter-for-asynchronous-bio-sensors.md b/content/publications/2018/a-0-006-mm-tsqrd-1-2-rmu-w-analogue-to-time-converter-for-asynchronous-bio-sensors.md new file mode 100644 index 0000000..0560a9c --- /dev/null +++ b/content/publications/2018/a-0-006-mm-tsqrd-1-2-rmu-w-analogue-to-time-converter-for-asynchronous-bio-sensors.md @@ -0,0 +1,257 @@ +--- +title: "A 0.006 mm2 1.2 uW Analog-to-Time Converter for Asynchronous Bio-Sensors" +date: 2018-07-23T15:26:46+01:00 +draft: false +toc: true +type: posts +math: true +tags: + - publication + - CMOS + - circuits + - data-converter + - biomedical +--- + +Lieuwe B. Leene, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +This work presents a low-power analogue-to-time converter (ATC) for integrated bio-sensors. The proposed circuit facilitates the direct conversion of electrode biopotential recordings into time-encoded digital pulses with high efficiency without prior signal amplification. This approach reduces the circuit complexity for multi-channel instrumentation systems and allows asynchronous digital control to maximise the potential power savings during sensor inactivity. A prototype fabricated using a 65 nm CMOS technology is demonstrated with measured characteristics. Experimental results show an input-referred noise figure of 3.8 Ī¼ Vrms for a 11 kHz signal bandwidth while dissipating 1.2 Ī¼ W from a 0.5 V supply and occupying 60\\(\times\\)80 Ī¼ mĀ² silicon area. This compact configuration is enabled by the proposed asynchronous readout that shapes the mismatch components arising from the multi-bit quantiser and the use of capacitive feedback. + +# 2 Introduction + +The current trend in sensor systems is to integrate many analogue sensors together with larger digital systems to provide smart data collection for miniaturised wearables or low cost system-in-package (SiP) electronics [^2][^1]. The digital oriented design flow of these systems compels designers to look for sensor interfaces that accommodate the trends in CMOS technology scaling and smaller supply voltages for digital power reduction. For this reason many data converters and sensing circuits have utilised voltage controlled oscillators (VCO) to convert analogue signals into a periodic digital waveform where information is encoded by its frequency. This type of conversion is highly applicable at every technology node and the time encoded output is considerably more robust than the voltage output of conventional amplifiers when considering supply noise and the process, voltage and temperature (PVT) variations. The time-domain concept has seen extensive use in recent publications because the voltage to frequency conversion provides high gain and exceptional dynamic range [^5][^4][^3] that can also accommodate conventional chopper techniques [^6][^7]. + +The conversion from analogue to frequency is not the only means by which analogue circuits can encode signals in the time-domain. It is well known that both synchronous [^8] and asynchronous [^9] oversampling modulators will generate a pulse-width-modulated (PWM) output bitstream. However these realisations conventionally do not perform integration in the time-domain and instead use charge pumps that suffer from typical drawbacks in advanced CMOS technologies such as gain degradation and limited voltage swing [^10]. In contrast the modulating characteristic of oscillators can negate component mismatch in any proceeding digital-to-analogue conversion since the digital output inherently provides data-weighted averaging [^5]. + +{{< figure src="/images/jssc2018/obi.svg" title="Figure 1: The proposed Analogue-to-Time Converter (ATC) that provides closed loop conversion of an analogue input voltage into an asynchronous multi-bit digital data stream." width="500" >}} + +In order to retain high performance and minimise the requirement of ideal analogue components, time-based systems should be designed in a fashion where only small error signals are processed in the analogue domain with constrained linearity. Signals with large dynamics should be time-encoded and manipulated with robust digital logic. The proposed ATC realisation that follows this concept is shown in Fig. 1. This topology presents an asynchronous delta-sigma modulator (ADSM) that accumulates a phase difference between two oscillators to realise time-based integration and utilises capacitive feedback to linearise the conversion. + +Here the sensor's voltage fluctuations on VIN modulate the pulse width of the PWM signal generated by the phase detector by combining multiple phases from each stage in the oscillator. In this fashion the output bit-stream DOUT can in effect resolve finer quantisation levels. In contrast to prior oscillator-based systems that are clocked, the asynchronous operation proposed here enables high-speed signal processing with oscillator-based filters [^11] or a continuous-time digital core [^12]. Both avoid the need for a high speed clock when processing a large number of recording channels and can therefore enable substantial power saving. + +This work is a first step towards realising a sensor system that fundamentally only processes using time-encoded signals and can potentially operate using a supply voltage of only several hundred millivolts since the circuit can accurately convert millivolt level signals without prior analogue signal amplification [^14][^13]. This is because oscillator based integrators can operate with a voltage headroom close to transistor threshold voltage without diminishing loop gain or dynamic range. This advantage is not diminished by practical issues and large common-mode interference or electrode offset can be rejected because the sensor input is capacitively coupled to the main feedback loop. There are a number of established techniques such as using a DC servo loop or performing ripple rejection that prevent these issues from degrading circuit performance [^15]. This means that the voltage appearing at VX well controlled through feedback and that the amplifier can maximise power-efficiency-factor (PEF) [^16] without requiring additional voltage overhead to accommodate voltage fluctuation at its input. + +This paper presents the implementation and modelling aspects of the oscillator based ATC using the following organisation: Section 3 details the instrumentation topology and Section 4 describes the corresponding transistor level implementation, Section 9 discusses the impact of technology and mismatch parameters of this circuit, Section 12 presents the measured results of a fabricated prototype, and Section 13 concludes this work. + +# 3 Concept and ATC Architecture + +This section introduces the operating principle and circuit dynamics of the proposed instrumentation system that is used to sense intra-cortical neural activity using a conventional electrode instrumentation setup. Such a scenario would record activity in-vivo or ex-vivo from the 1 Hz to 10 kHz frequency band where the signals are no larger than a few millivolts in amplitude[^17]. The circuit sensitivity must match the noise characteristics of the electrode or biological tissue and target a noise floor of around 50 nV/\rtxt{Hz}[^18]. These sensitivity conditions require the circuit dissipate several microamps and easily leads to a circuit bandwidth much larger than 10 kHz. For this reason this ATC will provide gain for a bandwidth exceeding 10 kHz since it is more resource effective to rely on proceeding processing stages to perform filtering when necessary. + +{{< figure src="/images/jssc2018/obi_sys.svg" width="500" >}} + +{{< figure src="/images/jssc2018/obi_blk.svg" title="Figure 2: Detailed system topology in a) and equivalent analytical model in b) of the proposed chopper stabilised ATC." width="500" >}} + +A block diagram of the proposed architecture is detailed in Fig. 2a. For clarity, this shows the single ended equivalent of the fully differential circuit that was implemented. The difference in potential between two electrode inputs VR & VIN is chopped at the chopper frequency fchp to generate a up-modulated voltage waveform that couples the input onto VX through CI. The essential mechanism here is that signals appearing on VX induce a current that feeds into two oscillators with different polarities after being demodulated. This current forces the oscillators accumulate a relative phase difference because the phase is dependent on the integral of injected current [^19]. This phase difference is then evaluated for each oscillator tap using XOR logic to yield multiple time-encoded PWM signals that can also be chopped using digital logic. The resulting digital signal is capacitively coupled onto VX in parallel to close the loop. This is the main signal amplifying path that realises a first-order asynchronous Ī”Ī£ modulator and this sense using N phase detectors in parallel represents asynchronous quantization of the phase difference with a resolution of log2(1+N) bits. Using this interpretation we can construct the corresponding analytical model that is shown in Fig. 2b and will assist in deducing the design's parameter dependencies. + +$$ H(s) = \frac{ 1 }{ s / k_1 + N f } \approx \frac{1}{s\cdot \frac{N C_{gate} V_{RG}}{Gm}+\frac{C_F}{C_I}\frac{C_U}{C_U+\:\:\text{\makebox[-3pt][l]{\\(\nearrow\\)}}C_G/N}} $$ + +$$ f = {\frac{C_F}{C_{I}+C_{F}}} \cdot \frac{N C_{U}}{C_{F}+N C_{U}+ \text{\makebox[-3pt][l]{\\(\nearrow\\)}}C_{G}} $$ + +First the expression in Eq. 1 can be derived to characterise the signal amplifying loop. The feedback factor \\(f\\) evaluated in Eq. 2 corresponds to the capacitive coupling of a particular PWM phase Q on to VX with respect to the capacitors CI, CF, CG, CU. In this case CG can be digitally tuned to provide varying gain settings (41-53 dB). The oscillator's integration factor k1 is derived by evaluating the impulse sensitivity function (ISF). The ISF captures how the oscillator phase is affected as a function of charge being injected into the virtual supply of the oscillator VR [^19]. Following the derivation for Eq. 2 in [^11] this factor can be assumed constant and is simply dependent on the transconductance Gm, loading capacitance of each delay stage Cgate, and the voltage across the oscillator VRG such that k1=Gm/(N Cgate VRG). + +The second control loop is used to reject near-DC aggressors that will appear at the input of the main transconductor. Chopping will prevent the input-referred noise profile from being corrupted by flicker noise but in turn several large tones will appear at harmonics of fchp because off-set is being up-modulated. Moreover because this structure is not providing narrowband amplification the feedback must actively suppress these tones to avoid the output from being saturated and distorted. These components are integrated with a gain of approximately Aripple=k1/fchp which induces a 90\\(^\circ\\) phase shift. The phase-shift can be corrected for by using the chopper clock that is delayed by 1/4th of the period when demodulating Q to recover the off-set. The flicker rejection further depends on the transfer function F(s) which represents how the recovered signal is smoothed and fed back onto VX. Using a charge pump in addition to the pseudo-resistor RP will yield an expression for F(s) according to Eq. 3 where CL and I\tss{Ī”} represent the main integration capacitor and charge pump bias current respectively. This is also shown in Fig. 2. + +$$ F(s) = \frac{N I_{\Delta}}{s (C_{L} C_{I} R_{P} s + C_{L} + C_{I})} $$ + +Combining F(s) and Aripple will then predict how the noise aggressors at Vx are removed. The frequency dependent response in Fig. 3 evaluates this control mechanism at different points in the loop using the following implemented circuit parameters: N=5, fchp=75 kHz, CI=288 fF, CG=69 fF, CF=CU=14 fF, RP=100 MĪ©, CL=1.6 pF, I\tss{Ī”}=5 nA. This shows the influence of noise at the input (eĀ²flk) with respect to the ripple at the ATC output and the fluctuations on VX as a function of frequency. First notice the increased chopper frequency enables this circuit to increase its bandwidth and reject more of the low-frequency band including common-mode signals that asymmetrically couple onto VX. In addition the second order low-pass characteristic provides increased rejection of the chopper and oscillator tones such that the two control loops operate in isolation. A known drawback of increasing fchp is the reduction in input impedance but as shown in Sec. 10 this reduction can be mitigated with technology scaling and using a smaller value for CI. + +{{< figure src="/images/jssc2018/noise_tf.svg" title="Figure 3: The closed loop response of the flicker rejection loop due to input-referred noise eĀ²flk evaluated with respect to the ripple magnitude seen at Q (solid), the feedback seen at VX (dotted), and the open loop response F(s)\\(\cdot\\)Aripple (dashed)." width="500" >}} + +Given these dynamics there is still important distinction to be made with regards to the rate of information seen at the output and the 3 dB bandwidth for signal amplification that in this case is the product of \\(f\\) k1\\(\approx\\)250 kHz. The digital output will encode an effective number of bits (ENOB) that relates to the ATC's precision (i.e. SNDR) and presents pulse width information of every cycle that in this case is oversampled by N parallel phases. However for one phase the entropy rate can be estimated in terms of fosc (SNDR-1.76)/6.02. This highlights an important motivation for time-domain processing since this information rate may easily be 10\\(\times\\) larger than a clocked digital bit-stream that maximally yields 1 bit per clock cycle. Optimistically this implies that time-domain techniques achieve a proportional boost in power efficiency since the digital power dissipation is a function of fosc even though a higher rate of information is being processed. For the latter to hold we must require the analogue and oscillator sub-blocks to operate with negligible power budget. + +# 4 Circuit Implementation + +{{< figure src="/images/jssc2018/obi_sch.svg" title="Figure 4: The transistor level implementation of the ATC circuit in Fig. 2a. Here the complementary structure in a) represents the main transconductor; b) represents the pseudo-differential oscillator where each delay cell is shown in c); The flicker rejection stage is shown in d) where only the grey section is replicated for each phase. Note that all devices have their body connected to the corresponding supplies with the exception of M\tss{5-8} which have the body connected to the drain of M9. Furthermore M\tss{13-16} and M\tss{21-22} their body connected to VR and either terminal of CL respectively." width="500" >}} + +The transistor schematic for the proposed ATC is presented in Fig. 4 and the sizing of each device is listed in Table 1. This circuit can be segmented into four parts corresponding to the transconductor, oscillator, delay stage, and flicker rejection circuit. Each sub-block, including the capacitor array, will be described below. This configuration uses two bias voltages VBN & VBP to source the annotated drain currents. Both of these voltages are derived on-chip using a simple current mirror structure and a 1 Ī¼ A off-chip reference. Furthermore an external reference voltage VC is used to control the common mode voltage of VR that is placed at VDD/2. Note that the 65 nm technology used here provides transistors that can be configured with 150 mV (lvt), 250 mV (vt), and 350 mV (hvt) threshold voltages (VTH). The lvt option is used exclusively to reduce the supply voltage to 0.5 V with the exception of M\tss{23-24} which use a 250 mV threshold. + +Table 1: Device Sizing in micrometers with the labels from Fig. 4 +| Device | Size (W/L) | Device | Size (W/L) | +|----|----|----|----| +| M0 | 26/5 | M\tss{15-16} | 0.2/2.5 | +| M\tss{1-2} | 16/0.25 | M\tss{17-18} | 2/5 | +| M\tss{3-4} | 2/1 | M\tss{19-20} | 10/0.2 | +| M\tss{5-6} | 4/0.5 | M\tss{21-22} | 1.6/0.4 | +| M\tss{7-8} | 0.8/1.4 | M\tss{23-24} | 0.96/4 | +| M9 | 32/0.1 | Logic | 0.3/0.1 | +| M10 | 6/5 | SwitchCHP | 1/0.1 (Ptype) | +| M\tss{11-12} | 1.5/2.4 | SwitchX | 1/0.2 (Ntype) | +| M\tss{13-14} | 2.3/2.5 | CL | 21/21 | + +## 5 Low-Noise Transconductor + +The complementary style transconductor (Fig. 4a) is adopted from [^20] to exploit two aspects of oscillator based integration. The first is that the operating conditions and transistor characteristics do not influence the loop gain of the time-based integrator but rather effect the noise characteristics which are already improved due to current recycling. Secondly the voltage fluctuation across VX & VS is negligible particularly if all transistors in the Gm cell and oscillator are in sub-threshold operation. This implies that the circuit can operate reliably with a narrow VDS margin for each transistor since the gate voltage VX is carefully controlled in closed loop and there is little concern for instability. The self-biasing cascodes M3,6 biases each input pair with a VDS that is highly correlated with the threshold voltage and provides abundant dummy devices to improve matching. The cascodes also reduce the parasitic gate capacitance of the transconductor by reducing the Miller effect that may otherwise lead to increased noise. + +Achieving good noise performance for this configuration relies on minimising the drain current noise from each transistor in the oscillator when referred to the input[^7]. As the ratio IM10/IM0 is reduced the NEF of this circuit will asymptotically decrease to the optimal value for this topology (i.e. Ī·\rtxt{2})[^21]. On the other hand IM10 controls the oscillation frequency which must be sufficiently large such that the oscillator harmonics lie out of band similar to the chopper harmonics. + +The lack of filtering requirements allows the asynchronous implementation to chose a large fosc by reducing Cgate such that any intermodulation products with fchp do not fall in-band [^22] and the circuit size is minimised. When using this configuration as a clocked Ī”Ī£ modulator[^23] this freedom is lost because k1 must be directly related to the oversampling ratio. If the system can afford a fast oversampling clock fosc can still be large but it would be more effective to chose fosc close to the Nyquist frequency such that the harmonics of fosc can be removed reliably during decimation as they have already be shaped by the loop-filter. This circuit also constrains the minimum value for N due to the limited linearity of the transconductor for a given input range. This is because the ratio 2VDD \\(f\\)/(N+1) determines the maximum peak-to-peak amplitude of the error signal seen at VX. Fortunately for high-gain applications \\(f\\) is small resulting in sub-millivolt signal at VX and therefore high linearity can be achieved while using just a few phases in parallel. + +## 6 Pseudo-Differential Oscillator + +The main feature of the oscillators (Fig. 4b) used by this ATC is that it uses differential logic and the delay stage (Fig. 4c) is biased around the middle of the supply making the digital buffers for phase detection more power efficient. The corresponding advantages are best contrasted with a simple inverter delay cell that uses a capacitive load to ground. First the inverter based implementation would experience voltage spikes on VR due to discontinuous conduction of current but would also contaminate the ground with the AC current pulses. The configuration adopted from [^24] exhibits continuous charging & discharging currents that can be confined within the virtual supply nodes VG/VR. Moreover using switching transistors that are several Ī¼ mĀ² in size to load for the preceding gate reduces the sensitivity to process variation with smaller area requirements since the transistor gate capacitance achieves a higher density than poly-poly or metal-oxide-metal (MOM) capacitors. + +## 7 Flicker Rejection Stage + +The flicker removal circuit (Fig. 4d) biases the input of the transconductor by feeding back common mode and differential mode signals using a cross coupled load to enable low voltage operation without an additional common-mode-feedback circuit[^20]. The differential feedback provides flicker cancellation by demodulating the digital output using a switched current DAC that integrates on CL which is a large vertical metal-insulator-metal (MIM) capacitor placed over the analogue circuitry. The diode connected devices M\tss{21-22} represent pseudo-resistors of 100 MĪ© that provide a resistive path to VX and further smooths high frequency tones from fchp and fosc. A significant variation in resistive value is inherently expected but it is important to note that it does not influence the signal amplifying path and the non-dominant poles are far away from the 8 kHz bandwidth of F(s) in Eq. 3 by virtue of not using a second analogue integrator that may compromise stability. The common mode feedback regulates VR with respect to VC by biasing the common mode of VX. For this loop the gain arises from transconductance ratio gm\tss{M19-M20}/gm\tss{M23-M24} together with the drain resistance ratio rdsM10/(rdsM0+rdsM9). This readily provides over 30 dB of gain with the dominant pole provided by the pseudo-resistors that will also attenuate the input common mode signals. + +## 8 Capacitive Feedback Network + +Both electrode inputs feed into separate capacitor arrays that off-set the scaled PWM signal generated at the output to calculate the differential error signal on VX. Each array is 20\\(\times\\)23 Ī¼ mĀ² in size and uses 28 elements in a 4 by 7 configuration with 2.7\\(\times\\)2.7 Ī¼ mĀ² horizontal MOM capacitors with 6 fingers on metal layers 2-7. The following allocation is used: CI=17\\(\times\\), CF=1\\(\times\\), CU=5\\(\times\\), CG=[0-5]\\(\times\\). The particular configuration in Fig. 2 can readily accommodate changes in dynamic range or adjustments in N. This is because \\(f\\) is dominated by the ratio CF/CI such that the design can freely change the number of phases being fed back without significantly changing the amplification dynamics. Additionally increasing CF will extend the dynamic range of the circuit since the noise floor will remain unchanged while providing less signal gain and having excessive circuit bandwidth. + +# 9 The Impact of Technology Parameters + +This section further highlights two features of the proposed topology that can be taken advantage of in advanced CMOS technologies where mismatch and process variation are the leading concern for designers. First we will summarise the scaling properties that arise when chopping in the input signal and secondly we will show that also for the asynchronous case the time-domain integration fundamentally helps with mitigating mismatch in digital to analogue conversion using a behavioural model as example. + +## 10 CMOS Scaling of Chopper Impedance + +First consider the input impedance RIN of the simple chopper structure used here[^25]. For sensor applications it is essential to maintain a large input impedance that avoids signal attenuation because many integrated sensors exhibit a source resistance of several M\\(\Omega\\). + +$$ C_{I} = 10 C_{GM} = \frac{20}{3} W L C_{ox} $$ + +$$ f_{chp} = 2 f_{cor} = \frac{2 K_F}{W L C^2_{ox} e^2_{gd}} $$ + +The expression in Eq. 4 is first used select CI as 10\\(\times\\) the parasitic capacitance CGM seen on VX due the transconductor. This configuration avoids degrading the noise performance during amplification[^17]. CI is further equated in terms of the width W and length L of the input transistors. The chopper frequency is placed at exactly twice the corner frequency fcor which is the frequency at which the flicker noise is equal to the thermal noise floor eĀ²gd of the target input-referred noise profile. Rearrangement of the terms will yield Eq. 5 which uses the trap density KF to estimate for flicker noise for a specific fabrication process[^26]. + +$$ R_{IN} = \frac{1}{2 C_{I} f_{chp} } = \frac{ 3 C_{ox} e^2_{gd} }{80 K_F } $$ + +{{< figure src="/images/jssc2018/sizing.svg" title="Figure 5: Chopper based input impedance as a function of CMOS technology using typical process parameters KF=3.2e-38 and Cox=1.6e-12 [F/Ī¼ mĀ²]/L where L is the technology feature size in nanometre with the oxide thickness being estimated as 1/50 times the feature size." width="500" >}} + +Eq. 6 calculates the expected input resistance and provides a first order estimation of amplifier impedance with respect to process parameters. The fact that RIN depends linearly on Cox implies that input resistance can be improved by using more advanced technologies. The expected values for RIN are plotted in Fig. 5 as a function of CMOS technology with varying noise requirements. Eventually the gate leakage will inhibit this trend as the associated shot-noise limits the sensitivity for technologies beyond 65 nm. This result primarily constrains the selection of transistor size[^25] that in turn determines fchp and fosc. + +## 11 Modulated Mismatch in Oscillators + +Mismatch due to process variation is the primary cause of distortion during multi-bit signal conversion. Minimising this source of nonlinearity is essential for both synchronous and asynchronous Ī”Ī£ modulators because mismatch in the feedback DAC is not shaped by the loop filter [^27]. Fortunately the modulating property of the oscillator can remove this distortion if the phase readout is performed in a parallel fashion [^5]. Here we will concisely demonstrate that property arises because the mismatch induced components are simply being averaged and induce a DC-offset together with tones at the harmonic components of fosc. This uses a mapping that relates the phase difference \\(x\\) to the generated PWM waveform as a function of time \\(\tau\\) defined in Eq. 7. The following expression in Eq. 8 then evaluates the analogue feedback voltage that appears on VX in the ideal case for a given a phase difference of Ī”Ļ† between the two oscillators. + +$$ A(\tau,x) \triangleq\begin{cases} 1 & \tau (mod\: 1) \: < \:x 0 & \text{otherwise} \end{cases} $$ + +$$ V_{X}(t) = f \cdot \sum_{k=0}^{N-1} \underbrace{A( t \cdot f_{osc}+\frac{k}{N}\:,\: \Delta \phi )}_{Q_{k}(t)} $$ + +$$ Q_{k}(t) = (1+\frac{\sigma_{C,k}}{C_U}) A( t \cdot f_{osc} + \frac{k}{N} \: , \: \sigma_{\tau-\mu,k} + \Delta \phi) $$ + +There are two independent sources of mismatch for each phase: the deviation in capacitor weights of CU ĻƒC,k and the differential delay variation in oscillator stages as a fraction of the oscillation period Ļƒ\tss{Ļ„,k} that includes the digital gates generating Q (i.e. inverters and XOR-gate). These are used to formulate Eq. 9 which considers a particular phase of Q(t) and the random mismatch variables that have process dependent normal distributions. The variation in delay will locally increase/decrease the pulse-width of Q for a specific phase \\(k\\). This is a time-invariant component of the gate delay while Ī”Ļ† and Tosc are signal dependent. Precisely formulating the cumulative variation of Ļƒ\tss{Ļ„} will relate the transistor sizing, gate capacitance, and threshold voltage of each delay during operation. + +Notice that A is a linear function of Ī”Ļ† with a gain of 1 for the DC component of the PWM output which can be further expanded to extract the high frequency behaviour. However by design these components are intentionally avoided which should reveal that that the capacitor weights are always uniformly averaged irrespective Ī”Ļ†. Closed-loop operation feeds back each Ļƒ\tss{Ļ„,k} such that the sum all components has zero mean, that is Ļƒ\tss{Ļ„-Ī¼,k}\ = Ļƒ\tss{Ļ„,k}-(\\(\sum_{k=0}^{N-1}\\) Ļƒ\tss{Ļ„,k}/N). The residual variation in delay for each phase inevitably induces spurs at at harmonics of fosc. + +{{< figure src="/images/jssc2018/vco_model.svg" title="Figure 6: A continuous-time multi-phase VCO model for evaluating parameter sensitivity with transient simulations using the logical operator **B** in Eq. 10." width="500" >}} + +Verifying this behaviour is best done by modifying the behavioural model commonly used for oscillators[^28] to accommodate multi-phase readout using the above expressions. Such a model is shown in Fig. 6. This configuration uses an internal time variable at VT that accumulates according to fosc. Given a set of quantisation levels Lk or equivalently the number of phases, a logical function **B** will compute the corresponding PWM waveform of Q which are weighted by the associated capacitor Ck. In this case the digital gate delay arising from computing the phase difference and applying feedback to the capacitive DAC can also be modelled by adjusting Ļ„dly. + +$$ \begin{split}\mathbf{B}(\phi_{S},\phi_{R},L) \triangleq & \left(\phi_{S} > L > \phi_{R} \right) \lor \left(\phi_{S} < \phi_{R} < L \right) & \lor \left( L < \phi_{S} < \phi_{R} \right)\end{split} $$ + +The logical expression in Eq. 10 simply compares the two phases with respect to L and evaluates the digital condition for which the output should be high. This representation implies that the delays correspond to the interval between each level which can be distributed uniformly as Lk=(0.5+k)/L for integers k from 0 to N-1. By distributing the quantisation levels from 0 to 1 the corresponding delays are inherently normalised to the periodicity of Ļ†\tss{S/R} without explicitly having to compute values with respect to fosc even when it is dynamically changing. In addition a difference in oscillator frequency between X\tss{1-2} can also be accommodated by adding a second integrated frequency component to the summation node. + +{{< figure src="/images/jssc2018/dac_mm.svg" title="Figure 7: Simulated output spectrum with a 2.5 kHz input at -6 dB of the full input-range for a equivalent asynchronous flash quantiser with 2.6 bits of resolution and 5 % mismatch in Ļƒ\tss{Ļ„,k} and ĻƒC,k." width="500" >}} + +{{< figure src="/images/jssc2018/dac_mm2.svg" title="Figure 8: Simulated output spectrum with a 2.5 kHz input at -6 dB of the full input-range for a asynchronous VCO quantiser with 2.6 bits of resolution, 300 kHz fosc and 5 % mismatch in Ļƒ\tss{Ļ„,k} and ĻƒC,k." width="500" >}} + +Now the impact of mismatch can be simulated by adding parameter variation in the quantiser levels and the feedback weights (f). The analogous case where the mismatch is not modulated (i.e. fosc is 0) loosely corresponds to a flash-based ADC since the phase is simply being compared with N thresholds. The corresponding spectra of the flash quantiser is shown in Fig. 7 and oscillating quantiser is shown in Fig. 8 where we observe the distortion components in different bands of the spectrum. + +# 12 Measured Results + +{{< figure src="/images/jssc2018/micrograph.svg" title="Figure 9: Micro-photograph of the fabricated prototype showing an annotated floor plan in (a) and the poly layer together with the first three metal layers of the circuit layout in (b)." width="500" >}} + +{{< figure src="/images/jssc2018/setup.svg" title="Figure 10: Experimental setup used for characterising the ATC for low-noise signal conversion showing the respective instruments that were used." width="500" >}} + +The commercially available TSMC 65 nm CMOS LP MS RF technology (1P9M 6X1Z1U RDL) was used to prototype the proposed circuit and demonstrate measured noise and linearity characteristics. The chip micro-photograph of this prototype is shown in Fig. 9. The setup used to take these measurements is shown in Fig. 10 and uses a custom PCB to regulate VDD on-board with additional decoupling. + +The external biasing allows this setup to first tune the circuit sensitivity by adjusting the 1 Ī¼ A reference current which scales all bias currents proportionally and then using VC the oscillation frequency can be fine tuned as VR is controlled which modulates IM10. The supply voltage can be tuned but reducing the supply below 0.5 V limits the biasing current and reduces the circuit sensitivity. Similarly increasing the supply is mainly constrained by the buffers that digitise the oscillator waveform and can induce a large leakage current beyond a voltage of 0.65 V. + +The tone generated by the Agilent signal generator is attenuated resistively by a factor of 10 to achieve a low-noise differential test signal at the input of the instrumentation circuit. Two phases from the asynchronous output Q are captured at 500 MS/s using high-speed digital scope which can then be post-processed off-line to investigate the features of separate PWM signals during different operating conditions. Both the chopper tones and PWM carrier can be observed outside the signal bandwidth at harmonics of 78 kHz and 350 kHz respectively. + +The characterisation procedure evaluates the signal to noise and distortion ratio (SNDR) for varying input amplitudes and frequencies. For a particular device, this characteristic is shown in Fig. 11. In extension, Fig. 12-13 show the distortion components as a function of amplitude along SA and the frequency along SF respectively. Fig. 14 shows what the input-referred power-spectral-density of Q looks like for a particular operating point at P. Here the lowest gain setting of 41 dB was used to demonstrate operation with maximum dynamic range. Although the circuit bandwidth theoretically exceeds the range of frequencies resolved here, the interfering tones seen in Fig. 14 prevent inaccurate measurements to confirm this result. Using a similar procedure the CMRR is characterised and shown in Fig. 15. Again, Fig. 17-16 show the distortion components due to a common mode input as a function of amplitude along SA and frequency along SF respectively. Due to the limited voltage overhead from the current sources in the transcondutor the high-frequency common-mode interference can result in degenerated operation as they are not attenuated by the pseudo-resistor. This mode of failure where the oscillators are saturated is out-lined by the dashed region. + +Note that flicker noise from each oscillator is not removed by the chopper configuration in Fig. 4. However there is no apparent 1/f noise profile in the 10-100 Hz band even though the oscillators are small in size. This is because the rms-gate-voltage fluctuation due to flicker noise at each device is scaled by the open-loop gain of the ATC when referred to the input. + +The maximum achieved THD was 60 dB for a 1 kHz sinusoidal input. The main source of performance degeneration in this circuit for larger input signals is due to the use of poorly regulated bias currents in the differential pair and relying on pseudo-differential phase read-out that allows some common-mode fluctuation at VS to couple to the output Q. Either introducing cascodes or using a folded cascode topology may improve linearity at the cost of increasing the required voltage headroom or reducing the noise efficiency. However the dynamic range exceeding 50 dB should be sufficient for the physiological range of amplitudes for neural activity given that there are no external aggressors present during recording. We can further confirm the effectiveness of the mismatch rejection technique as the Monte Carlo simulation results indicate that each phase should exhibit 1.1 % standard deviation in coupling factor for a 3-Ļƒ\: confidence interval. This should lead to a similar distortion characteristic shown in Fig. 7 with a large number of dominant harmonics being generated due to mismatch errors. Instead distortion is dominated by the second and third harmonic typical of more conventional analogue nonlinearity. + +{{< figure src="/images/jssc2018/sndr_dm_sweep.svg" title="Figure 11: Characterisation sweep evaluating the SNDR performance using differential sinusoid at the input with varying amplitudes and frequencies. " width="500" >}} + +{{< figure src="/images/jssc2018/thd_dm_vid.svg" title="Figure 12: Measured output harmonics due to a differential-mode 1 kHz input signal at different amplitudes corresponding to the SNDR measurement along SA in Fig. 11." width="500" >}} + +{{< figure src="/images/jssc2018/thd_dm_frq.svg" title="Figure 13: Measured output harmonics due to a differential-mode 1.5 mVpp input signal at different frequencies corresponding to the SNDR measurement along SF in Fig. 11." width="500" >}} + +{{< figure src="/images/jssc2018/spec_1k.svg" title="Figure 14: Measured output spectrum due to a differential 2 mVpp input signal at 1 kHz corresponding to the SNDR measurement at point P in Fig. 11." width="500" >}} + +{{< figure src="/images/jssc2018/cmrr_cm_sweep.svg" title="Figure 15: Characterisation sweep evaluating the CMRR performance using large common-mode sinusoid at the input with varying amplitudes and frequencies." width="500" >}} + +{{< figure src="/images/jssc2018/thd_cm_frq.svg" title="Figure 16: Measured output harmonics due to a common-mode 10 mVpp input signal at different frequencies corresponding to the CMRR measurement along SF in Fig. 15." width="500" >}} + +{{< figure src="/images/jssc2018/thd_cm_vid.svg" title="Figure 17: Measured output harmonics due to a common-mode 1 kHz input signal at different amplitudes corresponding to the CMRR measurement along SA in Fig. 15." width="500" >}} + +{{< figure src="/images/jssc2018/ccouple.svg" title="Figure 18: Measured frequency response due to differential 2 mVpp input signal that is capacitively coupled to the ATC input using 0.47 nF capacitors." width="500" >}} + +The input impedance of this circuit was estimated by removing the resistive attenuation network and instead capacitively coupling the signal generator to the input. This assumes that the input will exhibit a RC time constant that is dominated by the coupling capacitor and the resistive/leakage component from the chopper in combination with the ESD protection that can be measured directly. The frequency dependent response is shown in Fig. 18. The 3dB cut-off frequency was estimated at 21.8 Hz. In this case two 0.47 nF capacitors were used to couple both inputs which implies the input resistance is around 31 MĪ©. Parasitics at the input or capacitor variation can inflate this value and it is likely the impedance is closer to the analytical estimate of 22 MĪ© \:according to Eq.6. + +Table 2: System Characteristics and Comparison with State-of-the-Art +| Parameter [unit] | This Work | [^8] | [^29] | [^7] | [^6] | [^30] | [^31] | [^32] | [^33] | [^34] | +|----|----|----|----|----|----|----|----|----|----|----| +| Year | **2017** | 2017 | 2017 | 2017 | 2017 | 2016 | 2016 | 2015 | 2013 | 2012 | +| Application | **EAP** | ECG | LFP | - | LFP | ECG | EAP | EAP | EAP | EAP | +| Technology[nm] | **65** | 40 | 130 | 40 | 40 | 65 | 65 | 90 | 180 | 65| +| Modality | **Time** | Time | Volt. | Time | Volt. | Volt. | Volt. | Volt. | Volt. | Mix | +| Supply-V[V] | **0.5** | 0.6 | 1.2 | 1.2 | 1.2 | 0.6 | 1 | 1 | 0.45 | 0.5 | +| Supply-I[A] | \textbf{2.55 Ī¼} | 5.5 Ī¼ | 5.3 Ī¼ | 14 Ī¼ | 2.5 Ī¼ | 3 n | 3.3 Ī¼ | 2.8 Ī¼ | 2.1 Ī¼ | 10 Ī¼ | +| Bandwidth[Hz] | **11 k** | 150 | 500 | 5 k | 200 | 370 | 8.2 k | 10.5 k | 10 k | 10 k | +| Input Range[mVpp] | **4** | 40 | - | 8 | 100 | 25 | 220 | 1 | 1 | 1 | +| CMRR[dB] | \textbf{(>)60(^\star)} | 60 | 90 | 97 | - | 60 | (>)80 | (>)45 | 73 | 75 | +| SFDR[dB] | **60** | 56 | 72 | 70 | 79 | 75 | (>)40 | (>)37 | (>)46 | (>)34 | +| Noise Floor[V/\rtxt{Hz}] | **36 n** | 0.6 Ī¼ | 46n | 32 n | - | 1.4 Ī¼ | 27.5n | 35n | 29n | 100n | +| RMS Noise[Ī¼ Vrms] | **3.8** | 7.8 | 1.1 | 2.3 | 5.2 | 26 | 4.1 | 3.04 | 3.2 Ī¼ | 4.9 Ī¼ | +| Area[mmĀ²] | **0.006** | 0.015 | 0.013 | 0.015 | 0.135 | 0.15 | 0.042 | 0.137 | 0.25 | 0.013 | +| NEF / PEF | \textbf{2.2 / 2.4} | 8.1 / 39| 2.9 / 10| 4.7 / 27| 22 / 581| 2.1 / 2.6| 3.2 / 10| 1.9 / 3.6 | 1.57 / 1.1 | 5.99 / 18 | + + +{{< figure src="/images/jssc2018/breakdown.svg" title="Figure 19: Power and area contributions from each sub-circuit." width="500" >}} + +The detailed system characteristics are summarised in Table 2. The system power dissipation was specified at 1.3 Ī¼ W from these measurements. The relative power and area utilisation of each subcircuit is compared in Fig 19. As expected, a large fraction of both power and area is used by the main analogue circuits that consists of the low-noise transconductor and the flicker rejection stage. This distribution maximises the NEF and shows that the asynchronous digital logic can provide additional functionality without a significant resource overhead. In relation to the work in [^7], this ATC topology exhibits as significant reduction in power budget although input-referred noise figure is slightly increased. This improvement is not as pronounced in comparison with [^8] but instead the figure of merit is superior. Other works show that both time-based and voltage-based instrumentation can achieve near ideal noise efficiency but only select topologies enable more advanced CMOS process to yield a smaller silicon footprint. The pioneering work in [^34] already demonstrated that resource efficient signal acquisition is best realised by combing signal quantisation and amplification into a single loop. The main drawback was that this mixed signal topology was still relatively complex for hundreds of channels and linearising the feedback for closed loop quantisation came with a considerable reduction in noise efficiency. However the Ī£Ī” operation of the clocked VCO and the Ī£Ī” modulated DAC in the feedback enable a powerful technique that trades off excessive bandwidth for reduced circuit size or DAC complexity. The same technique is applied here to enable a compact multichannel configuration. Our future work will extend on the current prototype by additionally providing electrode off-set cancellation for \textit{in-vivo} experiments with multi-channel recording capabilities. + +# 13 Conclusion + +This work proposes a chopper-stabilised ATC to enable high-impedance electrode instrumentation for integrated sensing systems that require ultra low-voltage operation for power saving. The time-domain techniques enabled by this ATC topology alleviate the difficulty of performing precise instrumentation in advanced CMOS technologies while also providing improved power efficiency together with a substantial reduction in size. The presented configuration achieves a power budget of 1.2 Ī¼ W for a 36 nV/\rtxt{Hz} noise floor requirement and a compact silicon footprint of 0.006 mmĀ². In extension to presenting the implementation details, this work also provides essential modelling and analytical tools for further optimisation. This will enable other mixed-signal systems that require high noise-efficiency, high-speed, or asynchronous signal conversion to effectively adopt time-based techniques and utilise the presented circuit implementation. + +# 14 Acknowledgement + +The authors would like to thank Dr. Pantelis Georgiou, and the Europractice Advanced Technology Stimulation programme for providing access to the TSMC 65 nm technology. The authors additionally thank Yan Liu and the anonymous reviewers for their valuable assistance with this manuscript. + +# Refernces: + +[^18]: J.Guo, J.Yuan, and M.Chan, ''Modeling of the cell-electrode interface noise for microelectrode arrays,'' IEEE Trans. Biomed. Circuits Syst., vol.6, no.6, pp. 605--613, Dec 2012. +[^2]: C.Huang and S.Chakrabartty, ''An asynchronous analog self-powered cmos sensor-data-logger with a 13.56 MHz RF programming interface,'' IEEE J. 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Kuo, ''An improved technique for reducing baseband tones in sigma-delta modulators employing data weighted averaging algorithm without adding dither,'' IEEE Trans. Circuits Syst. II, vol.46, no.1, pp. 63--68, Jan 1999. diff --git a/content/publications/2018/autonomous-soc-for-neural-local-field-potential-recording-in-mm-scale-wireless-implants.md b/content/publications/2018/autonomous-soc-for-neural-local-field-potential-recording-in-mm-scale-wireless-implants.md new file mode 100644 index 0000000..c7a79be --- /dev/null +++ b/content/publications/2018/autonomous-soc-for-neural-local-field-potential-recording-in-mm-scale-wireless-implants.md @@ -0,0 +1,144 @@ +--- +title: "Autonomous SoC for neural local field potential recording in mm-scale wireless implants" +date: 2018-07-23T15:26:46+01:00 +draft: false +toc: true +type: posts +math: true +tags: + - publication + - CMOS + - wireless + - system-on-chip + - biomedical +--- + +Lieuwe B. Leene, Peilong Feng, Michal Maslik, Katarzyna M. Szostak, Federico Mazza, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +Next generation brain machine interfaces fundamentally need to improve the information transfer rate and chronic consistency. This needs them to be highly scalable but also to observe signals that are stable over time. Towards this aim, this paper presents a novel System-on-Chip (SoC) for a mm-scale wireless neural recording node that can be implanted in a distributed fashion. The proposed self-regulating architecture allows each implant to operate autonomously and adaptively load the electromagnetic field to extract a precise amount of power for full-system operation. This can allow for a large number of recording sites across multiple implants extending through cortical regions without increased control overhead in the external head-stage. By observing only local field potentials (LFPs), chronic stability is improved and good coverage is achieved whilst reducing the spatial density of recording sites. The system features a \\(\Delta\Sigma\\) based instrumentation circuit that digitises high fidelity signal features at the sensor interface thereby minimising analogue resource requirements while maintaining exceptional noise efficiency. This has been implemented in a 0.35 Ī¼ m CMOS technology allowing for wafer-scale post-processing for integration of electrodes, RF coil, electronics and packaging within a 3D structure. The presented configuration will record LFPs from 8 electrodes with a 825 Hz bandwidth and an input referred noise figure of 1.23Ī¼ Vrms. The resulting electronics has a core area of 2.1 mmĀ² and a power budget of 80 Ī¼W. + +# 2 Introduction + +There has been significant effort in developing integrated circuits for Brain Machine Interfaces (BMIs)[^1]. These systems enable a wide range of applications from recording neural signals for scientific study to treating neurological conditions. They integrate a multitude of functions for sensing, processing, telemetry and power management. There is a drive to develop wireless modules that are hermetically packaged for chronic implant applications[^2]. Moreover, any reduction in size can substantially improve device efficacy by reducing the impact on surrounding tissue. Any reduction in weight is also highly desirable for behaving animal studies. While a number of proposed systems have relied on PCB[^3] or flexible [^4] technologies that allow low cost, rapid development. This approach leads to substantially larger implants when compared to silicon-based integration[^1]. This is because the silicon substrate enables a large number of electrodes to be integrated directly onto the active die in the shape of an implantable shank[^5]. In contrast, making a large number of intra-device connections has a significant impact on device footprint as well as fabrication complexity with added bio-compatibility constraints [^6]. For this reason a number of groups are investigating millimetre-scale solutions for recording[^7] and stimulation[^8] with all aspects of the implant integrated within the silicon die or micro-machined package. + +{{< figure src="Figures/ENGINI.pdf" title="Figure 1: The ENGINI concept showing: (a) multiple freely floating probes being wirelessly interrogated by a headstage unit; (b) schematic representation." width="500" >}} + +The 'Empowering Next Generation Implantable Neural Interfaces' (ENGINI) project achieves its scalability by utilising multiple mm-scale probes that are each implanted and 'freely floating' in the cortex. These observe field potentials along the cortical column but also laterally through different probes. These are wirelessly coupled to an external headstage with trancutanious and transdural inductive links to deliver power and exchange data. This is illustrated in Fig. 1. + +This particular system relies on the autonomous behaviour of each probe such that a downlink is not required and each probe simply backscatters recorded activity using load shift keying (LSK) modulated at different preconfigured frequencies derived from the carrier. This allows each probe to be uniquely identified without increased control overhead for larger ensembles of probes. The probe circuit additionally includes all front-end instrumentation. An aggressive strategy is thus needed to reduce system complexity to enable package miniaturisation. Such a system may therefore not be able to incorporate more advanced functionality found in the state-of-the-art[^9]. Instead the electronics will perform direct quantization of the 1-825 Hz local field potential (LFP) signal bandwidth that is transmitted directly without compression to allow long term recordings with sub-millimetre spacial resolution for chronic BMI applications. The rest of this paper is organised as follows: Section 3 details the overall system operation and high level implementation; Section 4 describes the circuit implementation; Section 8 presents simulation results and system characteristics; and Section 9 concludes this work with respect to the achieved performance. + +# 3 System Architecture + + +The integrated system architecture is shown in Fig. 2. This shows a single recording unit which is inductively coupled to a primary coil L1 that provides power using a 433 MHz carrier to leave sufficient bandwidth for frequency division multiplexing multiple recording units. In fact the receiving coil L2 will be located on a passive undoped silicon interposer that is flip-chip bonded to the active instrumentation IC. The resonant tank L2 C2 receives the transmitted power and establishes a DC voltage on VDD once the rectifier down-converts the carrier. First a biasing circuit is powered that generates digital flags that indicate the supply voltage level. These flags assist the self-tuning control algorithm to adjust the loading capacitance CT to tune or detune the resonant tank L2C2 and receive a specific amount of power to establish 1.5 V on the VDD supply. This feedback regulates the supply voltage in a course manner without needing active control from the primary side (external controller). This implies the analogue circuits need to accommodate for any fluctuations without diminishing sensor precision. The continuous-time fully-differential modulator topology will further prevent these supply noise aggressors from being aliased in-band during sampling. The system clock can be directly extracted from the resonant tank using adiabatic logic elements to implement a series of frequency dividers before passing the clock to the digital core[^10]. + +{{< figure src="Figures/SYS.pdf" title="Figure 2: ENGINI system architecture for recording LFP at high resolution. This tunes the receiving resonant tank L2C2 to regulate VDD." width="500" >}} + + +# 4 Circuit Implementation + + +This ENGINI prototype has been developed for a 0.35 Ī¼ m CMOS technology such that assembly of the 3D probe can be performed in-house using low-cost micro-fabrication and micro-packaging techniques. The implementation of each subsystem will be detailed below. + +## 5 Self-Regulated Power Harvesting + + +This provides a stable power supply for the electronics and back-scatters digitised recordings. The circuit architecture is shown in Fig. 3. This contains a binary weighted capacitor bank CT, a passive full wave rectifier, and a sensing circuit which are all digitally-controlled. The principle of operation can be described as follows. First, the cross-coupled rectifier converts the induced AC voltage to a DC power on Vx. Then, the low voltage amplifier A2 performs auto-zeroing by shorting CF and simultaneously sampling the rectified voltage onto CI. After sampling, the parallel binary-weighted capacitor bank CT is adjusted to tune or de-tune LC tank on the secondary side. There is therefore a voltage fluctuation at node Vx. The change in Vx is amplified 30\\(\times\\) by A2 which corresponds to the ratio CI/CF. The polarity of the resulting change is digitised using the comparator, instructing the digital control to add or remove parallel capacitors in the next cycle of regulation. Two supply voltage level indicators from the biasing circuit further assist this feedback to increase or reduce the supply voltage and whether to perform LSK respectively. The resistor Rz is added after the output of rectifier such that the speed at which VX can be controlled is not dependent on the load capacitance CL which may be quite large. This allows fast regulation with a clock speed of 846 kHz at the cost of some reduction in power efficiency due to the voltage drop from VX to VDD. + +{{< figure src="Figures/REG.pdf" title="Figure 3: Adaptive power conversion and regulation circuit using full-wave rectifier, tunable LC tank, auto-zeroing amplifier and strong arm comparator" width="500" >}} +% + +## 6 \\(\Delta\Sigma\\) Instrumentation Circuit + + + +The instrumentation circuit used to acquire the electrode recordings is based on the time-domain \\(\Delta\Sigma\\) modulator in [^11]. This uses differential oscillators as the integration element with an asynchronous signal quantizer. However the implementation presented here introduces an additional Gm-C integrator and a feed-forward path to realise second-order noise shaping. This reduces the oversampling ratio (OSR) requirement and substantially increases the dynamic range of the system. A single-ended equivalent of the fully-differential structure used here is shown in Fig. 4. + +{{< figure src="Figures/SDM.pdf" title="Figure 4: Simplified equivalent of the second-order \\(\Delta\Sigma\\) modulator using time-domain signal quantization exhibiting a bandpass response due to the switched current DAC which removes any electrode offset." width="500" >}} +% + +Note that this is a DC-coupled configuration where the analogue node VO tracks the electrode potential. An electrode offset larger than \\(\pm\\)100 mV can be accommodated without saturating the modulator by adding the digitally switched and duty cycled current in the feedback path. The quantized signal Q is AC coupled onto VO with a relatively large attenuation factor due to capacitive division Ī±=1/(C0/CC+1) which will allow the in-band signal gain. This can be confirmed using the small signal model for this circuit described in Eq. 1-4 where H(s) represents the second-order loop filter and C(s) the charge pump with capacitive feed-forward. The factor k1=OSR fsmp/2 reflects the modulator bandwidth in terms of the target sampling frequency fsmp. The factor k2=2\\(\pi\\) fhp represents the integration constant of the charge pump in terms of the high-pass cut-off frequency fhp. This approach is inspired by the first order modulator in [^12]. The implemented circuit uses an OSR of 64, a 1 Hz high-pass corner frequency, and third order CIC filter to decimate the output. This leads to the noise and signal transfer functions shown in Fig. 5. + +$$ STF(s) = \frac{H}{1+\alpha C H} $$ + +$$ H(s) = \left( 2 + \frac{k1}{s} \right) \frac{k1}{\alpha s} $$ + +$$ NTF(s) = \frac{1}{1+\alpha C H} $$ + +$$ C(s) = 1 + \frac{k2}{s} $$ + +{{< figure src="Figures/BODE.pdf" title="Figure 5: Analytical quantisation noise and signal transfer functions of the proposed modulator configuration." width="500" >}} + +## 7 Reference and Biasing Circuit + +The reference circuit loosely based on [^13] is used to establish the required noise shaping and precision in the \\(\Delta\Sigma\\) modulators. This provides a stable bias current using the structure shown in Fig. 6. Its core entails a Ī²-multiplier generating a reference current of 800 nA flowing through resistor R1. This is scaled and mirrored to generate 8 current sinks for the front-end. Generation of a nominal 1.2 V reference is achieved by passing the reference current through a diode-connected PNP BJT B1 and multiplying the BE (base-emitter) voltage using amplifier A2 with resistive feedback. As the output voltage VREF primarily depends on the BJT BE voltage and ratio of R2 and R3 it is possible to achieve a very accurate voltage output independent of process variation. + +Since the circuit is going to be operated in a neural implant it is expected that its operating temperature is going to remain stable and it is therefore not necessary to optimise the circuit for temperature independence. The main design target therefore lies in maximisation of the achieved PSRR (Power Supply Ripple Rejection) and minimisation of power consumption. The PSRR of the Ī²-multiplier is maximised by cascoding both PMOS and NMOS current mirrors (M1\&M2, M3\&M4) [^14]. The same is achieved for VREF by employing a regulated cascode for BJT current generation. + +In addition, the reference circuit generates logic levels indicating that the supply voltage has reached \\(\approx\\) 1 V, 1.3 V and 1.5 V used by the control loop of the SoC. The first indicator (1 V) is designed using a current source inverter as described in [^15]. The remaining two indicators are derived from VREF to ensure good tolerance to process variations. + +{{< figure src="Figures/refc.pdf" title="Figure 6: Schematic of the reference and biasing circuit (start-up circuit not shown)." width="500" >}} + +# 8 Simulation Results + +The circuit was designed and validated using PSP models from the commercially available AMS 0.35 Ī¼ m CMOS technology (C35B4C3 4M/2P/HR/5V). + +Preliminary simulation results show the instrumentation achieves a thermal noise floor of 45 nVrms/\\(āˆš{\text{Hz}}\\) and uses 2.25Ī¼ A of current from a 1.5 V supply including also the decimation filter. This indicates a 3.4 Ī¼ W power budget per recording channel. The decimated output is shown in Fig. 7, achieving a dynamic range larger than 80 dB since the maximum modulator input range is \\(\pm\\)6 mV excluding the \\(\pm\\)100 mV linear range of the charge pump feedback. + +The designed reference circuit consumes a bias current of 5 Ī¼ A and generates an output nominal voltage V\tss{REF,Ī¼}=1.208 V with a standard deviation of Ļƒ =10.87 mV as shown by post-layout Monte Carlo simulation of 500 runs. Similarly, the output bias current was found to be I\tss{REF,Ī¼}=150.4 nA and Ļƒ IREF=15.6 nA. The mismatch between two different bias currents has a standard deviation of Ļƒ \tss{\\(\Delta\\)IREF}=5.35 nA. The PSRR of the reference voltage with respect to frequency can be seen in Fig. 8. This shows that the reference circuit features an almost flat frequency response and a PSRR higher than 70 dB at small and high frequencies. + +The overall system specifications are summarised in Table 1. Comparing the ENGINI system with other SoCs for brain machine interfaces demonstrates an increase in dynamic range and reduction in core size for equivalent noise performance as a result of the proposed architecture. The active silicon CMOS is currently being fabricated and will be flip-chip bonded onto a silicon based carrier. The two dies are illustrated and annotated in Fig. 9. Both dies are 16 mmĀ² in size however the interposer is passive and only needs to embed the seal, coil, and electrode interconnect metallisation. Preliminary characterisation has shown that the L2 can have an inductance of 5 nH with a Q-factor \textgreater12. + +{{< figure src="Figures/SPEC.pdf" title="Figure 7: Output spectrum of the \\(\Delta\Sigma\\) instrumentation circuit from transient simulation using a 10 mVpp sinusoidal input tone at 210 Hz." width="500" >}} + +{{< figure src="Figures/PSRR.pdf" title="Figure 8: PSRR (Power Supply Ripple Rejection) at VREF. This shows a PSRR of Ī¼ =78.29 dB & Ļƒ =1.58 dB, Ī¼ =69.94 dB & Ļƒ =1.59 dB and Ī¼ =79.95 dB & Ļƒ =0.52 dB at DC, 64 kHz and 433 MHz respectively." width="500" >}} + +Table 1: System Characteristics and Comparison with State-of-the-Art +| Parameter [unit] | This Work \\(\dagger\\) | [^1] | [^16] | [^3]| +|----|----|----|----|----| +| Year | **2017** | 2017 | 2015 | 2016 | +| Application | **LFP** | ECoG | ECoG | EAP | +| Tech.[nm] | **350** | 180 | 65 | 350 | +| Supply-V[V] | **1.5** | 0.8 | 0.5 | 1.8| +| Total-P[W] | \textbf{80 Ī¼}(\star) | 0.1 m | 0.2 m | 51 m | +| Core-A[mmĀ²] | **2.1** | 9 | 5.8 | 12.5 | +| \# Channels | **8** | 16 | 64 | 8| +| Bandwidth[Hz] | **825** | 1 k | 500 | 11 k| +| DR[dB] | **85** | 55 | 52 | 50 | +| IRN [Ī¼ Vrms] | **1.3** | 1.5 | 1.3 | 2.9 | +\\(\dagger\\) Based on preliminary simulation results. \\(\star\\) Includes rectifier loss. + +{{< figure src="Figures/D2D.pdf" title="Figure 9: Annotated design for each silicon die that will be flip-chip bonded together. This shows the bonding pads, inductive coil, seal ring, and core ENGINI system to scale." width="500" >}} + +# 9 Conclusion + +This work demonstrates a compact system on chip architecture for LFP based recording systems that aims to distribute several implantable probes into the cortical tissue in a scalable fashion by relying on autonomous sensor operation. Using the resonant tuning for supply regulation and \\(\Delta\Sigma\\) modulator instrumentation has lead to a significant reduction in system complexity typically seen in BMI SoCs. Moreover this configuration is able to operate at high efficiency without much constraint on technology requirements since the overall system power budget is estimated to be 80 Ī¼ W from preliminary simulation results. The approach to brain machine interfaces presented here will lead to safer and simpler systems while delivering high fidelity multi-electrode recordings which is essential for applications in a clinical environment.% + +# 10 Acknowledgement + +This work was supported by EPSRC grant EP/M020975/1. + +# References: + +[^9]: M.A.B. Altaf, C.Zhang, and J.Yoo, ''A 16-channel patient-specific seizure onset and termination detection SoC with impedance-adaptive transcranial electrical stimulator,'' IEEE J. Solid-State Circuits, vol.50, no.11, pp. 2728--2740, Nov 2015. +[^1]: S.Ha etal., ''Silicon-integrated high-density electrocortical interfaces,'' Proc. IEEE, vol. 105, no.1, pp. 11--33, Jan 2017. +[^16]: R.Muller etal., ''A minimally invasive 64-channel wireless $\mu$ECoG implant,'' IEEE J. Solid-State Circuits, vol.50, no.1, pp. 344--359, 2015. +[^8]: A.Khalifa, J.Zhang, M.Leistner, and R.Etienne-Cummings, ''A compact, low-power, fully analog implantable microstimulator,'' in IEEE Proc. ISCAS, May 2016, pp. 2435--2438. +[^7]: E.Moradi etal., ''Backscattering neural tags for wireless brain-machine interface systems,'' IEEE Trans. Antennas Propag., vol.63, no.2, pp. 719--726, Feb 2015. +[^6]: Y.K. Lo etal., ''A fully integrated wireless SoC for motor function recovery after spinal cord injury,'' IEEE Trans. Biomed. Circuits Syst., vol.11, no.3, pp. 497--509, June 2017. +[^11]: L.Leene, T.Constandinou etal., ''A 0.5 V time-domain instrumentation circuit with clocked and unclocked operation,'' in IEEE Proc. ISCAS, May 2017, pp. 2619--2622. +[^5]: C.M. Lopez etal., ''A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13$\mu$m SOI CMOS,'' IEEE Trans. Biomed. Circuits Syst., vol.11, no.3, pp. 510--522, June 2017. +[^4]: S.A. Mirbozorgi etal., ''A single-chip full-duplex high speed transceiver for multi-site stimulating and recording neural implants,'' IEEE Trans. Biomed. Circuits Syst., vol.10, no.3, pp. 643--653, June 2016. +[^12]: H.Kassiri etal., ''27.3 all-wireless 64-channel 0.013mm$^2$/ch closed-loop neurostimulator with rail-to-rail DC offset removal,'' in IEEE Proc. ISSCC, Feb 2017, pp. 452--453. +[^2]: D.A. Schwarz etal., ''Chronic, wireless recordings of large-scale brain activity in freely moving rhesus monkeys,'' Nature Methods, vol.11, pp. 670--676, April 2014. +[^15]: M.H. Cho etal., ''Development of undervoltage lockout (UVLO) circuit configurated schmitt trigger,'' in IEEE Proc. ISOCC, Nov 2015, pp. 59--60. +[^14]: G.Giustolisi and G.Palumbo, ''A detailed analysis of power-supply noise attenuation in bandgap voltage references,'' IEEE Trans. Circuits Syst. I, vol.50, no.2, pp. 185--197, Feb 2003. +[^13]: Y.Osaki, T.Hirose, N.Kuroki, and M.Numa, ''1.2-V supply, 100-nW, 1.09-V bandgap and 0.7-V supply, 52.5-nW, 0.55-V subbandgap reference circuits for nanowatt CMOS LSIs,'' IEEE J. Solid-State Circuits, vol.48, no.6, pp. 1530--1538, June 2013. +[^10]: S.Houri etal., ''Limits of CMOS technology and interest of NEMS relays for adiabatic logic applications,'' IEEE Trans. Circuits Syst. I, vol.62, no.6, pp. 1546--1554, June 2015. +[^3]: S.B. Lee etal., ''An inductively-powered wireless neural recording system with a charge sampling analog front-end,'' IEEE Sensors J., vol.16, no.2, pp. 475--484, Jan 2016. diff --git a/content/publications/2018/direct-digital-wavelet-synthesis-for-embedded-biomedical-microsystems.md b/content/publications/2018/direct-digital-wavelet-synthesis-for-embedded-biomedical-microsystems.md new file mode 100644 index 0000000..f9f1e84 --- /dev/null +++ b/content/publications/2018/direct-digital-wavelet-synthesis-for-embedded-biomedical-microsystems.md @@ -0,0 +1,137 @@ +--- +title: "Direct Digital Wavelet Synthesis for Embedded Biomedical Microsystems" +date: 2018-10-17T15:26:46+01:00 +draft: false +toc: true +type: posts +math: true +tags: + - publication + - CMOS + - digital-logic + - signal-synthesis + - wavelets +--- + +Lieuwe B. Leene, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +This paper presents a compact direct digital wavelet synthesizer for extracting phase and amplitude data from cortical recordings using a feed-forward recurrent digital oscillator. These measurements are essential for accurately decoding local-field-potentials in selected frequency bands. Current systems extensively to rely large digital cores to efficiently perform Fourier or wavelet transforms which is not viable for many implants. The proposed system dynamically controls oscillation to generate frequency selective quadrature wavelets instead of using memory intensive sinusoid/cordic look-up-tables while retaining robust digital operation. A MachXO3LF Lattice FPGA is used to present the results for a 16 bit implementation. This configuration requires 401 registers combined with 283 logic elements and also accommodates real-time reconfigurability to allow ultra-low-power sensors to perform spectroscopy with high-fidelity. + +# 2 Introduction + +Spectrum analysis is an essential tool for many biomedical applications to provide electrode impedance characteristics[^2][^1] and assist in signal decomposition for brain machine interfaces (BMI)[^4][^3]. These techniques typically rely on generating a precise reference tone to characterise the spectral power distribution of a signal or analyse the frequency dependent response of a subsystem. However generating a sinusoid demands a significant mount of valuable hardware resources for both analogue[^5] and digital[^6] implementations and can inhibit an efficient solution. For this reason numerous techniques such as Ī”Ī£\:modulation[^7] and closed loop adaptive filtering[^8] have been proposed to reduce system integration costs and enhance the capability of biomedical sensing systems. + +In line with these developments, this work proposes a hardware efficient direct digital wavelet synthesizer (DDWS) to extract both time and frequency information simultaneously. The DDWS extends on conventional direct digital frequency synthesis (DDFS) systems[^9] the same way the generalised s-transform[^10] extends on the Fourier transform by resolving the time-evolving frequency content of non-stationary signals. Current systems typically use the CT/DT wavelet-transform to extract this type of information because it is more hardware efficient than the windowed/short-time Fourier transform[^11]. However for applications like electrode-impedance spectroscopy and measuring phase synchrony in brain activity, wavelets cannot be used because the phase information is either not preserved or does not use a global reference leading to incomplete measurements. This presents an opportunity for mixed signal techniques to be used instead of resorting to transforms in the digital domain to extract time-frequency-phase signal components[^12]. The DDWS presents one approach to reduce hardware requirements for this type of measurement because it allows the direct extraction of a specific signal band but also appropriately decimates the output as each wavelet correlation yields a single result for that particular time-frame thereby reducing overall data rate. + +{{< figure src="/images/biocas2018/concept.svg" title="Figure 1: Instrumentation system that extracts non-stationary frequency components from electrode recordings using wavelets that are generated by the proposed DDWS." width="500" >}} + +The overall system architecture is shown in Fig. 1. This represents the front-end for a local-field-potential decoding system for BMIs[^13]. After amplification the electrode potential is mixed with two quadrature wavelets that have 50% overlapping time-frames. Similar to conventional spectroscopy[^6], the phase and amplitude can be recovered for each frame by evaluating the down-converted DC-component and will correspond to the frequency band set by the DDWS configuration. The DDWS will generate timing information for each frame that can be used to reset an analogue integrator that proceeds the mixing process and accurately extract the DC value. The proposed topology follows the principle of analogue-to-information conversion where the input signal is mixed linearly/non-linearly to maximally reduce the sampling speed of the data converter and optimise the spectral efficiency at the output. This alleviates the speed of signal conversion and digital processing. If the synthesis of these wavelets can be made highly resource efficient and programmable, several signal features can be directly extracted in the analogue domain by using multiple DDWS modules in parallel. + +The rest of this paper if organised as follows: Sec 3 will introduce a recurrent digital oscillator core that forms the basis of the DDWS. Sec 4 describes the DDWS topology and Sec 5 presents synthesis data together with simulation results. Finally, Sec 6 will conclude this work. + +# 3 A Feed-Forward Digital Oscillator Core + +{{< figure src="/images/biocas2018/core.svg" title="Figure 2: Feed-forward digital oscillator showing the block diagram in (a) and the z-domain pole-zero plot of the feedback loop in (b) with decreasing k for a fixed frequency." width="500" >}} + +There are a number of recursive oscillator topologies available in the literature with two identifiable basis; biquads and waveguides[^9]. The feed-forward structure proposed here is derived from the standard coupled quadrature structure that provides feedback with equi-amplitude quadrature outputs. This structure is shown in Fig. 2a. The feed-forward configuration uses two integrators in negative feedback with two coefficients f and k to specify frequency and Q-factor respectively. This will require the same number of coefficient multiplications as the coupled quadrature configuration but uses 4 2-input summation nodes opposed to 2. The benefit here is that there are only 2 scaling coefficients and they are linearly dependent on the desired oscillation frequency. The conventional structure has fĀ²\:dependence that requires excessive integrator precision to accurately resolve very small frequencies typically of interest for biomedical signals. + +$$ \begin{bmatrix}\hat{x}_Q \hat{x}_I\end{bmatrix} =\underbrace{\begin{bmatrix}(1-k f) & -f f & (1-k f)\end{bmatrix}}_{\mathbf{R}(k,f)}\cdot\begin{bmatrix}x_Q x_I\end{bmatrix} $$ + +Digital oscillators are usually characterised in terms of a rotation matrix \\(\mathbf{R}\\)(k,f) that is applied to two state variables xQ and xI. This representation is formulated in Eq. 1. For clarity the kĀ²\: factor is ignored in this analysis since it yields a simpler solution to the basic feed-forward configuration. In this case we are interested in manipulating the pole location adaptively which is why we will solve for the complex pole positions of this dynamic system below. + +$$ D_O(z) = f^2 \left(\frac{z^{-1}}{1-z^{-1}} \right)^2 + 2k f \frac{z^{-1}}{1-z^{-1}} $$ + +$$ denum\left(\frac{1}{1+D_O(z)}\right) = z^2 + (2 f k - 2)z + (f^2 - 2 f k + 1 ) $$ + +The z-domain representation of the open loop response DO is shown in Eq. 2 and the the corresponding expression for the denumerator of the closed loop response is shown in Eq. 3. + +$$ \begin{split}poles\left(\frac{1}{1+D_O(z)}\right) = 1 - k f \pm āˆš{ f^2 k^2 - f^2}\end{split} $$ + +Finding the poles yields the two solutions in Eq. 4 that correspond to the complex pair P\tss{Q/I} which dictate the oscillatory behaviour of this circuit. This reveals the behaviour shown in Fig. 2b which is that adjusting k will rotate the pole-pair in and out of the unit circle resulting in a growing or receding complex exponential or oscillation. It is also readily seen that for the case k=0 the pole locations lie outside the unit circle. Solving for a steady state solution where P\tss{Q/I} are on the unit circle gives k=f/2. + +# 4 DDWS Core]{\\(\Delta\Sigma^2\\) type DDWS Core + +In order to realise the proposed multiplier-free DDWS, two additional components will be introduced. The first is a second order digital Ī”Ī£ \: modulator that will allow us to mitigate the need to for high-precision multipliers and the second is a controller module that will regulate the dynamic oscillatory behaviour given a set input parameters. This configuration is shown in Fig. 3 together with sub-blocks for amplitude tracking and noise shaping. + +{{< figure src="/images/biocas2018/ddws-core.svg" title="Figure 3: Block diagram of the direct-digital wavelet synthesizer showing the system in (a), the amplitude tracking logic in (b) and the Ī”Ī£Ā² \: modulator in (c)." width="500" >}} + +Introducing a Ī”Ī£ \: modulator is a well established means reduce hardware complexity for multiplication as the \\(\pm\\)1 single bit-stream implies that the coefficients (f & k) can be directly accumulated accordingly [^14]. This is particularly appropriate here because the typical clock speed will be at a substantially higher frequency than the signal bandwidth of interest. For biomedical systems these frequencies are almost always sub-10 kHz. Hence we can freely choose an oversampling ratio (OSR) according to our dynamic range requirement using DR=-11 dB+50 log(OSR)[^15]. + +The block diagram in Fig. 3 also includes logic for tracking the peak to peak amplitude of the internal oscillation. This is done by detecting zero-crossings of either integrator and latching the other that will at that moment be at the peak amplitude. The oscillation amplitude is used to control the dynamics of the wavelet generator and prevents saturation. + +\begin{algorithm} + \DontPrintSemicolon + \KwIn{Wavelet synthesis parameters (f, cbw, ic, vpp)} + \KwResult{Quadrature bit-streams (D1\tss{Q/I}, D2\tss{Q/I})} + **Initialise:** x1Q=ic, x1I=0, x2Q=vpp/2, x2I=0, s1=cbw, s2=-cbw + \Begin{ + \ShowLn + k1 = 0.5 + s1(D1PP - vpp) + k2 = 0.5 + s2(D2PP - vpp) + \\(\mathbf{x1}\\)\tss{Q/I}[n] = \\(\mathbf{R}\\)(k1,f) \\(\cdot\\) \\(\mathbf{x1}\\)\tss{Q/I}[n-1] + \\(\mathbf{x2}\\)\tss{Q/I}[n] = \\(\mathbf{R}\\)(k2,f) \\(\cdot\\) \\(\mathbf{x2}\\)\tss{Q/I}[n-1] + \uIf{ D1PP \textgreater vpp **or** $|\\(k1\\)|$ \textless cbw/2}{s1=-cbw} + \ElseIf{ D1PP \textless ic **and** s2\textless0 }{s1=cbw} + \uIf{ D2PP \textgreater vpp **or** $|\\(k2\\)|$ \textless cbw/2}{s2=-cbw} + \ElseIf{ D2PP \textless ic **and** s1\textless0 }{s2=cbw} + } + \BlankLine + \caption{DDWS Controller} + \label{algo:ddws-control} +\end{algorithm} + +An overview of the control logic is described in Alg. 1. Here the notation from Eq. 1 is used to simplify how the oscillator states evolve by using the rotation matrix. In the behavioural implementation lines 5-6 are realised by a series of conditional statements that increment/decrement the oscillator states \\(\mathbf{x}\\)\tss{Q/I} and then compute the feed forward value by adding or subtracting k1/k2. Notice that we use the state variable s1/s2 to iteratively make sure only one oscillator is growing in amplitude while the other is shrinking in amplitude but at all times the growth is bounded by how close the peak to peak value is to the target maximum vpp. In fact several configurable parameters are used here in addition to vpp to specify the wavelet dynamics. Like before f controls the oscillation frequency in rads per second. The parameter ic determines the extinction ratio between the minimum and maximum oscillation amplitudes and cbw controls the window bandwidth together with ic to allow high or low out-of-band rejection. + +Let us briefly identify the type of envelope modulation used here that allows these wavelets to perform time-frequency analysis. First it is important to point out that the phase state of each oscillator is not effected by small changes in k during operation. This means that the phase of the quadrature oscillator always accumulates with respect to the global reset. From our derivation in Sec 3 we can evaluate that, while s1/s2 does not change, the change in envelope can be expressed as Eq. 5 and which is resolved in Eq. 6 to show that the envelope has a sigmoid characteristic. In fact, As s1/s2 toggles the DDWS generates double sided sigmoid with a small discontinuity in the derivative the sinusoids that is proportional to cbw. + +$$ \frac{dx(t)}{dt} = a x \cdot (b - x(t)) $$ + +$$ x(t) = \frac{b}{1+(b)e^{-a b x(t)}} $$ + +# 5 Implementation Results + +A behavioural verilog model of the proposed wavelet generator has been implemented and synthesized using a low-power, small-footprint, LCMXO3LF FPGA device from Lattice Semiconductor and the Lattice Synthesis Engine (Version 3.10.2). The logic requirements and simulation results provide preliminary validation and can be further optimised given application constraints such as precision or resource limitations. The synthesis results are presented in Table 1 to show the relative hardware complexity for the 4-Ī”Ī£\: modulators, the two quadrature oscillators DX 1 & 2, and the top level FSM that controls the dynamics according to the input parameters. These requirements can be further compared using the pie chart in figure 4. Including the modulator hardware is useful if analogue requirements need to be relaxed to 1-bit digital-to-analogue conversion but this may not always be applicable. In fact, if a multi-bit output can be used instead, the modulators can be replaced by two multipliers to further optimise the resource requirements. + +Table 1: Synthesis Summary +| Resource | LUT4 | Register | SLICE | +|----|----|----|----| +| FSM | 10 | 24 | 10 | +| DX \: (2x) | 5 | 217 | 125 | +| Ī”Ī£ \: (4x) | 16 | 160 | 112 | +| DDWS Total | 31 | 401 | 252| + +{{< figure src="/images/biocas2018/resource.svg" title="Figure 4: Resource distribution for the DDWS with the cost each sub-system annotated." width="500" >}} + +Using a hypothetical configuration, the model was also simulated to demonstrate overall characteristics to filter out a specific 3.5 mHz normalised frequency band. The later implies that a 1.4 kHz system clock yields a 5 Hz center frequency. With reference to Algo \ref{algo:ddws-control} we used the following parameters: f=0.011, OSR=32, vpp=1, ic=2\\(^{-6}\\). In figure 5 cbw=2\\(^{-2}\\) and in figure 6 cbw=2\\(^{-6}\\) in order to show narrow and wide bandpass selection settings. Both figures show the time & frequency domain characteristics as well as the dynamic change in the pre-scaled feed-forward factor as the amplitude of oscillation increases before the controller changes state and starts suppressing the oscillation to near the end of the time window. + +{{< figure src="/images/biocas2018/narrow.svg" title="Figure 5: Simulation result showing the transient output after decimation of the two quadrature bit-streams (top), the adaptive control of k (middle), and the frequency response of the generated wavelet. " width="500" >}} + +{{< figure src="/images/biocas2018/wide.svg" title="Figure 6: Simulation result showing similar results as in figure 5 but with a smaller value of cbw." width="500" >}} + +# 6 Conclusion + +This work demonstrated a novel approach to generate wavelets using direct digital synthesis opposed to storing them in memory which is particularly useful for ultra-low-power medical devices that need to perform coherent time-resolved analysis of low frequencies. The synthesis results demonstrate that the dynamic approach avoids large memory requirements and digital complexity while retaining high precision frequency selection with reconfigurable bandwidths. + +# Refernces: + +[^11]: I.Daubechies, ''The wavelet transform, time-frequency localization and signal analysis,'' IEEE Trans. Inf. Theory, vol.36, no.5, pp. 961--1005, Sep 1990. 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[Online]: http://dx.doi.org/10.1109/TBME.2005.847523 diff --git a/content/publications/2019/a-3rd-order-time-domain-delta-sigma-modulator-with-extended-phase-detection.md b/content/publications/2019/a-3rd-order-time-domain-delta-sigma-modulator-with-extended-phase-detection.md new file mode 100644 index 0000000..0694754 --- /dev/null +++ b/content/publications/2019/a-3rd-order-time-domain-delta-sigma-modulator-with-extended-phase-detection.md @@ -0,0 +1,126 @@ +--- +title: "A 3rd order time domain delta sigma modulator with extended-phase detection" +date: 2019-05-26T15:26:46+01:00 +draft: false +toc: true +type: posts +math: true +tags: + - publication + - CMOS + - time-domain + - instrumentation + - circuit +--- + +Lieuwe B. Leene, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +This paper presents a novel analogue to digital converter using an oscillator-based loop filter for high-dynamic range bio-sensing applications. This is the first third-order feed-forward Ī”Ī£ modulator that strictly uses time domain integration for quantisation noise shaping. Furthermore we propose a new asynchronous extended-phase detection technique that increases the resolution of the 4 bit phase quantiser by another 5 bits to significantly improve both dynamic range and reduce the noise-shaping requirements. Preliminary simulation results show that this type of loop-filter can virtually prevent integrator saturation and achieves a peak 88 dB SNDR for kHz signals. The proposed system has been implemented using a 180 nm CMOS technology occupying 0.102 mmĀ² and consumes 13.7 Ī¼ W of power to digitise the 15 kHz signal bandwidth using a 2 MHz sampling clock. + +# 2 Introduction + +Time and frequency based circuit techniques have received considerable interest in the recent years as a means to solve key challenges with integrating traditional analogue functionality into digital systems and take advantage of technology scaling [^1]. A feature in many of these developments relies on the ease by which an analogue voltage or current can be converted into time encoded signals using a simple digital ring oscillator that interfaces directly with standard logic elements. Generally time encoding implies that the analogue signal is represented by the time interval between digital events where we may use the frequency or phase difference to encode digital bit streams that are termed continuous time binary value (CTBV) signals. + +In ADCs specifically, frequency readout carefully counts the number of oscillations relative to a precise reference clock period[^2] while phase readout digitises the relative phase difference of two matched oscillators using an array of phase detectors [^3]. Seemingly the advantage of using a counter is that the dynamic range of the output is more flexible in the sense that the counter depth is adjustable to realise low or high precision readout. In contrast phase readout directly relates the number of delay stages to the number of quantisation levels which makes high resolution phase quantisation resource intensive in the analogue sense as these delay stages should be matched to avoid off-sets and spurious tones. The advantage of the later is that the output is unary encoded with inherent mismatch averaging properties that simplifies the feedback circuitry during digital to analogue conversion [^3]. That said, effort has been made to improve the phase digitisation in other ways but has been limited to single bit improvements [^4] or constrains the system to use synchronous operation [^5]. + +Both readout techniques conventionally use synchronous circuits where the the timing information is latched which makes it difficult to further process signals in the time-domain without incurring quantisation noise. This can obstruct higher order noise shaping schemes although several solutions have already been proposed. For instance [^6] uses gated ring oscillators to realise a multi-stage noise shaping (MASH) topology and [^7] uses a higher-order analogue loop-filter to precede the oscillator to improve dynamic range. However both have yet to demonstrate the feasibility for high dynamic range data conversion and the analogue reliance limits the scalability of time-based operation in a way that is characteristically more useful for digital systems. + +More recent work considers the use of asynchronous readout that may be able to process signals entirely in the time-domain with reduced analogue complexity [^10][^8][^9]. This is promising as a variety of specialised loop filter topologies can not be realised using synchronous prior art. Moreover asynchronous digital systems can utilise a number of power-saving techniques such as signal-activity dependent processing [^11] or event driven control to reduce complexity and speed up operation [^12]. + +{{< figure src="/images/iscas2019/td_sdm.svg" title="Figure 1: Block diagram of the third-order \\(\Sigma\Delta\\) instrumentation loop that uses time-domain integrator for noise shaping and an extended phase detector for high-resolution phase digitisation." width="500" >}} + +The system proposed here is shown in Fig. 1. This represents a third-order time domain Ī”Ī£ modulator that uses capacitive feedback to linearise the digitisation process similar to [^9]. The primary contributions here aim to make improvements in the overall dynamic range of time based ADCs that use oversampled noise shaping. The negative feedback mechanism uses the error signal appearing on Vx to feed a cascade of oscillator-based integrators inside the continuous-time (CT) loop filter H(s) that accumulates quantisation errors. This is followed by a phase detector that digitises the phase difference of a pseudo-differential oscillator. The distinction is that the loop filter uses a feed-forward topology with better noise-shaping dynamics than prior-art together with an extended-phase-detector (EPD) that asynchronously accounts for phase overflow without incurring distortion. Both of these innovations result in higher dynamic range by performing higher-order quantisation noise-shaping and resolving the baseline phase state with a total precision of 9 bits. + +This paper is organised as follows: Sec 3 will present the operating principle of oscillator-based Ī”Ī£ modulation which guides the design for the proposed circuit described in Sec 4. Sec 5 will then demonstrate operating characteristics followed by Sec 7 that concludes this work. + +# 3 Oscillator Based \\(\Delta\Sigma\\) Conversion + +The design procedure of an oscillator based loop filter follows closely to that of conventional Gm-C based CT modulators as the anti-aliasing properties are retained with similar concerns for paracitic pole locations. The difference is that the small-signal currents are integrated by modulating the phase of a current controlled oscillator (CCO) instead of the voltage on a capacitor. This results in better output dynamic range as the oscillator based integrator can be full swing while Gm-C integrators usually have limited voltage-swing for intermediate stages to avoid non-linear behaviour of the proceeding stage. The large signal swing can be tolerated by using a digital current DAC inside intermediate integration stages that exhibit better linearity with a full-swing input. Arguably Gm-C integrators will exhibit better noise performance than current DACs which is why the first stage of the oscillator-based loop filter also uses a transconductor in sub-threshold operation to maximise noise efficiency of the overall system. + +$$ \phi (t) = \frac{f_{osc}}{I_{bias}} \int_{-\infty}^{t} i_{\Delta}(\tau) \: d\tau $$ + +As a basis for oscillator based circuits, Equation 1 formulates the small-signal phase response Ļ†(t) of a CCO in terms of the oscillation frequency fosc, the static bias current Ibias, and the small-signal current input i\tss{Ī”}[^13]. This simply tells us that the total amount of charge injected over time is accumulated and scaled by an integration factor. It is interesting to note that Ļ†\: is dimensionless and represents a unit of time relative to the oscillator period. The signal driving this circuit is typically a transconductor or a current-steering DAC while the output Ļ†\: can be read using a phase detector. Realising the loop filter uses the coefficients from an optimised CT-Ī”Ī£ signal flow-graph for a 16 level quantiser and scales the transconductive elements according for a given set of oscillator frequencies. + +While this integration property is well established, it is important to point out that the oscillator output is inherently discretised in the value domain in a non-linear fashion before it is clocked. This process generates distortion tones at harmonics of the oscillation frequency and can be interpreted in terms of a pulse-width-modulation process. Consolidating the impact of these out-of-band spurs does not have an established framework for analysis for more complex oscillator configurations and extensively relies on simulator based validation. Some progress has been made for analysing open loop configurations[^14] that use frequency readout. In a closed loop environment however the oscillator frequency is not stationary but instead modulated by the signal and quantisation errors which is in turn dithered by the oscillation. The main concern here is down conversion of tones into the signal band although they are actively suppressed during closed loop operation. Choosing co-prime frequency ratios through scaled bias currents such as 2:3:13 as is used here is best way to avoid undesirable oscillator interaction. + +# 4 Circuit Implementation + +The proposed instrumentation circuit can be split into three sub-circuits and will be detailed following the sequence by which the analogue input signal is processed. The first stage is the capacitive feedback structure shown in Fig. 2. This figure shows the input analogue signal being chopped and coupled though CIN while a capacitor array also feeds the chopped digital codes which will allow the flicker noise of the input-transconductor to be modulated out of the signal-band. The digitised output Q\tss{9-5} uses binary weighting while the PWM signals \\(\Phi\\)\tss{1-15} use unary weighting and together they evaluate the quantisation error. The PWM encoded signals \\(\Phi\\)\tss{1-15} are used to compute the remaining binary least-significant codes for Q\tss{4-1} seen at the ADC output. The unary weighting averages out any mismatch components and will also assist in performing foreground calibration of binary weighted DAC by correlating the output derivative code transitions in Q\tss{9-5}[^15]. + +{{< figure src="/images/iscas2019/td_cdac.svg" title="Figure 2: Capacitive feedback network that resolves the error signal when comparing the analogue input with the digitised output." width="500" >}} + +The error signal on the capacitive DAC can be directly applied to the loop filter used here. This structure is shown in Fig. 3. The first stage of the feed-forward topology is a high-power transconductor that boosts the noise efficiency factor of this structure and dominates the overall noise performance as it directly drives the first and last differential oscillator through the current biasing terminal. All oscillating taps of X\tss{1-2} are buffered and processed by a XOR phase-detector to evaluate the phase-state. This controls the current-output from each DAC and enables us to cascade several time-based integrators without inducing quantisation errors or requiring strict digital timing requirements. It is important to point out that in this case the extended phase-detection is only applied to the last integrator and thus the limited dynamic range of X\tss{1-2} can result in undesirable modulator dynamics for high-frequency inputs. For this reason the second-order integration component is derived by feeding the first integration state forward instead of the input component. In addition the last oscillator presents a \\(4\times\\) smaller integration load thereby inducing additional gain at the output. This strategy is also found in conventional CT-\\(\Delta\Sigma\\) modulators as its allows the integration constants for the first two stages to be reduced giving more headroom for signal dynamics. + +{{< figure src="/images/iscas2019/td_lf.svg" title="Figure 3: Configuration of the third-order modulator that uses a cascade of integrators with feed-forward compensation." width="500" >}} + +Fig. 4 shows the circuit implementation of the EPD that similarly monitors each oscillating tap of X3. Clearly the phase difference is also being detected using an XOR gate however this circuit also generates overflow and underflow events as UP and DN signals. These are generated by combining a double-edge sensitive flip-flop with time-domain processing to perform level detection[^13]. The principle of operation here is that the Q5 will always track whichever oscillator in the differential structure is leading. When the XOR gate indicates a change has occurred, a phase-overflow will be triggered when the AND level detector is high otherwise the NOR level detector triggers a phase-underflow. These events trigger a counter that will increment or decrement accordingly thereby also correcting Q5 and setting the overflow event indicators low. In high-speed scenarios a unary counter can also be used to generate thermometer codes directly at the cost of added circuit complexity to speed up code transitions in the feedback DAC. + +{{< figure src="/images/iscas2019/td_epd.svg" title="Figure 4: Schematic of the extended-phase read-out circuit that extracts both phase information and detects cycle over-flow for the Nth section." width="500" >}} + +Fig. 5 shows the internal EPD signals during closed loop operation to clarify the circuit behaviour. This also shows that several phase-overflow events can be generated as X3 undergoes cycle slipping. Note that only the digital output is clocked and the internal counter state generates Q asynchronously in response to these events. Due to quantisation noise modulation multiple UP/DN events can be generated but this configuration processes the digital control in a feed-forward manner allowing tight timing control to guarantee a glitch free output. This is done by using a 2 ns window during every rising clock edge that holds the UP/DN signal in a tri-state to prevent latching invalid counter codes. + +{{< figure src="/images/iscas2019/transition.svg" title="Figure 5: Transient waveform showing from top to bottom the pseudo differential oscillator output in volts, the phase-overflow trigger signal, and the two digital output codes \\(\Phi\\)1-15 & Q9-5." width="500" >}} + +Table 1: Performance summary and comparison with state of the art +| Specification | This Work | [^9] | [^8] | [^7] | [^16] | [^4] | [^17] | [^3] | +|----|----|----|----|----|----|----|----|----| +| Year | 2018 | 2018 | 2018 | 2018 | 2017 | 2017 | 2015 | 2008 | +| Tech.[nm] | 180 | 65 | 130 | 65 | 40 | 130 | 180 | 130 | +| Supply[V] | 1.8/1.2 | 0.5 | 1.8 | - | 0.6 | 1.2 | 5/1.8 | 1.2 | +| Power[W] | 13.6Ī¼ | 1.28Ī¼ | 0.56m | 51.8m | 3.3Ī¼ | 1.05m | 140Ī¼ | 40m | +| Phase/Freq. | Ī¦-VCO | Ī¦-VCO | F-VCO | Ī¦-VCO | - | Ī¦-VCO | F-VCO | Ī¦-VCO | +| Calibration | Yes | No | No | Yes | No | No | No | No | +| NS-Order | 3 | 1 | 2 | 3 | 1 | 1 | 2 | 1 | +| OSR | 64 | 128 | 500 | 15 | 83k | 313 | 64k | 100 | +| BW[Hz] | 15.6k | 11k | 20k | 50M | 150 | 0.4M | 1.25 | 10M | +| SNDR[dB] | 88 | 54 | 77 | 72 | 56 | 83 | 73 | 72 | +| Area[mmĀ²] | 0.102 | 0.006 | 0.04 | 0.35 | 0.015 | 0.13 | 0.36 | 0.01 | +| FoMS[dB] | 178(^\star) | 153 | 152 | 162 | 133 | 169 | 97 | 156 | + +\\(^\star\\) Estimated based on simulation results where FoMS = SNDR + 10log10(BW/P). + +# 5 Simulation Results + +The time domain modulator presented here has been designed and validated using a commercially available 180 nm TSMC technology (1P6M HV BCD GEN II). The ADC core is configured to use a 1.8 V analogue supply to power the low noise transconductor as well as perform current biasing for each of the switched current DAC while using a 500 nA external reference current. The 1.8 V supply is also used as reference voltage when the digital codes are coupled onto VX using an array of level shifters since all the digital logic runs at 1.2 V to save power. A differential 2 kHz sinusoid at -3 dBFS (900 mVpp) is used during transient simulations to show preliminary performance characteristics. Fig. 6 shows one cycle where all three integrators are processing quantisation errors that are accumulated in X3. This also shows X3 rapidly overflowing multiple times while triggering increments in the binary codes. At maximum input swing the speed is limited due to the slewing of X3 but we do not expect such rapid signal dynamics for our application. Instead this extended dynamic range will capture drift and electrode offset components while the artefacts are typically 10 to 100 mV that the modulator can track at full-speed. The photo in Fig. 7 shows the floor plan as well as the layout of the fabricated prototype. + +{{< figure src="/images/iscas2019/sim_tran.svg" title="Figure 6: Simulation result transient behaviour of the time based integration where each phase state is asynchronously PWM encoded but only the output X3 uses extended phase detection to allow overflow." width="500" >}} + +{{< figure src="/images/iscas2019/floor_plan.svg" title="Figure 7: Micro-photograph showing labelled blocks in relation to the schematics in Sec. 4." width="500" >}} + +The spectral characteristics are summarised in Fig. 8. We can observe that third-order noise shaping can be achieved but some of the oscillator spurs are still present in high-frequency bands. However the components close to the signal band are significantly suppressed. The oscillator frequencies have also been annotated where X1 is around 78 kHz, X2 is around 117 kHz, and X3 is around 507 kHz. The chopper tones are still present outside the signal band since no off-set cancellation is performed which will be considered at a later point. The performance metrics are compared with other time based data converters in Table 1. While the figure of merit (FOM) seems to favour this work, the calibration mechanism is not yet integrated and measurements will need to confirm the these figures using a prototype that is currently in the process of being fabricated. + +{{< figure src="/images/iscas2019/sim_thd.svg" title="Figure 8: Simulation result showing the noise-shaped output spectrum from a -3 dBFS input sinusoid at 2 kHz." width="500" >}} + +# 6 Acknowledgement + +This work was supported by the UK Engineering and Physical Sciences Research Council (EPSRC) grants EP/M020975/1 & EP/R024642/1. + +# 7 Conclusion + +We have presented the implementation and operation of a third-order Ī£Ī” ADC that uses an oscillator based loop filter with extended phase detection. As a result this work shows a significant improvement in precision over prior-art that strictly uses time-based signal processing. While the preliminary results show the performance for an analogue 180 nm CMOS technology, the digital operation of these circuits will enable these ideas to easily be adopted in a modern digital process or target high-speed applications. More importantly this work demonstrates that asynchronous time domain systems can be configured to achieve well over 80 dB dynamic range and realise intergrators that will not induce distortion due to saturation or phase-overflow. + +# Refernces: + +[^17]: P.Prabha etal., ''A highly digital VCO-based ADC architecture for current sensing applications,'' IEEE J. Solid-State Circuits, vol.50, no.8, pp. 1785--1795, Aug 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2414428 +[^7]: S.Dey, K.Reddy, K.Mayaram, and T.S. Fiez, ''A 50 MHz BW 76.1 dB DR two-stage continuous-time delta-sigma modulator with VCO quantizer nonlinearity cancellation,'' IEEE J. Solid-State Circuits, vol.53, no.3, pp. 799--813, March 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2777455 +[^2]: R.Naiknaware, H.Tang, and T.S. Fiez, ''Time-referenced single-path multi-bit $\Delta \Sigma$ ADC using a VCO-based quantizer,'' IEEE Trans. Circuits Syst. II, vol.47, no.7, pp. 596--602, July 2000. [Online]: http://dx.doi.org/10.1109/82.850418 +[^3]: M.Z. Straayer and M.H. Perrott, ''A 12 bit, 10 MHz bandwidth, continuous-time $\Sigma\Delta$ ADC with a 5 bit, 950 MS/s VCO-based quantizer,'' IEEE J. Solid-State Circuits, vol.43, no.4, pp. 805--814, April 2008. [Online]: http://dx.doi.org/10.1109/JSSC.2008.917500 +[^16]: R.Mohan etal., ''A 0.6 V, 0.015 mm sqrd, time-based ECG readout for ambulatory applications in 40 nm CMOS,'' IEEE J. Solid-State Circuits, vol.52, no.1, pp. 298--308, Jan 2017. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2615320 +[^10]: S.Ziabakhsh, G.Gagnon, and G.W. Roberts, ''A time-mode LDI-based resonator for a band-pass $\Delta\Sigma$ TDC,'' Aug 2017, pp. 1296--1299. [Online]: http://dx.doi.org/10.1109/MWSCAS.2017.8053168 +[^8]: F.Cardes etal., ''0.04 mm sqrd 103 dB-A dynamic range second-order VCO-based audio $\Sigma\Delta$ ADC in 0.13 $\mu$m CMOS,'' IEEE J. Solid-State Circuits, vol.53, no.6, pp. 1731--1742, June 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2018.2799938 +[^9]: L.B. Leene and T.G. Constandinou, ''A 0.006 mm sqrd 1.2 $\mu$W analog-to-time converter for asynchronous bio-sensors,'' IEEE J. Solid-State Circuits, vol.53, no.9, pp. 2604--2613, Sept 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2018.2850918 +[^1]: G.W. Roberts and M.Ali-Bakhshian, ''A brief introduction to time-to-digital and digital-to-time converters,'' IEEE Trans. Circuits Syst. II, vol.57, no.3, pp. 153--157, March 2010. [Online]: http://dx.doi.org/10.1109/TCSII.2010.2043382 +[^13]: L.B. Leene and T.G. Constandinou, ''Time domain processing techniques using ring oscillator-based filter structures,'' IEEE Trans. Circuits Syst. I, vol.64, no.12, pp. 3003--3012, Dec 2017. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2715885 +[^14]: E.Gutierrez, L.Hernandez, F.Cardes, and P.Rombouts, ''A pulse frequency modulation interpretation of VCOs enabling VCO-ADC architectures with extended noise shaping,'' IEEE Trans. Circuits Syst. I, vol.65, no.2, pp. 444--457, Feb 2018. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2737830 +[^12]: J.Beaumont, A.Mokhov, D.Sokolov, and A.Yakovlev, ''High-level asynchronous concepts at the interface between analog and digital worlds,'' IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.37, no.1, pp. 61--74, Jan 2018. [Online]: http://dx.doi.org/10.1109/TCAD.2017.2748002 +[^11]: B.Schell and Y.Tsividis, ''A continuous-time ADC/DSP/DAC system with no clock and with activity-dependent power dissipation,'' IEEE J. Solid-State Circuits, vol.43, no.11, pp. 2472--2481, Nov 2008. [Online]: http://dx.doi.org/10.1109/JSSC.2008.2005456 +[^15]: L.B. Leene and T.G. Constandinou, ''A 0.016 mm sqrd12 b $\Delta \Sigma$ SAR with 14 fJ/conv. for ultra low power biosensor arrays,'' IEEE Trans. Circuits Syst. I, vol.64, no.10, pp. 2655--2665, Oct 2017. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2703580 +[^5]: W.Jiang etal., ''A Ā±50 mV linear-input-range VCO-based neural-recording front-end with digital nonlinearity correction,'' IEEE J. Solid-State Circuits, vol.52, no.1, pp. 173--184, Jan 2017. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2624989 +[^4]: S.Li, A.Mukherjee, and N.Sun, ''A 174.3 dB FoM VCO-based CT $\Delta \Sigma$ modulator with a fully-digital phase extended quantizer and tri-level resistor DAC in 130 nm CMOS,'' IEEE J. Solid-State Circuits, vol.52, no.7, pp. 1940--1952, July 2017. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2693244 +[^6]: W.Yu, J.Kim, K.Kim, and S.Cho, ''A time-domain high-order MASH $\Delta\Sigma$ adc using voltage-controlled gated-ring oscillator,'' IEEE Trans. Circuits Syst. I, vol.60, no.4, pp. 856--866, April 2013. [Online]: http://dx.doi.org/10.1109/TCSI.2012.2209298 diff --git a/content/publications/2019/a-68-rmu-w-31-ks-s-fully-capacitive-noise-shaping-sar-adc-with-102-db-sndr.md b/content/publications/2019/a-68-rmu-w-31-ks-s-fully-capacitive-noise-shaping-sar-adc-with-102-db-sndr.md new file mode 100644 index 0000000..a086bc7 --- /dev/null +++ b/content/publications/2019/a-68-rmu-w-31-ks-s-fully-capacitive-noise-shaping-sar-adc-with-102-db-sndr.md @@ -0,0 +1,135 @@ +--- +title: "A 68 Ī¼W 31 kS/s fully-capacitive noise-shaping SAR ADC with 102 dB SNDR" +date: 2019-05-26T15:26:46+01:00 +draft: false +toc: true +math: true +type: posts +tags: + - publication + - CMOS + - data-converter + - instrumentation + - circuit +--- + +Lieuwe B. Leene, Timothy G. Constandinou + +Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK + +Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK + +# 1 Abstract + +This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB. We propose a novel fully-capacitive topology which allows for high-speed asynchronous conversion together with a background calibration scheme to reduce the oversampling requirement by 10\\(\times\\) compared to prior-art. A 0.18Ī¼ m CMOS technology is used to demonstrate preliminary simulation results together with analytic measures that optimise parameter and topology selection. The proposed system is able to achieve a FoMS of 183 dB for a maximum signal bandwidth of 15.6 kHz while dissipating 68 Ī¼ W from a 1.8 V supply. A peak SNDR of 102 dB is demonstrated for this rate with a 0.201 mmĀ² \:area requirement. + +# 2 Introduction + +Analogue-to-digital converter (ADC) efficiency remains to be the highlight for many current developments in both industry and academia. It used to be the case that oversampling converters (Ī”Ī£ ADCs) and successive-approximation register converters (SAR ADCs) found separate application domains where this factor peaks. State-of-the-art ADCs however have mixed these two digitisation techniques to improve performance beyond a 170 dB Schreier Figure-of-Merit (FoMS)[^5][^4][^3][^1][^2]. This trend is in-part driven by the growing bio-metric and bio-medical electronics market that necessitates low-power high dynamic-range signal acquisition as many phenomena of interest exhibit signal dynamics with several orders of magnitude in variation. For example a peripheral neuro-modulation device with digitally assisted artifact rejection[^6] requires over \\(>\\)100 dB of dynamic range to detect micro-volt level sensory neuron activity in the presence of large mili-volt level interference from stimulation or motor-unit activity which is the application of interest that motivated this work. + +The emerging ADC topologies for bio-sensors use multi-stage noise shaping or pipe-lined operation where multiple quantisers are integrated together and the quantisation error of the first quantiser is either resolved by another quantiser after amplification or may be used directly with an alternate feedback mechanism to similarly resolve additional bits. The noise-shaping SAR (NS-SAR) [^2][^7] however adopts a different approach by sampling and converting the input multiple times while simultaneously employing multiple feedback mechanisms that up-modulate any conversion errors out of the signal bandwidth. In this way the signal can be resolved with much finer precision once the output is decimated and the out-of-band frequency components are filtered out. + +{{< figure src="/images/iscas2019/sar_sys.svg" title="Figure 1: Block diagram of the proposed high-resolution data converter showing the SAR digital controller applying feedback through 3 separate capacitor arrays and is augmented by the switched-capacitor loop filter H(z\tps{-1})." width="500" >}} + +Here we present a novel fully-capacitive NS-SAR topology using active higher-order noise shaping that achieves state-of-the-art efficiency for high resolution signal acquisition. The proposed configuration is shown in Fig. 1. This figure summarises which signals are processed by each block in a closed-loop fashion to resolve the sampled analogue input signal VIN. The main data-conversion mechanism is based on the conventional SAR controller that uses the comparator decisions K to successively set the MSB and LSB bits[^8]. However to augment this operation two separate noise-shaping mechanisms are added; one for quantisation noise, H(z\tps{-1}), and another for mismatch noise by means of data-weighted averaging (DWA) together with mismatch-error shaping techniques (MES). + +The NS-SAR approach is advantageous because the first several bits can be resolved rapidly using SAR and the remaining bits are resolved using Ī”Ī£ modulation over several samples with reduced oversampling-ratio (OSR) to yield a significant overall improvement in conversion efficiency. Reusing the sampling mechanism of the SAR allows the quantisation residue left on VDAC to be directly integrated by the loop filter H(z\tps{-1}) that off-sets future conversions and shapes the quantisation noise as 1/(1+H(z\tps{-1})). The main drawback here in comparison to high-resolution \rDS\: modulators is that, while the conversion is faster, the mismatch in the high-resolution DAC must be carefully mitigated. This is where the DWA[^9] and MES[^10] are introduced to eliminate mismatch errors. DWA manipulates the selection of elements used within the MSB capacitive DAC such that the capacitor mismatch is not only decorrelated from the input but is also shaped with a (1-z\tps{-1}) characteristic. The MES module in the LSB section directly off-sets the sampled input using past conversion results to realise a FIR feedback structure such as (1-z\tps{-1}) or (1-2z\tps{-1}+z\tps{-2}) high-pass characteristics to minimise signal-band noise components. + +The rest of this paper is organised as follows; Sec. 3 will relate the main design parameters to conversion precision in relation to primary noise sources. Once these are established the circuit implementation is presented in Sec. 4 together with simulation results in Sec. 5 and Sec. 7 will then conclude this work. + +# 3 NS-SAR Design + +Comparing with other data-converters, the NS-SAR topology is quite complex with a large number of design parameters that need to be optimised for efficient operation. Below, several of these parameters are discussed in relation to the ADC precision explaining the proposed configuration. Following the single-ended configuration shown in Fig. 1, we will estimate the expected sampling noise power (SNP), quantisation noise power (QNP), and mismatch noise power (MNP) for the signal bandwidth of fs/(2 OSR) where fs is the sampling speed. This formulation is purposely presented in brief since it based on established theory from [^11] but it does well to illustrate several trade-off considerations quantitatively when configuring this topology for a particular precision requirement. + +$$ SNP \approx \frac{kT}{C_T} \cdot \frac{2.4}{OSR} $$ + +The expression in Eq. 1 should be a familiar representation for evaluating the input-referred sampling noise associated with a switched-capacitor integrator. In particular, this corresponds to the input being sampled with a total capacitive value of CT using kT as the Boltzman temperature factor. The second term simply arises from averaging the input over OSR cycles together with a correction factor of 2.4 due to the integrator topology in H(z\tps{-1})[^12]. Fig. 2 shows the estimated resolution for several capacitor values assuming we use an input sinusoid with maximum signal power (SP) given a 1.8 V ADC reference voltage as VDD. Inevitably, achieving high resolution implies a large sampling capacitance or a large oversampling ratio. Typically the former is preferred because increasing the capacitive load also decreases the mismatch power from the capacitive DACs. + +$$ QNP \approx \underbrace{\left( V^2_{DD} e^{-3\tau} + \frac{V^2_{DD}}{2^{2N}} \right)}_{\text{SAR settling + quantisation }\epsilon} \cdot \frac{\pi^{2M}}{12 (1+2M) OSR^{1+2M}} $$ + +The expression in Eq. 2 parametrises the overall SAR resolution as N, the loop fillter order as M, and the number of time constants we allow the capacitive DAC to settle as Ļ„ \:in order to estimate QNP. This construction shows that settling and quantisation errors are shaped by the loop filter reducing the noise power by the term outside the brackets. Both in Fig. 3 and in the formulation we observe a strong dependency with regard to M as long as we provide sufficient settling time during SAR conversion. This result suggests that the noise-shaping feed-back must avoid driving the capacitive DAC with active amplifiers during successive-approximation to avoid slowing down the conversion speed or equivalently increasing the power requirement of each amplifier. We can also confirm here that the order of the loop filter does not need to be very high if the QNP needs to match the SNP. + +$$ MNP \approx \underbrace{\left( \frac{\pi^2 2^{-2D}}{3 \cdot 2^K OSR^3} + \frac{\pi^{2E} 2^{-2K}}{(1+2E) OSR^{1+2E}} \right)}_{\text{DWA-MSB + MES-LSB DAC}} \frac{\sigma^2 V^2_{DD}}{3} $$ + +The MNP is evaluated in Eq. 3 with respect to the MES noise shaping order E, the number of bits D used to calibrate each capacitor in the MSB DAC in an idealised way. K represents the MSB DAC resolution in bits. Using a capacitor standard deviation \\(\sigma=0.5%\\) and K=4, the MNP of several configurations is shown in Fig. 4. The observation here is that for small OSR values the mismatch noise is typically dominated by the MSB DAC as the mismatch is not sufficiently shaped. It is relatively expensive to increase the number of elements in the MSB DAC since the scaling is linear and increasing the OSR diminishes the advantage of performing SAR. Instead we propose to calibrate the 15 capacitors in the MSB section as D will reduce the MNP more efficiently. The mismatch from the LSB section contains many more elements and is more effectively shaped using a second-order MES technique. + +The above trends are used to optimise the FOMS in a similar fashion to [^3] by correlating hardware requirements with power and accuracy estimators for several configurations. Given an initial 18 bit target precision, we propose the following configuration: CT=50 pF, M=2,Ļ„=5, K=5, D=4, E=2 with the OSR set to 16 to ease the decimation effort. + +{{< figure src="/images/iscas2019/osr_snp.svg" title="Figure 2: ADC precision as a function of oversampling ratio with respect to SNP while varying sampling capacitance CT." width="500" >}} + +{{< figure src="/images/iscas2019/osr_qnp.svg" title="Figure 3: ADC precision as a function of oversampling ratio with respect to QNP while varying settling times \\(\tau\\) and noise-shaping order M." width="500" >}} + +{{< figure src="/images/iscas2019/osr_mnp.svg" title="Figure 4: ADC precision as a function of oversampling ratio with respect to MNP while varying calibration D and mismatch-shaping order E." width="500" >}} + +# 4 Circuit Implementation + +The analogue part of the ADC implementation is shown in Fig. 5. Note that the implemented ADC uses an equivalent fully-differential configuration to gain extra input-dynamic range as well as digital noise suppression. This realisation is entirely based on manipulating the capacitive DAC and enables low-power operation for varying sampling rates. A second distinguishing feature of the proposed topology is that the comparator only requires one input terminal opposed to two seen in prior-art [^2][^7] which leads to better linearity and noise performance. In addition the input is bottom plate sampled such that sensitivity to parasitic capacitance and comparator non-linearity is considerably reduced. This figure also shows three capacitor arrays where the DACM section corresponds to the DWA modulated MSBs and the DAC\tss{L1/L2} section represents the MES modulated LSBs being fed back from the SAR controller. Implementing the second-order MES noise-shaping uses the ping-pong configuration from [^13]. + +{{< figure src="/images/iscas2019/sar_cdac.svg" title="Figure 5: Implementation of the capacitor network used to perform signal conversion using the bottom sampled capacitor arrays DACM for the DWA bits and DACL1 & DACL2 for the MES bits. The loop filter is also shown where A1 amplifies the quantisation residue that is then integrated by A2 & A3 for noise-shaping." width="500" >}} + +Three switched-capacitor amplifiers are used to realise a second-order cascaded-feed-forward-integrator (CFFI) loop filter topology where the first stage provides auto-zeroing as well as signal amplification by \\(C_T/C_1\approx30\\). This design uses an asynchronous SAR conversion process [^14] which is why there are only 3 phases in the switched capacitor circuit; the sampling phase (SMP), the successive approximation phase (SAR), and the quantisation filtering phase (QNF). The SAR only takes 100 ns and the FSM immediately initiates the QNF phase reducing the input clock to twice the sampling rate. The three phases operate as follows: + +\begin{enumerate} + \item[**SMP**] First A1 actively samples its offset on the top plate while bottom plate samples VIN on DACM together with the MES code on DAC\tss{L1/L2}. A\tss{2/3} are simultaneously integrating quantisation errors and sampling the result V\tss{X2/X3} with respect to VDAC on C6 and C7. + \item[**SAR**] VDAC then converges to virtual ground by switching the input to DAC\tss{M/L1/L2} while quantisation errors from prior conversions are removed by grounding the bottom plate of C\tss{6/7}. This also disconnects A\tss{1/2/3} from VDAC. + \item[**QNF**] Finally DAC\tss{M/L1/L2} is held and the resulting quantisation residue left on VDAC is amplified by A{1} on VX1. C\tss{2/4} samples the voltages V\tss{X1/X2} which are used to integrate during the following SMP phase. +\end{enumerate} + +This configuration scales well for varying loop filter structures as 80% of the power is dissipated by A1 and the total sampling noise is dominated by CT. The comparator uses a conventional strong-arm topology that is carefully designed to minimise off-set since this off-set will be seen at the output of A3 after amplification which can diminish the output-swing. Conversely the noise and distortion characteristics of the analogue filtering chain is proportionally reduced when the signal is fed back onto the capacitor array during sampling as the attenuation ratio \\(C_{6-7}/C_T\\) inverts the amplification ratio with good matching. + +The MSB DAC calibration mechanism is uses a digital shuffling technique to identify mismatch by switching out different sets of capacitors that will only incur voltage fluctuation on VDAC in the presence of mismatch[^15]. These errors are then amplified by A1 after the SAR & QNF process and digitally tunes each MSB capacitor using a capacitive sub-DAC. The sign of each shuffling result is accumulated to adjust the the 15 calibration codes thereby eliminating the mismatch in the MSB DAC. This process can be performed in the background without requirements on the input signal because DWA randomises the capacitor selection mechanism during shuffling. + +Table 1: Performance summary and comparison with state of the art +| Spec. | This Work | [^16] | [^15] | [^4] | [^5] | [^3] | [^7] | [^2] | +|----|----|----|----|----|----|----|----|----| +| Year | 2018 | 2018 | 2018 | 2018 | 2018 | 2017 | 2016 | 2012 | +| Tech.[nm] | 180 | 180 | 180 | 28 | 40 | 180 | 55 | 65 | +| Supply[V] | 1.8 | 1.8 | 1.8/5 | 1.1/1.2 | 2.5/1.1 | 1.2 | 1.2 | 1.2 | +| Power[W] | 68Ī¼ | 7.93Ī¼ | 12.9m | 4.2m | 140Ī¼ | 5.16Ī¼ | 15.7Ī¼ | 806Ī¼ | +| Topology | NS-SAR | \rDS-SAR | SAR | CT-\rDS | \rDS-SAR | \rDS-SAR | NS-SAR | NS-SAR | +| DAC Res.[b] | 10 | 9 | 20 | 4 | 7 | 8 | 12 | 8 | +| NS-Order | 2(^\dagger) | 1 | 0 | 2(^\dagger) | 3 | 2 | 1(^\dagger) | 1(^\dagger) | +| OSR | 16 | 256 | 1 | 16 | 12 | 24 | 256 | 4 | +| BW[Hz] | 15.6k | 1k | 500k | 10M | 40k | 100k | 4k | 11M | +| SNDR[dB] | 102 | 85 | 102 | 94 | 84 | 67 | 96.1 | 62 | +| Area[mmĀ²] | 0.201 | 0.68 | 4 | 0.1 | 0.07 | 0.02 | 0.07 | 0.03 | +| FoMS[dB] | 183(^\star) | 166 | 176 | 168 | 169 | 170 | 180 | 164 | + +\\(^\star\\) Estimated based on post-layout simulation results where FoMS = SNDR + 10log10(BW/P). \\(^\dagger\\) FIR & digital noise-coupling poles excluded. + +# 5 Simulation Results + +The proposed NS-SAR has been designed and validated using a commercially available 180 nm TSMC technology (1P6M HV BCD GEN II). All sub-circuits have been integrated with reconfigurable Ī”Ī£, DWA, MES, and calibration modes to fully characterise post-silicon performance that will confirm the evaluation in Sec. 3. This circuit uses an analogue and digital supply at 1.8 V, a 1 Ī¼ A current reference to bias A\tss{1-3}, and a 0.9 V common-mode reference for VCM-based capacitor switching. Preliminary post-layout simulation results are shown in Fig. 6. This demonstrates the ADC can resolve 17 bits of precision without distortion while using an external clock of 1 MHz where one cycle is used to sample the input and one cycle is used for conversion plus quantisation noise shaping and another cycle is optionally used for background calibration. The last phase can be skipped if the MSB capacitors are already tuned to speed-up signal conversion to 31.25 kS/s since temperature and voltage variations over time during normal operation will typically not corrupt the calibrated capacitor characteristics. + +{{< figure src="/images/iscas2019/sar_sim_thd.svg" title="Figure 6: Post-layout simulation result showing the noise-shaped output spectrum from a -3 dBFS input sinusoid at 6.5 kHz." width="500" >}} + +{{< figure src="/images/iscas2019/sar_floor_plan.svg" title="Figure 7: ADC micro-photograph showing labelled blocks in relation to Fig 1 where the MES and DWA circuitry is included in the main digital core. Decoupling capacitors are placed over active circuitry or underneath active mim-caps." width="500" >}} + +The layout for this ADC is shown in Fig. 7. A large majority of silicon area is dedicated towards the MSB capacitive array as the sampling noise must be suppressed. The switched capacitor integrator can be relatively small because the internal loop-filter gain reduces its sampling noise. The digital core takes up a considerable amount of area and power budget primarily as a result of using a 180 nm CMOS technology where more advanced technologies may lead to further improvements if the 1.8 V rating can be maintained. Each MSB capacitor is trimmed using a 8 bit sub-DAC that tunes about 5% of the 1.7 pF unit capacitance which accommodates well over 3Ļƒ of the expected capacitor mismatch as well as wafer level variations that may not be captured by the typical mismatch model. The performance measures for the proposed ADC are shown in Table 1. Again we highlight the fact that while all these works have highly optimised power budgets, this topology is able to achieve over 100 dB SNDR with a 10\\(\times\\) lower oversampling ratio than prior art for this level precision. While this does imply a marginally increased area requirement, the peak efficiency can be achieved over a greater span of sampling frequencies. Note that this particular TSMC process kit does not allow post-layout Monte-Carlo so the calibration will be validated using post-silicon results. + +# 6 Acknowledgement + +This work was supported by the UK Engineering and Physical Sciences Research Council (EPSRC) grants EP/M020975/1 & EP/R024642/1. + +# 7 Conclusion + +This works presents a 17 bit Noise Shaping SAR ADC with reduced oversampling ratio and a purely capacitive implementation which enables in state-of-the-art conversion efficiency over a large range of sampling frequencies. In comparison with conventional over-sampling ADCs simulation results suggest this NS-SAR is able to achieve 102 dB SNDR with substantially lower noise-shaping requirements with comparable or reduced circuit complexity while achieving better power efficiency. We also demonstrated a high-level parameter selection methodology that is used to optimise the FoMS and identify the factors limiting ADC precision. + +# Refernces: + +[^11]: S.Pavan, R.Schreier, and G.C. Temes, Understanding Delta-Sigma Data Converters.\hskip 1em plus 0.5em minus 0.4em elax IEEE, 2017. [Online]: http://dx.doi.org/10.1002/9781119258308 +[^12]: R.Schreier, J.Silva, J.Steensgaard, and G.C. Temes, ''Design-oriented estimation of thermal noise in switched-capacitor circuits,'' IEEE Trans. Circuits Syst. I, vol.52, no.11, pp. 2358--2368, Nov 2005. [Online]: http://dx.doi.org/10.1109/TCSI.2005.853909 +[^10]: M.Aboudina and B.Razavi, ''A new DAC mismatch shaping technique for sigmaā€“delta modulators,'' IEEE Trans. Circuits Syst. II, vol.57, no.12, pp. 966--970, Dec 2010. [Online]: http://dx.doi.org/10.1109/TCSII.2010.2083172 +[^13]: J.Liu, G.Wen, and N.Sun, ''Second-order DAC MES for SAR ADCs,'' IET Elec. Letters, vol.53, no.24, pp. 1570--1572, 2017. [Online]: http://dx.doi.org/10.1049/el.2017.3138 +[^9]: B.H. Leung and S.Sutarja, ''Multibit sigma - delta A/D converter incorporating a novel class of dynamic element matching techniques,'' IEEE Trans. Circuits Syst. II, vol.39, no.1, pp. 35--51, Jan 1992. [Online]: http://dx.doi.org/10.1109/82.204108 +[^8]: B.P. Ginsburg and A.P. Chandrakasan, ''500 MS/s 5 bit ADC in 65 nm CMOS with split capacitor array DAC,'' IEEE J. Solid-State Circuits, vol.42, no.4, pp. 739--747, April 2007. [Online]: http://dx.doi.org/10.1109/JSSC.2007.892169 +[^5]: A.AlMarashli, J.Anders, J.Becker, and M.Ortmanns, ''A nyquist rate SAR ADC employing incremental sigma delta DAC achieving peak SFDR=107 dB at 80 kS/s,'' IEEE J. Solid-State Circuits, vol.53, no.5, pp. 1493--1507, May 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2776299 +[^4]: I.Jang etal., ''A 4.2 mW 10 MHz BW 74.4 dB SNDR continuous-time delta-sigma modulator with SAR-assisted digital-domain noise coupling,'' IEEE J. Solid-State Circuits, vol.53, no.4, pp. 1139--1148, April 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2778284 +[^3]: L.B. Leene and T.G. Constandinou, ''A 0.016 mm sqrd 12 b $\Delta\Sigma$ SAR with 14 fJ/conv. for ultra low power biosensor arrays,'' IEEE Trans. Circuits Syst. I, vol.64, no.10, pp. 2655--2665, Oct 2017. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2703580 +[^1]: Y.Chae, K.Souri, and K.A.A. Makinwa, ''A 6.3 mu W 20 bit incremental zoom-ADC with 6 ppm INL and 1 mu V offset,'' IEEE J. Solid-State Circuits, vol.48, no.12, pp. 3019--3027, Dec 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2278737 +[^16]: S.Choi etal., ''An 84.6 dB-SNDR and 98.2 dB-SFDR residue-integrated SAR ADC for low-power sensor applications,'' IEEE J. Solid-State Circuits, vol.53, no.2, pp. 404--417, Feb 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2774287 +[^2]: Y.Shu, L.Kuo, and T.Lo, ''An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS,'' IEEE J. Solid-State Circuits, vol.51, no.12, pp. 2928--2940, Dec 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2592623 +[^7]: J.A. Fredenburg and M.P. Flynn, ''A 90 MS/s 11 MHz bandwidth 62 dB SNDR noise-shaping SAR ADC,'' IEEE J. Solid-State Circuits, vol.47, no.12, pp. 2898--2904, Dec 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2217874 +[^6]: A.E. Mendrela etal., ''A bidirectional neural interface circuit with active stimulation artifact cancellation and cross-channel common-mode noise suppression,'' IEEE J. Solid-State Circuits, vol.51, no.4, pp. 955--965, April 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2506651 +[^15]: H.Li etal., ''A signal-independent background-calibrating 20 b 1 MS/S SAR ADC with 0.3ppm INL,'' in IEEE Proc. ISSCC, Feb 2018, pp. 242--244. [Online]: http://dx.doi.org/10.1109/ISSCC.2018.8310274 +[^14]: R.Sekimoto etal., ''A 0.5 V 5.2 fJ/conversion-step full asynchronous SAR ADC with leakage power reduction down to 650 pW by boosted self-power gating in 40 nm CMOS,'' IEEE J. Solid-State Circuits, vol.48, no.11, pp. 2628--2636, Nov 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2274851 diff --git a/content/publications/2019/an-oscillator-based-potentiostat-with-switch-cap-feedback-for-current-sensing-applications.md b/content/publications/2019/an-oscillator-based-potentiostat-with-switch-cap-feedback-for-current-sensing-applications.md new file mode 100644 index 0000000..6a2aa58 --- /dev/null +++ b/content/publications/2019/an-oscillator-based-potentiostat-with-switch-cap-feedback-for-current-sensing-applications.md @@ -0,0 +1,14 @@ +--- +title: "An Oscillator Based Potentiostat with Switch-Cap Feedback for Current Sensing Applications" +date: 2019-05-26T15:26:46+01:00 +draft: true +toc: true +type: posts +math: true +tags: + - publication + - CMOS + - data-converter + - instrumentation + - circuit +--- diff --git a/content/publications/2019/towards-a-distributed-chronically-implantable-neural-interface.md b/content/publications/2019/towards-a-distributed-chronically-implantable-neural-interface.md new file mode 100644 index 0000000..96b0ca9 --- /dev/null +++ b/content/publications/2019/towards-a-distributed-chronically-implantable-neural-interface.md @@ -0,0 +1,13 @@ +--- +title: "Towards a distributed, chronically-implantable neural interface" +date: 2019-03-20T15:26:46+01:00 +draft: true +toc: true +type: posts +math: true +tags: + - chapter + - packaging + - biomedical + - instrumentation +--- diff --git a/content/publications/2021/analogue-front-end-design-for-neural-recording.md b/content/publications/2021/analogue-front-end-design-for-neural-recording.md new file mode 100644 index 0000000..0834c33 --- /dev/null +++ b/content/publications/2021/analogue-front-end-design-for-neural-recording.md @@ -0,0 +1,13 @@ +--- +title: "Analogue Front-End Design for Neural Recording" +date: 2020-01-10T15:26:46+01:00 +draft: true +toc: true +type: posts +math: true +tags: + - chapter + - circuit + - biomedical + - instrumentation +--- diff --git a/content/publications/2021/design-flow-for-hybrid-cmos-memristor-systems-part-i-modelling-and-verification-steps.md b/content/publications/2021/design-flow-for-hybrid-cmos-memristor-systems-part-i-modelling-and-verification-steps.md new file mode 100644 index 0000000..8a7331a --- /dev/null +++ b/content/publications/2021/design-flow-for-hybrid-cmos-memristor-systems-part-i-modelling-and-verification-steps.md @@ -0,0 +1,13 @@ +--- +title: "Design Flow for Hybrid CMOS/Memristor Systemsā€”Part I: Modeling and Verification Steps" +date: 2021-11-13T15:26:46+01:00 +draft: true +toc: true +math: true +type: posts +tags: + - publication + - CMOS + - process-integration + - memsistors +--- diff --git a/content/publications/2021/design-flow-for-hybrid-cmos-memristor-systems-part-ii-circuit-schematics-and-layout.md b/content/publications/2021/design-flow-for-hybrid-cmos-memristor-systems-part-ii-circuit-schematics-and-layout.md new file mode 100644 index 0000000..73aea54 --- /dev/null +++ b/content/publications/2021/design-flow-for-hybrid-cmos-memristor-systems-part-ii-circuit-schematics-and-layout.md @@ -0,0 +1,13 @@ +--- +title: "Design Flow for Hybrid CMOS/Memristor Systemsā€”Part II: Circuit Schematics and Layout" +date: 2021-11-13T15:26:46+01:00 +draft: true +toc: true +math: true +type: posts +tags: + - publication + - CMOS + - process-integration + - memsistors +--- diff --git a/content/resume.md b/content/resume.md new file mode 100644 index 0000000..756ff0b --- /dev/null +++ b/content/resume.md @@ -0,0 +1,201 @@ +--- +title: "Lieuwe Leene PhD. MSc. BEng." +date: 2021-08-23T17:52:07+02:00 +draft: false +toc: true +tags: + - personal + - resume + - employment +--- + + +Since 2019, I have been part of the [Novelda](https://novelda.com/) RFIC design +group where we design the most accurate human presence sensor in the world based +on ultra wide band technology. We are a team of 8 designing a IEEE 802.15 +compliant single-chip solution for short-range radar applications using a +custom transceiver. I primarily work on the critical timing circuits for clock +redistribution, frequency scaling, and synchronization taking custom +mixed-signal circuits from concept and layout implementation all the way to +characterization and wafer sort planning. + +Prior to 2019 I was with the [NGNI](https://www.imperial.ac.uk/next-generation-neural-interfaces) +lab at Imperial College London developing implantable medical devices +specialized for neuro-scientific studies and electroceutical therapies such as +deep-brain-stimulation and brain-machine-interfaces. I specialized in realizing +ultra-low-power instrumentation systems that can be implanted and innovated circuit +techniques for efficiently processing biomedical signals. Most of my success +came from applying time-domain techniques to realize sensing circuits with +exceptional dynamic range such that a wider variety of neurological components +can be picked up during recording or stimulation. + +# Employment Record + +{{< columns src="/images/about/novelda_logo_white.svg" >}} + +``` +Senior IC Design Engineer +IC Design Team Oslo Office, +Novelda AS Oslo, Norway +Aug. 2019 - Now +``` + + - Responsible for RF transceiver clocking module and phase locked loop design + for a Ultra-Wideband human presence sensor operating in the 7.8 GHz band. + - Acting as System and IP integration lead handling design delivery such as + netlist, layout, timing, and constraint files along with sign-off reports. + - Designing full-custom high-speed digital logic for both asynchronous and + timing critical modules. + +{{< /columns >}} + +{{< columns src="/images/about/IC_white.svg" >}} + +``` +Research Associate +Centre for Bio-Inspired Technology, +Imperial College London, United Kingdom +Dec. 2016 ā€“ Dec. 2019 +``` + + - System architect for the ENGINI project worked towards a wireless +chip scale neural implant for chronic neuroscience and healthcare applications. + - CMOS fabrication and CAD tool integration lead for the FORTE project +which aims to integrate memristive devices with standard CMOS. + - Lead designer for ASIC implementation and deļ¬ned target deliverables +Contributed to publications, grants, and the development of intellectual property + - Facilitated goal driven team management and technical project planning +Presented at conferences to communicate ļ¬ndings to the academic community + +``` +Analog Signal Processing Technical Committee Member +Centre for Bio-Inspired Technology, +Imperial College London, United Kingdom +Dec. 2015 ā€“ Dec. 2019 +``` + + - Reviewed 40+ manuscripts in the past 5 years from JSSC, TCASI, TCASII, and TBCAS journals + - Facilitated ISCAS conference review process for selected analogue signal processing tracks + - Coordinated a ICECS conference special session on Oscillator Based Computing + +``` +Cadence System Administrator +Centre for Bio-Inspired Technology, +Imperial College London, United Kingdom +Sept. 2012 ā€“ Dec. 2019 +``` + + - Served as contact for the maintenance of IT infrastructure for research group + - Provided support for computing solutions and tool conļ¬guration + - Maintained a Linux build for CAD tools (i.e. Cadence, Synopsys, Mentor, CST) + - Maintained process development kits for core IC technologies (TSMC, AMS, UMC) + +``` +Graduate Teaching Assistant +Department of Electrical and Electronic Engineering, +Imperial College London, United Kingdom +Sept. 2013 ā€“ Dec. 2018 +``` + + - Supervised & mentored master student ļ¬nal year projects + - Assisted for laboratory/tutorial IC design sessions as demonstrator + - Assessed of oral and written work for EE4-20 & EE9-ALAB + - Lectured analogue IC design topics for EE4-20 + +{{< /columns >}} + + +{{< columns src="/images/about/hkust_logo.svg" >}} + +``` +Undergraduate Research Assistant +Department of Electrical and Electronic Engineering, +Hong Kong University of Science and Technology, China +Aug. 2010 ā€“ May 2011 +``` + + - Project Topic: ASIC development for micro electrode array based testing platforms for the study of cell cultures involving low-noise front-end design and analogue-to-digital conversion. + +``` +Undergraduate Research Assistant +Department of Electrical and Electronic Engineering, +Hong Kong University of Science and Technology, China +Jun. 2010 ā€“ Dec. 2010 +``` + + - Project Topic: Feasibility study of opto-mechanical CMOS structures for +detecting aerosol micro-particles actuated by photonics involving modelling +of micro-scale mechanical oscillators for phonon emission. + +{{< /columns >}} + +# Academic Record + +{{< columns src="/images/about/IC_white.svg" >}} + +``` +PhD Electrical Engineering +Department of Electrical and Electronic Engineering, +Imperial College London, United Kingdom, +Sept. 2012 ā€“ Aug. 2016 +``` + + - Engineering & Physical Sciences Research Council studentship (EPRC-1676620) + - Thesis Topic: Large scale integration of CMOS based sensors for brain machine interfaces. + + +``` +MSc Analogue and Digital IC Design +Department of Electrical and Electronic Engineering, +Imperial College London, United Kingdom, +Sept. 2011 ā€“ Aug. 2012 +``` + + - Graduated with Distinction + - Thesis Topic: Ultra-wideband radio and telemetry for medical implants + - Outstanding achievement prize for the MSc in A&D IC Design + - Integrated circuit design lab prize for the MSc in A&D IC Design + +{{< /columns >}} + +{{< columns src="/images/about/hkust_logo.svg" >}} + +``` +BEng Analogue and Digital IC Design +Department of Electrical and Electronic Engineering, +Hong Kong University of Science and Technology, China +Aug. 2008 ā€“ May 2011 +``` + + - Graduated with First-Class Honours + - Thesis Topic: CMOS Instrumentation for biological in-vitro multi-electrode systems. + - Swire international young fellows program scholarship + +{{< /columns >}} + +# Personal Achievements + +{{< columns src="/images/about/sscs_logo.svg" >}} + +One of my main aspirations during my PhD was to publish in the prestigious +[IEEE Journal of Solid-State Circuits](https://sscs.ieee.org/publications/ieee-journal-of-solid-state-circuits-jssc) +which I successfully did 2018 on my second attempt. The publication presented +a voltage-controlled oscillator circuit for sensing neural activity with +integrated off-set rejection. The publication process took well over half a year +with the two rounds of peer-review in order to improve the article's presentation. + +{{< /columns >}} + + +{{< columns src="/images/about/isa_logo.svg" >}} + +In 2008, together with a couple of friends I founded the +[International Student Association](https://isa.hkust.edu.hk/) at HKUST which +as of 2022 is the 3rd largest student organization at the University. When +I started my studies in Hong Kong the international student community was still +relatively small and we mostly organized events among our selves. Encouraged +by the student-office we formed a group to represent the growing body of +international student and help each other adapt to the university lifestyle +away from home. + +{{< /columns >}} diff --git a/build.sh b/scripts/build.sh similarity index 100% rename from build.sh rename to scripts/build.sh diff --git a/static/images/replace_style.awk b/scripts/replace_style.awk similarity index 100% rename from static/images/replace_style.awk rename to scripts/replace_style.awk diff --git a/static/images/about/IC_black.svg b/static/images/about/IC_black.svg new file mode 100644 index 0000000..7291929 --- /dev/null +++ b/static/images/about/IC_black.svg @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/static/images/about/IC_blue.svg b/static/images/about/IC_blue.svg new file mode 100644 index 0000000..68cb22b --- /dev/null +++ b/static/images/about/IC_blue.svg @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + 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