WIP: formatting publications on personal website.

content/about.md

@@ -1,5 +1,5 @@
 ---
-title: "About"
+title: "About This Site"
 date: 2022-05-21T19:52:54+02:00
 draft: false
 tags:
@@ -16,15 +16,12 @@ then processed for interesting features. Besides my day-to-day job that I enjoy
 a bit of casual programming as a hobby which is now predominantly based on
 python which makes it easy to adapt or share code.
 
-Currently my casualy programming projects are mainly oriented towards image
+Currently my casually programming projects are mainly oriented towards image
 processing for object recognition and vectorization techniques. Basically
 I am trying to approximate a rasterized images using absolute geometries and
-polynomial color contours such that they have infinite or vector-based precision.
+polynomial colour contours such that they have infinite or vector-based precision.
-Surprisingly the hardest part here has been detecting and extracting the
+Besides that I self-host a variety of web-services
-underlying line-art and resolving contours.
+both as an educational opportunity with the added benefit that I can enjoy more
-
-Besides that I try to self-host the web-services I used as much as possible
-both as an educational oppertunity with the added benifit that I can enjoy more
 privacy than the average person. While it is a bit of effort, I feel that this
 is an important part of software freedom and lets me avoid malicious services
 that I would otherwise be subject to.
@@ -45,32 +42,29 @@ realizing certain functions and implementations.
 
 ### Time-Domain-Processing
 
-There are always some suprising consistencies when re-imagining the
+There are always some surprising consistencies when re-imagining the
 representation of information. For example in time-domain systems we can realize
-resolve units of time with almost arbirtary precision, very often down to a
+resolve units of time with almost arbitrary precision, very often down to a
-KT/C equivilent limit. Howver some-how similar to traditional analog systems,
+KT/C equivalent limit. However some-how similar to traditional analogue systems,
 where the maximum dynamic range is limited by the voltage-supply, in
 time-domain systems this limit comes from rate at which we can make
 observations. For example say we have a 1 MHz pulse-width-encoded signal then
 we can only resolve relative timing information at 1 MHz. We could increase
 our dynamic range by reducing the pulse-repetition-rate but our information
 rate stays constant since we only double the information-per-pulse but half
-its rate. Comparing this again to traditional analog with a simple RC circuit
+its rate. Comparing this again to traditional analogue with a simple RC circuit
 where our maximum dynamic is set by the supply voltage to KT/C ratio and this
 is fixed irrespective of the resistor or bandwidth of the circuit. Again we can
 show that this is a fundamental consequence of the
-[equi-partition-theorum](https://www.wikipedia.org/equipartition-theorum)
+[equi-partition-theorum](https://en.wikipedia.org/wiki/Equipartition_theorem)
 irrespective of how we represent/encode information.
 
 The main advantage of time-domain processing is that we can exhaustively use
-digital logic. This is not only highly-adventagious when designing in a
+digital logic. This is not only highly-advantageous when designing in a
-deep sub-nanometer technology since they are geared towards these kind of
+deep sub-nanometre technology since they are geared towards these kind of
-circuits but also we dont suffer from performance losses due to device parameter
+circuits but also we don't suffer from performance losses due to device parameter
-degredation in the same way a tranditional op-amp might. In fact you can show
+depredation in the same way a traditional op-amp might. In fact you can show
 that time-domain circuits can realize almost ideal operators for summation,
-integration, multiplication, and thier inverses through closed-loop operation.
+integration, multiplication, and their inverses through closed-loop operation.
 
-### Over-Sampling Techniques
+### To Be Continued...
-
-Another facinating topic for embedded sensing circuits is the application of
-over-sampling techniques. 

content/posts/2021/assisted-vectorization.md

@@ -1,7 +1,7 @@
 ---
 title: "Image Vectorization 🖇🍮"
 date: 2021-12-08T19:26:46+01:00
-draft: false
+draft: true
 toc: true
 tags:
   - svg

content/posts/2021/mile-stones.md

@@ -1,7 +1,7 @@
 ---
 title: "Mile Stones 📚"
 date: 2021-08-28T16:13:52+02:00
-draft: false
+draft: true
 tags:
   - content
   - plan

content/posts/2021/spice-monkey.md

@@ -1,7 +1,7 @@
 ---
 title: "Spice Monkey 💻🐒"
 date: 2021-10-29T18:54:32+02:00
-draft: false
+draft: true
 toc: false
 images:
 tags:

content/posts/2022/hugo-short-codes.md

@@ -1,7 +1,7 @@
 ---
 title: "Hugo Short Codes"
 date: 2022-06-14T19:36:18+02:00
-draft: false
+draft: true
 toc: false
 tags:
   - hugo
@@ -73,4 +73,3 @@ railroad.Diagram("foo", railroad.Choice(0, "bar", "baz"), css=style)
 {{< python-svg dest="/images/posts/test.svg" title="This is a python-svg exmaple." >}}
 railroad.Diagram("foo", railroad.Choice(0, "bar", "baz"), css=style)
 {{< /python-svg >}}
-

content/posts/2022/latex-to-markdown.md

@@ -13,9 +13,9 @@ tags:
 Recently I started porting some of my latex articles to markdown as they would
 make a fine contribution to this website in simpler format. Making a simple
 parser python isn't that bad and I could have used [Pandoc](https://pandoc.org/index.html)
-but I wanted a particular format for rendering a hugo markdown page. So I
+but I wanted to keep formatting as simple as possible when rendering a hugo
-prepared several regex-based functions in python to dereference and construct
+markdown page. So I prepared several regex-based functions in python to
-a hugo-compatible markdown file.
+dereference and construct a hugo-compatible markdown file.
 
 ``` python3
 class LatexFile:
@@ -39,16 +39,18 @@ class LatexFile:
 ```
 
 The general process for converting a Latex document is outlined above. The
-principle here is to create a flat text source which we then incrementally
+principle here is to process a flat text source which we then incrementally
-format such that Latex components are translated correctly.
+format such that Latex components are translated incrementally and replaced
+by plain text with markdown syntax.
 
 
 ## Latex Components
 
 In order to structure the python code I created several named-tuples for
-self-contained Latex contexts such as figures, tables, equations, etc. then
+self-contained Latex contexts such as figures, tables, equations, etc. Then
-by adding a `markdown` property we can replace these sections with hugo
+by adding a `markdown` property we can create a collection of objects
-friendly syntax using short-codes where appropriate.
+where we can simple replace the corresponding latex code in a predictable
+manner.
 
 ``` python3
 class Figure(NamedTuple):
@@ -68,8 +70,85 @@ class Figure(NamedTuple):
             fig_str += "{{" + f'< figure src="{file}" width="500" >' + "}}\n"
         fig_str += (
             "{{"
-            + f'< figure src="{self.files[-1] if self.files else ""}" title="Figure {self.index}: {self.caption}" width="500" >'
+            + f'< figure src="{self.files[-1] if self.files else ""}" '
+            + f'title="Figure {self.index}: {self.caption}" width="500" >'
             + "}}\n"
         )
         return fig_str
 ```
+
+Notice that here we use a hugo short-code for when representing the figure in
+markdown. This lets us set with and other properties in a simpler and more
+systematic way.
+
+## Replacement Procedure
+
+As mentioned before the replacement simply looks for sections in the source and
+directly replaces them with appropriate markdown text. In order to do this it
+is important to process the source code in reverse order such that the text
+location references remain correct as the replacement occurs.
+
+``` python3
+def replace_figures(self) -> None:
+    """Dereference and replace all figures with markdown formatting."""
+    fig_list = self.figures
+    fig_list.reverse()
+    for figure in fig_list:
+        self.tex_src = (
+            self.tex_src[: figure.span[0]]
+            + figure.markdown
+            + self.tex_src[figure.span[1] :]
+        )
+    for figure in fig_list:
+        self.tex_src = re.sub(
+            "\\\\ref\{" + figure.label + "\}",
+            str(figure.index),
+            self.tex_src,
+        )
+```
+
+Secondly we also replace the latex references with plain text references. This
+means that instead of using labels that are translated during compilation into
+numbers we directly reference the figure number.
+
+``` python3
+@property
+def figures(self) -> List[Figure]:
+    """Parse TEX contents for context eces."""
+    return [
+        Figure(
+            span=(begin.start(), stop.end()),
+            index=index + 1,
+            files=[
+                elem[1]
+                for elem in re.findall(
+                    "\\\\includegraphics(.*)\{(.*)\}",
+                    self.tex_src[begin.start() : stop.end()],
+                )
+            ],
+            caption=self.first(
+                re.findall(
+                    "\\\\caption\{(.*)\}",
+                    self.tex_src[begin.start() : stop.end()],
+                )
+            ),
+            label=self.first(
+                re.findall(
+                    "\\\\label\{(.*)\}",
+                    self.tex_src[begin.start() : stop.end()],
+                )
+            ),
+        )
+        for index, (begin, stop) in enumerate(
+            zip(
+                re.finditer("\\\\begin\{figure\*?\}", self.tex_src),
+                re.finditer("\\\\end\{figure\*?\}", self.tex_src),
+            )
+        )
+    ]
+```
+
+The piece of python code above exemplifies how we capture all figures found in
+the latex source code and aggregate them in a list of named-tuples. Naturally
+this is dependent on the style used when writing latex but I generally try
+to keep latex-code a simple and systematic as possible.

content/publications/2018/autonomous-soc-for-neural-local-field-potential-recording-in-mm-scale-wireless-implants.md

@@ -27,7 +27,7 @@ Next generation brain machine interfaces fundamentally need to improve the infor
 
 There has been significant effort in developing integrated circuits for Brain Machine Interfaces (BMIs)[^1]. These systems enable a wide range of applications from recording neural signals for scientific study to treating neurological conditions. They integrate a multitude of functions for sensing, processing, telemetry and power management. There is a drive to develop wireless modules that are hermetically packaged for chronic implant applications[^2]. Moreover, any reduction in size can substantially improve device efficacy by reducing the impact on surrounding tissue. Any reduction in weight is also highly desirable for behaving animal studies. While a number of proposed systems have relied on PCB[^3] or flexible [^4] technologies that allow low cost, rapid development. This approach leads to substantially larger implants when compared to silicon-based integration[^1]. This is because the silicon substrate enables a large number of electrodes to be integrated directly onto the active die in the shape of an implantable shank[^5]. In contrast, making a large number of intra-device connections has a significant impact on device footprint as well as fabrication complexity with added bio-compatibility constraints [^6]. For this reason a number of groups are investigating millimetre-scale solutions for recording[^7] and stimulation[^8] with all aspects of the implant integrated within the silicon die or micro-machined package.
 
-{{< figure src="Figures/ENGINI.pdf" title="Figure 1: The ENGINI concept showing: (a) multiple freely floating probes being wirelessly interrogated by a headstage unit; (b) schematic representation." width="500" >}}
+{{< figure src="/images/biocas2017/ENGINI.svg" title="Figure 1: The ENGINI concept showing: (a) multiple freely floating probes being wirelessly interrogated by a headstage unit; (b) schematic representation." width="500" >}}
 
 The 'Empowering Next Generation Implantable Neural Interfaces' (ENGINI) project achieves its scalability by utilising multiple mm-scale probes that are each implanted and 'freely floating' in the cortex. These observe field potentials along the cortical column but also laterally through different probes. These are wirelessly coupled to an external headstage with trancutanious and transdural inductive links to deliver power and exchange data. This is illustrated in Fig. 1.
 
@@ -38,7 +38,7 @@ This particular system relies on the autonomous behaviour of each probe such tha
 
 The integrated system architecture is shown in Fig. 2. This shows a single recording unit which is inductively coupled to a primary coil L<sub>1<sub> that provides power using a 433 MHz carrier to leave sufficient bandwidth for frequency division multiplexing multiple recording units. In fact the receiving coil L<sub>2<sub> will be located on a passive undoped silicon interposer that is flip-chip bonded to the active instrumentation IC. The resonant tank L<sub>2<sub> C<sub>2<sub> receives the transmitted power and establishes a DC voltage on V<sub>DD<sub> once the rectifier down-converts the carrier. First a biasing circuit is powered that generates digital flags that indicate the supply voltage level. These flags assist the self-tuning control algorithm to adjust the loading capacitance C<sub>T<sub> to tune or detune the resonant tank L<sub>2<sub>C<sub>2<sub> and receive a specific amount of power to establish 1.5 V on the V<sub>DD<sub> supply. This feedback regulates the supply voltage in a course manner without needing active control from the primary side (external controller). This implies the analogue circuits need to accommodate for any fluctuations without diminishing sensor precision. The continuous-time fully-differential modulator topology will further prevent these supply noise aggressors from being aliased in-band during sampling. The system clock can be directly extracted from the resonant tank using adiabatic logic elements to implement a series of frequency dividers before passing the clock to the digital core[^10].
 
-{{< figure src="Figures/SYS.pdf" title="Figure 2: ENGINI system architecture for recording LFP at high resolution. This tunes the receiving resonant tank L<sub>2<sub>C<sub>2<sub> to regulate V<sub>DD<sub>." width="500" >}}
+{{< figure src="/images/biocas2017/SYS.svg" title="Figure 2: ENGINI system architecture for recording LFP at high resolution. This tunes the receiving resonant tank L<sub>2<sub>C<sub>2<sub> to regulate V<sub>DD<sub>." width="500" >}}
 
 
 # 4 Circuit Implementation
@@ -51,7 +51,7 @@ This ENGINI prototype has been developed for a 0.35 μ m CMOS technology such th
 
 This provides a stable power supply for the electronics and back-scatters digitised recordings. The circuit architecture is shown in Fig. 3. This contains a binary weighted capacitor bank C<sub>T<sub>, a passive full wave rectifier, and a sensing circuit which are all digitally-controlled. The principle of operation can be described as follows. First, the cross-coupled rectifier converts the induced AC voltage to a DC power on V<sub>x<sub>. Then, the low voltage amplifier A<sub>2<sub> performs auto-zeroing by shorting C<sub>F<sub> and simultaneously sampling the rectified voltage onto C<sub>I<sub>. After sampling, the parallel binary-weighted capacitor bank C<sub>T<sub> is adjusted to tune or de-tune LC tank on the secondary side. There is therefore a voltage fluctuation at node V<sub>x<sub>. The change in V<sub>x<sub> is amplified 30\\(\times\\) by A<sub>2<sub> which corresponds to the ratio C<sub>I<sub>/C<sub>F<sub>. The polarity of the resulting change is digitised using the comparator, instructing the digital control to add or remove parallel capacitors in the next cycle of regulation. Two supply voltage level indicators from the biasing circuit further assist this feedback to increase or reduce the supply voltage and whether to perform LSK respectively. The resistor R<sub>z<sub> is added after the output of rectifier such that the speed at which V<sub>X<sub> can be controlled is not dependent on the load capacitance C<sub>L<sub> which may be quite large. This allows fast regulation with a clock speed of 846 kHz at the cost of some reduction in power efficiency due to the voltage drop from V<sub>X<sub> to V<sub>DD<sub>.
 
-{{< figure src="Figures/REG.pdf" title="Figure 3: Adaptive power conversion and regulation circuit using full-wave rectifier, tunable LC tank, auto-zeroing amplifier and strong arm comparator" width="500" >}}
+{{< figure src="/images/biocas2017/REG.svg" title="Figure 3: Adaptive power conversion and regulation circuit using full-wave rectifier, tunable LC tank, auto-zeroing amplifier and strong arm comparator" width="500" >}}
 %
 
 ## 6  \\(\Delta\Sigma\\) Instrumentation Circuit
@@ -60,7 +60,7 @@ This provides a stable power supply for the electronics and back-scatters digiti
 
 The instrumentation circuit used to acquire the electrode recordings is based on the time-domain \\(\Delta\Sigma\\) modulator in [^11]. This uses differential oscillators as the integration element with an asynchronous signal quantizer. However the implementation presented here introduces an additional Gm-C integrator and a feed-forward path to realise second-order noise shaping. This reduces the oversampling ratio (OSR) requirement and substantially increases the dynamic range of the system. A single-ended equivalent of the fully-differential structure used here is shown in Fig. 4.
 
-{{< figure src="Figures/SDM.pdf" title="Figure 4: Simplified equivalent of the second-order \\(\Delta\Sigma\\) modulator using time-domain signal quantization exhibiting a bandpass response due to the switched current DAC which removes any electrode offset." width="500" >}}
+{{< figure src="/images/biocas2017/SDM.svg" title="Figure 4: Simplified equivalent of the second-order \\(\Delta\Sigma\\) modulator using time-domain signal quantization exhibiting a bandpass response due to the switched current DAC which removes any electrode offset." width="500" >}}
 %
 
 Note that this is a DC-coupled configuration where the analogue node V<sub>O<sub> tracks the electrode potential. An electrode offset larger than \\(\pm\\)100 mV can be accommodated without saturating the modulator by adding the digitally switched and duty cycled current in the feedback path. The quantized signal Q is AC coupled onto V<sub>O<sub> with a relatively large attenuation factor due to capacitive division α=1/(C<sub>0<sub>/C<sub>C<sub>+1) which will allow the in-band signal gain. This can be confirmed using the small signal model for this circuit described in Eq. 1-4 where H(s) represents the second-order loop filter and C(s) the charge pump with capacitive feed-forward. The factor k1=OSR f<sub>smp<sub>/2 reflects the modulator bandwidth in terms of the target sampling frequency f<sub>smp<sub>. The factor k2=2\\(\pi\\) f<sub>hp<sub> represents the integration constant of the charge pump in terms of the high-pass cut-off frequency f<sub>hp<sub>. This approach is inspired by the first order modulator in [^12]. The implemented circuit uses an OSR of 64, a 1 Hz high-pass corner frequency, and third order CIC filter to decimate the output. This leads to the noise and signal transfer functions shown in Fig. 5.
@@ -73,7 +73,7 @@ $$  NTF(s) = \frac{1}{1+\alpha C H} $$
 
 $$  C(s) = 1 + \frac{k2}{s} $$
 
-{{< figure src="Figures/BODE.pdf" title="Figure 5: Analytical quantisation noise and signal transfer functions of the proposed modulator configuration." width="500" >}}
+{{< figure src="/images/biocas2017/BODE.svg" title="Figure 5: Analytical quantisation noise and signal transfer functions of the proposed modulator configuration." width="500" >}}
 
 ## 7 Reference and Biasing Circuit
 
@@ -83,7 +83,7 @@ Since the circuit is going to be operated in a neural implant it is expected tha
 
 In addition, the reference circuit generates logic levels indicating that the supply voltage has reached \\(\approx\\) 1 V, 1.3 V and 1.5 V used by the control loop of the SoC. The first indicator (1 V) is designed using a current source inverter as described in [^15]. The remaining two indicators are derived from V<sub>REF<sub> to ensure good tolerance to process variations.
 
-{{< figure src="Figures/refc.pdf" title="Figure 6: Schematic of the reference and biasing circuit (start-up circuit not shown)." width="500" >}}
+{{< figure src="/images/biocas2017/refc.svg" title="Figure 6: Schematic of the reference and biasing circuit (start-up circuit not shown)." width="500" >}}
 
 # 8 Simulation Results
 
@@ -95,26 +95,26 @@ The designed reference circuit consumes a bias current of 5 μ A and generates a
 
 The overall system specifications are summarised in Table 1. Comparing the ENGINI system with other SoCs for brain machine interfaces demonstrates an increase in dynamic range and reduction in core size for equivalent noise performance as a result of the proposed architecture. The active silicon CMOS is currently being fabricated and will be flip-chip bonded onto a silicon based carrier. The two dies are illustrated and annotated in Fig. 9. Both dies are 16 mm² in size however the interposer is passive and only needs to embed the seal, coil, and electrode interconnect metallisation. Preliminary characterisation has shown that the L<sub>2<sub> can have an inductance of 5 nH with a Q-factor \textgreater12.
 
-{{< figure src="Figures/SPEC.pdf" title="Figure 7: Output spectrum of the \\(\Delta\Sigma\\) instrumentation circuit from transient simulation using a 10 mVpp sinusoidal input tone at 210 Hz." width="500" >}}
+{{< figure src="/images/biocas2017/SPEC.svg" title="Figure 7: Output spectrum of the \\(\Delta\Sigma\\) instrumentation circuit from transient simulation using a 10 mVpp sinusoidal input tone at 210 Hz." width="500" >}}
 
-{{< figure src="Figures/PSRR.pdf" title="Figure 8: PSRR (Power Supply Ripple Rejection) at V<sub>REF<sub>. This shows a PSRR of μ =78.29 dB & σ =1.58 dB, μ =69.94 dB & σ =1.59 dB and μ =79.95 dB & σ =0.52 dB at DC, 64 kHz and 433 MHz respectively." width="500" >}}
+{{< figure src="/images/biocas2017/PSRR.svg" title="Figure 8: PSRR (Power Supply Ripple Rejection) at V<sub>REF<sub>. This shows a PSRR of μ=78.29 dB & σ=1.58 dB, μ=69.94 dB & σ=1.59 dB and μ =79.95 dB & σ =0.52 dB at DC, 64 kHz and 433 MHz respectively." width="500" >}}
 
 Table 1: System Characteristics and Comparison with State-of-the-Art
-|		Parameter  [unit]	| This Work \\(\dagger\\)  | [^1] | [^16] | [^3]|
+|		Parameter  [unit]	| This Work | [^1] | [^16] | [^3]|
 |----|----|----|----|----|
 |		Year 				| **2017** | 2017 | 2015 | 2016 |
 |		Application				| **LFP** | ECoG | ECoG | EAP |
 |		Tech.[nm]		| **350**	 | 180  | 65 | 350 |
 |		Supply-V[V]	| **1.5**   | 0.8 | 0.5 | 1.8|
-|		Total-P[W]	| \textbf{80 μ}(\star) | 0.1 m | 0.2 m | 51 m |
+|		Total-P[W]	| 80μ | 0.1 m | 0.2 m | 51 m |
 |    Core-A[mm²]	| **2.1** |	9 | 5.8 | 12.5 |
 |    \# Channels				| **8** | 16 | 64 | 8|
 |    Bandwidth[Hz]		| **825** | 1 k | 500	| 11 k|
 |    DR[dB] 			| **85**	|	55 | 52 | 50 |
-|    IRN  [μ V<sub>rms<sub>] | **1.3** | 1.5 | 1.3 | 2.9 |
+|    IRN  [μV<sub>rms<sub>] | **1.3** | 1.5 | 1.3 | 2.9 |
-\\(\dagger\\) Based on preliminary simulation results. \\(\star\\) Includes rectifier loss.
 
-{{< figure src="Figures/D2D.pdf" title="Figure 9: Annotated design for each silicon die that will be flip-chip bonded together. This shows the bonding pads, inductive coil, seal ring, and core ENGINI system to scale." width="500" >}}
+
+{{< figure src="/images/biocas2017/D2D.svg" title="Figure 9: Annotated design for each silicon die that will be flip-chip bonded together. This shows the bonding pads, inductive coil, seal ring, and core ENGINI system to scale." width="500" >}}
 
 # 9 Conclusion
 

content/resume.md

@@ -39,12 +39,13 @@ worked in smaller design groups of 5-10 people where you need to be familiar wit
 the entire development process for a device from start to finish touching on process selection,
 tool configuration, and production planning.
 
-Besides that I am very comfortable with software development. Currently I
+Besides that I am very comfortable with software development. I
 extensively program in python, maintaining packages for command-line-tool-chains
-and some of my hobby projects. However I administer and deploy several web
+and some of my hobby projects. In addition I administer and deploy several web
 services based on ruby, php, and node/js with a postgresql backend. Most of
-my earlier projects while at Imperial were C++ based with Qt as the go-to
+my earlier projects while at Imperial College were C++ based with Qt as the
-graphical library.
+go-to graphical library and revolved around creating interfaces with custom
+devices and processing data.
 
 # Employment Record