---
title: "A 0.016 mm² 12 b ΔΣSAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays"
date: 2017-06-15T15:26:46+01:00
draft: false
toc: true
math: true
type: posts
tags:
  - publication
  - instrumentation
  - CMOS
  - biomedical
  - data-converter
---

Lieuwe B. Leene, Timothy G. Constandinou

Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK

Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK

# 1 Abstract

The instrumentation systems for implantable brain machine interfaces represent one of the most demanding applications for ultra low power analogue-to-digital-converters (ADC) to date. To address this challenge this paper proposes a \\(\Delta\Sigma\\)SAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0-2 MASH topology. This configuration uses a specialized FIR window to decimate the \\(\Delta\Sigma\\) modulator output and reject mismatch errors from the SAR quantizer which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision.} A fully differential prototype was fabricated using \cmostech to demonstrate 10.8 ENOB precision with a 0.016 mm² silicon footprint. Moreover a 14 fJ/conv figure-of-merit (FOM) can be achieved while resolving signals with the maximum input amplitude of \\(\pm\\)1.2 Vpp sampled at 200 kS/s.} The ADC topology exhibits a number of promising characteristics for both high speed and ultra low power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio which are critical parameters for many sensor applications.

# 2 Introduction

The emergent market for wearable electronics and implantable devices for personalized health care has resulted in a growing demand for miniaturized battery powered systems that wirelessly connect a network of sensors[^1]. These systems rely extensively on high precision analogue to digital conversion to leverage digital processing techniques and accommodate stringent diagnostic requirements[^2]. As a result the ADC power, area, and precision can have a profound impact on a system's overall capabilities. For this reason oversampling techniques using \\(\Delta\Sigma\\) ADCs have already been used extensively to accommodate the niche characteristics of biomedical devices and acquire low frequency bio-signals [^3].}

More recent developments allow these techniques to be more applicable to large sensor arrays using an incremental analogue to digital converter (IADC) topology [^4]. This is in contrast to the conventional use where a single oversampling ADC continuously converts the signal from a single sensing unit with exceptional efficiency. IADC designs are unique in the sense that they periodically reset the loop filter which enables a single ADC to process multiple analogue inputs with reduced latency. This periodic reset associates a particular conversion time for each result and enables pipelined [^4], two-step [^5], or multi-step operation [^6]}. The resulting modulator can exhibit reduced mismatch sensitivity and require a smaller oversampling ratio while achieving equivalent performance to that of higher order modulators[^7]. This is crucial for larger sensor arrays because reduced circuit complexity leads to more compact designs and faster signal conversion. These earlier publications realize an IADC structure that explicitly transfers the quantization residue from one quantizer to the next using a sample and hold mechanism which is not necessarily required. For instance the zoom technique used in [^8] reuses the capacitive DAC during conversion thereby reducing complexity and power consumption. The resulting system achieves exceptional precision by combining a SAR with a second order switched capacitor (SC) \\(\Delta\Sigma\\) modulator. A common problem however is that the SAR INL/DNL errors are not shaped by the loop filter and end up limiting the overall precision unless dynamic element matching techniques (DEM) are used. This can lead to exhaustive digital overhead for DEM control and necessitate additional redundancy in the capacitive digital to analogue converter (DAC) to remove the SAR nonlinearity[^9].}

{{< figure src="/images/tcas2017/block_sys.svg" title="Figure 1: Block level implementation of the proposed ADC array structure for sensor arrays using SAR and \\(\Delta\Sigma\\) quantizers where a digital filter is applied to the comparator bit stream to perform decimation and mismatch correction." width="500" >}}

The system proposed by this paper is illustrated in Fig. 1 which uses a SAR and CT-\\(\Delta\Sigma\\) together to convert the signal from four analogue inputs. This configuration is then tiled 16 times in parallel to record from 64 channels simultaneously for neural recording applications. The topology is introduced as a $\Delta \Sigma$SAR because it emerged from introducing higher order CT-\\(\Delta\Sigma\\) type noise shaping to the SAR by processing the residue charge left after the SAR conversion. Using SC techniques with a similar motivation also lead to the noise shaping SAR (NSSAR) topology from [^10] which has been used extensively to achieve very high resolution SARs [^11] and higher order modulators with reduced active filter structures [^12]. In fact the fully-passive NSSAR technique can increase the SAR precision by several bits while immune to PVT variation [^13]. The distinction here is that the NSSAR will shape the quantization noise over multiple samples by introducing 1 to 3 extra cycles per sample where as the $\Delta \Sigma$SAR will allow one-shot conversions but introduce considerably more cycles corresponding to the oversampling ratio of the modulator. The later is characteristic of IADC operation. Additionally the CT approach leads to an inherent reduction in size because the loop filter is not subject to extra sources of sampling noise typical in CS circuits.} The IADC 0-2 multi-stage noise shaping (MASH) quantization scheme used by the \\(\Delta\Sigma\\)SAR can be interpreted as first resolving the sampled input using a conventional SAR and then applying a \\(\Delta\Sigma\\) feedback loop to resolve the remaining quantization residue left on the capacitor array equivalent to the zoom technique. The resulting bit stream from the comparator output consists of both SAR and oversampled quantization results. The advantage this topology presents is that it can be configured without the need for DEM or analogue dithering techniques because SAR INL/DNL errors can instead be cancelled by calibrating the FIR filter that processes this bit stream in the digital domain. This minimises capacitive switching during signal conversion and reduces overall complexity. Moreover by virtue of resolving a small SAR residue, the CT loop filter can maximize its noise efficiency without much concern for distortion or modulator nonlinearity.}

This paper presents an analytic design method for evaluating which condition allows the zoom type IADCs to exhibit high performance and which two-step configuration will lead to the best efficiency or size. Preliminary efforts to realize the system in Fig. 1 are presented in [^14] and the circuits proposed here are improved to achieve better power efficiency as part of a larger reconfigurable neural recording system [^15]. This system uses an array of miniaturised ADCs that distributes the digital processing over many parallel segments leading to lower clock frequencies and better efficiency opposed to demanding a single high frequency ADC and digital core.} To present the design characteristics of the \\(\Delta\Sigma\\)SAR, this paper is organized as follows. Section \ref{sec:design} introduces the principle design relations of this ADC structure with regard to system efficiency and size. This is followed by the proposed mismatch compensation method in Section \ref{sec:cali}. The circuit level implementation is proposed in Section \ref{sec:circ} with design considerations for the loop filter, capacitive DAC and FIR filter. Finally measured results are presented in Section \ref{sec:mes} which are used to draw conclusions in Section \ref{sec:con}.


# 3 \\(\Delta\Sigma\\)SAR Architecture

The \\(\Delta\Sigma\\)SAR topology closely resembles the SAR with an additional loop filter that can switch between amplifying \\(A(s)\\) and integrating \\(H(s)\\) behaviour following the last SAR conversion. This similarity is shown in Fig. 2 which represents a single ended equivalent of the fully differential implementation described here. The input signal is sampled on the bottom plate of the capacitive array such that conventional SAR feedback can be applied while the loop filter is initially providing wideband amplification of 10x. Once the first \\(N\\) bits are resolved the comparator output is connected directly to a unit element in the capacitive array for the \\(\Delta\Sigma\\) quantization phase. Simultaneously the loop filter is switched to introduce second order noise shaping and resolves another \\(M\\) bits using DC extra oversampling cycles. In theory this will result in \\(M+N\\) bits of precision but in practice the SAR conversion will need to evaluate \\(N+1\\) bits with 1 bit of redundancy. This redundancy implies that the residue will always be half of the modulator input range to prevent overloading the \\(\Delta\Sigma\\) ADC[^16]. If 1 cycle is used for sampling the ADC will need to be clocked at \\((N+DC+2)f_{smp}\\) for a sampling frequency \\(f_{smp}\\) with a modulator bandwidth \\(f_{bw}\\) at half this clock frequency. A typical conversion is illustrated by the timing diagram in Fig. 3 which shows the FSM using 1 cycle for sampling, \\(N+1\\) cycles for SAR, and DC cycles for \\(\Delta\Sigma\\) modulation. Meanwhile the comparator results will infer if the corresponding FIR coefficient provided by a shared controller is added or subtracted from a local accumulator thereby resolving the input signal. To provide insight to the design considerations we will first discuss the noise requirements needed for achieving a \\(N+M\\) ADC precision. This will reveal the dominant power requirements due to the filter and capacitive DAC and also give some indication about the size of each capacitor in Fig. 2 which can then be used to estimate area. Note however that the defining characteristic of this quantization process is that the SAR residue is bound to a well defined voltage range of $\pm V_{R}/2^{N+1}$ where \\(V_{R}\\) is the ADC reference voltage. The reduced input range implies that feedback may not be needed to linearise the Gm-C loop filter used during \\(\Delta\Sigma\\) conversion but it also indicates the filter coefficients have to be carefully adjusted to achieve second order noise shaping. }

{{< figure src="/images/tcas2017/sch_adc.svg" title="Figure 2: Proposed topology that interoperates SAR and oversampling quantizers in the same signal loop using a capacitive DAC, switched loop filter, and single bit quantizer." width="500" >}}

{{< figure src="/images/tcas2017/fsm.svg" title="Figure 3:  Timing diagram of the sampling (SMP), SAR (S0-SN), and oversampling (\\(\Delta\Sigma\\)) modes of operation where \\(C_{0}\\) to \\(C_{N+DC}\\) correspond to the calibrated coefficients of the FIR filter. EOC is the end-of-conversion signal that is put low when the quantization process is finished. " width="500" >}}

## 4 Topology Optimization

The efficient operation of low speed ADCs primarily relies on the careful consideration of various noise sources to avoid dissipating excess power. However the two modes of operation have characteristically different requirements. Concisely stated the \\(\Delta\Sigma\\) modulator will focus on achieving a specific noise floor because out of band noise is removed after decimation while the SAR operation is sensitive to integrated noise over the entire circuit bandwidth. To illustrate the design relations quantitatively the following discussion will reiterate on several expressions from well established \\(\Delta\Sigma\\) theory [^17]. This will allow us to determine system constraints particularly with respect to the analogue filter that provides second order noise shaping and in this case consumes most of the power.}

## 5 Filter Noise Constraints

First recall that the oversampling ratio for a second order modulator is dictated by Eq. 1 in terms of resolving \\(M\\) bits. This will later be used in association with the expression in Eq. 2 to evaluate acceptable quantization noise power \\(S^2_{n}\\) for a \\(N+M\\) precision ADC.}

$$  DC \geq \sqrt[5]{ \frac{2  \pi^4}{15 \cdot 2^{-2(M+1)}}} $$

$$  S^2_{n} =\frac{1}{12}   \left( \frac{V_R}{2^{N+M+1}}  \right)^2 $$

Now in order to capture the subjective performance of the circuit level implementation and its impact, this analysis uses the Noise Efficiency Factor (NEF). The expression for NEF in Eq. 3 normalizes the input referred noise \\(e^2_{in}\\) of a particular implementation to that of a bipolar transistor with a biasing current equivalent to that used by the filter \\(I_{filt}\\). As a result we can abstractly consider noise-power relations without considering a specific filter topology that will exhibit some particular NEF.}

$$  NEF^2 \deff \frac{2 I_{filt}  e^2_{in}}{\pi U_T   4kT  f_{bw}} $$

In fact by combining this with the ADC noise requirement in Eq. 2, \\(I_{filt}\\) can be predicted as a function of circuit topology and its equivalent NEF. This is detailed in Eq. 4 under the condition that \\(e^2_{in} = S^2_{n}\\) where the relevant circuit noise bandwidth is reduced \\(f_{bw}/DC\\) due to oversampling.}

$$  I_{filt} = \pi U_T   24kT  \frac{ f_{bw} }{ DC } \left( \frac{ 2^{N+M+1}   NEF }{V_R} \right)^2 $$

Similarly \\(I_{filt}\\) can be evaluated for just the SAR operation as a special case: $I_{SAR} \deff I_{filt}(DC=1,M=0)$. In the case that \\(I_{SAR}\\) is larger than the estimate in Eq. 4 we should adopt that value instead. This result is mainly relevant for SAR converters where an analogue amplifier is used to precede the comparator and thereby dominating the noise requirements[^18]. Here it will also be used to indicate the preliminary performance with respect to \\(N\\) & \\(M\\) with a fixed clock speed and the associated conversion time of \\(N+DC+2\\) cycles. The resulting conversion efficiency is proportional to \\(2^{N+M}/P_A(N+DC+2)\\) as conversion per Watt where total analogue power is estimated as $P_{A} \approx V_{R}I_{filt}$. In this case the filter supply voltage is simply equal to the reference voltage. Normalization allows the relative efficiency to be visualized in Fig. 4 which provides some evidence that the filter alone tends to be more efficient as \\(M\\) becomes larger than \\(N\\). However \\(N\\) can not be arbitrarily small if the residue need to be kept in the linear range of the modulator. This implies a direct relationship between the ADC reference voltage and the minimum SAR resolution.} The details of this requirement is strongly dependent on the full ADC precision and its sensitivity towards transistor nonlinearity. However as a priori the minimum SAR resolution \\(N\\) can be approximated by considering that the linear input range for a sub-threshold differential input pair is related to the thermal voltage $\pm U_{T}$[^19] which suggests that \\(N \geq\log_2(V_{R}/U_{T})\\) to keep the residue inside the linear range.}

{{< figure src="/images/tcas2017/Cost.svg" title="Figure 4: Power efficiency as \\(2^{N+M}/P_A(N+DC+2)\\) in terms of conversions per Watt where \\(N+M\\) is the target precision of the analogue filter for different values of \\(N\\) & \\(M\\) normalised by the best case where \\(M=8\\) & \\(N=1\\).}" width="500" >}}

## 6 Estimating System Power

The previous result is relatively optimistic in the sense that it does not consider the decimation filter or DAC power dissipation. To warrant an accurate estimation of the ADC's efficiency and resource requirements the Digital \\(P_{D}\\), and capacitive switching \\(P_{C}\\) losses should also be estimated.}

$$  P_C = C_{U}    f_{smp}  V^2_R \left(DC/2 + \sum_{i=1}^{N} (2^i-1) 2^{N-2i-2}  \right) $$

Eq. 5 includes the SAR energy dissipation in terms of the capacitive switching using the analysis from [^20].} The \\(V_{cm}\\) based switching method employed here retains a stable common mode on \\(V_{DAC}\\) with good conversion efficiency. This will help to preserve the linearity of the modulator. Variation in common mode voltage changes the offset of the loop filter as well as the impact of top plate parasitics[^20]. Both will introduce nonlinearity that is convoluted by the SAR quantization process and can be challenging to compensate accurately. \\(P_{C}\\) is evaluated for \\(N+1\\) SAR cycles where the unit capacitor \\(C_{U}\\) size introduces some degree of freedom. Strictly the total capacitance is bounded such that the \\(kT/C\\) noise is smaller than noise requirement of Eq. 2. For instance we could let the sampling noise contribute half the allowable noise power which leads to a minimum capacitance according to Eq. 6 given a \\(2^{N+1}\\) unit binary DAC.

$$  C_U = \frac{12  kT}{V_R^2}   2^{N+2M+1} $$

This unit element should be noticeably larger than what may be expected from SAR configurations due to the small number of elements in the capacitor array resulting in reduced matching and interconnect complexity. Generally such a configuration will favour high density vertical metal-insulator-metal (MIM) capacitors that have large minimum size requirements and can be placed over active circuitry to reduce silicon footprint. In fact by using a split capacitor configuration the size of \\(C_{U}\\) can be even larger with less elements in the array for the same sampling capacitance leading to very efficient utilization of MIM capacitor area[^21]. It may still be the case that \\(C_{U}\\) is smaller than the minimum capacitance \\(C_{min}\\) for intermediate precision of 6-10 bits. In such a case this model will simply adopt \\(C_{min}\\). This will also apply to the load capacitance \\(C_{L1}\\) when it is calculated with respect to the modulator bandwidth as \\(f_{bw}=gm_{1}/C_{L1}\\). However this should carefully consider the reduced input swing of \\(V_{R}/2^{N+1}\\) which means the transconductance for a conventional fully-differential input in sub-threshold operation would be $gm_{1}=V_{R} I_{filt}/(\eta U_{T} 2^{N})$ where \\(\eta\\) is the transistor slope factor.

In order to estimate the digital losses this model extrapolates the energy dissipation per clock cycle extracted from a 1 bit accumulator taken as \\(E_{reg}\\). The associated register depth \\(R_{D}=N+M+log_{2}(DC)\\) bits is derived by considering the accumulated rounding errors from DC additions during FIR decimation}. This leads to Eq. 7 which is expected to be insignificant at higher resolutions because decimation filter has reduced requirements when compared to the full precision of the integrator.

$$  P_D = R_D   E_{reg}   f_{smp} \underbrace{(DC+N+2)}_{Cycles/Sample} $$

## 7 FOM Dependence

The above relations should provide a good indication for the power requirements even though some system components such as the comparator and auxiliary circuits have been ignored. The Walden \\(FOM_{W}\\) and Schreier \\(FOM_{S}\\) are presented in Eq. 8 & 9. These performance metrics are plotted in Fig. 5 by assuming typical values from the \cmostech process. \\(V_{R}\\) is adjusted to \\(0.6/1.2/2.4 V\\) which keeps the linear input range of the \\(\Delta\Sigma\\) modulator consistent while resolving different SAR resolutions for fair comparison. Other constants are assumed as follows; \\(\eta=1.2\\), \\(NEF=1.4\\), \\(E_{reg}=1\\) fJ, \\(C_{min}=10\\) fF, \\(f_{smp}=10^5\\) Hz, \\(f_{bw}=10^5 (N+DC+2)/2\\) Hz. The general trend presented here is that the topology operates at maximal performance when the most of the power is dissipated by the oversampling loop and the lowest energy per conversion is dissipated when the capacitive switching and modulator power become comparable. It is not surprising that reducing the supply voltage makes it more difficult to achieve a good FOM because the absolute noise performance becomes more difficult to achieve. For reference a conventional $\Delta \Sigma$ modulator [^22] is designed with the same target specifications and using the same analysis method to configure the OPAMP integrators and resistive input network. Such a configuration achieves 167 dB \\(FOM_{S}\\) irrespective of target resolution when we consider just the filter power dissipation. In fact this figure is commonly achieved by state of the art [^8]. This highlights how the \\(\Delta\Sigma\\)SAR configuration can theoretically achieve more than 2X better performance for resolutions above 12 bits even when operating at lower supply voltages.

$$  FOM_W = \frac{P_C + P_D + P_A}{f_{smp}   2^{N+M}} $$

$$  FOM_S = 6.02  (N+M) + 10   \log_{10}\left( \frac{f_{smp}/2}{P_C + P_D + P_A}\right) $$

{{< figure src="/images/tcas2017/AMD.svg" title="Figure 5: Estimation on the expected \\(FOM_{S}\\) and \\(FOM_{W}\\) for a resolution and varying SAR precision. The red star and blue circle indicate the target and measured performance respectively. The blue stars correspond to \\(FOM_{W}\\) achieved by other works." width="500" >}}

{{< figure src="/images/tcas2017/APM.svg" title="Figure 6: Estimated area requirements with respect to ADC resolution for various SAR resolutions.  The red star and blue circle indicate the target and measured performance respectively. The blue stars correspond to area achieved by other works." width="500" >}}

{{< figure src="/images/tcas2017/FOMS_EA.svg" title="Figure 7: The estimated DOP with respect to the target ENOB and the \\(\Delta\Sigma\\) modulator resolution. This normalised by the best configuration where \\(M=5.8\\) & \\(ENOB=10.9\\) (i.e. \\(N=5.1\\)). \\(V_{R}\\) is assumed to be 1.2 V and the red star indicates the target performance for this implementation.}" width="500" >}}

$$  EA = \left( 2 C_{L1} + C_{U}   2^{N+2} \right) / C_{dens} $$

The required area for this configuration is estimated by Eq. 10 which uses the MIM capacitor density \\(C_{dens}\\) of 2fF/\mmu m². As shown in Fig. 6 high resolution configurations will tend towards noise limited requirements that are closely related to the integration and sampling capacitors. Lower resolutions are largely dependent on technology and how the SAR DAC is configured to address mismatch. Fig. 7 shows the impact of \\(M\\) on overall ADC efficiency in combination with the area requirement. This is characterised using the density of performance $DOP = FOM_{S}-10 log_{10}(EA)$ which peaks for an ENOB of 11.4 bits with \\(M\\) being 5.8 bits.} The overall quantitative results show exceptional figures of merit with highly compact configurations for 10-16 bit designs from first principles. The design described above only focuses on achieving an optimal noise performance because it dominates the low frequency FOM metrics.} Naturally a number of extra considerations need to be made for achieving the desired ENOB. Finding the requirements for open loop gain, parasitics, nonlinearity, and digital filtering is done by using numerical optimization on simplified models guided by analytic results from prior work [^22][^24]. However we can observe some agreement with this simplified model and the performance achieved in other works.}

# 8 Foreground Calibration for the $\Delta \Sigma$SAR

{{< figure src="/images/tcas2017/cal_tran.svg" title="Figure 8: Simplified model of the ADC structure quantization process illustrating how capacitor weight estimation \\(W_{SAR}\\) and actual capacitor weights \\(W_{DAC}\\) propagate to the output.}" width="500" >}}

The foregoing analysis suggests that the resources dedicated to SAR operation should be kept small in order to achieve the peak performance of the oversampling modulator. As a result the DAC linearity may be much worse than the target precision. Ideally before instrumentation the system should perform a calibration procedure that determines the actual capacitor weights \\(\mathbf{W}_{DAC}\\) and recovers any lost accuracy due to mismatch in the digital domain[^26][^25]. Digital calibration techniques are extensively used for SAR converters because they enable more aggressive capacitor sizing without introducing extra analogue complexity that does not benefit from technology scaling[^27]. A simplified model of the quantization process is shown in Fig. 8 where the SAR result is fed back according to the 7 capacitor weights \\(\mathbf{W}_{DAC}\\) to produce a residue that is oversampled by the modulator and decimated by the FIR filter. The mismatch errors arise when the coefficients \\(\mathbf{W}_{SAR}\\) do not correctly calculate the exact charge offset by the capacitors (i.e. $\mathbf{W}_{DAC} \neq \mathbf{W}_{SAR}$). The structural advantage here is that all mismatch induced errors are accurately evaluated by the oversampling loop which can operate with extra noise shaping during calibration without needing a more precise reference ADC. First note that the DNL errors due to DAC mismatch are only observed upon changes in the SAR codes. Secondly the single bit \\(\Delta\Sigma\\) modulator can present significantly better linearity without calibration if SAR codes remain unchanged. Moreover if the weights are correctly estimated we should expect no discontinuities in the DNL characteristic for slowly varying inputs. The proposed calibration method takes advantage of these observations by correlating the first order difference of the ADC output and the SAR codes to find the correct coefficients for \\(\mathbf{W}_{SAR}\\). In addition by using a triangular test signal to perform calibration this procedure does not need full precision multipliers. This is because the triangular waveform distributes the occurrences of each SAR code evenly when at least one sample is taken per SAR code. Therefore the number of toggles on each SAR bit is exactly distributed as powers of two. Now if each SAR coefficient is adjusted when the respective SAR bit toggles then the rate of adjustment for each capacitor weight will be uniform if the adjustments are proportionally scaled by powers of two.}

$$  \mathbf{W}_{SAR}[n+1] = \mathbf{W}_{SAR}[n] + \boldsymbol{\alpha} \underbrace{ sign(\dot{Q_{out}}[n]   \dot{\mathbf{Q}_{SAR}}[n])}_{\text{ternary result (+1/0/-1) } } $$

Eq. 11 introduces the proposed method for iteratively updating \\(\mathbf{W}_{SAR}\\) for the n\textsuperscript{th} sample using \\(\alpha\\) as fixed adjustment factor. \\(\dot{Q_{out}}\\) is the first order difference of the quantized output which is a function of the SAR \\(Q_{SAR}\\) and modulator \\(Q_{\Sigma\Delta}\\) outputs. The exact relation is expressed in Eq. 12. No multiplication is required here because whether a SAR bit has toggled is strictly Boolean and represented by \\(\dot{\mathbf{Q}_{SAR}}[n]\\). This leads to a ternary result with respect to the adjustment rule for incrementing or decrementing the estimated weights that can be implemented using 7 up/down counters of varying depth. In this case the MSB counter has a logical depth of 16 bits while the LSB uses 22 bits.}

$$  Q_{out}[n] = \mathbf{Q}_{SAR}[n] \cdot \mathbf{W}_{SAR}[n] + 2^{-N} \mathbf{Q}_{\Sigma\Delta} \cdot\mathbf{W}_{FIR} $$

If we presume our \\(\Delta\Sigma\\) converter has ideal performance then $2^{-N} \mathbf{Q}_{\Sigma\Delta} \cdot\mathbf{W}_{FIR} = V_{IN}[n] - \mathbf{W}_{DAC}[n]$ which leads to \\(\dot{Q_{out}}\\) as:}

$$  \dot{Q_{out}}[n] = \dot{V_{IN}[n]} + \dot{\mathbf{W}_{SAR}[n]} - \dot{\mathbf{W}_{DAC}[n]}   $$

Eq. 13 reveals that during calibration the output will consist of two components. The first is due to the input as the ramp's rate of change \\(\dot{V_{IN}}\\) that is either increasing or decreasing. The second term results from an incorrect weight estimate on whichever SAR bit changed.} In fact depending on the sign of this error we know if the estimated weight needs to be larger or smaller. In essence Eq. 11 uniformly averages over all DNL errors to approach the correct weights.

# 9 Circuit Implementation

Using the foregoing results, the presented implementation targets a 12 bit resolution using \\(N=6\\) & \\(M=6\\) which should lie just on the inflection point of estimated area requirement curve. In particular we will present the configuration for a fully differential sensor array using analogue and digital supplies at 1.2 V and a commercially available 6-Metal \cmostech technology (AMS/IBM C18A6/7SF).}

## 10 Loop Filter

The loop filter topology used here is a second order feed forward architecture that is used extensively in CT modulators due to its reduced complexity and low distortion[^29][^28]. This particular structure reduces the number of summation nodes and digital feedback elements to minimise power consumption. The signal and noise transfer functions due the loop filter \\(H(s)=2^N (s^2+2 \omega_{bw} s)/\omega^2_{bw}\\) and the feedback factor $f\approx 2^{-N}$ are summarised in Eq. 14 & 15 where \\(\omega_{bw}\\) is the filter bandwidth in radians. The feedback \\(f\\) is determined by evaluating the capacitive coupling from \\(C_{\Delta\Sigma}\\) onto \\(V_{DAC}\\). Since \\(f\\) is quite small there is an apparent gain in the STF but not in the NTF. This gain is provided by increasing the bandwidth of the first stage by \\(2^{N}\\) which substantially diminishes the input referred noise from the second integrator and comparator.} Then using the requirements from Sec. 5 will allow the capacitors to be specified for this implementation as $f_{smp} (N+DC+2)/2=4V_{R} I_{B1}/(\eta U_{T}  2^{N}  C_{L1})=2V_{R} I_{B2}/(\eta U_{T}  C_{L2})$.}

$$  NTF(s) = \frac{s^2}{s^2 + 2 \omega_{bw} s + \omega^2_{bw}} $$

$$  STF(s) = 2^{N}\frac{2 \omega_{bw} s + \omega^2_{bw}}{s^2 + 2 \omega_{bw} s + \omega^2_{bw}} $$

{{< figure src="/images/tcas2017/sch_lf.svg" title="Figure 9: Schematic level implementation of the switched loop filter using noise efficient complementary transconductors and a current mode summation circuit." width="500" >}}

The transistor level implementation is shown in Fig. 9 where the switches \\(S_{\Delta\Sigma}\\) allow the filter to change its operation. The first stage uses a fully differential complementary or inverter-based transconductor that can tolerate small variations in input common mode fluctuation by \\(\pm\\)100 mV and this specific configuration exhibits an \\(NEF\approx1.6\\). The sizing of this complementary pair requires some attention regarding the capacitive loading on \\(V_{DAC}\\) due to the gate to drain capacitance of the transistors. In fact \\(C_{u}\\) needs to be considerably larger than this parasitic such that the open loop gain of the first integrator is not reduced and thereby diminishing filter performance.} The circuit is segmented into three sections; two analogue integrators and one summation stage. The first integrator will switch between resistive and capacitive loads. This stage will have the most demanding bandwidth requirement when providing pre-amplification during SAR quantization. Both integration capacitors are reset outside of the $\Delta \Sigma$ phase and the last two stages should achieve -40 dB HD<sub>3<sub> for a \\(\pm\\)100 mV input signal which is derived from simulations [^24]. The common mode feedback on the two integrators uses linear mode devices that reference \\(V_{DD}/2\\). These transistors can be quite large and introduce considerable parasitics because of the large current dissipated in the first stage. To avoid a reduction in bandwidth, a sub-set of these gates are connected to the loading capacitor \\(C_{L1}\\) that is switched out during SAR conversion which retains the steady state common mode voltage.} The 1-bit quantization is realized using a dynamic latch where offset associated concerns should follow conventional wisdom for accurate SAR conversion. The diode connected load in the summing stage places the input common mode of the comparator close to \\(V_{DD}\\). This improves both the bandwidth and noise performance of the latch[^30].}

## 11 Capacitive DAC

A 7-bit fully differential binary weighted capacitive DAC is used to perform the SAR quantization. The single ended structure is shown in Fig. 10. The voltage scaling on the last conversion cycle reduces the number of capacitors needed and takes advantage of the reduced reference sensitivity for the last SAR conversion. Because calibration is performed with respect to \\(C_{\Delta\Sigma}\\) that references \\(V_{R}\\) the mismatch in the last SAR coefficient will also accommodate the mismatch in voltage reference.} The array is realized by precision top metal-on-metal capacitor devices which utilize M5-M6. A M4 \\(V_{CM}\\) shield is introduced to isolate this array from active analogue and digital circuitry placed below. While bottom plate sampling diminishes the effect of parasitics on \\(V_{DAC}\\), the split capacitor needs tuning according to the extracted parasitics on the LSB section particularly with respect to the shielding layer. The unit capacitor is 71 fF with 6\\(\times\\)6 \mmu m\\(^2\\) dimensions yielding 0.2% deviation of capacitor mismatch for a \\(3\sigma\\) confidence interval. This should allow a precision of 9 ENOB without calibration [^31] and will utilise all the top metal area needed for the sub-blocks placed below.

{{< figure src="/images/tcas2017/sch_dac.svg" title="Figure 10: Single ended equivalent of the 7-bit split-capacitive SAR DAC using voltage scaling on the smallest weight. " width="500" >}}

During sampling each input will be loaded by a total of 768 fF for an equivalent 52 \mmu V<sub>rms<sub> sampling noise. This should indicate that the upper bound of maximum signal to noise and distortion ratio (SNDR) for this DAC is 78 dB. Also note that the INL characteristic of the SAR and comparator noise will inevitably lead to additional sources of quantization error which implies the \\(\Delta\Sigma\\) input range will correspondingly increase from its expected value. Moreover resolving a sampled input with a \\(\Delta\Sigma\\) modulator can lead to increased distortion due to idle tones. This is why the modulator should be designed such that signals that are -3 dB of the maximum \\(\Delta\Sigma\\) input range can still be adequately resolved. Fortunately comparing single bit modulators reveals second order feed-forward structures are substantially more capable of processing signals close to the full range input due to improved stability dynamics [^16]. This means the DAC mismatch requirements are less stringent and will not need a sub-binary weighting or additional calibration capacitors to minimize the sources of excess residue.} The simpler binary weighted structure will allow good baseline matching for the unit capacitors with the minimum number of elements in the DAC. Moreover introducing the split capacitor in addition to the \\(V_{cm}\\) switching method dramatically reduces the total switching energy to the extent that it is dominated by the oversampling phase. Particularly when multiple data converters are operated in parallel the excessive capacitive switching raises a concern for high frequency supply noise of the reference voltage that is outside the LDO bandwidth. The anti-aliasing provided by the loop filter will partly reject this component as a result of opting for a CT implementation. The \\(\Delta\Sigma\\) feedback will dissipate at most 77 fC every cycle which needs to be partly absorbed by decoupling capacitors local to the ADC. High density MOS capacitors are therefore introduced to load the reference voltage by 20 pF per ADC. The reduced switching noise should represent a clear advantage over switched capacitor modulators. An improvement over the conventional SAR may only be expected when calibration overhead is unavoidable because the sampling noise constraint makes energy dissipation in SAR switching mostly indifferent to its resolution.

## 12 FIR Filtering

Decimation of the \\(\Delta\Sigma\\) bit stream of incremental topologies finds the application of FIR filters particularly suitable. This is in part because resetting the integrators for each sample and discards residual components from the previous conversion and the corresponding group delay requirement can limit the IIR filter design.} Moreover sharing FIR filter coefficients with multiple ADCs reduces the hardware requirements to a shared lookup table with individual accumulators for each modulator. Using an \\(OSR\\) of 24 implies \\(N+DC+1=31\\) additions are needed per sample where a second order CIC filter would need at least \\(N+2DC+3=57\\) additions per sample for a full evaluation and four times the number of registers[^32]. From Sec. \ref{sec:model} we know that the register depth \\(R_{D}\\) should be 16 bits while the FIR coefficient precision needs to be 8 bits.} The application of a symmetric FIR window also assists with a number of circuit considerations for rejecting noisy aggressors near \\(f_{bw}\\)[^8]. Supply noise is a typical culprit but it may be less obvious that the FIR also reduces the sensitivity due to the second integrator's offset when the quantization mode switched.} Hanning or raised cosine FIR windows are known to provide exceptional aliasing particularly when applied to sample limited \\(\Delta\Sigma\\) decimation [^33]. Using a general family of raised cosine windows[^34] a configuration is proposed here that matches the noise shaping of the loop filter order (\\(L\\)) with that of the FIR side-lobe roll-off by defining its coefficients as:}

$$  FIR[n] = cos^{K}\left(\frac{\pi   n}{OSR+1}-\frac{\pi}{2}\right) $$

The factor \\(K\\) in Eq. 16 determines the spectral characteristics of the filter similar to that of the kaiser windows. The rapid side-lobe roll-off is related to \\(K\\) as \\(30K \\)dB/Dec with the first zero location at \\(\pi(1+K/2) f_{smp}\\). Because the quantization noise is shaped in relation to \\(L\\) at \\(20L \\)dB/Dec[^5], \\(K\\) can be defined as \\(K=2/3 L\\). This leads to a near uniform quantization noise profile with a reduced transition band from better pole placement. The \\(K\\)-factor dependent frequency characteristics are shown in Fig. 11 for an \\(OSR=16\\) applied to the output of a second order modulator. Note that when \\(K=2\\) the FIR is equivalent to that of a Hanning window. The overall system transfer function \\(Sys(z)\\) can be analysed in the z-domain using a bilinear transform of the loop filter \\(H(s)\\) and convolving it with that of the FIR response. To see how well decimation is achieved we compare the decimation performance to that of an ideal filter .}

{{< figure src="/images/tcas2017/QFIR.svg" title="Figure 11: Overall noise shaping profile of the modulator and FIR in cascade for \\(K=2\\) and \\(K=1.33\\)." width="500" >}}

$$  S_Q^2 = \frac{ 2\pi^{2L} }{3(2L+1)(OSR)^{2L+1} } $$

Eq. 17 introduces the expected in-band quantization noise power \\(S_Q^2\\) from analytic relations[^35] which assume an ideal brick-wall filter with a cut off frequency at \\(f_{smp}/2\\) that is not limited in any way.} Similarly integrating over the resulting power densities in \\(Sys(z)\\) will indicate the expected quantization noise from the proposed configuration. Comparing these two results will indicate how effectively the quantization noise is rejected by the FIR filter.} The noise excess is shown in Fig. 12 as a function of OSR and filter order. This shows that using the proposed window results in loss smaller than 0.5 bits.} Also notice that we do not pay special attention to how the \\(\Delta\Sigma\\) quantization noise folds onto the signal band. After the signal is convolved by the SAR quantization process the residue no longer shares the same structure as the input signal and therefore better in band decimation performance will not lead to better in band SNR.}

{{< figure src="/images/tcas2017/OBT.svg" title="Figure 12: Quantization noise suppression based on numerical simulations and Eq. 17 and the respective precision loss for varying \\(OSR\\)." width="500" >}}

# 13 Measured Results

{{< figure src="/images/tcas2017/chip_micro.svg" title="Figure 13: Microphotograph of the 64 channel neural recording system showing two 32 channel macros used in parallel with integrated power management and digital processing.}" width="500" >}}

{{< figure src="/images/tcas2017/fab_exhibit.svg" title="Figure 14: Fabricated \\(\Delta\Sigma\\)SAR prototype showing a) an isolated test ADC structure used for characterization b) a close up micrograph showing the capacitive DAC and top metal c) the ADC layout with annotated sub-blocks. The SAR capacitors are highlighted in blue and numbered in term of which SAR bit they represent. The analogue MOS and MIM capacitors are highlighted in red showing the filter capacitors L1 & L2 and the decoupling capacitors.}" width="500" >}}

A chip micrograph is shown in Fig. 13 depicting the 64 channel instrumentation system with die size of 6.2 mm<sup>2<sup>. This configuration uses two macros each of which integrates eight ADCs together with the DSP in a tiled fashion to post-process the recordings from 32 instrumentation amplifiers. In fact the architecture may be scaled to accommodate more channels by virtue of the pipelined architecture that distributes the processing capacity. The measured results presented here are taken from an isolated test structure that allows detailed characterization without overhead from the whole system.} The physical implementation of the \\(\Delta\Sigma\\)SAR sub-block is shown in Fig. 14 which is 96\mmu m\\(\times\\) 164\mmu m in size. Because the DSP is assisted by a specialized execution unit that also performs neural signal decomposition only the digital accumulator is included in this figure. The active components inside the modulator contribute to a small portion to the overall system. Instead the most demanding layout consideration is with regard to the switches driving the capacitive DAC. Even though the capacitance is not too large, the switch resistance in \\(\Delta\Sigma\\) mode can introduce a pole leading to excess loop delay that could result in performance degradation [^36].

{{< figure src="/images/tcas2017/INL2.svg" title="Figure 15: Measured INL of the ADC before and after calibration with 2.4 V differential amplitude. " width="500" >}}


{{< figure src="/images/tcas2017/CALC.svg" title="Figure 16: Convergence of DNL rms and peak to peak values during calibration subject to a 90 Hz triangular waveform." width="500" >}}

Initial ADC characterization used a low-frequency 180 Hz tone at half to the full input range where the comparator bit stream was directly acquired off-chip for post-processing. This allowed the proposed calibration mechanism to be compared with more robust methods. In fact when using more elaborate numerical optimization methods to adjust \\(\mathbf{W}_{SAR}\\) the THD only showed 2 dB improvement although convergence is typically much faster. Both testing and calibration waveforms were generated off-chip using an Agilent 33120a with additional bandpass filtering. The measured INL characteristics are shown in Fig. 15. The calibration method decreases the SAR nonlinearity by a factor of 10. As shown in Fig. 16 the main drawback of this method is that in order to reject noisy perturbations the \\(\alpha\\) rate must be small amounting to slow convergence on the order of 10<sup>6<sup> quantization cycles or around 10 seconds. The DAC used for generating the ramp signal will need to be more accurate than the ADC precision to allow correct calibration. On the other hand instead of using a more powerful centralized DSP unit to perform tuning, this system allows all channels to calibrate simultaneously resulting in a speed up for multichannel systems that can share a single high resolution DAC.} The discontinuities visible in this trend result from the fitting method used to calculate DNL as a function of time which is not very consistent.

{{< figure src="/images/tcas2017/Spectrum2.svg" title="Figure 17: Measured ADC performance showing the spectral characteristics of a) SAR residue at the output of the \\(\Delta\Sigma\\) and b) the full precision output which has a SNDR of 66.8 dB. This recording was taken using a 2.35 Vpp 95 kHz input tone sampled at 200 kHz .}" width="500" >}}

{{< figure src="/images/tcas2017/QRES.svg" title="Figure 18: FIR output over time due to a 1.2 Vpp 180  Hz input tone showing the quantized residue after SAR conversion. " width="500" >}}

{{< figure src="/images/tcas2017/MMO.svg" title="Figure 19: Measured quantization noise spectrum of the second order \\(\Delta\Sigma\\) modulator that is clocked at 7 MHz averaged over 10<sup>3<sup> conversions with an OSR of 24.}" width="500" >}}

Fig. 17 shows the spectral characteristics of the ADC after the capacitor weights have been estimated with 16 bit precision together with the SAR residue that can be obtained by only taking the decimated modulator output. This illustrates that SAR residue has its spectral power distributed over the entire bandwidth at multiple tones. This wideband quantization 'noise' will in effect present dithering on modulator's nonlinearity before appearing at the output.} Fig. 18 shows the signal resolved by the modulator as a function of time. Interestingly the polarity in residue will directly correspond to the polarity of the sampled input signal because swapping the reference voltage on the capacitive DAC will imply a successive approximation while maintaining correspondingly positive or negative residues. Then by performing a Fourier transform on the measured modulator output for each conversion separately we can evaluate the noise shaping characteristic of the loop filter. This result is shown in Fig. 19 which follows closely to the expected second order noise shaping.}

{{< figure src="/images/tcas2017/SDOS.svg" title="Figure 20: Measured \\(FOM_{S}\\) dependency for varying OSRs but keeping a 7 MHz system clock frequency for a 10\\( kHz\\) 2.4 Vpp input tone." width="500" >}}

{{< figure src="/images/tcas2017/FDP.svg" title="Figure 21: Measured SNDR dependency for varying input frequency for a 2.35 Vpp input tone." width="500" >}}

Table 1: Comparison of State-of-The-Art ADC specifications
|		**Parameter** | Unit	| [^18] | [^23] | [^7]	| [^13] | [^38] | [^39] | [^40] | [^41]	| [^6] | **This Work** |
|----|----|----|----|----|----|----|----|----|----|----|----|
|		**Year**  |     | 2007  | 2014  | 2015 | 2015  | 2016  | 2016  | 2016  | 2016  | 2017  | **2017** |
|		**Tech.** | [nm]| 180   | 65    | 180  | 65    | 110   | 65    | 180   | 55    | 180   | **180** |
|		**Topology**  |     | SAR   | NSSAR | IADC | NSSAR | SAR   | SAR   | IADC  | NSSAR | IADC  | \textbf{(\Delta\Sigma)SAR} |
|		**Supply-V**  | [V] | 1     | 0.8   | 1.8  | 0.8   | 0.9   | 0.4 | 1.8 | 1.2 | 1.5 | **1.2** |
|		**Supply-I**  | [\mmu A] | 25   | 1.7  | 19  | 151  | 27   | 1.8  | 16.4 | 13.1  | 23   | **4.3** |
|		**Speed**     | [S/s] | 100 k  | 32 k   | 8 k   | 6.25 M | 1 M    | 1 k    | 313 k  | 4 k    | 2 k    | **200 k ** |
|		**ENOB**  | [bits] | 10.55 | 12.4  | 12.3 | 9.35  | 11.0}  | 7.81  | 9.3   | 15.7  | 16.1  | **10.8**} |
|		**SNDR**  | [dB] | 65    | 76    | 75   | 58    | 67    | 49    | 57    | 96    | 97    | **67**} |
|		**Area**  | [mm²] | 0.63  | 0.18  | 0.33 | 0.012 | 0.097 | 0.013 | 0.002 | 0.072 | 0.5   | **0.016 ** |
|		**FOMW**  | [fJ/conv] | 165   | 8     | 862  | 14.8  | 11.7  | 3.19  | 151   | 73.8  | 320   | **14**} |
|		**FOMS**  | [dB]  | 156   | 177   | 159  | 163   | 170   | 137   | 154   | 180   | 175   | **170**} |


In Table 1 the performance is summarized and state-of-the-art noise shaping ADC structures are compared. This work achieves exceptional compactness for the 12 bit target resolution particularly in relation to the conversion efficiency [^37]}. The measured power dissipation is about 5 \mmu W of which simulations indicate 40% is dissipated in the loop filter and 23% in capacitive switching. Note that power dissipation from the look up table is not included in this figure. Fig. 20 presents the measured SNDR and \\(FOM_{W}\\) for varying oversampling ratios. During calibration the OSR was doubled to gain 3 dB in precision while the typical operation uses an \\(OSR\\) of 24.} The total conversion uses an additional 11 cycles for SAR and sampling phases to give the resulting 200 kS/s speed for a 7 MHz system clock. We also show the measured SNDR for varying input frequencies in Fig. 21. This shows that maximum precision is maintained for signals below 20 kHz but also shows some degradation at frequencies near the maximum input bandwidth. The main experimental difficulty resulting from the proposed configuration is that the filter characteristics are closely tied to the reference voltage in a practical setting. On occasion it is useful to give additional voltage overhead for aggressive digital and analogue systems to accommodate process voltage and temperature variance. However in this case the biasing circuit will need extra tuning parameters to keep the modulator's linearity consistent while adjusting the reference voltage. Multi channel systems can generally accommodate complex tuning for all ADCs to eliminate wafer/process level variations without substantial overhead since this functionality is already needed by instrumentation circuits to perform precise filtering. The power management block in Fig. 13 provides 12 bit digital trimming on the ADC reference voltages and bias currents such that most of the off-set can be accommodated although this is performed externally on the test structure.}


# 14 Conclusion

A novel 12-bit analogue-to-digital data converter has been proposed that uses SAR & \\(\Sigma\Delta\\) quantization schemes to realize a compact and ultra low power data converter for a 64 channel neural sensor system. Using an efficient Gm-C filter, compact 7 bit binary DAC, and optimized FIR decimation this work aims to eliminate the circuit complexity from DEM and increase power efficiency which is highly desirable for biomedical sensors.} A prototype fabricated in \cmostech demonstrates 10.8 ENOB precision at the nyquist frequency with a state-of-the-art 0.016 mm² silicon footprint and is capable of resolving full scale signals at 200 kS/s.} The proposed techniques are appropriate for a variety of sampling frequencies making this configuration applicable to numerous other applications that require aggressive ADC miniaturization. In addition a calibration technique suitable for large sensor arrays is presented that takes advantage of the two step quantization scheme to calibrate multiple ADCs simultaneously.}

# 15 Acknowledgement

The authors would like to thank Nicolas Moser and the reviewers for helpful comments and assistance with improving this manuscript.

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