---
title: "Continuous-time micropower interface for neural recording applications"
date: 2015-10-16T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
  - publication
  - instrumentation
  - CMOS
  - biomedical
---

Marios Elia, Lieuwe B. Leene, Timothy G. Constandinou

Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK

Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK

# 1 Abstract

This paper presents a novel amplifier architecture intended for low power neural recording applications. By using continuous-time signal representation, the proposed topology predominantly leverages digital circuits and is thus well-suited for scaling to new technologies.
This includes digital integration providing direct quantization of the input voltage and superior filtering. Schematic-level simulations demonstrated the amplifier's bandwidth to be 6 kHz, with highly linear full dynamic range output. Achieving a static power consumption of 1.145 μW from a 0.5V supply voltage with an input referred thermal noise of 7.7 μVrms.   

# 2 Introduction

Recent advancements in neuroscience have enabled simultaneous activity monitoring from multiple neurons, creating the need for fully implantable multi-neuron recording. Next-generation implanted systems must be able to simultaneously monitor between 100 and 1000 neurons [^1]. With neural signals being as small as 30 μV, a dedicated low-noise amplifier (LNA) is required for each electrode. However, implantable devices have restricted power budget so that tissue cells are not destroyed by the generated heat. It is therefore suggested that front-end amplifiers should dissipate no more than 2 μW. Thus, a trade-off between noise performance and power consumption emerges as thermal noise is directly related to bias current.  

Utilising a current-mirror OTA topology with weakly-inverted PMOS inputs, authors of [^1] where able to achieve an input referred noise of 2.2 μV integrated over 0.25 Hz - 7 kHz. However, the amplifier dissipated 80 μW of power, potentially exceeding thermal-dissipation safe limits if scaling to hundreds of channels.

Extracellularly recorded neural action potentials have amplitudes in the range of 30 μV - 500 μV and frequency content in 100 Hz- 7kHz spectrum. On the other hand, local-field potentials can be as large as 5mV with energy present in sub-Hz frequencies, putting a system's dynamic range (DR) to the test. Moreover, electrodes demonstrate DC offsets up to 2 V [^1], requiring the integration of a sub-Hz high-pass filter.  The design is further challenged by technological scaling; shrinking devices lead to reduced transistor impedances requiring higher power to maintain intrinsic gain and linearity.  

Reduced DC gain can be effectively mitigated by the use of voltage controlled oscillator (VCO) based integrators [^3], [^4]. Furthermore, VCO-based topologies preserve signal information in the time domain allowing for very large dynamic range (DR). Similarly, authors of [^5] propose a switched-mode Op-Amp with a class-D output stage. The two-level operation renders the system inherently more linear, alleviating the linearity-power consumption trade-off. It is therefore beneficial to devise architectures based on these digital circuits, suited to fabrication using digitally-oriented CMOS technology. This is further motivated by the fact that biomedical instrumentation applications make extensive use of Digital-Signal Processing (DSP).

This paper presents the implementation of a low-power, VCO-based amplifier for neural recording applications. The system encodes information in time domain by utilising differential oscillators. A Phase-Frequency Detector (PFD) detects relative phase/frequency variations and generates high-frequency UP/DN pulses. An up/down binary counter integrates the PFD output and tracks the quantization of the signal; the binary value is now ready for digital processing.
The remainder of the paper is organised as follows. Section II introduces and analyses the proposed system architecture with circuit implementation presented in section III. Section IV demonstrates simulated results followed by conclusions in Section V.    

# 3 Concept and System Architecture

The proposed amplifier architecture is shown in Fig 1. A fully differential Gm-cell integrates the residue signal, on the Miller-equivalent capacitance, and drives the VCO blocks.

A digitally registered integrator rejects high frequency harmonics and produces the system's quantized output. This integrator is implemented with a 9-bit binary up/down counter that is driven by events generated by the PFD. The asynchronous behaviour prevents down modulation of coherent noise in the system and quantization from producing strong tones in band. Finally all active integration nodes feedback to through a charge-scaling capacitive array. Utilizing multi-pathing of signal components, this topology attempts to reject out of band noise in the GM-VCO signal loop such that the band limited counter output contains a clean signal band without needing in large band limiting capacitors.

## 4 Amplifier Compensation

A pole is contributed to the transfer function, by each of the following stages; Gm-cell, VCO and counter integrator. Feed-forward compensation is achieved by capacitively coupling the PFD output to the charge-scaling array output with gain  A<sub>v<sub>. As such, a zero is introduced in the transfer function, cancelling the effect of the counter-contributed pole. The amplifier is then approximated by a two-pole system allowing for Miller compensation. The Miller equivalent of C<sub>M<sub> places a DC pole at the output of the Gm-cell and pushes the VCO pole to higher frequencies. Laplace-domain analysis yields the system's transfer function; Eq. 1.

$$ H(s) = Gm\frac{1+\frac{s}{\omega_{z}}}{s(1+\frac{s}{\omega_{p2}})} $$

$$ \omega_z = A_{v}K_{INT},\ \omega_{p1} = DC $$

$$ \omega_{p2} = \frac{1+C_{M}A_{v}K_{VCO}K_{PFD}K_{INT}}{C_{M}K_{VCO}K_{PFD}} $$

The amplifier has sufficient phase margin (PM) if \\(\omega\\)<sup>p2<sup> and \\(\omega\\)<sub>z<sub> are very close in the frequency response, cancelling each other out. This will be satisfied if C<sub>M<sub>A<sub>v<sub>K<sub>VCO<sub>K<sub>PFD<sub>K<sub>INT<sub> >> 1, reducing \\(\omega\\)\textsubscript{p2}  to A<sub>v<sub>K<sub>INT<sub>. The transfer function can then be approximated to \\(\frac{Gm}{s}\\) suggesting a single pole system and ideal integrator behaviour near DC.

{{< figure src="/images/iscas2016/system.svg" title="Figure 2: System Architecture with unit capacitor as 4 fF." width="500" >}}

It should be noted that K<sub>INT<sub> is input-dependent, in other words the integrator's gain dynamically changes when the amplifier is slewing. Nonetheless, both \\(\omega\\)\textsubscript{p2} and \\(\omega\\)<sub>z<sub> are a function of K<sub>INT<sub> thus, the system's overall transfer function is not affected.

## 5 Topological Advantages

The amplifier's digital nature offers a number of benefits compared to the analogue equivalent. As technology scales, propagation delays and power consumption are also expected to scale down offering increased performance. Moreover, reduced input capacitance yields higher input impedance. This is particularly useful in biomedical LNAs, as tissue built-up increases the electrode's impedance with time [^7].

Another key advantage, is that the binary counter continuously quantizes the input signal. As such the system's output is compatible with arbitrary & event-based processing rates. The circuit contains a minimal number of analogue nodes; the input node and the Gm-cell's output node. External and internal feedback ensure negligible voltage swing on all nodes. Resulting in minimal linearity restrictions by the power rails allowing the use of very low supply voltage.

Signal quantisation is performed in closed-loop. As such, quantization noise and non-linearities, induced by the counter-DAC combination, are shaped and pushed to higher frequencies. With distortion being suppressed by the internal feedback, aggressive reduction of the capacitors used in the charge-scaling array is allowed.

Another mechanism that improves noise performance results from the feed-forward stage Av. As it bypasses the counter circuit, any high frequency noise, generated by the Gm-cell and VCO circuits, will bypass the counter and propagate through the feedback loop. Thus, only low frequency noise components will reach the system's digitised output. As such, it is essential to maintain signal specific counter bandwidth.

# 6 Circuit Implementation

The circuit has been designed and simulated in a 0.18 μm CMOS process provided by AMS (H18A4). A circuit-level analysis of the system blocks follows.

## 7 Gm-cell

The first stage is implemented using a differential pair topology, Fig. 2.

{{< figure src="/images/iscas2016/1.svg" title="Figure 3: Gm-cell" width="500" >}}

For DC signals, devices M1 and M3 behave as diode-connected transistors, providing a well-defined output biasing as well as the high-pass DC off-set rejection cut off at 1 Hz. Noise analysis reveals that thermal noise is inversely proportional to device transconductance. By AC coupling the input signal to both NMOS and PMOS devices, the circuit's transconductance efficiency is significantly boosted. Small-signal analysis yields the circuit's transfer function; Eq. 2.

$$ H(s) = Gm\frac{r_{O}}{1 + sr_{O}C^{eq}_{M}} $$

$$ Gm = g_{m1} + g_{m2},\ r_O = r_{O1}//r_{O2} $$

$$ C^{eq}_{M} = C_{M} \frac{K_{VCO}}{s} K_{PFD} ( \frac{K_{INT}}{s} + \frac{1}{A_{v}} ) $$

Eq. 2 reveals that the finite output impedance of MOSFET devices, pushes the first stage pole to frequencies higher than DC. However, owed to the nearly infinite gain provided by the second stage integrators, the Miller capacitor will appear very large, pushing the pole back to very low frequencies.

## 8 Voltage-Controlled Oscillator

The implemented VCO circuit is shown in Fig. 3. Devices M2 and M3 form an inverter-based ring-oscillator. The oscillator's frequency is a linear function of the current it sinks and it is given by Eq. 3 [^8].

$$ f_{OSC} = \frac{I_{DS}}{N C_{TOT} VDD} $$

N being the number of inverter stages and C<sub>TOT<sub> the total capacitance per inverter stage. Device M1 directly controls the oscillator's frequency by modulating the current available to it. The circuit's gain is then given by

$$ K_{VCO} = 2\pi \frac{g_{m1}}{N C_{TOT} VDD} [radians V^{-1} s^{-1}] $$

{{< figure src="/images/iscas2016/4.svg" title="Figure 4: Voltage-Controlled Oscillator" width="500" >}}

Transistor M4 is biased in the triode region acting as a level shifter. It serves a dual purpose by ensuring correct biasing of device M6 and isolating the oscillator from high frequency noise present on the ground rail.  

## 9 Phase-Frequency Detector

The circuit of the 3-state PFD utilised is shown in Fig. 4(a) [^9]. It is based on True-Single Phase Logic and its operation principle follows. Assuming VCO1 and VCO2 are low, nodes U1 and D1 are pre-charged to VDD via M1. On the rising edge of VCO1,  M5 turns ON, and the dynamic inverter formed by M4 and M6 pull node U2 down causing UP signal to rise. On the rising edge of VCO2, DN signal also rises. M2 and M3 discharge nodes UI and D1 thus UP and DN signals are also pulled down. The circuit has returned to its initial condition [^9]. It should however be noted that to ensure reset of UP/DN signals at equal instances, I<sub>DS2,3<sub> >> I<sub>DS1<sub> must be satisfied.

Maximum output voltage is produced when the two input signals are perfectly out-of-phase; that is, they are 2\\(\pi\\) apart. The circuit's gain is then defined as K<sub>PFD<sub> = 1/2\\(\pi\\).

{{< figure src="/images/iscas2016/pfd_2.svg" title="Figure 5: (a) PFD circuit (b) SIGN bit generation" width="500" >}}

## 10 Counter Driving Circuit

Clock generation is achieved by the circuit in Fig. 5(a). Two edge-detector circuits generate pulses of well-defined width, at every rising edge generated by the VCOs. The pulses propagate through the OR, driving the DFF, to the divide-by-two circuit. Thus, the generated clock's frequency is the average of the two VCOs'.

{{< figure src="/images/iscas2016/clk_circuit.svg" title="Figure 6: (a) CLK circuit generation (b) 2-state to 3-state signal conversion" width="500" >}}

The circuit of Fig. 4(b) illustrates the PFD implementation. DFF1 detects the leading signal and accordingly registers a logic output. DFF2 ensures that the SIGN bit can only change after the clock's rising edge. As such, the SIGN bit is always stable when the counter registers its value, avoiding metastability issues.  

The SIGN bit is also used to convert the 2-state UP/DN outputs to 3-state signals. This is achieved by using the SIGN bit to determine whether the signal oscillates between -1 and 0 or 0 and +1. By increasing the available logic levels, the maximum quantisation noise present on the signals is reduced improving system dynamics. The circuit implementing this function is shown in Fig. 5(b). The 3-state signals are now fed forward to the output node in order to introduce a zero in the transfer function and satisfy the stability requirements mentioned in Section II. %cancelling the effect of the output pole. %State +1 is represented by the binary value 11, zero by 01 and -1 by 00.

## 11 Integrator

The binary counter's building element is a Toggle Flip-Flop and a multiplexer; the multiplexer being controlled by the SIGN bit. Each TFF will toggle or hold its state, depending on the value presented to it by the multiplexer.

The counter's binary value is converted to an analogue signal by a charge-scaling capacitive array. The integrator's transfer function can be derived as follows. Each time the counter increments its value, the output voltage increases by V<sub>DD<sub>/2<sup>N<sup>; N being the number of binary bits. Approximating the output voltage by a ramp, it is given by

$$ V_{out}(t) = \frac{V_{DD}}{2^{N}}t\times u(t)\times f_{OSC} $$

yielding the following transfer function

$$ \frac{\Delta V_{out}}{\Delta\Phi_{in}}(s) = \frac{V_{DD}}{2^N}\times \frac{f_{OSC}}{\Delta\Phi_{in}}\times \frac{1}{s} $$

Eq. 6 suggests that the integrator's transfer function is input dependent as stated in Section II.

# 13 Simulated Results

The design was simulated in Cadence IC 6.1.5 Design Environment, using foundry-supplied PSP models. Owed to the circuit's dynamic time domain behaviour, only transient noise simulations can correctly predict system performance. As such, the provided bode plots were generated by simulating the linearized system transfer function.

{{< figure src="/images/iscas2016/bode.svg" title="Figure 8: Frequency response of linearised model" width="500" >}}

Fig. 6 demonstrates the system's frequency response revealing a closed loop 40dB voltage gain. The system's static current consumption is measured to be 2.29 μA from a 0.5V supply voltage yielding a power dissipation of 1.145 μW. Spectrum analysis of the output for a 2kHz, 5mV peak-to-peak input signal is shown  in Fig. 7. The input referred noise floor of the transconductance state evaluated at 100nV/√Hz with the corner frequency at 1 kHz. High levels of flicker noise can be mitigated with common signal chopping techniques. Table I summarises system performance and compares with a typical analogue design. The used figure-of merit is defined by Eq. 7.  

$$ FoM = v_{ni,RMS}\sqrt{\frac{2I_{TOT}V^2_{DD}}{\pi U_{T} 4KT\times BW}} $$

Table 1: Performance Comparison
| Parameter | This work |[^1]|
|----|----|----|
|Power [μW] | 1.14 | 80 |
|Supply [V] | 0.5 |	±2.5 |
|Bandwidth [Hz] | 1- 6k | 25m-7.2k |
|THD	[%]	| 1.05		| 1	|
|Noise [μVrms] | 7.7 | 2.2|
|Figure of Merit | 2.25 | 20|

# 14 Conclusion

A novel amplifier architecture is proposed, that makes extensive use of digital circuits attempting to overcome the issues resulting from technological scaling. By encoding and processing the information in time-domain, the system's DR is no longer restricted by the power rails. As such the entire system operates from a supply voltage of 0.5V consuming 2.29 μA of current.

The complementary input stage increases the circuit's transconductance efficiency while the capacitive feedback applied to the second stage ensures superior low voltage integration characteristics owed to the feedback mechanics. The output capacitive DAC, artificially increases closed loop gain of the second stage, further relaxing the noise-bandwidth trade-off as both depend on input transconductance. Lastly, the noise shaping on the output guarantees relaxed requirements in supply noise, capacitor matching while retaining linearity under very low supply voltages. Based on an event driven design, utilisation of Continuous-Time DSP could prove especially advantageous for this particular system [^6].

# Refernces:

[^1]: R.R. Harrison and C.Charles, ''A Low-Power Low-Noise CMOS Amplifier for  Neural Recording Applications,'' IEEE JSSC, vol.38, no.6, pp.  958--965, 2003.
[^2]: S.I. Chang and E.Yoon, ''A 1$\mu$W 85nV/√Hz pseudo open-loop preamplifier  with programmable band-pass filter for neural interface system,''  Proc. IEEE EMBS Conf., pp. 1631--1634, 2009.
[^3]: B.Drost, M.Talegaonkar, and S.Member, ''Analog Filter Design Using Ring  Oscillator Integrators,'' IEEE JSSC, vol.47, no.12, pp. 3120--3129,  2012.
[^4]: C.-w. Hsu and P.R. Kinget, ''A 40MHz 4th-order Active-UGB-RC Filter using  VCO-Based Amplifiers with Zero Compensation,'' pp. 359--362, 2014.
[^5]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-Mode Operational  Amplifiers and Their Application to Continuous-Time Filters in Nanoscale  CMOS,'' IEEE JSSC, vol.49, no.12, pp. 2758--2772, 2014.
[^6]: Y.Tsividis, ''Continuous-time digital signal processing,'' Electronics  Letters, vol.39, 2003.
[^7]: J.Xu, T.Wu, W.Liu, and Z.Yang, ''A frequency shaping neural recorder with  3 pF input capacitance and 11 plus 4.5 bits dynamic range,'' IEEE  BIOCAS, vol.8, no.4, pp. 510--527, 2014.
[^8]: R.J. Baker, CMOS Circuit Design, Layout and Simulation, 3rded.\hskip  1em plus 0.5em minus 0.4em
elax JOHN WILEY & SONS, 2010.
[^9]: B.Lee and L.Siek, ''A CMOS Phase Frequency Detector for Charge Pump  Phase-Locked Loop,'' Electronic Engineering, pp. 5--8, 1999.
