---
title: "Brain machine interfaces: Neural Recording Front End Design"
date: 2016-08-08T15:26:46+01:00
draft: false
toc: true
math: true
type: posts
tags:
  - chapter
  - thesis
  - CMOS
  - biomedical
---

Lieuwe B. Leene, Yan Liu, Timothy G. Constandinou

Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK

Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK

This chapter focuses on the multitude of questions associated with the mixed signal design for multi channel integrated neural recording systems. As a result, a significant section will be directed at developing an abstract understanding of how design parameters influence the various design challenges. This discussion will clarify the key limitations for these systems and propose how they can be mitigated or efficiently designed for. In the scope of integrating a large number of recording channels together, clearly understanding how each resource trades for another is crucial for optimizing a complex system. Optimization methods found in the literature typically assume a certain configuration which limits to what extent improvements can be made [^109]. However here we specifically identify abstractions that allow us to consider the impact of different topologies and filter structures simultaneously. This should enable a much boarder sense of optimization that will reflect in the improved performance characteristics demonstrated here.

We will focus on elaborately evaluating the dominant resource requirements with respect to noise, mismatch, quantization, and functional aspects for signal conditioning together that is mostly implementation independent. In addition we propose several circuit implementations based on this analysis that present highly efficient and compact instrumentation. The corresponding abstractions that we use attempt to realize clarity respect to underlying dependencies. This should allow better analytic models that make the limiting factors appear obvious and reveal means to circumvent specific constraints with alternative techniques. For example we may be interested to know when it is worthwhile to put certain functions in the digital domain in terms of the CMOS technology parameters. Approaching the ideal instrumentation structure in such a scenario remains highly desirable for constrained applications. Thus conforming to the technology parameters could reveal that conventional methods do not deliver the most effective solution.

The chapter is organized as follows; Section 17 describes the general problem statement related to the analogue front end which is followed by the associated amplifier design considerations in Section 19. The method for improving the analogue to digital conversion is outlined in Section \ref{ch:T1_converter}. These results are then collected in Section \ref{ch:T1_model} to evaluate the impact of system level parameters as a function of resource requirements.

# 17 Architecture for Neural instrumentation

The analogue dimension of neural recording system can be broken down into two objectives for signal conditioning that will maximize the performance of the proceeding digital signal processing. The first is related to getting adequate signal quantization by amplifying the signals to full input range of the data converter without corrupting the signal of interest. The second objective is performing some kind of filtering that removes noisy or irrelevant components in the recording and only captures the relevant signals of interest.

{{< figure src="technical_1/T1_SIG_Spectrum.pdf" title="Figure 20: Illustration of the spectral power density characteristic for a typical neural recording with the associated frequency bins. " width="500" >}}


As depicted in Figure 20, the input spectrum of a typical \text{in-vivo} electrode recording can be classified using a few frequency bands. The energy from extracellular spiking activity is primarily concentrated around \\(300 Hz\\) to \\(6 kHz\\) and is characteristically intermittent resulting in a distinct difference between the average and instantaneous spectral power [^110]. This characteristic is also present in the LFP band to a lesser extent. From an electrical standpoint the design constraints are derived from the tolerated noise levels in each frequency band to maintain a proper signal to noise ratio. As a consequence it important to specify the signal to noise ratio in terms of noise density opposed to integrated noise figures as digital processing accuracy is not limited by the later term. Here we should also note that the electrode spectral noise power $N^2_{electrode} = 4 kT R_{en} \Delta f$ depends on the resistive component of the electrode impedance. This is typically matched by that of the amplifier noise characteristic \\(N_{amp}\\) so that no excess power is wasted and is expressed in terms of the electrode resistance \\(R_{en}\\), Boltzmann energy \\(kT\\), and the frequencies of interest $\Delta f$.


## 18 Instrumentation Requirements



This kind of electrical sensing can be broken down in the a number of system blocks each of which perform an essential operation to this process. These are shown in Figure 21 and consist of an amplifier, a filter, a sampler, and a quantizer. Occasionally one circuit can combine multiple of these operations together depending on the construction. Table 3 presents the overall performance requirements that should be demonstrated when these components are integrated together. These are also the specifications that we will target as the design is being considered in the following discussion. The reasoning behind these specific requirements are mainly related to conventional signal acquisition given the bandwidth and noise requirements. Moreover these seem to be sufficient for most decoding/characterization methods hence similar figures can be found in most BMI publications.

{{< figure src="technical_1/ISYS.pdf" title="Figure 21: " width="500" >}}


Table 3: Summary of the target specifications for the analogue instrumentation system.
|	Parameter      | Symbol     		 | Specification    |
|----|----|----|
|    	Integrated Channels | | 64    	|
|	Supply Voltage | (V_{DD})| (<)1.8V |
|	Power Dissipation | (P_{SYS}) | (<)5 (\mu)W |
|    	Diff. Signal |  | 5 (\mu) - 5 mVpp 	|
|    	Common Signal |  | 50 mVpp 	|
|	CMRR/PSRR | | (>)80 dB			|
|	Input Referred Noise | (e^2_{in}) | (<)5 (\mu)Vrms |
|	Total Gain | (A_T) | (>)40 dB 	|
|	THD at max input | | (>)40 dB  |
|	3dB Bandwidth | (f_{3dB}) | 6 kHz  	|
|	High pass frequency | (f_{hp}) | (<)1 Hz |
|    	Sampling rate | (f_{smp}) | 25 kS/s 	|
|	Input Impedance | (R_{IN}) | (>)50$  M \Omega$ @( 1 )kHz |
|	ADC Resolution | (ENOB) | 12 bits |
|	Active Area | | 0.01 mm(^2) |


# 19 Amplifier Principles for Miniaturization




{{< figure src="technical_1/Harrison.pdf" title="Figure 22: " width="500" >}}


The principle design considerations for neural instrumentation have been well established particularly with regard to the Harrison topology [^111] that been widely adopted in many systems and shown in Figure 22. Objectively the optimization techniques have become both more specialized and specific for maximizing the average signal to noise ratio in the LFP or EAP bandwidth with the absolute minimum power budget. Interestingly due to the use of more advanced CMOS technologies there is a persistent trend towards sub-threshold operation. This is motivated by trading in the excess transistor bandwidth for improved current efficiency that measured in terms of the achieved transconductance per dissipated ampere of current. In fact this is purely a result of maximizing the individual transistor performance with respect to the speed efficiency product [^112]. This is expressed in Eq 4 using \\(f_T\\), \\(U_T\\), \\(v_sat\\), \\(\mu\\) as the transition frequency, thermal voltage, velocity saturation voltage, and carrier mobility respectively.

$$  \max\limits_{IC} \left\lbrace f_{T}   \frac{gm}{I_{DS}} \right\rbrace  = \frac{v_{sat}^2}{4\pi   \mu \eta   U_{T}^2} \: \frac{1}{IC_{max}} \approx \frac{22}{IC_{max}}   \left[ \frac{THz}{V} \right]  Where  IC_{max} = \left( \frac{L_{sat}}{L_{tech}} \right)^2 $$

Here \\(L_{sat}\\) is a technology independent BSIM6 parameter that reflects the impact of ballistic carrier transport during velocity saturation and normalizes the minimum feature length \\(L_{tech}\\) for a specific technology as an effective length. The implication of Equation 4 is that the transistors for optimized low frequency instrumentation amplifiers are exclusively in the sub-threshold regime because \\(f_T\\) is always in excess with respect to the signals of interest. The subthreshold operation results in each transistor's transconductance being defined as $gm = \frac{I_{DS}}{\eta   U_{T}}$ which only depends on drain current. Instead of noise optimization though the overdrive voltage, \\(V_{ov}\\), the topology can only reduce noise by removing non-amplifying transistors or biasing them with reduced drain current when compared to the input transistor(s). This reflects the need for a different design methodology as the input referred contribution is dominated by how the total amplifier current distributed to all the transistors. At least in the small signal sense the key requirement is that the amplifying transistors dissipate all the current while biasing/non-amplifying transistors dissipate relatively very little.

In principle due to the under-determined nature of transistor level design the optimization methodology is initially constrained by one of the most important objective characteristics. This could be low noise, wide bandwidth, good linearity, etc. Hence this discussion will digress by distinguishing the design considerations for noise or bandwidth limited amplifiers as separate cases. This should reveal some key relations with respect how power efficiency is achieved. For each case we evaluate the implications with respect to different resource requirements.

## 20 Noise limited Amplifiers



This discussion is guided by the leading challenge for instrumentation systems which is maximizing efficiency while maintaining good linearity. For this reason a noise efficiency factor (NEF) was first introduced in [^113] and is expressed in Equation 5.

$$  NEF^2 = e^2_{in} \frac{I_{tot}}{ U_T   4kT   \omega_{3db}} $$

This figure represents a normalized efficiency or in other words it evaluates how much extra current is dissipated by a particular circuit when compared to an ideal bipolar junction transistor for the same noise performance. Here \\(e^2_{in}\\), \\(I_{tot}\\) and \\(\omega_{3db}\\) represent the input referred noise power, the total current dissipation and the -3dB bandwidth in radians respectively. NEF reflects how well a particular topology achieves efficient amplification for a particular noise floor and thus it inherently trades off with a multitude of other parameters. Here we shall use it as design parameter that reflects the chosen transistor level topology. With this in mind, we propose the following reformulation from Equation 5:

$$  e^2_{in} = \frac{kT}{C} \frac{NEF^2}{\eta   A_{cl}} \frac{I_{in}}{I_{tot}}  \text{where}  C = \frac{gm}{\omega_{3db}   A_{cl}}  \text{and}  gm=\frac{I_{in}}{\eta   U_T} $$

This result leads to:

$$  gm = \omega_{3db} \frac{kT}{e^2_{in}} \frac{\zeta}{\eta}  Equivalently  I_{in} = \omega_{3db} \frac{q   U_T^2}{e^2_{in}}   \zeta   \text{where}   \zeta = NEF^2 \frac{I_{in}}{I_{tot}} $$

Note that this relation is exclusive to noise limited characteristics and implies nothing with regard to the output load or linearity conditions. Moreover there is a fundamental requirement for transconductance with respect to noise and an implementation related factor \\(\zeta\\). This factor represents the noise efficiency of the topology and the slope factor \\(\eta\\) that tells us about the transistor performance as a fundamental process parameter. Numerous techniques for improving NEF can be found in the literature. As a generalization these can be put into two categories. The first reducing the transconductance of non-signal amplifying transistors using degeneration such that their input referred noise is minimized [^114]. The second approach is AC coupling the amplifier's input signal to biasing transistors such that the total transconductance is increased and the current efficiency is improved. Interestingly because this factor relates to current efficiency the NEF can be smaller than 1 or exceed the efficiency of a BJT using a stacked mixer structure that reuses the same biasing current for multiple amplifiers [^115]. This hints at the fact that NEF should be normalized to the voltage supply but in some sense these structures trade off dynamic range for power efficiency. Theoretical NEF figures for some of the primitive low noise topologies are listed in Table 4 assuming biasing transistors have negligible contribution and taking \\(V_{th}\\) as the NMOS & PMOS threshold voltage.

Table 4: Theoretical figures for NEF for various amplifier topologies. \\(^\star\\) N is the number of stages sharing the structure.
|	Topology           		 | NEF                           	   | Minimum (Vdd)   			| Reference          	|
|----|----|----|----|
|	Single Transistor  		 | $\eta $                         	   | (V_{th})   				|     -              	|
|	Differential Pair  	 	 | $\eta   √{2}$                  | $V_{ds} + V_{th}$			| [^116]  		|
|	Complementary Pair 		 | $\eta $                             | $2   V_{th}+2   V_{ds}$	| [^117]  	|
|	Common Reference(^\star)    | $ \eta √{\frac{1+N}{N}}$     | $V_{ds} + V_{th}$			| [^118]     	|
|	Common Bias(^\star)         | $ \eta √{\frac{2}{N}}$       | $(1+N)   V_{ds} + V_{th}$	| [^115]     	|


These relations highlight the fact NEF primarily dependent on the chosen topology and less sensitive to the actual transistor design after optimization. Choosing a topology for the instrumentation amplifier with respect to its ideal NEF performance is significantly more effective than starting with a particular structure and introducing resistive degeneration on transistors that should not contribute noise.

Also notice that the expression for noise in Equation 6 only has one degree of freedom and that is the ratio between the closed loop gain and capacitive load of the amplifier. This implies the 3dB bandwidth of the amplifier is fixed but its unity gain frequency is arbitrary. In fact by satisfying the relation for Equation 7 it is automatically the case the the equivalent noise density requirement is also satisfied. This is significant because we could allow the first stage to provide wide band gain and rely on a second stage to perform filtering. The second stage will have a capacitor gain product that is \\(A_1^2\\) times smaller than if the fist stage had to perform filtering. This can has a large impact on analogue circuit area that is typically dominated by capacitors used for filtering and setting closed loop gain.

{{< figure src="technical_1/flickker.png" title="Figure 23: " width="500" >}}


So far we have only considered the implication thermal noise requirements on the design. We must also address the flicker noise sources because neural signals have a lot of low frequency content. Moreover because flicker noise sources concentrate the noise power at the lower frequencies, the total noise profile inside the LFP frequency band can be dominated by this type of noise. The nature of flicker noise from transistor physics can be due to a number of phenomena; mobility fluctuation $\Delta \mu$, carrier density fluctuation $\Delta N$, and changes in access resistances $\Delta R$. Each of these phenomena will exhibit a \\(1/f\\) frequency dependence when computing the input referred power spectrum. Typically for a given inversion coefficient IC only one of these phenomena will dominate the overall noise characteristic of a transistor. This is illustrated in Figure 23 which shows that $\Delta N$ is typically the leading cause for flicker noise generated additively to the drain current. IC is a factor that indicates to what extent a transistor is operating in the subthreshold region by using the definition IC=I<sub>D<sub>/($2\mu   C_{ox}   W/L   U^2_T$). This uses The more general parameters \\(q\\), \\(W\\), \\(L\\), \\(C_{ox}\\) that represent electron charge, transistor width, transistor length, and gate oxide sheet capacitance respectively. The region of interest for biomedical circuits is typically when \\(IC<1\\) which exhibits good current efficiency and subthreshold operation. The phenomenological model corresponding to carrier density fluctuation $\Delta N$ component is expressed in Equation 8 after being referred to the transistor gate as an equivalent voltage noise density [^119].

$$  e^2_{fl}   \Delta f = \frac{q^2   kT   \lambda   N_T}{W L   C^2_{ox}   f} \cdot K_{G}  \text{where}  K_{G} \approx (1 + \frac{\alpha   \mu}{2})^2  \text{for}  IC < 1 $$

Here \\(\alpha\\) and \\(\lambda\\) represent the coulomb scattering coefficient and tunnelling attenuation distance respectively. Notice that this expression has relatively weak biasing dependency in weak inversion contrast to the strong inversion region as shown in Figure 23. This trend follows very closely to the \\((gm/I_D)^2\\) characteristic which implies a fixed SNR for varying IC. The parameter \\(N_T\\) reflects the density of trapped charges at the oxide interface inside the transistor's conducting channel. Whether this parameter is consistent across various technology nodes is naturally put into question [^120] but similarly there is evidence supporting that indeed this factor is process independent [^121]. Now we should keep in mind that increasing the input transistor size will accommodate lower flicker noise but also result in increased noise. This is because of the signal loss when coupling \\(C_{in}\\) to \\(C_{fb}\\) that is loaded by the parasitic input capacitance of the amplifier \\(C_{g}\\) (see Figure 22). Keeping the ratio \\(C_{g}/C_{fb}\\) fixed as a \\(\delta\\), we can express the required input capacitance in Equation 9 in terms of general amplifier requirements using \\(A_{cl}\\), \\(K_F\\), \\(f_{cor}\\) as the closed loop gain, flicker charge density, corner frequency respectively.

$$  C_{in} = \delta A_{cl}   C_{g} = \frac{3}{4}  \delta   A_{cl}   C_{ox}   W L = \frac{3}{4} \frac{K_F   A_{cl}  \delta  }{C_{ox}   e^2_{in}   f_{cor}}  \text{where}  K_F = q^2   kT \lambda   N_T   K_G $$

This expression indicates that attempting to achieve all desirable characteristics; small \\(e^2_{in}\\), small \\(f_{cor}\\), large \\(A_{cl}\\) simultaneously in a single amplifier structure comes at the cost of a very large input capacitance that scales proportionally to all factors. This representation suggests the Harrison topology has limited flexibility for improving input capacitance as the only solution appears to be minimising \\(\frac{KF}{C_{ox}}\\) through CMOS process selection. Moreover \\(\delta\\) cannot be made arability small as it will more typically be bounded by the minimum feedback capacitor \\(C_{fb}\\). This need to be large enough to set the high pass pole location at sufficiently small frequency to prevent the resistor \\(R_{fb}\\) from introducing noise inside the signal band which has a integrated power of \\(\frac{kT}{C_{fb}}\\) [^111]. Not to mention that the resulting size of the input transistors can be very large for this particular topology.

## 21 Chopper Stabilized Amplifiers



Alternatively we can apply chopping techniques to deal with these noise requirements which is used extensively in bio-signal instrumentation systems [^69]. By up modulating the signal to a higher frequency before amplification, the flicker noise is added to the usual near-DC band which no longer coincides with out input signal. The output is then demodulated to recover the input. The difference is that the flicker components now lie at the chopper frequency \\(f_{chp}\\) which is typically out of band and can be rejected easily. This eliminates the requirements from Eq 9 on the input capacitance and shifts the focus to rejecting up modulated aggressors at higher frequencies. We suggest using keeping the sampling and chopper frequency coherent because it allows low order FIR filter reject all up modulated harmonics. For instance by chopping at the half the Nyquist frequency (\\(f_s/2\\)) or odd multiples of it (i.e. \\([2n+1] f_s/2\\) $|$ $n \in \mathbb{Z}$) will fold chopper harmonics onto \\(f_s/2\\). The resulting filter are quite relaxed because of the large fractional bandwidth in the transition band that separates our signal bandwidth \\(f_{3dB}\\) from \\(f_{chop}\\). In this particular case we employ a sampling frequency of \\(25 kS/s\\) and use a chopping frequency at \\(37.5 kHz\\) to achieve this functionality [^122]. Conveniently any common mode signals from the sensor or analogue supplies are also rejected using this configuration because they will appear at the chopper frequency.

In addition to basic chopping functionality, the performance can be further improved by providing closed loop feedback to actively cancel aggressors on top of filtering the resulting up modulated aggressors. This can be achieved in multiple ways and in some cases could improve linearity. One possible technique is using a DC-servo loop and another is performing ripple rejection both of which remove different components [^123]. Here we will consider the implementation of three such techniques that improve chopping performance that specifically have negligible power and area requirements. The considerations made here will be similar to that of [^124] [^125] but with explicit focus on area reduction.

{{< figure src="technical_1/T1_CAMP.pdf}" width="500" >}}
{{< figure src="technical_1/T1_CAMP_T.pdf}" title="Figure 24: Proposed compact chopper stabilized neural amplifier topology. " width="500" >}}


Figure 24 shows the proposed configuration that promises a significant reduction in input capacitance and the required silicon area. This configuration has two gain stages where the first stage A1 is a wideband low noise stage and the second provides A2 low pass filtering as motivated by Section 20. This enables the rejection of flicker noise from the first stage completely and effectively shifts the corner frequency of the second stage by gain of first stage squared. Moreover this the configuration does not require auxiliary integrators provide feedback on the capacitive feedback network around A1 that would lead to increased complexity.

The pseudo resistor across A1 in this configuration provides closed loop rejection of low frequency noise below the high pass pole with the time constant $\tau_{HP} = C_{F1} R_{HP}$. The noise components in the band from \\(f_{HP}\\) to \\(f_{CHP}\\) will be a mixture of flicker and thermal noise that are up-modulated by the chopper proceeding A1. This is because A1's corner frequency will lie inside of this band after sizing the input transistors such that \\(C_G\\) is about 5% of \\(C_{IN}\\) which usually leads to a target area of about 100 $\mu m^2$.

It is important that the gains of A1 and A2 are carefully selected because this configuration only provides a first order role off in terms of analogue filtering. It could be that \\(f_{CHP}\\) is not sufficiently outside of the \\(6kHz\\) filter bandwidth resulting in some aggressors to appear on the output of A2. For this reason we require an aggressive high pass pole location to minimize this total up modulated power. More specifically we can say that the total noise contribution below the \\(f_{HP}\\) is mainly from \\(R_{HP}\\) which has a noise power of $\frac{kT}{A1^2   C_{F1}}$ when referred to the input of A1. The main concern here is that we have to sacrifice a small amount of dynamic range on A2 to prevent distortion. Although this power is quite limited, we need make sure the FIR filter can reject up-modulated noise components effectively.

In addition we take advantage of the reduced output referred sampling noise a the input of the second stage that scales by \\(f_{3dB}/f_{CHP}\\). This is because most of the sampling noise will lie outside of the filter bandwidth. The size of \\(C_{I2}\\) can be reduced to alleviate the slewing errors due to the band limited behaviour of A1. In addition the parasitics at the output of A1 will pre-charge before \\(C_{I2}\\) is connected reducing the settling error due to the active nodes switching at the input and output.

A common concern for chopper stabilized circuits is the resistive element of each chopper which in this case is seen at the input of the amplifier. This resistance is due to the switching capacitor \\(C_{I1}\\) that is continuously dissipating dynamic current. This can partially be compensated for by performing positive feedback from the output to assist in cancelling the dynamic current through \\(C_{PF}\\) [^123]. However this will rely on the matching of the capacitor ratios $\frac{C_{I1}}{C_{F1}} \frac{C_{I2}}{C_{F2}}$ to be equal to \\(\frac{C_{I1}}{C_{PF}}\\). This can be quite challenging if small configurations are desired that do not need exhaustive calibration. The use of a high precision ADC makes this somewhat easier because the total gain A1\\(\cdot\\)A2 does not need to be as large implies smaller ratios and better matching. Evaluating this resistance in terms of the switching capacitance will result in the expression in Equation 10.

$$  R_{in} = \frac{1}{2 f_{CHP} \cdot (C_{I1} + C_{par} -  \frac{C_{I1}}{C_{F1}} \frac{C_{I2}}{C_{F2}}   C_{PF})} $$

This dependency should indicate that if the dynamic switching current cannot be well matched due to parasitics or variability the next objective would be to reduce the total switching capacitance. From our discussion however it appears that reducing the input capacitance is limited by the psuedo resistive noise that induces aggressors at the chopper frequency. This constraint can be mitigated using a distributed amplifier structure that splits A1 into two identical sections. This should be configured such that the second stage has its high pass pole and corner frequency proportionally larger than the first stage but scaled the gain of the prior stage. However such a topology is more constrained by parasitics that worsen the settling errors in $0.18 \mu m$ CMOS. In addition the poor control of psuedo resistive characteristics does not allow this to be convincing solution [^126]. The feasibility may be more favourable in more advanced technology nodes. Considering a value of \\(1 pF\\) for \\(C_{I1}\\) we expect slightly over \\(20 M\Omega\\) without positive feedback and approximately \\(200 M\Omega\\) with \\(10%\\) matching. This may be acceptable in either cases depending which type of electrode is used but generally any thing above \\(100 M\Omega\\) is satisfactory for most scenarios.


## 22 Bandwidth Limited Amplifiers



Biomedical instrumentation has the advantage that the slowly varying signals prevent most implementations from facing problems due to limited bandwidth. The exception however lies with the stage that drives the input capacitance of the ADC and the settling time during sampling can be quite challenging[^127]. Particularly when multiple channels are multiplexed to the same data converter. In some sense there is an similarity when we look at NEF and bandwidth efficiency because they are strongly dependent on maximizing transconductance efficiency.

$$  FOM   \left[ \frac{MHz \: pF}{mA} \right] = \frac{f_{UGF} \cdot C_{L}}{I_{tot}}  \text{for diff. pair}  FOM = \frac{10^{3}}{4 \pi   \eta U_{T}} $$

{{< figure src="technical_1/MCAmp.pdf" title="Figure 25: " width="500" >}}


Strictly stated in Equation 11, a bandwidth constrained circuit should minimize the total current consumption \\(I_{tot}\\) for a given unity gain bandwidth \\(f_{UGF}\\) and capacitive load \\(C_L\\). It is typical to find dedicated structures out side of the signal processing chain that drive the ADC input capacitance and focus specifically on maximizing the FOM by employing current recycling, adaptive biasing, and positive feedback techniques. The challenge here is efficiently introducing these techniques while also preserving the capability for full output swing, stability and particularly low distortion. The later is likely the most challenging and demands high loop gain that is generally not found in adaptive single pole structures if full output swing is also required. With that said, two stage Miller compensated topologies can provide an excellent solution to this problem because high gain in the second stage will suppress a number nonlinearities excited by the input stage. Further more the capacitive coupling of the output to the input of the second stage implies the settling speed is limited by bandwidth of the second stage. This allows the configuration to simultaneously  provide filtering and settling while sharing many of the biasing and feedback elements. Using the model shown in Figure 25. We can show that sampling induced kick back from the ADC at \\(V_{out}\\) has negligible in pact on internal integration node as it is inversely proportional to the product $A_{cl}\cdot \frac{gm2}{gm1}$ where \\(gm1\\) and \\(gm2\\) are the transconductance of the first and second stage. This is derived from evaluating a step response due to discharging the output load \\(C_{L}\\) which has the Laplace domain response as Equation 12.

$$  H_{step}(s) = \frac{s^2}{s^2 + (\omega_2 - \frac{\omega_1   C_{M}}{A_{cl}   C_{L}} ) s + \frac{\omega_{1} \omega_{2}}{A_{cl}}}  \text{where}  \omega_{1} = \frac{gm_1}{C_{M}} \: \: , \: \: \omega_{2} = \frac{gm_2}{C_{L}} $$

{{< figure src="technical_1/T1_T2AMP.pdf" title="Figure 26: " width="500" >}}


Figure 26 shows the proposed circuit implementation of the two-stage amplifier used inside the second instrumentation stage in Figure 24. This structure has the advantage of providing very high loop gain across the Miller capacitor and allows full output swing due to the positive feed back structures in the current mirrors. The PMOS mirror provides high gain by cancelling the \\(1/gm\\) transresistance of from the diode connected pair leaving the high impedance node and the NMOS mirror provides positive feedback to speed up the transient behaviour on the PMOS side. When this structure provides closed loop gain larger than 20 dB it is sufficient to rely on the NMOS current mirror for stability. In fact this is equivalent to a feed-forward stabilization technique that by passes high frequency signal lag induced by the pole at the PMOS side. However when good phase margin is required at the unity gain frequency stability becomes more stringent. In this case we suggest introducing an additional capacitor across \\(V_n\\) & \\(V_p\\) to realize a zero that cancels the pole in the PMOS branch [^128]. The zero will in fact boost the effective \\(\omega_{2}\\) from $N   M   \frac{gm_{M5}}{C_{L}}$ to $\frac{N   M + M }{2-N}   \frac{gm_{M5}}{C_{L}}$. The factor M in this structure has a rather interesting implication with respect to NEF. If M is large enough this topology will have a NEF equivalent to the complementary structure. However in effect the biasing current of the intermediate branch is reduced when M is large which can move the parasitic poles in side the amplifier bandwidth. The apparent trade off between stability and NEF is unique to this structure but it is not challenging to have M=8 for low power applications.

$$  FOM = \frac{10^3}{4\pi   \eta U_{T}} \cdot \frac{2   C_L }{ C_M   (1+M/K+1/K)} $$

The components that improve bandwidth efficiency are detailed in Equation 13. Referring this back to Equation 6 however implies the noise is dominated by the capacitor that introduces the dominant pole of the system. The observation made here is that unlike the single stage topologies, the two stage configuration can trade off input referred noise for a better speed FOM by adjusting the \\(\frac{C_M}{C_L}\\) ratio. The high level methodology applied here is replacing the \\(C_L\\) with a smaller capacitor that requires less power with the hope that stability can still be maintained by boosting transconductance power with positive feedback and current recycling.

## 23 Circuit Implementation



{{< figure src="technical_1/T1_T1AMP.pdf}" width="500" >}}
{{< figure src="technical_1/AMP_Feedback.pdf}" title="Figure 27: Schematic showing circuit implementation of the proposed compact neural amplifier. " width="500" >}}


Figure 27 shows the transistor level implementation of the topology used in Figure 24. The first gain stage is a highly compact complementary structure that exhibits exceptional noise performance. The second stage transistor implementation is the high gain two-stage topology discussed in Section 22. The variable gain configuration is facilitated by the digital controlled low leakage switches that connect a selected set of capacitors in feedback. This particular configuration provides more generic instrumentation of the 1 Hz to 6 kHz bandwidth. It is well known that the analogue filters introduce frequency dependent group delay near the pole locations which has been shown to degrade processing capabilities of spike sorting techniques [^129]. By placing the high pass pole well inside of the LFP band the spike wave-forms exhibit less distortion due to analogue filtering and is instead filtered using linear phase filters in the digital domain that do not suffer from such drawbacks.

The reset mechanism on instrumentation amplifiers using pseudo-resistive elements is essential. Either during stimulation, start-up, or amplifier saturation the charge across the feedback capacitor must be neutralized before correct operation can begin. This mechanism allows the rejection of various distortion components that would other wise corrupt the latent signal integrity or digital signal processing. However there is an inherent problem with these reset switches due to the parasitic charge injection induced on the intermediate semi-floating nodes. Moreover if these elements are cascaded to increase resistance or dynamic range these sensitive floating nodes are also increased thereby building up more residue charge. A significant amount of charge can introduce a permanent reset artefact after reset as this charge redistributes internally inside the resistor. The proposed solution to this problem is by minimizing the floating nodes and guarding the floating N-Well from injected noise. This should allow  a very large pseudo resistance for a sub-Hz high pass cut off frequency while maintaining exceptional reset characteristics. We minimize the resulting charge residue by absorbing the leaky diode currents and residues into the guarding amplifier. Now there will be some instantaneous off-set as the reset signal injects charge directly onto the feedback capacitor but this can be quite small when using small switches. The drawback here is that there may exist a very slow drift on the order of \\(V/sec\\) from the guarding amplifiers due to $V_{os}   R_{diode}$. But simple digital assistance will suffice in eliminating this concern by periodically resetting the structure and cancelling the residue off-set. This re-introduces the high pass pole at a well defined location depending on the periodicity of the reset signal and reconstructing signal in the digital domain [^130].

{{< figure src="technical_1/AMP_Label.pdf}" width="500" >}}
{{< figure src="technical_1/AMP_Chip.pdf}" title="Figure 28: Physical implementation of amplifier using a 6-metal $0.18   \mu m$ CMOS process measuring $75 \times 82   \mu m^2$ in size. " width="500" >}}


The floor plan for this implementation is annotated in Figure 28. The typical focus for analogue layout is achieving good matching for the input transistors and capacitors to minimise off-set or undesirable signal coupling. In this case the chopper introduces a lot switching that is difficult isolate from the signal so instead we focused on minimising parasitics of the clocked nets. The common mode feedback on the second stage uses a switched capacitor and wide band amplifier to ensure accurate common mode settling without deteriorating linearity. This is important because the ADC can be quite sensitive to the sampled common mode resulting in a reduced precision if there is an unexpected offset on the sampled output. Simulated performance of the implemented topology is shown in Figure 29. This compact configuration can achieve an input referred noise of $5.6 \mu V_{rms}$ over the specified bandwidth with a noise corner frequency of 20 Hz. The performance is detailed with a clear reduction in size can be observed when compared to other chopper systems in Table 5. The total gain is \\(421 V/V\\) for this particular configuration which can be adjusted using the digital calibration bits integrated into the structure allowing different gain and power settings. The maximum available gain setting is shown in Figure 30.

{{< figure src="technical_1/Noise_PLO.pdf}" width="500" >}}
{{< figure src="technical_1/Amp_Thd.pdf}" title="Figure 29:  Post layout simulated results of the proposed instrumentation circuit. " width="500" >}}



{{< figure src="technical_1/sim_gain.pdf" title="Figure 30:  Post layout simulated results using periodic steady state analysis to evaluate the closed loop gain of the instrumentation circuit. " width="500" >}}


Table 5: Summary of performance specifications of the proposed instrumentation topology and other bio-signal chopper stabilized amplifiers found in the literature.
|	Parameter      |  Units       |   This Work     | Markovic [^125] | Makinwa [^123] |
|----|----|----|----|----|
|	technology 		|		[nm]		|	180 | 40 | 65 |
|	Supply Voltage   |      [V]     			| (1.2)    | (1.2)    | (1)   |
|	Total Current    |    [(\mu)A]			| (1.05) | (1.67) | (2.1)|
|	Bandwidth        |       [Hz]      		| (<1)-(6 k) | (1-5k) | (0.5-1k)  |
|	Filter Order \ Roll-off | [dB/Dec]  | (20) | (20) | (20) |
|	Noise Floor   |  [$nV / √{Hz}$]     	| (55)  | (101) | (60)|
|	Noise Corner   |     [Hz]             	| $20   Hz$   | (100) | (<1)|
|	Dynamic Range |	[dB] 	  	| (58)   | (69) | (64) |
|	Area         |    [(\mu)m(^2)]       	| $6.2\cdot 10^3 $ | $7.2\cdot 10^4$| $2\cdot 10^5$ |
|	Area-Power-Product | [(\mu)W (\mu)m(^2)] | (7.3 10^3) | (141 10^3) | (420 10^3) |
|	NEF | | (1.08) | (2.5) | (1.66) |


Overall the proposed implementation performs well for supply voltages larger than \\(1.1 V\\) where the limiting factor is due to the current biased complimentary input stage. This configuration necessitates a voltage overhead requirement of \\(2V_{TH}+2V_{ov}\\). However both of the gain stages are class-A which at exhibit relatively well behaved current transients on the supplies. Class-AB alternatives do not share this feature and are more prone to disturb neighbouring recording circuits. Minimizing the dynamic current dissipation should lead to better LDO performance and lower supply induced sensor noise when many channels are integrated together. This also motivates another aspect for using a wide-band amplifier configuration for the first amplification stage because it usually implies that the common mode will also have wide band regulation. This leads to better common mode rejection in the signal band due to additional loop gain.

# 24 Analogue Signal Conversion


\label{ch:T1_converter}

Analogue to digital conversion remains to a crucial component instrumentation, particularly for full signal characterization. Even when considering the demanding constraints for integrated neural sensors, the prevalence of full spectrum signal characterization is ubiquitous in the literature. This is motivated by the efficiency and reliability of various digital processing methods that require very efficient signal conversion to discreet samples instead of processing recordings in the analogue domain. Typically the most valued performance criteria for such a system is the ADC power consumption. A Successive Approximation Register (SAR) ADC is commonly used for quantizing biomedical signals because it only dissipates switching energy that can be very small for slow sampling rates. The SAR topology is depicted in 31 and can be found extensively in BMI recording publications.

{{< figure src="technical_1/Split_Cap_Schmtc.pdf" title="Figure 31:  Schematic of a conventional N bit SAR ADC with the split capacitor at position M." width="500" >}}


## 25 Capacitive array miniaturization



This discussion pays special attention to acquiring neural recordings that include LFPs while minimizing the required silicon area per sensor. This is motivated by wanting to integrate many sensors on chip for large arrays and secondly reducing any capacitive switching noise that can be quite difficult to reject in fully integrated systems. Recording LFPs and EAPs simultaneously will require increased ADC resolution so that the instrumentation dynamic range exceeds 60dB. Equivalently this means 10 to 14 bit precision is needed depending on the nonlinearity tolerances of the proceeding processing methods. This can be quite difficult it terms of the SAR specifications because the capacitor mismatch and sampling noise can prevent aggressive sizing on the unit capacitor. For a given ADC precision N, the SAR capacitor array will require $M \cdot 2^{N/M}+M$ unit capacitors \\(C_{unit}\\) where M is the number of equally split sections. By splitting the array into sections it should be obvious that the total capacitor requirement \\(C_{Total}\\) can be reduced to some extent. The quantization errors resulting from capacitor mismatch on the other hand is also closely related to these parameters. For given standard deviation \\(\sigma\\) and confidence interval CI we can use Equation 14 to make a simple estimate for the expected quantization error \\(E_Q\\) [^131].

$$  E_Q = V_{ref} \frac{\sum \Delta Ci}{2^N C_{unit} - \Delta C_{Total}} = V_{ref} \cdot \alpha(N) \frac{√{2^N}-1}{√{2}-1} $$

The above expression assumes no split configuration is used where \\(\alpha\\) represents a scaling factor that is dependent on the number control bits for each sub-DAC, $\alpha(x)= \frac{CI \sigma}{2^x - CI \sigma √{2^x}}$. \\(V_{ref}\\) is the reference voltage by which the sampled input is normalized to arrive at the binary encoded result. Now extending this formulation to include the dependency of M and bounding $E_Q < LSB/2$ in accordance with the required ADC precision leads to the expression in Equation 15.

$$  \frac{1}{2^{N+1}} \geq \alpha(N/M) \sum_{k=0}^{M} \left[ \sum_{i=0}^{M} √{2^{i}} \right] \cdot \left( \frac{\alpha(N/M)}{2^{N/M}} \right)^k $$

There several higher order terms with respect \\(\sigma CI\\) not shown here because they have vanishing contribution as N is increased and require a numerical solution to the problem. Otherwise for M=2 and arbitrary placing the split capacitor K position in the array we can similarly reconstruct the equality from 14 in Equation 16.

$$  \frac{1}{2^{N+1}} \geq \frac{CI\sigma(√{2^{N-k}}-1)}{(2^{N-K} - CI \sigma 2^{\frac{N-K}{2}} )(√{2}-1)} + \frac{(√{2^{K}}-1) CI \sigma} {(√{2}-1) 2^K (2^K -CI \sigma 2^{\frac{K}{2}})} $$

The standard deviation \\(\sigma\\) is closely related to the exact requirements for the whole capacitive DAC in terms of the total area and unit capacitor size. The dependency of \\(E_Q\\) is mainly subject to the variance due to the MSB capacitors and for each less significant bit (from MSB to LSB) the expected variance increases by \\(√{2}\\) while its capacitive coupling decreases by 2. This is because $\sigma \propto 1/√{A_C}$ where \\(A_C\\) is the area of the capacitor. Clearly there is a process related figure of merit here that relates to the quality of capacitors since small capacitors with excellent matching will result in the best characteristics ADCs such that we minimize the % deviation per \\(\mu m^2\\).

{{< figure src="technical_1/Split_CAP.pdf" title="Figure 32: Numerical solution to Equation 16 relating the capacitive DAC area requirement with the DAC resolution (N) and the position of the split capacitor before capacitor K. " width="500" >}}


Figure 32 shows a numerical solution to the equality in Equation 16. This allows us to consider the effect of split capacitor positioning with respect to the optimal area allocation for the capacitor array. The visible plateau for small N represents the case when the design is bounded by the minimal unit capacitance. This is determined using the process documentation for the target 0.18 \\(\mu m\\) CMOS technology that gives its mismatch specifications and minimum sizing. Generally split capacitor configurations are more sensitive to parasitics they can lead to more pronounced nonlinearities. However in some cases that the unit capacitor size limits the array size such that splinting the array is an effective solution for improving power dissipation. We reiterate that this also indicates that the binary weighted configuration without splitting maximizes area efficiency if we are not limited by sampling noise or minimal capacitor sizing. In addition a fully differential DAC counter intuitively reduces the minimum size if the switching method first detects polarity before applying successive feedback [^132]. This is because the first quantization cycle does not depend on the capacitive division. This in turn means that the array can tolerate twice the mismatch error implying a 4 times smaller unit capacitance while only doubling the number of capacitors in the array.

## 26  Model based topology selection



From here there are multiple directions we can take in order to ensure efficient operation and simultaneously achieve a compact configuration. A common approach is to multiplex the SAR ADC to a large number of channels but this will also require the analogue stage driving the ADC to dissipate proportionally more power due to settling requirements on the sampling capacitance. From a high level perspective, distributing the quantization effort into a large array of ADCs with staggered operation should lead to much more systematic power dissipation due to their uncorrelated operation. Opposed to using a single high speed ADC that requires a much higher clock frequency with stronger tones in the generated supply noise. Another SAR based alternative using calibration for the capacitive array such that it can specifically be designed with the smallest possible unit capacitors. Then we could correct any nonlinearity or quantization errors that arise from capacitor mismatch if the array is characterized precisely enough. This does require either foreground or background calibration modules to extract the individual capacitor weights. Because we aim to perform a number of processing techniques in the digital domain for characterizing neural recording, it makes sense for us to consider effective means to perform calibration.

{{< figure src="technical_1/SDADC.pdf" title="Figure 33: Schematic of the proposed $\Sigma \Delta$ assisted SAR ADC topology for achieving a more compact configuration." width="500" >}}


The structure illustrated in 33 represents a hybrid topology based on SAR and sigma delta structures. The motivation is driven by the efficiency of SAR quantization for large signals and the compactness of high resolution quantization from sigma delta loops. The digital control will perform fully differential bottom plate sampling of the input which is then rapidly quantized to \\(2^N\\) levels using the typical binary search. After the SAR operation the resulting residue left on the capacitive array is quantized using a sigma delta control loop that feedback on the nodes \\(V\Sigma\Delta\pm\\).

There is a strict advantage over conventional sigma delta loops which is that the residue error that needs to be quantized is reduced to \\(\frac{V_{ref}}{2^{N}}\\) which can easily be designed to lie within the linear range of a differential pair. This negates having to use passive or active feedback to deal with transconductance nonlinearity and significantly improves the power efficiency by retaining a relatively simple control loop topology. Moreover as the feedback loop is typically responsible for small dynamic range of 30dB the requirements on clock jitter and decimation filtering is made more relaxed.

The more desirable advantage over a high resolution SAR is that the capacitive DAC may designed in a highly optimal configuration with as few bits as possible. This allows sizing that primarily focuses on suppressing parasitic effects with minimal sampling capacitance. As will be demonstrated this topology does not require an axillary calibration DAC or a pseudo random dithering source for performing mismatch correction. This is due to the capability that the internal sigma delta structure is in the same signal loop as the SAR operation and can trade-off bandwidth for increased noise rejection simply by adjusting the sampling frequency \\(f_s\\). Naturally because this topology inherently needs a pre-amp stage for SAR conversion we should not expect the FOM to do better than low resolution SARs.

Intuitively one can think that when combining the two topologies the individual sources for power dissipation now scale with \\(2^{\frac{N}{2}}\\). More specifically these sources come from the capacitive DAC and decimation filter. The components that do not have reduced scaling are related to the sampling noise and the thermal noise floor of the oversampling modulator. To demonstrate this quantitatively we will build an analytic model for the SAR and \\(\Delta\Sigma\\) SAR topologies to demonstrate some of the inherent characteristics. This will also reveal the techniques for optimizing of the proposed structure.

$$  FOM_{ADC} = \frac{P_{sys}}{2^{N} f_s} $$

Maximizing the performance indicator from Equation 17 will represent our objective function which reflects the efficiency by which each sample is converted into a digital code. Through the simplicity of this relation, any comparison primarily requires an accurate expectation for power budget in terms of the required resolution or precision requirements.

$$  P_{Ideal} = \underbrace{ E_{search} \cdot f_s C_{unit} V_{ref}^2 (2^{N-2}+2^2)}_{Capacitor Array} + \underbrace{2N (N+2) f_s E_{gate} }_{Register Logic} $$

Equation 18 Considers the primitive structure with an ideal comparator where \\(E_{search}\\) represents the average dissipation for binary search switching method and \\(E_{gate}\\) is the average gate dissipation per clock cycle. Both these parameters adjust to different core libraries or various switching methods that typically trade off efficiency for parasitic tolerance [^133]. This ideal structure is extended by the requirements of either a dynamic latch comparator or an analogue pre amplifier that allows negligible comparator requirements at the expense of consuming a static current. The classic pre-amplifier approach also tends to deal with mitigating kick back noise but in general the straightforward application of classic \\(kT/C\\) relations conveniently give;

$$  P_{amp} = 32   \pi   \ln(2) \cdot \underbrace{\frac{(U_T   N   2^N)^2}{V_{ref} \cdot \eta   q}}_{Noise} \cdot \underbrace{A_{ol}   f_s   NEF^2}_{Bandwidth} $$

Here \\(A_{ol}\\) represents the gain provided by the pre-amplifier. Notice the very typical inverse relationship with respect to \\(V_{ref}\\) which motivates the use of the more efficient dynamic comparator structure. However evaluating the equivalent input referred noise of a dynamic structure accurately requires the a piece wise evaluation for different phases of operation and the respective stochastic integrals [^134]. The contribution can be associated with two dominant sources, that of sampled noise;


$$  \sigma_{S} = \frac{4   kT}{3   C_x   F} + \frac{ kT}{3   C_x   F^2   H} + \frac{ kT}{12   C_x   F^2   H^2} $$

And noise contributed from transconductive elements;

$$  \sigma_{M} = \frac{kT}{C_x   F^2} + \frac{kT}{2   C_x   F^2   H}  + \frac{kT}{8   C_x   F^2   H^2} $$

$$  F = \frac{2 \rho V_{th}}{V_{ref} - V_{th} }  \text{and}  H = \frac{V_{ref}}{2  V_{ov}} \cdot {2 \rho }{1 + \rho} $$

As before, this must be bounded by the acceptable quantization noise, $ V_{ref} \cdot {2^{-N-2}} = √{\sigma_M + \sigma_S } $, which give the values for \\(C_x\\). Strictly there is a strong dependence on the input signal in order to evaluate the dissipated power but on average it is reasonable to approximate this to the capacitive switching energy of $P_{Latch} \approx f_{s}  C_x   V^2$.

Now consider the components of the \\(\Delta\Sigma\\) structure. Clearly it will follow closely to that of the pre-amplifier based relations with the exception that the primitive components from Equation 18. Instead this will scale with \\(N-K\\) where \\(K\\) is the number of bits resolved by the sigma delta loop. Here two additional components will be accounted for, the first is the integrator and the second is the digital FIR that decimates the modulated residue quantization. A second order feed forward integration topology is chosen for \\(H(s)\\) based on its efficacy of being applied to the configuration shown in Figure 33 and primarily minimizing the number of summing operators and coefficients prone to mismatch. For the sake of discussion we make the assertion that decimation noise rejection is bounded $K \leq (FIR)^{-1/2}$ in the case of a rectangular window for analytic clarity [^135]. Furthermore, note that as we increase the SAR quantization the first stage will proportionally see a reduction of the input signal that needs to be accounted for to achieve the correct integration constant.

$$  P_{int} = 32 \pi \cdot \underbrace{\frac{(U_T   2^{N}   NEF)^2 }{ q   V_{ref}}}_{Noise} \cdot \underbrace{FIR   f_s   (1+2^{N-K}) }_{Bandwidth} $$

And similarly the digital decimation filter will scale in the form of;

$$  P_{fir} = \underbrace{2^{K}}_{OSR}   \underbrace{( K + \log_{2}(K))}_{Quantization}   fs   E_{gate} $$

Collecting these terms for each topology will equate to expressions that typically have scalar dependencies on technology or implementation which we must make a set of reasonable assumptions for.  The literature will indicate numerous means by which each component can be reduced through specialized logic cells, adaptive comparator power allocation, or power saving switching methods. Our particular interest lies with the dependency on N that will imply the effectiveness of a certain topology for a given dynamic range requirement. In addition this familiarizes us with specific factors fundamental to power dissipation with respect to resolution.

{{< figure src="technical_1/P_TOP_N.pdf}" width="500" >}}
{{< figure src="technical_1/P_TOP_A.pdf}" title="Figure 34:  Summary of the FOM (\\(P_{sys}/2^{N} f_s\\)) for each topology with respect to different resolution requirements. " width="500" >}}


Figure 34 presents the expected merit for each topology as the target resolution is varied. Without consideration for area, there is a clear power advantage for the dynamic SAR structure mediated primarily by the fact that the comparator does not have settling associated tolerance. This is the main reason why the pre-amp topology requires a proportionally increased bandwidth/power as resolution is increased. What stands out is that the \\(\Delta\Sigma\\) structure has a power dependency $\propto   2^{3N}$ for achieving the required input referred noise in contrast to more conventional dependency of \\(2^{2N}\\). The mechanism behind this is due to the SAR quantization that reduces the signal input range which needs to be recovered to achieve the correct integration factors. Moreover the over sampling ratio increases simultaneously which has an overall multiplicative effect. Clearly the resolution of the SAR quantizer should only perform a few conversion that put the residue in the linear range of the loop filter and let the modulator perform most of the quantization effort. When all topologies are using the same unit capacitor, this result demonstrates that for \\(N < 5\\) & \\(N > 14\\) the \\(\Delta\Sigma\\) topology becomes strictly unfavourable in terms of power but performs comparably with respect to power efficiency for \\(N \approx 10\\). Taking the FOM area product by considering the capacitors in terms of \\(\Box\\) units the advantage of the \\(\Delta\Sigma\\) topology becomes more obvious. For the precision significant to neural recording, \\(8<N<12\\), the hybrid structure consistently grantees a more compact configuration by a factor of 10.

{{< figure src="technical_1/FOM_Space.pdf" title="Figure 35:  Figure of merit dependency of the proposed \\(\Delta\Sigma\\)SAR topology with respect to design parameters K1 & K2. " width="500" >}}


Considering the design space of the \\(\Delta\Sigma\\)SAR structure in more detail will expose a more optimal strategy for increasing FOM. Figure 35 exemplifies how the FOM behaves as either the SAR of sigma delta accuracy is increased. After the optimal basin at N = 9 & K=4 the best strategy for improving ADC resolution is by increasing SAR quantization at half the rate of the sigma delta increase in resolution. For reference a conventional $\Delta \Sigma$ modulator [^136] is designed with the same target specifications and using the same design method to configure the OPAMP integrators and resistive input network. Such a configuration achieves 167 dB FOM<sub>s<sub> irrespective of target resolution when we consider just the analogue power dissipation. In fact this figure is commonly achieved by state of the art [^137]. As shown in Figure 36 the \\(\Delta\Sigma\\)SAR configuration can theoretically achieve more than 4X better performance than conventional \\(\Delta\Sigma\\) modulators for resolutions above 12 bits even when operating at lower supply voltages. This is because of the improved noise efficiency. Please refer to Section 58 for additional details regarding derivations and topology comparisons that are omitted here for clarity.

{{< figure src="technical_1/AMD.pdf" title="Figure 36:  Estimation on the expected figure of merit for a target resolution and varying SAR precision. The red star and blue circle indicate the target and measured performance respectively. " width="500" >}}


## 27 Circuit Implementation



Extending the conventional SAR structure to perform sigma delta modulation is achieved with relatively little changes to the overall topology. The main difference is that during the last phase of SAR conversion a register must be toggled that switches in the integrators intermediate to the comparator. Simultaneously the \\(V\Sigma\Delta\pm\\) capacitors are directly connected to the comparator bipolar output instead of the common mode voltage \\(VCM\\) for differential feedback. This configuration is integrated on chip and performs 7 bits of differential SAR quantization with another 5 bits resolved by the noise shaping modulator with an over sampling rate of 32. At the system level, 4 analogue recording channels will be multiplexed to the input of the ADC which implies sampling rate of \\(100 kS/s\\) is required to sample each output at \\(25 kS/s\\).

{{< figure src="technical_1/SAR_Arch.pdf}" width="500" >}}
{{< figure src="technical_1/SAR_Logic.pdf}" title="Figure 37: Schematic configuration of the top level control for the \\(\Delta\Sigma\\)SAR data converter." width="500" >}}


Figure 37 shows the top level configuration of this data converter. By using a specialized register logic slice a small reduction in complexity is achieved in addition to the mitigation of timing issues typical with the conventional self clocking register configuration. This topology uses a bottom plate sampling strategy to neutralize the effect of parasitics and common mode comparator nonlinearities while operating at 1.2V with a 10MHz clock frequency. Although there are only \\(N-K+OSR\\) active phases, settling the output of the recording amplifiers on to the capacitor array will require several cycles because of the band limited behaviour present in the driving stage.

The implementation of the capacitive DAC and second order feed-forward integrator are shown in Figure 37. This configuration also opts to scale the voltage reference for the LSB in order to reduce the total number of capacitor required. As the capacitor array is implemented using CMIM devices the 7 bit differential structure with a split capacitor for \\(M=3\\) will grantee 10.1b for a confidence interval of \\(3\sigma\\) using Equation 16 and process documentation parameters that show a $8\times8 \mu m$ has \\(0.23 %\\) mismatch induced standard deviation. The reasoning for this configuration is that we are guaranteed \\(>9.5 bits\\) without calibration and will allow \\(>12 bits\\) with calibration. For either case the accuracy is sufficient for recording LFP and EAP signals simultaneously. This result was also confirmed with monte-carlo analysis using foundry supplied PSP models.

{{< figure src="technical_1/T1_SDSAR_CDAC.pdf}" width="500" >}}
{{< figure src="technical_1/T1_SDSAR_INT.pdf}" title="Figure 38: Schematic implementation of the \\(\Delta\Sigma\\)SAR structure. " width="500" >}}


The integrator topology primarily deals with the contrasting bandwidth requirement of the SAR operation and the sigma delta integration for the first stage. Particularly when taking the SAR decisions at the oversampled clock the first stage can only provide wideband gain if the capacitor is switched out and a resistive element is used instead. The circuit complexity can be dramatically reduced by using triode region transistors that regulate the PMOS biasing current for a well defined common mode. Because these transistor can be large in area they could slow down the maximum SAR speed. To avoid this the CMFB circuit is semi open loop during the SAR quantization leading to an increase bandwidth by using the common mode voltage that preserved on the integration capacitor. Also by switching the biasing current of the analogue summing stage a constant common mode can be presented to the comparator input thereby reducing any off-set disparity between the two operation phases.

{{< figure src="technical_1/ADC_Label.pdf}" width="500" >}}
{{< figure src="technical_1/ADC_Chip.pdf}" title="Figure 39: Physical implementation of ADC using a 6-metal $0.18   \mu m$ CMOS process measuring $93 \times 147   \mu m^2$ in size." width="500" >}}


Figure 39 shows the fabricated structure of the ADC. Since the capacitors are placed on top of the active circuits this floor plan distances the integrators and the MSB capacitors to physically isolate the digital switching noise sources. A number of shielding structures are employed to improve post layout performance. There include various guard rings and isolating N-wells but due to the proximity of the digital switching the most effective strategy is appropriately orienting fully differential structures in order to equalize the coupling components. Here metal layers 1-3 are used for transistor interconnect, layers 5-6 for the capacitive DAC, and layer 4 is interposed in order to shield the two sections while connected to the common mode voltage. This is because the transient fluctuations on \\(V_{cm}\\) are only due to mismatch and should be the most quiet reference in the system with large capacitive loading.

In order to take advantage of this structure we reveal two distinguishing characteristics that can not be found in either conventional topologies or other hybrid topologies. When the capacitive DAC is considered as a set of weights that need to be determined we realize that the derivative for slow varying signals is predominantly quantized by the sigma delta loop. With the exception when the SAR bits switch the quantization is independent of the mismatch in these weights. As a result all the mismatch coefficients can be accounted for with respect to the $\Sigma \Delta C$ capacitor.

{{< figure src="technical_1/adc_cloop.pdf" title="Figure 40:  Control loop used to perform calibration with a slow test signal at the ADC input." width="500" >}}


The calibration technique discussed is abstractly represented by Figure 40 where there are two IIR control loops with the coefficients \\(a_1\\) and \\(b_1\\). In part this loop performs normal operation by evaluating the signal quantization \\(Q_{sig}\\). This is done adding the SAR quantization with calibrated weights and decimating the oversampled residue with a \\(32^{nd}\\) order FIR window quantized with 8 bit coefficients for each sample. Here \\(a_{1}\\) simply has to be small enough to track the signal and reject noisy components to determine $\Delta Q$. $\Delta Q$ represents DNL nonlinearities that are used to adjust the coefficients \\(K_{DAC}\\). The multiplication operator is in fact a bitwise evaluation that indicates if a coefficient needs to be adjusted due to a correlation between $\Delta Q$ and a change in that bit. Hence \\(b_{1}\\) needs to be small enough to prevent level dependent tuning and \\(V_{test}\\) should be a full range slow varying signal.

{{< figure src="technical_1/adc_UC.pdf}" width="500" >}}
{{< figure src="technical_1/adc_CC.pdf}" title="Figure 41: INL Plots illustrating the mismatch artefact reduction due to calibration." width="500" >}}


The improvement in INL is evident in Figure 41 due to the calibration mechanism with \\(a_1=1/4\\) and \\(b_1=2^{-8}\\). The close interaction between INL & DNL errors over the full dynamic range for a capacitive array in addition to the sigma delta loop's capability of quantizing $\pm 2   LSB$ of the array allows this method to converge accurately. Here it is observed that the calibration improves the quantization accuracy by two additional bits.

{{< figure src="technical_1/adc_thdsnr.pdf" title="Figure 42:  Measured THD and SNR of the fabricated data converter." width="500" >}}


{{< figure src="technical_1/ADC_TEST.jpg}" width="500" >}}
{{< figure src="technical_1/adc_TI.pdf}" title="Figure 43:  Testing setup used for characterizing the ADC." width="500" >}}


Figure 43 shows the test bench used during device characterization. The saleae logic device is a digital probe that offers 100 MS/s digital signal acquisition for measurements of up to 10 seconds. Here the raspberry pi module simply provides real time interaction with the device configuration using automated spi control and a graphical user interface that will indicate ADC precision based on the selected operation. This allows us to tweak the operating conditions and find which noise sources are disturbing the configuration. The analogue bias \\(I_{BIAS}\\) is generated by a 2602A Keithley system source meter and fed in using a guarded triax cable. The differential input signals are generated using a Agilent 33522A arbitrary waveform generator and fed to the ADC input using BNC cables.

Table 6 outlines the characteristics of the implemented ADC configuration while comparing it to recent oversampling/noise shaping data converter publications. Figure 42 demonstrates the spectral characteristics of the quantization output for a input signal at half the full input range after calibration. In comparison to the analogue instrumentation, the resource related specifications are significantly larger. However note that there requirements are distributed over a number of channels as a result of multiplexing this structure.

Table 6: Summary of performance specifications for the \\(\Delta\Sigma\\)SAR data converter and other oversampling/noise shaping data converter structures found in the literature.
|		Parameter     | Units  | This Work  | Lo [^138] | Roermund [^139] |
|----|----|----|----|----|
|		Technology | [nm] | 180 | 65 | 65 |
|		Supply Voltage  | [V]  | (1.2)   | (1.2) | (0.8)         |
|		Total Current   |[(\mu)A]   | (12)   |  (13) |  (1.7)   |
|		Sampling Frequency  | [kS/s] | $200 $ | (8) | (16)   |
|		ENOB           | [bits]  | (11.3) | (17.5) | (14.5) |
|		SFDR           | [dB]    | (86)     | (105) | $ 87 $ |
|		Area           |  [$\mu m^2$]  | $93 \times 147$ | $400 \times 180$ | $600 \times 300$|
|		Power-Area-Product | [$\mu W   \mu m^2$] | $1.9 \cdot 10^5$ | $1.1 \cdot 10^6$ | $2.4 \cdot 10^5$|
|		$P/(fs + 2^N)$           | [fJ/conv] | (10)  | (29) | (6.6) |
|		(SNDR+10log(BW/P))				| [dB] | (166) | (180) | (177) |


The trade off with respect to residue over sampling in Figure 44 demonstrates that there is some flexibility with respect to sampling rate and SINAD performance. In addition this also clarifies that post-fabrication adjustments do not exhibit significant resolution improvements beyond the design point. This is related to the sampling noise of the capacitor array and the noise floor of the analogue integrators that need to be programmable for different oversampling ratios. At which point the decimation also has more strenuous requirements that may result in an inefficient resource overhead. Strictly stated it is significantly more efficient to reject noise with digital bandpass filtering selected frequency components than having the ADC resolve the signal beyond the target precision.

{{< figure src="technical_1/adc_fom.pdf" title="Figure 44:  Measured Figure of Merit as a function of oversampling ratio." width="500" >}}


In the context of miniaturization the topology presented here follows closely to the expected improvement from the model for high resolution signal acquisition. We achieve nearly 12 bits of quantization with a 6 bit equivalent capacitive DAC which is reflected in the compact design foot print. When compared to similar compact ADC implementations found in recent publications we observe a competitive power budget with again significantly smaller area requirement. Some additional digital processing is required opposed to the simplicity of SAR converters to take full advantage of the topology. However such hardware is typically readily available in systems that also perform spike sorting and neural signal classification.

# 28 System Level Abstraction


\label{ch:T1_model}

Numerous specifications such as ADC resolution and input referred noise of the instrumentation amplifiers relate directly to signal specific parameters. Moreover a particular processing algorithm would favour certain filter configurations of others in terms of signal conditioning. In multi stage systems however there is a significant amount of flexibility related to choosing gain for individual stages or their filter parameters that is indifferent to the resulting transfer function. Here we consider such a primitive \\(N\\) stage analogue processing chain and discuss the allocation of resources to gain insight to some of the high level the optimization for selecting a specific configuration. Such a configuration is shown in Figure 45.

{{< figure src="technical_1/ACS.pdf" title="Figure 45: Multistage amplifier configuration using the series G to adjust the allocation power and area. " width="500" >}}


$$  G[n] = A_{g} \left( \beta + \alpha^{n} \right)  \text{where}  A_{g} = √[N]{\frac{G_{T}}{ \prod_{i=1}^{N} (\beta + \alpha^{n} )}} $$

Consider a geometric series for the gain of each stage as expressed in Equation 25. Here \\(G_{T}\\), \\(\alpha\\), \\(\beta\\) represent the total gain required, resource distribution factor, and a minimal contribution factor. The formulation is motivated by the fact that if \\(\alpha\\) is one resources are allocated equally. This means every stage has equal gain but it also implies that the sum of all gain factors is minimal leading to a minimum amount of area due to the feedback capacitors. More typically designs will choose a smaller \\(\alpha\\) such that most of the gain is situated at the first few stages. This allows some reduction in power in the proceeding stages because of the reduced noise requirement. \\(\beta\\) simply allows us to specify that a fraction of the total gain is uniformly distributed but is typically kept small in order to maximize the benefit from resource redistribution. This allows us to express the noise power requirement for a given set of parameters in Equation 26.

$$  P_{Amplifiers} = P_{unit}  \left( 1 + \sum_{k=1}^{N-1}\left[\prod_{i=1}^{k} \frac{1}{A_{g}   \beta + A_{g}   \alpha^{i} }  \right] \right)^2 $$

$$  A_{Gain}= A_{unit}\left( \sum_{k=1}^{N} \left[1 + A_{g} \beta + A_{g} \alpha^{k} \right] \right) $$

Here \\(P_{unit}\\) is simply evaluated from Equation 6 and leads to an area requirement that is simply expressed using Equation 27. Now taking some typical parameters we can evaluate a possible configuration of gains and thereby the associated allocation of resources. This is shown in Figure 46.

{{< figure src="technical_1/RDBG.pdf" title="Figure 46: Resource allocation for analogue power and area using the parameters \\(G_T=500\\), \\(\alpha=0.3\\), and \\(\beta=0.05\\). " width="500" >}}


Lets take \\(A_{unit}\\) as some unit capacitance size that allows the deviation of gain due to mismatch to fall inside the confidence interval. In order to realize Equation 26, each stage has its power and input referred noise reduced by accumulated gain for the preceding stages. This result presents us with the trend illustrated in Figure 47 where it appears that in many stage systems it is relatively beneficial to redistribute the resources to the front-end for a reduction in overall power. However when the number of stages is three or less we observe the increase in area can diminish this improvement for high gain system requirements.

{{< figure src="technical_1/NM_NP.pdf}" width="500" >}}
{{< figure src="technical_1/NM_PAP.pdf}" title="Figure 47: Normalized resource improvements for \\(\alpha\\) with respect the case when \\(\alpha=1\\) for each configuration. " width="500" >}}


So far we have neglected some aspects to the design consideration. The first is the multiplicative increase standard deviation as N is increases and the sensitivity to variance being inversely proportional to closed loop gain. Here we can account for the increased variance by proportionally increasing \\(A_{unit}\\) in order to neutralize this increase according to Equation 28.

$$  \Delta   \sigma^2 =\frac{A_{\mu+\sigma}}{A_{Gain}} \approx \prod_{i=1}^{k} \left( 1 + \sigma   CI \left[ 2 - \frac{2}{√{ A_{g}   \beta + A_{g}   \alpha^i }} \right] \right) $$

Again \\(\sigma\\) represents the deviation for a chosen unit capacitance and \\(CI\\) is our confidence interval. For completeness in estimating area we will also introduce the capacitance required for performing filtering on the last \\(K\\) stages. Rearranging Equation 6 in terms of output referred noise according to Equation 29.

$$  e^2_{out} = \frac{kT}{C}   {NEF^2}{\eta} $$

Combining these terms lets us define a more accurate area requirement that is reformulated in Equation 30.

$$  A_{filt} = A_{unit} \cdot \frac{kT}{C_{unit}}   \frac{NEF^2   SNR^2}{Vdd^2   \eta} \cdot \left( 1 + \sum_{k=1}^{K-1}  \prod_{i=1}^{k}  \left[A_{g} \beta + A_{g} \alpha^{N-i} \right] \right) $$

It is important to point out that SNR here refers to the SNR of the data converter as we have fixed the input referred noise of the system for a systematic comparison and we adjust \\(G_T\\) to fill this dynamic range. And extending this result with the requirements for signal conversion we can estimate system level power \\(P_{Total}\\) and area \\(A_{Total}\\) requirements as a sum of individual components according to Equation 31.

$$  A_{Total} = A_{filt} + A_{Gain} + A_{ADC}  \text{and}  P_{Total} = P_{Amplifiers} + P_{ADC} $$


Taking an appropriate set of parameter values, the system of relations is exemplified in Figure 48 with respect to the dependency on the supply voltage, \\(Vdd\\). As illustrated there are two domains when considering the area requirement. For small \\(Vdd\\) the sampling & filtering noise requirements overwhelm the design particularly in this case if \\(\alpha\\) is not taken small enough and a second order roll off is needed. When there is more voltage overhead available we observe reliably matching in input dynamic range of the ADC is the dominating factor.

{{< figure src="technical_1/NM_TSNA.pdf}" width="500" >}}
{{< figure src="technical_1/NM_TSNAP.pdf}" title="Figure 48: Analogue resource relations with respect to different supply voltages. " width="500" >}}


The area power product also tells an interesting story. When \\(Vdd\\) is larger than 1 V a clear proportional dependency on power is apparent that is mostly related to the total gain & noise requirements of the system because the ADC is not the limiting factor. However for small supply voltage the power dissipation requirement is more closely related to the lower noise quantization requirements presented by the SD-SAR topology. We should be careful because certain circuit topologies are simply not viable below specific supply voltages and as a result it would no be possible to achieve a NEF smaller than 2. Figure 48 also indicates when particular topologies are viable specific to the $0.18   \mu m$ CMOS process where $V_{th} \approx 350 mV$. That said it is likely a system can be designed with \\(0.6 V\\) supply in order to achieve significant power and area savings. The main challenge will be achieving acceptable total harmonic distortion as the supply will not easily allow cascoding transistors. Particularly sub-threshold transistors suffer from \\(Gm\\) nonlinearity as a function of \\(e^{\frac{-V_{DS}}{U_T}}\\) that can only be compensated by increased loop gain and multi-stage topologies. Since it is implementation dependent, it is difficult to quantify what this increase in area an power overhead this will result in. We can assert that \\(60 dB\\) precision with instrumentation has very significant diminishing returns when the conventional design approaches a \\(2 V_{th}\\) supply. The reader can find more details in regard to these comparisons in Section 60.

The approach taken here can be exhaustively extended towards including more detail in the system level design in order to leverage the capability of numerical methods. Higher order Gm-C filtering structures can be accounted for as a single stage by introducing new parameters that reflect the increase in \\(NEF\\) and filtering capacitors. Transistor area per amplifier can arguably be assumed static if chopping techniques are employed or alternatively this can accounted for by considering the flicker noise relations for the input transistors. However these contributions have negligible effect on changing the optimal resource destitution and will be more influenced by strategic positioning of poles to reject certain noise components. The most critical parameters on the systems level is the supply voltage as well as the requirement for channel to channel gain matching. As the power area product has a inverse square dependency as either \\(V_{DD}\\) or gain variance tends to zero. There are only a select number of scenarios where gain matching is of significance which is primarily in the case of distributed LFP recording and multi electrode (i.e. tetrode) recordings where exact coupling of neural circuitry is in question. The supply voltage has significance with respect to the expected power dissipation of the on chip digital processing and it is understandably advantageous to aggressively dissipate more power on the analogue side if the power saving in the digital domain indicate a overall improvement.

We note another aspect to technology selection in addition enabling voltage scaling is the increase in functional capacitor density. In fact we have shown that the dominant factor for area requirement in chopper stabilized structures is capacitance through the strong dependency on gain and filtering elements. More advanced processes have an increased number of metal layers and higher transistor gate capacitance. This ultimately leads to an increased capacitor density per square millimetre. In certain scenarios this should allow us to marginally shrink amplifier configurations while keeping the same filter characteristics. The main concern would be associated with capacitor nonlinearity that requires extra consideration or correction circuits.

# 29 Conclusion

This chapter has demonstrated the capacity for conventional analogue instrumentation with state-of-the-art circuit techniques. This presents capacity for achieving very compact performance that is sufficient for the full characterization of neural recordings. The fabricated system uses 0.03 mm\\(^2\\) size silicon footprint for 4 recording channels that can characterize 5 mVpp neural signals with over 11 bits of precision. In addition proposed $\Delta\Sigma SAR$ ADC topology demonstrates how oversampling converters can achieve 10fJ/conversion efficiency with minimal circuit complexity. The techniques applied here suggests chopping and sigma-delta modulation are key components for achieving better performance particularly for size constrained systems. In association we suggest immediate digitization & coherent mixed signal processing to leverage a number of advantages. Moreover we expect modern system will allow more processing capabilities in the digital baseband for BMI systems that needs to be used effectively.

The significance of minimizing the noise efficiency factor has been revealed in terms of having profound influence to power dissipation and area. In extension we have presented a number of topologies that excel at achieving excellent power and area efficiency in the case of single stage, two stage, and ADC structures. However we are left with little surprise when methodical optimization of various configurations is limited by the fundamental bounds in terms of noise and dynamic range. In fact various idealized configuration show little benefit with respect to one another if they have been optimized and exploited appropriately with the understanding presented. It is characteristic that improving resource efficiency for full bandwidth signal quantization is difficult because we simultaniously attempt to achieve lower supply voltages.

Although digitization is crucial to most neural recording systems for extracting the signal characteristics used to train and improve signal postprocessing. It is clear that improvements at the system level will lie very much in the domain of specialized instrumentation and analogue to information converters. This notion is motivated by the desire for the system to be limited by the law of equipartition and less so by the quantization process of the data converter. The direct classification of recordings in the analogue domain has significant implications on the responsibilities of the accompanied DSP on chip and the reduction of associated processing bandwidth.

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